target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "exec/helper-proto.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include "exec/cpu_ldst.h"
  11 #include "arm_ldst.h"
  12 #include <zlib.h> /* For crc32 */
  13
  14 #ifndef CONFIG_USER_ONLY
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 /* Return true if extended addresses are enabled.
 308  * This is always the case if our translation regime is 64 bit,
 309  * but depends on TTBCR.EAE for 32 bit.
 310  */
 311 static inline bool extended_addresses_enabled(CPUARMState *env)
 312 {
 313     return arm_el_is_aa64(env, 1)
 314         || ((arm_feature(env, ARM_FEATURE_LPAE)
 315              && (env->cp15.c2_control & TTBCR_EAE)));
 316 }
 317
 318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 319 {
 320     ARMCPU *cpu = arm_env_get_cpu(env);
 321
 322     raw_write(env, ri, value);
 323     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 324 }
 325
 326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 327 {
 328     ARMCPU *cpu = arm_env_get_cpu(env);
 329
 330     if (raw_read(env, ri) != value) {
 331         /* Unlike real hardware the qemu TLB uses virtual addresses,
 332          * not modified virtual addresses, so this causes a TLB flush.
 333          */
 334         tlb_flush(CPU(cpu), 1);
 335         raw_write(env, ri, value);
 336     }
 337 }
 338
 339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 340                              uint64_t value)
 341 {
 342     ARMCPU *cpu = arm_env_get_cpu(env);
 343
 344     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 345         && !extended_addresses_enabled(env)) {
 346         /* For VMSA (when not using the LPAE long descriptor page table
 347          * format) this register includes the ASID, so do a TLB flush.
 348          * For PMSA it is purely a process ID and no action is needed.
 349          */
 350         tlb_flush(CPU(cpu), 1);
 351     }
 352     raw_write(env, ri, value);
 353 }
 354
 355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 356                           uint64_t value)
 357 {
 358     /* Invalidate all (TLBIALL) */
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     tlb_flush(CPU(cpu), 1);
 362 }
 363
 364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 365                           uint64_t value)
 366 {
 367     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 368     ARMCPU *cpu = arm_env_get_cpu(env);
 369
 370     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 371 }
 372
 373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 374                            uint64_t value)
 375 {
 376     /* Invalidate by ASID (TLBIASID) */
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     tlb_flush(CPU(cpu), value == 0);
 380 }
 381
 382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 383                            uint64_t value)
 384 {
 385     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 386     ARMCPU *cpu = arm_env_get_cpu(env);
 387
 388     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 389 }
 390
 391 static const ARMCPRegInfo cp_reginfo[] = {
 392     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 393       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 394       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 395     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 396       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 397       .access = PL1_RW,
 398       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 399       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 400     REGINFO_SENTINEL
 401 };
 402
 403 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 404     /* NB: Some of these registers exist in v8 but with more precise
 405      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 406      */
 407     /* MMU Domain access control / MPU write buffer control */
 408     { .name = "DACR", .cp = 15,
 409       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 410       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 411       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 412     /* ??? This covers not just the impdef TLB lockdown registers but also
 413      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 414      */
 415     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 416       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 417     /* MMU TLB control. Note that the wildcarding means we cover not just
 418      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 419      */
 420     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 421       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 422       .type = ARM_CP_NO_MIGRATE },
 423     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 424       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 425       .type = ARM_CP_NO_MIGRATE },
 426     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 427       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 428       .type = ARM_CP_NO_MIGRATE },
 429     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 430       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 431       .type = ARM_CP_NO_MIGRATE },
 432     /* Cache maintenance ops; some of this space may be overridden later. */
 433     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 434       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 435       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 436     REGINFO_SENTINEL
 437 };
 438
 439 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 440     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 441      * over-broad.
 442      */
 443     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 444       .access = PL1_W, .type = ARM_CP_WFI },
 445     REGINFO_SENTINEL
 446 };
 447
 448 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 449     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 450      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 451      */
 452     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 453       .access = PL1_W, .type = ARM_CP_WFI },
 454     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 455      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 456      * OMAPCP will override this space.
 457      */
 458     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 459       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 460       .resetvalue = 0 },
 461     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 462       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 463       .resetvalue = 0 },
 464     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 465     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 466       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 467       .resetvalue = 0 },
 468     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 469      * implementing it as RAZ means the "debug architecture version" bits
 470      * will read as a reserved value, which should cause Linux to not try
 471      * to use the debug hardware.
 472      */
 473     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 474       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 475     REGINFO_SENTINEL
 476 };
 477
 478 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 479                         uint64_t value)
 480 {
 481     uint32_t mask = 0;
 482
 483     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 484     if (!arm_feature(env, ARM_FEATURE_V8)) {
 485         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 486          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 487          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 488          */
 489         if (arm_feature(env, ARM_FEATURE_VFP)) {
 490             /* VFP coprocessor: cp10 & cp11 [23:20] */
 491             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 492
 493             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 494                 /* ASEDIS [31] bit is RAO/WI */
 495                 value |= (1 << 31);
 496             }
 497
 498             /* VFPv3 and upwards with NEON implement 32 double precision
 499              * registers (D0-D31).
 500              */
 501             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 502                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 503                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 504                 value |= (1 << 30);
 505             }
 506         }
 507         value &= mask;
 508     }
 509     env->cp15.c1_coproc = value;
 510 }
 511
 512 static const ARMCPRegInfo v6_cp_reginfo[] = {
 513     /* prefetch by MVA in v6, NOP in v7 */
 514     { .name = "MVA_prefetch",
 515       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 516       .access = PL1_W, .type = ARM_CP_NOP },
 517     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 518       .access = PL0_W, .type = ARM_CP_NOP },
 519     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 520       .access = PL0_W, .type = ARM_CP_NOP },
 521     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 522       .access = PL0_W, .type = ARM_CP_NOP },
 523     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 524       .access = PL1_RW,
 525       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 526       .resetvalue = 0, },
 527     /* Watchpoint Fault Address Register : should actually only be present
 528      * for 1136, 1176, 11MPCore.
 529      */
 530     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 531       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 532     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 533       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 534       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 535       .resetvalue = 0, .writefn = cpacr_write },
 536     REGINFO_SENTINEL
 537 };
 538
 539 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 540 {
 541     /* Performance monitor registers user accessibility is controlled
 542      * by PMUSERENR.
 543      */
 544     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 545         return CP_ACCESS_TRAP;
 546     }
 547     return CP_ACCESS_OK;
 548 }
 549
 550 #ifndef CONFIG_USER_ONLY
 551
 552 static inline bool arm_ccnt_enabled(CPUARMState *env)
 553 {
 554     /* This does not support checking PMCCFILTR_EL0 register */
 555
 556     if (!(env->cp15.c9_pmcr & PMCRE)) {
 557         return false;
 558     }
 559
 560     return true;
 561 }
 562
 563 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 564                        uint64_t value)
 565 {
 566     uint64_t temp_ticks;
 567
 568     temp_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 569                           get_ticks_per_sec(), 1000000);
 570
 571     if (env->cp15.c9_pmcr & PMCRE) {
 572         /* If the counter is enabled */
 573         if (env->cp15.c9_pmcr & PMCRD) {
 574             /* Increment once every 64 processor clock cycles */
 575             env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
 576         } else {
 577             env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 578         }
 579     }
 580
 581     if (value & PMCRC) {
 582         /* The counter has been reset */
 583         env->cp15.c15_ccnt = 0;
 584     }
 585
 586     /* only the DP, X, D and E bits are writable */
 587     env->cp15.c9_pmcr &= ~0x39;
 588     env->cp15.c9_pmcr |= (value & 0x39);
 589
 590     if (env->cp15.c9_pmcr & PMCRE) {
 591         if (env->cp15.c9_pmcr & PMCRD) {
 592             /* Increment once every 64 processor clock cycles */
 593             temp_ticks /= 64;
 594         }
 595         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 596     }
 597 }
 598
 599 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 600 {
 601     uint64_t total_ticks;
 602
 603     if (!(env->cp15.c9_pmcr & PMCRE)) {
 604         /* Counter is disabled, do not change value */
 605         return env->cp15.c15_ccnt;
 606     }
 607
 608     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 609                            get_ticks_per_sec(), 1000000);
 610
 611     if (env->cp15.c9_pmcr & PMCRD) {
 612         /* Increment once every 64 processor clock cycles */
 613         total_ticks /= 64;
 614     }
 615     return total_ticks - env->cp15.c15_ccnt;
 616 }
 617
 618 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 619                         uint64_t value)
 620 {
 621     uint64_t total_ticks;
 622
 623     if (!(env->cp15.c9_pmcr & PMCRE)) {
 624         /* Counter is disabled, set the absolute value */
 625         env->cp15.c15_ccnt = value;
 626         return;
 627     }
 628
 629     total_ticks = muldiv64(qemu_clock_get_us(QEMU_CLOCK_VIRTUAL),
 630                            get_ticks_per_sec(), 1000000);
 631
 632     if (env->cp15.c9_pmcr & PMCRD) {
 633         /* Increment once every 64 processor clock cycles */
 634         total_ticks /= 64;
 635     }
 636     env->cp15.c15_ccnt = total_ticks - value;
 637 }
 638
 639 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 640                             uint64_t value)
 641 {
 642     uint64_t cur_val = pmccntr_read(env, NULL);
 643
 644     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 645 }
 646
 647 #endif
 648
 649 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 650                             uint64_t value)
 651 {
 652     value &= (1 << 31);
 653     env->cp15.c9_pmcnten |= value;
 654 }
 655
 656 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 657                              uint64_t value)
 658 {
 659     value &= (1 << 31);
 660     env->cp15.c9_pmcnten &= ~value;
 661 }
 662
 663 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 664                          uint64_t value)
 665 {
 666     env->cp15.c9_pmovsr &= ~value;
 667 }
 668
 669 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 670                              uint64_t value)
 671 {
 672     env->cp15.c9_pmxevtyper = value & 0xff;
 673 }
 674
 675 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 676                             uint64_t value)
 677 {
 678     env->cp15.c9_pmuserenr = value & 1;
 679 }
 680
 681 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 682                              uint64_t value)
 683 {
 684     /* We have no event counters so only the C bit can be changed */
 685     value &= (1 << 31);
 686     env->cp15.c9_pminten |= value;
 687 }
 688
 689 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 690                              uint64_t value)
 691 {
 692     value &= (1 << 31);
 693     env->cp15.c9_pminten &= ~value;
 694 }
 695
 696 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 697                        uint64_t value)
 698 {
 699     /* Note that even though the AArch64 view of this register has bits
 700      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 701      * architectural requirements for bits which are RES0 only in some
 702      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 703      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 704      */
 705     raw_write(env, ri, value & ~0x1FULL);
 706 }
 707
 708 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 709 {
 710     ARMCPU *cpu = arm_env_get_cpu(env);
 711     return cpu->ccsidr[env->cp15.c0_cssel];
 712 }
 713
 714 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 715                          uint64_t value)
 716 {
 717     raw_write(env, ri, value & 0xf);
 718 }
 719
 720 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 721 {
 722     CPUState *cs = ENV_GET_CPU(env);
 723     uint64_t ret = 0;
 724
 725     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 726         ret |= CPSR_I;
 727     }
 728     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 729         ret |= CPSR_F;
 730     }
 731     /* External aborts are not possible in QEMU so A bit is always clear */
 732     return ret;
 733 }
 734
 735 static const ARMCPRegInfo v7_cp_reginfo[] = {
 736     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 737     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 738       .access = PL1_W, .type = ARM_CP_NOP },
 739     /* Performance monitors are implementation defined in v7,
 740      * but with an ARM recommended set of registers, which we
 741      * follow (although we don't actually implement any counters)
 742      *
 743      * Performance registers fall into three categories:
 744      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 745      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 746      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 747      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 748      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 749      */
 750     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 751       .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
 752       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 753       .writefn = pmcntenset_write,
 754       .accessfn = pmreg_access,
 755       .raw_writefn = raw_write },
 756     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
 757       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
 758       .access = PL0_RW, .accessfn = pmreg_access,
 759       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
 760       .writefn = pmcntenset_write, .raw_writefn = raw_write },
 761     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 762       .access = PL0_RW,
 763       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
 764       .accessfn = pmreg_access,
 765       .writefn = pmcntenclr_write,
 766       .type = ARM_CP_NO_MIGRATE },
 767     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
 768       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
 769       .access = PL0_RW, .accessfn = pmreg_access,
 770       .type = ARM_CP_NO_MIGRATE,
 771       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 772       .writefn = pmcntenclr_write },
 773     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 774       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 775       .accessfn = pmreg_access,
 776       .writefn = pmovsr_write,
 777       .raw_writefn = raw_write },
 778     /* Unimplemented so WI. */
 779     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 780       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 781     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 782      * We choose to RAZ/WI.
 783      */
 784     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 785       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 786       .accessfn = pmreg_access },
 787 #ifndef CONFIG_USER_ONLY
 788     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 789       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 790       .readfn = pmccntr_read, .writefn = pmccntr_write32,
 791       .accessfn = pmreg_access },
 792     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
 793       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
 794       .access = PL0_RW, .accessfn = pmreg_access,
 795       .type = ARM_CP_IO,
 796       .readfn = pmccntr_read, .writefn = pmccntr_write, },
 797 #endif
 798     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
 799       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
 800       .access = PL0_RW, .accessfn = pmreg_access,
 801       .type = ARM_CP_IO,
 802       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
 803       .resetvalue = 0, },
 804     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 805       .access = PL0_RW,
 806       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 807       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 808       .raw_writefn = raw_write },
 809     /* Unimplemented, RAZ/WI. */
 810     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 811       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 812       .accessfn = pmreg_access },
 813     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 814       .access = PL0_R | PL1_RW,
 815       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 816       .resetvalue = 0,
 817       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 818     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 819       .access = PL1_RW,
 820       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 821       .resetvalue = 0,
 822       .writefn = pmintenset_write, .raw_writefn = raw_write },
 823     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 824       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 825       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 826       .resetvalue = 0, .writefn = pmintenclr_write, },
 827     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 828       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 829       .access = PL1_RW, .writefn = vbar_write,
 830       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
 831       .resetvalue = 0 },
 832     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 833       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 834       .resetvalue = 0, },
 835     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 836       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 837       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 838     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 839       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 840       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 841       .writefn = csselr_write, .resetvalue = 0 },
 842     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 843      * just RAZ for all cores:
 844      */
 845     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 846       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 847       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 848     /* Auxiliary fault status registers: these also are IMPDEF, and we
 849      * choose to RAZ/WI for all cores.
 850      */
 851     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 852       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 853       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 854     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 855       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 856       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 857     /* MAIR can just read-as-written because we don't implement caches
 858      * and so don't need to care about memory attributes.
 859      */
 860     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 861       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 862       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 863       .resetvalue = 0 },
 864     /* For non-long-descriptor page tables these are PRRR and NMRR;
 865      * regardless they still act as reads-as-written for QEMU.
 866      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 867      * definition.
 868      */
 869     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 870       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 871       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 872       .resetfn = arm_cp_reset_ignore },
 873     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 874       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 875       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 876       .resetfn = arm_cp_reset_ignore },
 877     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 878       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 879       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 880     REGINFO_SENTINEL
 881 };
 882
 883 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 884                         uint64_t value)
 885 {
 886     value &= 1;
 887     env->teecr = value;
 888 }
 889
 890 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 891 {
 892     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 893         return CP_ACCESS_TRAP;
 894     }
 895     return CP_ACCESS_OK;
 896 }
 897
 898 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 899     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 900       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 901       .resetvalue = 0,
 902       .writefn = teecr_write },
 903     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 904       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 905       .accessfn = teehbr_access, .resetvalue = 0 },
 906     REGINFO_SENTINEL
 907 };
 908
 909 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 910     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 911       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 912       .access = PL0_RW,
 913       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 914     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 915       .access = PL0_RW,
 916       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 917       .resetfn = arm_cp_reset_ignore },
 918     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 919       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 920       .access = PL0_R|PL1_W,
 921       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 922     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 923       .access = PL0_R|PL1_W,
 924       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 925       .resetfn = arm_cp_reset_ignore },
 926     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 927       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 928       .access = PL1_RW,
 929       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 930     REGINFO_SENTINEL
 931 };
 932
 933 #ifndef CONFIG_USER_ONLY
 934
 935 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 936 {
 937     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 938     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 939         return CP_ACCESS_TRAP;
 940     }
 941     return CP_ACCESS_OK;
 942 }
 943
 944 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 945 {
 946     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 947     if (arm_current_pl(env) == 0 &&
 948         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 949         return CP_ACCESS_TRAP;
 950     }
 951     return CP_ACCESS_OK;
 952 }
 953
 954 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 955 {
 956     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 957      * EL0[PV]TEN is zero.
 958      */
 959     if (arm_current_pl(env) == 0 &&
 960         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 961         return CP_ACCESS_TRAP;
 962     }
 963     return CP_ACCESS_OK;
 964 }
 965
 966 static CPAccessResult gt_pct_access(CPUARMState *env,
 967                                          const ARMCPRegInfo *ri)
 968 {
 969     return gt_counter_access(env, GTIMER_PHYS);
 970 }
 971
 972 static CPAccessResult gt_vct_access(CPUARMState *env,
 973                                          const ARMCPRegInfo *ri)
 974 {
 975     return gt_counter_access(env, GTIMER_VIRT);
 976 }
 977
 978 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 979 {
 980     return gt_timer_access(env, GTIMER_PHYS);
 981 }
 982
 983 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 984 {
 985     return gt_timer_access(env, GTIMER_VIRT);
 986 }
 987
 988 static uint64_t gt_get_countervalue(CPUARMState *env)
 989 {
 990     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
 991 }
 992
 993 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 994 {
 995     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
 996
 997     if (gt->ctl & 1) {
 998         /* Timer enabled: calculate and set current ISTATUS, irq, and
 999          * reset timer to when ISTATUS next has to change
1000          */
1001         uint64_t count = gt_get_countervalue(&cpu->env);
1002         /* Note that this must be unsigned 64 bit arithmetic: */
1003         int istatus = count >= gt->cval;
1004         uint64_t nexttick;
1005
1006         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1007         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1008                      (istatus && !(gt->ctl & 2)));
1009         if (istatus) {
1010             /* Next transition is when count rolls back over to zero */
1011             nexttick = UINT64_MAX;
1012         } else {
1013             /* Next transition is when we hit cval */
1014             nexttick = gt->cval;
1015         }
1016         /* Note that the desired next expiry time might be beyond the
1017          * signed-64-bit range of a QEMUTimer -- in this case we just
1018          * set the timer for as far in the future as possible. When the
1019          * timer expires we will reset the timer for any remaining period.
1020          */
1021         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1022             nexttick = INT64_MAX / GTIMER_SCALE;
1023         }
1024         timer_mod(cpu->gt_timer[timeridx], nexttick);
1025     } else {
1026         /* Timer disabled: ISTATUS and timer output always clear */
1027         gt->ctl &= ~4;
1028         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1029         timer_del(cpu->gt_timer[timeridx]);
1030     }
1031 }
1032
1033 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1034 {
1035     ARMCPU *cpu = arm_env_get_cpu(env);
1036     int timeridx = ri->opc1 & 1;
1037
1038     timer_del(cpu->gt_timer[timeridx]);
1039 }
1040
1041 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1042 {
1043     return gt_get_countervalue(env);
1044 }
1045
1046 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1047                           uint64_t value)
1048 {
1049     int timeridx = ri->opc1 & 1;
1050
1051     env->cp15.c14_timer[timeridx].cval = value;
1052     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1053 }
1054
1055 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1056 {
1057     int timeridx = ri->crm & 1;
1058
1059     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1060                       gt_get_countervalue(env));
1061 }
1062
1063 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1064                           uint64_t value)
1065 {
1066     int timeridx = ri->crm & 1;
1067
1068     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1069         + sextract64(value, 0, 32);
1070     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1071 }
1072
1073 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1074                          uint64_t value)
1075 {
1076     ARMCPU *cpu = arm_env_get_cpu(env);
1077     int timeridx = ri->crm & 1;
1078     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1079
1080     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1081     if ((oldval ^ value) & 1) {
1082         /* Enable toggled */
1083         gt_recalc_timer(cpu, timeridx);
1084     } else if ((oldval ^ value) & 2) {
1085         /* IMASK toggled: don't need to recalculate,
1086          * just set the interrupt line based on ISTATUS
1087          */
1088         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1089                      (oldval & 4) && !(value & 2));
1090     }
1091 }
1092
1093 void arm_gt_ptimer_cb(void *opaque)
1094 {
1095     ARMCPU *cpu = opaque;
1096
1097     gt_recalc_timer(cpu, GTIMER_PHYS);
1098 }
1099
1100 void arm_gt_vtimer_cb(void *opaque)
1101 {
1102     ARMCPU *cpu = opaque;
1103
1104     gt_recalc_timer(cpu, GTIMER_VIRT);
1105 }
1106
1107 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1108     /* Note that CNTFRQ is purely reads-as-written for the benefit
1109      * of software; writing it doesn't actually change the timer frequency.
1110      * Our reset value matches the fixed frequency we implement the timer at.
1111      */
1112     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1113       .type = ARM_CP_NO_MIGRATE,
1114       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1115       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1116       .resetfn = arm_cp_reset_ignore,
1117     },
1118     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1119       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1120       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1121       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1122       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1123     },
1124     /* overall control: mostly access permissions */
1125     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1126       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1127       .access = PL1_RW,
1128       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1129       .resetvalue = 0,
1130     },
1131     /* per-timer control */
1132     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1133       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1134       .accessfn = gt_ptimer_access,
1135       .fieldoffset = offsetoflow32(CPUARMState,
1136                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1137       .resetfn = arm_cp_reset_ignore,
1138       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1139     },
1140     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1141       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1142       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1143       .accessfn = gt_ptimer_access,
1144       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1145       .resetvalue = 0,
1146       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1147     },
1148     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1149       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1150       .accessfn = gt_vtimer_access,
1151       .fieldoffset = offsetoflow32(CPUARMState,
1152                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1153       .resetfn = arm_cp_reset_ignore,
1154       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1155     },
1156     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1157       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1158       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1159       .accessfn = gt_vtimer_access,
1160       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1161       .resetvalue = 0,
1162       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1163     },
1164     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1165     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1166       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1167       .accessfn = gt_ptimer_access,
1168       .readfn = gt_tval_read, .writefn = gt_tval_write,
1169     },
1170     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1171       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1172       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1173       .readfn = gt_tval_read, .writefn = gt_tval_write,
1174     },
1175     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1176       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1177       .accessfn = gt_vtimer_access,
1178       .readfn = gt_tval_read, .writefn = gt_tval_write,
1179     },
1180     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1181       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1182       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1183       .readfn = gt_tval_read, .writefn = gt_tval_write,
1184     },
1185     /* The counter itself */
1186     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1187       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1188       .accessfn = gt_pct_access,
1189       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1190     },
1191     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1192       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1193       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1194       .accessfn = gt_pct_access,
1195       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1196     },
1197     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1198       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1199       .accessfn = gt_vct_access,
1200       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1201     },
1202     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1203       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1204       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1205       .accessfn = gt_vct_access,
1206       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1207     },
1208     /* Comparison value, indicating when the timer goes off */
1209     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1210       .access = PL1_RW | PL0_R,
1211       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1212       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1213       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1214       .writefn = gt_cval_write, .raw_writefn = raw_write,
1215     },
1216     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1217       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1218       .access = PL1_RW | PL0_R,
1219       .type = ARM_CP_IO,
1220       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1221       .resetvalue = 0, .accessfn = gt_vtimer_access,
1222       .writefn = gt_cval_write, .raw_writefn = raw_write,
1223     },
1224     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1225       .access = PL1_RW | PL0_R,
1226       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1227       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1228       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1229       .writefn = gt_cval_write, .raw_writefn = raw_write,
1230     },
1231     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1232       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1233       .access = PL1_RW | PL0_R,
1234       .type = ARM_CP_IO,
1235       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1236       .resetvalue = 0, .accessfn = gt_vtimer_access,
1237       .writefn = gt_cval_write, .raw_writefn = raw_write,
1238     },
1239     REGINFO_SENTINEL
1240 };
1241
1242 #else
1243 /* In user-mode none of the generic timer registers are accessible,
1244  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1245  * so instead just don't register any of them.
1246  */
1247 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1248     REGINFO_SENTINEL
1249 };
1250
1251 #endif
1252
1253 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1254 {
1255     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1256         raw_write(env, ri, value);
1257     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1258         raw_write(env, ri, value & 0xfffff6ff);
1259     } else {
1260         raw_write(env, ri, value & 0xfffff1ff);
1261     }
1262 }
1263
1264 #ifndef CONFIG_USER_ONLY
1265 /* get_phys_addr() isn't present for user-mode-only targets */
1266
1267 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1268 {
1269     if (ri->opc2 & 4) {
1270         /* Other states are only available with TrustZone; in
1271          * a non-TZ implementation these registers don't exist
1272          * at all, which is an Uncategorized trap. This underdecoding
1273          * is safe because the reginfo is NO_MIGRATE.
1274          */
1275         return CP_ACCESS_TRAP_UNCATEGORIZED;
1276     }
1277     return CP_ACCESS_OK;
1278 }
1279
1280 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1281 {
1282     hwaddr phys_addr;
1283     target_ulong page_size;
1284     int prot;
1285     int ret, is_user = ri->opc2 & 2;
1286     int access_type = ri->opc2 & 1;
1287
1288     ret = get_phys_addr(env, value, access_type, is_user,
1289                         &phys_addr, &prot, &page_size);
1290     if (extended_addresses_enabled(env)) {
1291         /* ret is a DFSR/IFSR value for the long descriptor
1292          * translation table format, but with WnR always clear.
1293          * Convert it to a 64-bit PAR.
1294          */
1295         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1296         if (ret == 0) {
1297             par64 |= phys_addr & ~0xfffULL;
1298             /* We don't set the ATTR or SH fields in the PAR. */
1299         } else {
1300             par64 |= 1; /* F */
1301             par64 |= (ret & 0x3f) << 1; /* FS */
1302             /* Note that S2WLK and FSTAGE are always zero, because we don't
1303              * implement virtualization and therefore there can't be a stage 2
1304              * fault.
1305              */
1306         }
1307         env->cp15.par_el1 = par64;
1308     } else {
1309         /* ret is a DFSR/IFSR value for the short descriptor
1310          * translation table format (with WnR always clear).
1311          * Convert it to a 32-bit PAR.
1312          */
1313         if (ret == 0) {
1314             /* We do not set any attribute bits in the PAR */
1315             if (page_size == (1 << 24)
1316                 && arm_feature(env, ARM_FEATURE_V7)) {
1317                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1318             } else {
1319                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1320             }
1321         } else {
1322             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1323                 ((ret & (1 << 12)) >> 6) |
1324                 ((ret & 0xf) << 1) | 1;
1325         }
1326     }
1327 }
1328 #endif
1329
1330 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1331     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1332       .access = PL1_RW, .resetvalue = 0,
1333       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1334       .writefn = par_write },
1335 #ifndef CONFIG_USER_ONLY
1336     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1337       .access = PL1_W, .accessfn = ats_access,
1338       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1339 #endif
1340     REGINFO_SENTINEL
1341 };
1342
1343 /* Return basic MPU access permission bits.  */
1344 static uint32_t simple_mpu_ap_bits(uint32_t val)
1345 {
1346     uint32_t ret;
1347     uint32_t mask;
1348     int i;
1349     ret = 0;
1350     mask = 3;
1351     for (i = 0; i < 16; i += 2) {
1352         ret |= (val >> i) & mask;
1353         mask <<= 2;
1354     }
1355     return ret;
1356 }
1357
1358 /* Pad basic MPU access permission bits to extended format.  */
1359 static uint32_t extended_mpu_ap_bits(uint32_t val)
1360 {
1361     uint32_t ret;
1362     uint32_t mask;
1363     int i;
1364     ret = 0;
1365     mask = 3;
1366     for (i = 0; i < 16; i += 2) {
1367         ret |= (val & mask) << i;
1368         mask <<= 2;
1369     }
1370     return ret;
1371 }
1372
1373 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1374                                  uint64_t value)
1375 {
1376     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1377 }
1378
1379 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1380 {
1381     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1382 }
1383
1384 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1385                                  uint64_t value)
1386 {
1387     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1388 }
1389
1390 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1391 {
1392     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1393 }
1394
1395 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1396     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1397       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1398       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1399       .resetvalue = 0,
1400       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1401     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1402       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1403       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1404       .resetvalue = 0,
1405       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1406     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1407       .access = PL1_RW,
1408       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1409       .resetvalue = 0, },
1410     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1411       .access = PL1_RW,
1412       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1413       .resetvalue = 0, },
1414     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1415       .access = PL1_RW,
1416       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1417     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1418       .access = PL1_RW,
1419       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1420     /* Protection region base and size registers */
1421     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1422       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1423       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1424     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1425       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1426       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1427     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1428       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1429       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1430     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1431       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1432       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1433     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1434       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1435       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1436     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1437       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1438       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1439     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1440       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1441       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1442     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1443       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1444       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1445     REGINFO_SENTINEL
1446 };
1447
1448 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1449                                  uint64_t value)
1450 {
1451     int maskshift = extract32(value, 0, 3);
1452
1453     if (!arm_feature(env, ARM_FEATURE_V8)) {
1454         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
1455             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
1456              * using Long-desciptor translation table format */
1457             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1458         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
1459             /* In an implementation that includes the Security Extensions
1460              * TTBCR has additional fields PD0 [4] and PD1 [5] for
1461              * Short-descriptor translation table format.
1462              */
1463             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
1464         } else {
1465             value &= TTBCR_N;
1466         }
1467     }
1468
1469     /* Note that we always calculate c2_mask and c2_base_mask, but
1470      * they are only used for short-descriptor tables (ie if EAE is 0);
1471      * for long-descriptor tables the TTBCR fields are used differently
1472      * and the c2_mask and c2_base_mask values are meaningless.
1473      */
1474     raw_write(env, ri, value);
1475     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1476     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1477 }
1478
1479 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1480                              uint64_t value)
1481 {
1482     ARMCPU *cpu = arm_env_get_cpu(env);
1483
1484     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1485         /* With LPAE the TTBCR could result in a change of ASID
1486          * via the TTBCR.A1 bit, so do a TLB flush.
1487          */
1488         tlb_flush(CPU(cpu), 1);
1489     }
1490     vmsa_ttbcr_raw_write(env, ri, value);
1491 }
1492
1493 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1494 {
1495     env->cp15.c2_base_mask = 0xffffc000u;
1496     raw_write(env, ri, 0);
1497     env->cp15.c2_mask = 0;
1498 }
1499
1500 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1501                                uint64_t value)
1502 {
1503     ARMCPU *cpu = arm_env_get_cpu(env);
1504
1505     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1506     tlb_flush(CPU(cpu), 1);
1507     raw_write(env, ri, value);
1508 }
1509
1510 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1511                             uint64_t value)
1512 {
1513     /* 64 bit accesses to the TTBRs can change the ASID and so we
1514      * must flush the TLB.
1515      */
1516     if (cpreg_field_is_64bit(ri)) {
1517         ARMCPU *cpu = arm_env_get_cpu(env);
1518
1519         tlb_flush(CPU(cpu), 1);
1520     }
1521     raw_write(env, ri, value);
1522 }
1523
1524 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1525     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1526       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1527       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1528       .resetfn = arm_cp_reset_ignore, },
1529     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1530       .access = PL1_RW,
1531       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1532     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1533       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1534       .access = PL1_RW,
1535       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
1536     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1537       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1538       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1539       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1540     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1541       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1542       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1543       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1544     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1545       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1546       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1547       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1548       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1549     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1550       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1551       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1552       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1553     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1554     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1555       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1556       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
1557       .resetvalue = 0, },
1558     REGINFO_SENTINEL
1559 };
1560
1561 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1562                                 uint64_t value)
1563 {
1564     env->cp15.c15_ticonfig = value & 0xe7;
1565     /* The OS_TYPE bit in this register changes the reported CPUID! */
1566     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1567         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1568 }
1569
1570 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1571                                 uint64_t value)
1572 {
1573     env->cp15.c15_threadid = value & 0xffff;
1574 }
1575
1576 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1577                            uint64_t value)
1578 {
1579     /* Wait-for-interrupt (deprecated) */
1580     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1581 }
1582
1583 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1584                                   uint64_t value)
1585 {
1586     /* On OMAP there are registers indicating the max/min index of dcache lines
1587      * containing a dirty line; cache flush operations have to reset these.
1588      */
1589     env->cp15.c15_i_max = 0x000;
1590     env->cp15.c15_i_min = 0xff0;
1591 }
1592
1593 static const ARMCPRegInfo omap_cp_reginfo[] = {
1594     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1595       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1596       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
1597       .resetvalue = 0, },
1598     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1599       .access = PL1_RW, .type = ARM_CP_NOP },
1600     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1601       .access = PL1_RW,
1602       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1603       .writefn = omap_ticonfig_write },
1604     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1605       .access = PL1_RW,
1606       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1607     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1608       .access = PL1_RW, .resetvalue = 0xff0,
1609       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1610     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1611       .access = PL1_RW,
1612       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1613       .writefn = omap_threadid_write },
1614     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1615       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1616       .type = ARM_CP_NO_MIGRATE,
1617       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1618     /* TODO: Peripheral port remap register:
1619      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1620      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1621      * when MMU is off.
1622      */
1623     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1624       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1625       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1626       .writefn = omap_cachemaint_write },
1627     { .name = "C9", .cp = 15, .crn = 9,
1628       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1629       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1630     REGINFO_SENTINEL
1631 };
1632
1633 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1634                               uint64_t value)
1635 {
1636     value &= 0x3fff;
1637     if (env->cp15.c15_cpar != value) {
1638         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1639         tb_flush(env);
1640         env->cp15.c15_cpar = value;
1641     }
1642 }
1643
1644 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1645     { .name = "XSCALE_CPAR",
1646       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1647       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1648       .writefn = xscale_cpar_write, },
1649     { .name = "XSCALE_AUXCR",
1650       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1651       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1652       .resetvalue = 0, },
1653     /* XScale specific cache-lockdown: since we have no cache we NOP these
1654      * and hope the guest does not really rely on cache behaviour.
1655      */
1656     { .name = "XSCALE_LOCK_ICACHE_LINE",
1657       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1658       .access = PL1_W, .type = ARM_CP_NOP },
1659     { .name = "XSCALE_UNLOCK_ICACHE",
1660       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1661       .access = PL1_W, .type = ARM_CP_NOP },
1662     { .name = "XSCALE_DCACHE_LOCK",
1663       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1664       .access = PL1_RW, .type = ARM_CP_NOP },
1665     { .name = "XSCALE_UNLOCK_DCACHE",
1666       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1667       .access = PL1_W, .type = ARM_CP_NOP },
1668     REGINFO_SENTINEL
1669 };
1670
1671 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1672     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1673      * implementation of this implementation-defined space.
1674      * Ideally this should eventually disappear in favour of actually
1675      * implementing the correct behaviour for all cores.
1676      */
1677     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1678       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1679       .access = PL1_RW,
1680       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1681       .resetvalue = 0 },
1682     REGINFO_SENTINEL
1683 };
1684
1685 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1686     /* Cache status: RAZ because we have no cache so it's always clean */
1687     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1688       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1689       .resetvalue = 0 },
1690     REGINFO_SENTINEL
1691 };
1692
1693 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1694     /* We never have a a block transfer operation in progress */
1695     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1696       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1697       .resetvalue = 0 },
1698     /* The cache ops themselves: these all NOP for QEMU */
1699     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1700       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1701     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1702       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1703     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1704       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1705     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1706       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1707     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1708       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1709     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1710       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1711     REGINFO_SENTINEL
1712 };
1713
1714 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1715     /* The cache test-and-clean instructions always return (1 << 30)
1716      * to indicate that there are no dirty cache lines.
1717      */
1718     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1719       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1720       .resetvalue = (1 << 30) },
1721     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1722       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1723       .resetvalue = (1 << 30) },
1724     REGINFO_SENTINEL
1725 };
1726
1727 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1728     /* Ignore ReadBuffer accesses */
1729     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1730       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1731       .access = PL1_RW, .resetvalue = 0,
1732       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1733     REGINFO_SENTINEL
1734 };
1735
1736 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1737 {
1738     CPUState *cs = CPU(arm_env_get_cpu(env));
1739     uint32_t mpidr = cs->cpu_index;
1740     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1741      * in later ARM ARM versions), or any of the higher affinity level fields,
1742      * so these bits always RAZ.
1743      */
1744     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1745         mpidr |= (1U << 31);
1746         /* Cores which are uniprocessor (non-coherent)
1747          * but still implement the MP extensions set
1748          * bit 30. (For instance, A9UP.) However we do
1749          * not currently model any of those cores.
1750          */
1751     }
1752     return mpidr;
1753 }
1754
1755 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1756     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1757       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1758       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1759     REGINFO_SENTINEL
1760 };
1761
1762 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1763     /* NOP AMAIR0/1: the override is because these clash with the rather
1764      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1765      */
1766     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1767       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1768       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1769       .resetvalue = 0 },
1770     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1771     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1772       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1773       .resetvalue = 0 },
1774     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1775       .access = PL1_RW, .type = ARM_CP_64BIT,
1776       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1777     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1778       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1779       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1780       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1781     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1782       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1783       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1784       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1785     REGINFO_SENTINEL
1786 };
1787
1788 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1789 {
1790     return vfp_get_fpcr(env);
1791 }
1792
1793 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1794                             uint64_t value)
1795 {
1796     vfp_set_fpcr(env, value);
1797 }
1798
1799 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1800 {
1801     return vfp_get_fpsr(env);
1802 }
1803
1804 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1805                             uint64_t value)
1806 {
1807     vfp_set_fpsr(env, value);
1808 }
1809
1810 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1811 {
1812     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1813         return CP_ACCESS_TRAP;
1814     }
1815     return CP_ACCESS_OK;
1816 }
1817
1818 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1819                             uint64_t value)
1820 {
1821     env->daif = value & PSTATE_DAIF;
1822 }
1823
1824 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1825                                           const ARMCPRegInfo *ri)
1826 {
1827     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1828      * SCTLR_EL1.UCI is set.
1829      */
1830     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1831         return CP_ACCESS_TRAP;
1832     }
1833     return CP_ACCESS_OK;
1834 }
1835
1836 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
1837  * Page D4-1736 (DDI0487A.b)
1838  */
1839
1840 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1841                                uint64_t value)
1842 {
1843     /* Invalidate by VA (AArch64 version) */
1844     ARMCPU *cpu = arm_env_get_cpu(env);
1845     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1846
1847     tlb_flush_page(CPU(cpu), pageaddr);
1848 }
1849
1850 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1851                                 uint64_t value)
1852 {
1853     /* Invalidate by VA, all ASIDs (AArch64 version) */
1854     ARMCPU *cpu = arm_env_get_cpu(env);
1855     uint64_t pageaddr = sextract64(value << 12, 0, 56);
1856
1857     tlb_flush_page(CPU(cpu), pageaddr);
1858 }
1859
1860 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1861                                  uint64_t value)
1862 {
1863     /* Invalidate by ASID (AArch64 version) */
1864     ARMCPU *cpu = arm_env_get_cpu(env);
1865     int asid = extract64(value, 48, 16);
1866     tlb_flush(CPU(cpu), asid == 0);
1867 }
1868
1869 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1870 {
1871     /* We don't implement EL2, so the only control on DC ZVA is the
1872      * bit in the SCTLR which can prohibit access for EL0.
1873      */
1874     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1875         return CP_ACCESS_TRAP;
1876     }
1877     return CP_ACCESS_OK;
1878 }
1879
1880 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1881 {
1882     ARMCPU *cpu = arm_env_get_cpu(env);
1883     int dzp_bit = 1 << 4;
1884
1885     /* DZP indicates whether DC ZVA access is allowed */
1886     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1887         dzp_bit = 0;
1888     }
1889     return cpu->dcz_blocksize | dzp_bit;
1890 }
1891
1892 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1893 {
1894     if (!(env->pstate & PSTATE_SP)) {
1895         /* Access to SP_EL0 is undefined if it's being used as
1896          * the stack pointer.
1897          */
1898         return CP_ACCESS_TRAP_UNCATEGORIZED;
1899     }
1900     return CP_ACCESS_OK;
1901 }
1902
1903 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1904 {
1905     return env->pstate & PSTATE_SP;
1906 }
1907
1908 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1909 {
1910     update_spsel(env, val);
1911 }
1912
1913 static const ARMCPRegInfo v8_cp_reginfo[] = {
1914     /* Minimal set of EL0-visible registers. This will need to be expanded
1915      * significantly for system emulation of AArch64 CPUs.
1916      */
1917     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1918       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1919       .access = PL0_RW, .type = ARM_CP_NZCV },
1920     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1921       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1922       .type = ARM_CP_NO_MIGRATE,
1923       .access = PL0_RW, .accessfn = aa64_daif_access,
1924       .fieldoffset = offsetof(CPUARMState, daif),
1925       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1926     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1927       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1928       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1929     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1930       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1931       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1932     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1933       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1934       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1935       .readfn = aa64_dczid_read },
1936     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1937       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1938       .access = PL0_W, .type = ARM_CP_DC_ZVA,
1939 #ifndef CONFIG_USER_ONLY
1940       /* Avoid overhead of an access check that always passes in user-mode */
1941       .accessfn = aa64_zva_access,
1942 #endif
1943     },
1944     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1945       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1946       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1947     /* Cache ops: all NOPs since we don't emulate caches */
1948     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1949       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1950       .access = PL1_W, .type = ARM_CP_NOP },
1951     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1952       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1953       .access = PL1_W, .type = ARM_CP_NOP },
1954     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1955       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1956       .access = PL0_W, .type = ARM_CP_NOP,
1957       .accessfn = aa64_cacheop_access },
1958     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1959       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1960       .access = PL1_W, .type = ARM_CP_NOP },
1961     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1962       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1963       .access = PL1_W, .type = ARM_CP_NOP },
1964     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1965       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1966       .access = PL0_W, .type = ARM_CP_NOP,
1967       .accessfn = aa64_cacheop_access },
1968     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1969       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1970       .access = PL1_W, .type = ARM_CP_NOP },
1971     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1972       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1973       .access = PL0_W, .type = ARM_CP_NOP,
1974       .accessfn = aa64_cacheop_access },
1975     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1976       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1977       .access = PL0_W, .type = ARM_CP_NOP,
1978       .accessfn = aa64_cacheop_access },
1979     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1980       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1981       .access = PL1_W, .type = ARM_CP_NOP },
1982     /* TLBI operations */
1983     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1984       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1985       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1986       .writefn = tlbiall_write },
1987     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1988       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1989       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1990       .writefn = tlbi_aa64_va_write },
1991     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1992       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1993       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1994       .writefn = tlbi_aa64_asid_write },
1995     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1996       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1997       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1998       .writefn = tlbi_aa64_vaa_write },
1999     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
2000       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2001       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2002       .writefn = tlbi_aa64_va_write },
2003     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
2004       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2005       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2006       .writefn = tlbi_aa64_vaa_write },
2007     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
2008       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2009       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2010       .writefn = tlbiall_write },
2011     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
2012       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2013       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2014       .writefn = tlbi_aa64_va_write },
2015     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
2016       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2017       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2018       .writefn = tlbi_aa64_asid_write },
2019     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
2020       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2021       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2022       .writefn = tlbi_aa64_vaa_write },
2023     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
2024       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2025       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2026       .writefn = tlbi_aa64_va_write },
2027     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
2028       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2029       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
2030       .writefn = tlbi_aa64_vaa_write },
2031 #ifndef CONFIG_USER_ONLY
2032     /* 64 bit address translation operations */
2033     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
2034       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
2035       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2036     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
2037       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
2038       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2039     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
2040       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
2041       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2042     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
2043       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
2044       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
2045 #endif
2046     /* 32 bit TLB invalidates, Inner Shareable */
2047     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
2048       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2049     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
2050       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2051     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
2052       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2053     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
2054       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2055     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
2056       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2057     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
2058       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2059     /* 32 bit ITLB invalidates */
2060     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
2061       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2062     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
2063       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2064     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
2065       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2066     /* 32 bit DTLB invalidates */
2067     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
2068       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2069     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
2070       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2071     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
2072       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2073     /* 32 bit TLB invalidates */
2074     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2075       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2076     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2077       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2078     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2079       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2080     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2081       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2082     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2083       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2084     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2085       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2086     /* 32 bit cache operations */
2087     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2088       .type = ARM_CP_NOP, .access = PL1_W },
2089     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2090       .type = ARM_CP_NOP, .access = PL1_W },
2091     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2092       .type = ARM_CP_NOP, .access = PL1_W },
2093     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2094       .type = ARM_CP_NOP, .access = PL1_W },
2095     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2096       .type = ARM_CP_NOP, .access = PL1_W },
2097     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2098       .type = ARM_CP_NOP, .access = PL1_W },
2099     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2100       .type = ARM_CP_NOP, .access = PL1_W },
2101     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2102       .type = ARM_CP_NOP, .access = PL1_W },
2103     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2104       .type = ARM_CP_NOP, .access = PL1_W },
2105     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2106       .type = ARM_CP_NOP, .access = PL1_W },
2107     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2108       .type = ARM_CP_NOP, .access = PL1_W },
2109     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2110       .type = ARM_CP_NOP, .access = PL1_W },
2111     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2112       .type = ARM_CP_NOP, .access = PL1_W },
2113     /* MMU Domain access control / MPU write buffer control */
2114     { .name = "DACR", .cp = 15,
2115       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2116       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2117       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2118     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2119       .type = ARM_CP_NO_MIGRATE,
2120       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2121       .access = PL1_RW,
2122       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
2123     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2124       .type = ARM_CP_NO_MIGRATE,
2125       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2126       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2127     /* We rely on the access checks not allowing the guest to write to the
2128      * state field when SPSel indicates that it's being used as the stack
2129      * pointer.
2130      */
2131     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2132       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2133       .access = PL1_RW, .accessfn = sp_el0_access,
2134       .type = ARM_CP_NO_MIGRATE,
2135       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2136     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2137       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2138       .type = ARM_CP_NO_MIGRATE,
2139       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2140     REGINFO_SENTINEL
2141 };
2142
2143 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
2144 static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
2145     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2146       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2147       .access = PL2_RW,
2148       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
2149     REGINFO_SENTINEL
2150 };
2151
2152 static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
2153     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
2154       .type = ARM_CP_NO_MIGRATE,
2155       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
2156       .access = PL2_RW,
2157       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
2158     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
2159       .type = ARM_CP_NO_MIGRATE,
2160       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
2161       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
2162     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
2163       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
2164       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
2165     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
2166       .type = ARM_CP_NO_MIGRATE,
2167       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
2168       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
2169     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
2170       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
2171       .access = PL2_RW, .writefn = vbar_write,
2172       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
2173       .resetvalue = 0 },
2174     REGINFO_SENTINEL
2175 };
2176
2177 static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
2178     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
2179       .type = ARM_CP_NO_MIGRATE,
2180       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
2181       .access = PL3_RW,
2182       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
2183     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
2184       .type = ARM_CP_NO_MIGRATE,
2185       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
2186       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
2187     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
2188       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
2189       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
2190     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
2191       .type = ARM_CP_NO_MIGRATE,
2192       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
2193       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
2194     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
2195       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
2196       .access = PL3_RW, .writefn = vbar_write,
2197       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
2198       .resetvalue = 0 },
2199     REGINFO_SENTINEL
2200 };
2201
2202 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2203                         uint64_t value)
2204 {
2205     ARMCPU *cpu = arm_env_get_cpu(env);
2206
2207     if (raw_read(env, ri) == value) {
2208         /* Skip the TLB flush if nothing actually changed; Linux likes
2209          * to do a lot of pointless SCTLR writes.
2210          */
2211         return;
2212     }
2213
2214     raw_write(env, ri, value);
2215     /* ??? Lots of these bits are not implemented.  */
2216     /* This may enable/disable the MMU, so do a TLB flush.  */
2217     tlb_flush(CPU(cpu), 1);
2218 }
2219
2220 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2221 {
2222     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2223      * but the AArch32 CTR has its own reginfo struct)
2224      */
2225     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2226         return CP_ACCESS_TRAP;
2227     }
2228     return CP_ACCESS_OK;
2229 }
2230
2231 static const ARMCPRegInfo debug_cp_reginfo[] = {
2232     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
2233      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
2234      * unlike DBGDRAR it is never accessible from EL0.
2235      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
2236      * accessor.
2237      */
2238     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2239       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2240     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
2241       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
2242       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2243     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2244       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2245     /* Dummy implementation of monitor debug system control register:
2246      * we don't support debug. (The 32-bit alias is DBGDSCRext.)
2247      */
2248     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
2249       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2250       .access = PL1_RW,
2251       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
2252       .resetvalue = 0 },
2253     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2254     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
2255       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2256       .access = PL1_W, .type = ARM_CP_NOP },
2257     REGINFO_SENTINEL
2258 };
2259
2260 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
2261     /* 64 bit access versions of the (dummy) debug registers */
2262     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
2263       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2264     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
2265       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
2266     REGINFO_SENTINEL
2267 };
2268
2269 static void define_debug_regs(ARMCPU *cpu)
2270 {
2271     /* Define v7 and v8 architectural debug registers.
2272      * These are just dummy implementations for now.
2273      */
2274     int i;
2275     int wrps, brps;
2276     ARMCPRegInfo dbgdidr = {
2277         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
2278         .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
2279     };
2280
2281     brps = extract32(cpu->dbgdidr, 24, 4);
2282     wrps = extract32(cpu->dbgdidr, 28, 4);
2283
2284     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
2285      * of the debug registers such as number of breakpoints;
2286      * check that if they both exist then they agree.
2287      */
2288     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
2289         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
2290         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
2291     }
2292
2293     define_one_arm_cp_reg(cpu, &dbgdidr);
2294     define_arm_cp_regs(cpu, debug_cp_reginfo);
2295
2296     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
2297         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
2298     }
2299
2300     for (i = 0; i < brps + 1; i++) {
2301         ARMCPRegInfo dbgregs[] = {
2302             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
2303               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2304               .access = PL1_RW,
2305               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2306             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
2307               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2308               .access = PL1_RW,
2309               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2310             REGINFO_SENTINEL
2311         };
2312         define_arm_cp_regs(cpu, dbgregs);
2313     }
2314
2315     for (i = 0; i < wrps + 1; i++) {
2316         ARMCPRegInfo dbgregs[] = {
2317             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
2318               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2319               .access = PL1_RW,
2320               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2321             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
2322               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2323               .access = PL1_RW,
2324               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2325                REGINFO_SENTINEL
2326         };
2327         define_arm_cp_regs(cpu, dbgregs);
2328     }
2329 }
2330
2331 void register_cp_regs_for_features(ARMCPU *cpu)
2332 {
2333     /* Register all the coprocessor registers based on feature bits */
2334     CPUARMState *env = &cpu->env;
2335     if (arm_feature(env, ARM_FEATURE_M)) {
2336         /* M profile has no coprocessor registers */
2337         return;
2338     }
2339
2340     define_arm_cp_regs(cpu, cp_reginfo);
2341     if (!arm_feature(env, ARM_FEATURE_V8)) {
2342         /* Must go early as it is full of wildcards that may be
2343          * overridden by later definitions.
2344          */
2345         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2346     }
2347
2348     if (arm_feature(env, ARM_FEATURE_V6)) {
2349         /* The ID registers all have impdef reset values */
2350         ARMCPRegInfo v6_idregs[] = {
2351             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2352               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2353               .access = PL1_R, .type = ARM_CP_CONST,
2354               .resetvalue = cpu->id_pfr0 },
2355             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2356               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2357               .access = PL1_R, .type = ARM_CP_CONST,
2358               .resetvalue = cpu->id_pfr1 },
2359             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2360               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2361               .access = PL1_R, .type = ARM_CP_CONST,
2362               .resetvalue = cpu->id_dfr0 },
2363             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2364               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2365               .access = PL1_R, .type = ARM_CP_CONST,
2366               .resetvalue = cpu->id_afr0 },
2367             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2368               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2369               .access = PL1_R, .type = ARM_CP_CONST,
2370               .resetvalue = cpu->id_mmfr0 },
2371             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2372               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2373               .access = PL1_R, .type = ARM_CP_CONST,
2374               .resetvalue = cpu->id_mmfr1 },
2375             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2376               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2377               .access = PL1_R, .type = ARM_CP_CONST,
2378               .resetvalue = cpu->id_mmfr2 },
2379             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2380               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2381               .access = PL1_R, .type = ARM_CP_CONST,
2382               .resetvalue = cpu->id_mmfr3 },
2383             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2384               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2385               .access = PL1_R, .type = ARM_CP_CONST,
2386               .resetvalue = cpu->id_isar0 },
2387             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2388               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2389               .access = PL1_R, .type = ARM_CP_CONST,
2390               .resetvalue = cpu->id_isar1 },
2391             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2392               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2393               .access = PL1_R, .type = ARM_CP_CONST,
2394               .resetvalue = cpu->id_isar2 },
2395             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2396               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2397               .access = PL1_R, .type = ARM_CP_CONST,
2398               .resetvalue = cpu->id_isar3 },
2399             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2400               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2401               .access = PL1_R, .type = ARM_CP_CONST,
2402               .resetvalue = cpu->id_isar4 },
2403             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2404               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2405               .access = PL1_R, .type = ARM_CP_CONST,
2406               .resetvalue = cpu->id_isar5 },
2407             /* 6..7 are as yet unallocated and must RAZ */
2408             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2409               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2410               .resetvalue = 0 },
2411             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2412               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2413               .resetvalue = 0 },
2414             REGINFO_SENTINEL
2415         };
2416         define_arm_cp_regs(cpu, v6_idregs);
2417         define_arm_cp_regs(cpu, v6_cp_reginfo);
2418     } else {
2419         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2420     }
2421     if (arm_feature(env, ARM_FEATURE_V6K)) {
2422         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2423     }
2424     if (arm_feature(env, ARM_FEATURE_V7)) {
2425         /* v7 performance monitor control register: same implementor
2426          * field as main ID register, and we implement only the cycle
2427          * count register.
2428          */
2429 #ifndef CONFIG_USER_ONLY
2430         ARMCPRegInfo pmcr = {
2431             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2432             .access = PL0_RW,
2433             .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
2434             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
2435             .accessfn = pmreg_access, .writefn = pmcr_write,
2436             .raw_writefn = raw_write,
2437         };
2438         ARMCPRegInfo pmcr64 = {
2439             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
2440             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
2441             .access = PL0_RW, .accessfn = pmreg_access,
2442             .type = ARM_CP_IO,
2443             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2444             .resetvalue = cpu->midr & 0xff000000,
2445             .writefn = pmcr_write, .raw_writefn = raw_write,
2446         };
2447         define_one_arm_cp_reg(cpu, &pmcr);
2448         define_one_arm_cp_reg(cpu, &pmcr64);
2449 #endif
2450         ARMCPRegInfo clidr = {
2451             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2452             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2453             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2454         };
2455         define_one_arm_cp_reg(cpu, &clidr);
2456         define_arm_cp_regs(cpu, v7_cp_reginfo);
2457         define_debug_regs(cpu);
2458     } else {
2459         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2460     }
2461     if (arm_feature(env, ARM_FEATURE_V8)) {
2462         /* AArch64 ID registers, which all have impdef reset values */
2463         ARMCPRegInfo v8_idregs[] = {
2464             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2465               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2466               .access = PL1_R, .type = ARM_CP_CONST,
2467               .resetvalue = cpu->id_aa64pfr0 },
2468             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2469               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2470               .access = PL1_R, .type = ARM_CP_CONST,
2471               .resetvalue = cpu->id_aa64pfr1},
2472             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2473               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2474               .access = PL1_R, .type = ARM_CP_CONST,
2475               /* We mask out the PMUVer field, because we don't currently
2476                * implement the PMU. Not advertising it prevents the guest
2477                * from trying to use it and getting UNDEFs on registers we
2478                * don't implement.
2479                */
2480               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2481             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2482               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2483               .access = PL1_R, .type = ARM_CP_CONST,
2484               .resetvalue = cpu->id_aa64dfr1 },
2485             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2486               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2487               .access = PL1_R, .type = ARM_CP_CONST,
2488               .resetvalue = cpu->id_aa64afr0 },
2489             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2490               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2491               .access = PL1_R, .type = ARM_CP_CONST,
2492               .resetvalue = cpu->id_aa64afr1 },
2493             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2494               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2495               .access = PL1_R, .type = ARM_CP_CONST,
2496               .resetvalue = cpu->id_aa64isar0 },
2497             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2498               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2499               .access = PL1_R, .type = ARM_CP_CONST,
2500               .resetvalue = cpu->id_aa64isar1 },
2501             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2502               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2503               .access = PL1_R, .type = ARM_CP_CONST,
2504               .resetvalue = cpu->id_aa64mmfr0 },
2505             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2506               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2507               .access = PL1_R, .type = ARM_CP_CONST,
2508               .resetvalue = cpu->id_aa64mmfr1 },
2509             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2510               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2511               .access = PL1_R, .type = ARM_CP_CONST,
2512               .resetvalue = cpu->mvfr0 },
2513             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2514               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2515               .access = PL1_R, .type = ARM_CP_CONST,
2516               .resetvalue = cpu->mvfr1 },
2517             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2518               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2519               .access = PL1_R, .type = ARM_CP_CONST,
2520               .resetvalue = cpu->mvfr2 },
2521             REGINFO_SENTINEL
2522         };
2523         ARMCPRegInfo rvbar = {
2524             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2525             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2526             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2527         };
2528         define_one_arm_cp_reg(cpu, &rvbar);
2529         define_arm_cp_regs(cpu, v8_idregs);
2530         define_arm_cp_regs(cpu, v8_cp_reginfo);
2531     }
2532     if (arm_feature(env, ARM_FEATURE_EL2)) {
2533         define_arm_cp_regs(cpu, v8_el2_cp_reginfo);
2534     } else {
2535         /* If EL2 is missing but higher ELs are enabled, we need to
2536          * register the no_el2 reginfos.
2537          */
2538         if (arm_feature(env, ARM_FEATURE_EL3)) {
2539             define_arm_cp_regs(cpu, v8_el3_no_el2_cp_reginfo);
2540         }
2541     }
2542     if (arm_feature(env, ARM_FEATURE_EL3)) {
2543         define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
2544     }
2545     if (arm_feature(env, ARM_FEATURE_MPU)) {
2546         /* These are the MPU registers prior to PMSAv6. Any new
2547          * PMSA core later than the ARM946 will require that we
2548          * implement the PMSAv6 or PMSAv7 registers, which are
2549          * completely different.
2550          */
2551         assert(!arm_feature(env, ARM_FEATURE_V6));
2552         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2553     } else {
2554         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2555     }
2556     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2557         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2558     }
2559     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2560         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2561     }
2562     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2563         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2564     }
2565     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2566         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2567     }
2568     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2569         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2570     }
2571     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2572         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2573     }
2574     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2575         define_arm_cp_regs(cpu, omap_cp_reginfo);
2576     }
2577     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2578         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2579     }
2580     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2581         define_arm_cp_regs(cpu, xscale_cp_reginfo);
2582     }
2583     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2584         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2585     }
2586     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2587         define_arm_cp_regs(cpu, lpae_cp_reginfo);
2588     }
2589     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2590      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2591      * be read-only (ie write causes UNDEF exception).
2592      */
2593     {
2594         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2595             /* Pre-v8 MIDR space.
2596              * Note that the MIDR isn't a simple constant register because
2597              * of the TI925 behaviour where writes to another register can
2598              * cause the MIDR value to change.
2599              *
2600              * Unimplemented registers in the c15 0 0 0 space default to
2601              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2602              * and friends override accordingly.
2603              */
2604             { .name = "MIDR",
2605               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2606               .access = PL1_R, .resetvalue = cpu->midr,
2607               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2608               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2609               .type = ARM_CP_OVERRIDE },
2610             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2611             { .name = "DUMMY",
2612               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2613               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2614             { .name = "DUMMY",
2615               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2616               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2617             { .name = "DUMMY",
2618               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2619               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2620             { .name = "DUMMY",
2621               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2622               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2623             { .name = "DUMMY",
2624               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2625               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2626             REGINFO_SENTINEL
2627         };
2628         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2629             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2630              * variable-MIDR TI925 behaviour. Instead we have a single
2631              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2632              */
2633             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2634               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2635               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2636             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2637               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2638               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2639             REGINFO_SENTINEL
2640         };
2641         ARMCPRegInfo id_cp_reginfo[] = {
2642             /* These are common to v8 and pre-v8 */
2643             { .name = "CTR",
2644               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2645               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2646             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2647               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2648               .access = PL0_R, .accessfn = ctr_el0_access,
2649               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2650             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2651             { .name = "TCMTR",
2652               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2653               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2654             { .name = "TLBTR",
2655               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2656               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2657             REGINFO_SENTINEL
2658         };
2659         ARMCPRegInfo crn0_wi_reginfo = {
2660             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2661             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2662             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2663         };
2664         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2665             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2666             ARMCPRegInfo *r;
2667             /* Register the blanket "writes ignored" value first to cover the
2668              * whole space. Then update the specific ID registers to allow write
2669              * access, so that they ignore writes rather than causing them to
2670              * UNDEF.
2671              */
2672             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2673             for (r = id_pre_v8_midr_cp_reginfo;
2674                  r->type != ARM_CP_SENTINEL; r++) {
2675                 r->access = PL1_RW;
2676             }
2677             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2678                 r->access = PL1_RW;
2679             }
2680         }
2681         if (arm_feature(env, ARM_FEATURE_V8)) {
2682             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2683         } else {
2684             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2685         }
2686         define_arm_cp_regs(cpu, id_cp_reginfo);
2687     }
2688
2689     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2690         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2691     }
2692
2693     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2694         ARMCPRegInfo auxcr = {
2695             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2696             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2697             .access = PL1_RW, .type = ARM_CP_CONST,
2698             .resetvalue = cpu->reset_auxcr
2699         };
2700         define_one_arm_cp_reg(cpu, &auxcr);
2701     }
2702
2703     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2704         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2705             /* 32 bit view is [31:18] 0...0 [43:32]. */
2706             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2707                 | extract64(cpu->reset_cbar, 32, 12);
2708             ARMCPRegInfo cbar_reginfo[] = {
2709                 { .name = "CBAR",
2710                   .type = ARM_CP_CONST,
2711                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2712                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
2713                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2714                   .type = ARM_CP_CONST,
2715                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2716                   .access = PL1_R, .resetvalue = cbar32 },
2717                 REGINFO_SENTINEL
2718             };
2719             /* We don't implement a r/w 64 bit CBAR currently */
2720             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2721             define_arm_cp_regs(cpu, cbar_reginfo);
2722         } else {
2723             ARMCPRegInfo cbar = {
2724                 .name = "CBAR",
2725                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2726                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2727                 .fieldoffset = offsetof(CPUARMState,
2728                                         cp15.c15_config_base_address)
2729             };
2730             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2731                 cbar.access = PL1_R;
2732                 cbar.fieldoffset = 0;
2733                 cbar.type = ARM_CP_CONST;
2734             }
2735             define_one_arm_cp_reg(cpu, &cbar);
2736         }
2737     }
2738
2739     /* Generic registers whose values depend on the implementation */
2740     {
2741         ARMCPRegInfo sctlr = {
2742             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2743             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2744             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2745             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2746             .raw_writefn = raw_write,
2747         };
2748         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2749             /* Normally we would always end the TB on an SCTLR write, but Linux
2750              * arch/arm/mach-pxa/sleep.S expects two instructions following
2751              * an MMU enable to execute from cache.  Imitate this behaviour.
2752              */
2753             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2754         }
2755         define_one_arm_cp_reg(cpu, &sctlr);
2756     }
2757 }
2758
2759 ARMCPU *cpu_arm_init(const char *cpu_model)
2760 {
2761     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2762 }
2763
2764 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2765 {
2766     CPUState *cs = CPU(cpu);
2767     CPUARMState *env = &cpu->env;
2768
2769     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2770         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2771                                  aarch64_fpu_gdb_set_reg,
2772                                  34, "aarch64-fpu.xml", 0);
2773     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2774         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2775                                  51, "arm-neon.xml", 0);
2776     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2777         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2778                                  35, "arm-vfp3.xml", 0);
2779     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2780         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2781                                  19, "arm-vfp.xml", 0);
2782     }
2783 }
2784
2785 /* Sort alphabetically by type name, except for "any". */
2786 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2787 {
2788     ObjectClass *class_a = (ObjectClass *)a;
2789     ObjectClass *class_b = (ObjectClass *)b;
2790     const char *name_a, *name_b;
2791
2792     name_a = object_class_get_name(class_a);
2793     name_b = object_class_get_name(class_b);
2794     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2795         return 1;
2796     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2797         return -1;
2798     } else {
2799         return strcmp(name_a, name_b);
2800     }
2801 }
2802
2803 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2804 {
2805     ObjectClass *oc = data;
2806     CPUListState *s = user_data;
2807     const char *typename;
2808     char *name;
2809
2810     typename = object_class_get_name(oc);
2811     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2812     (*s->cpu_fprintf)(s->file, "  %s\n",
2813                       name);
2814     g_free(name);
2815 }
2816
2817 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2818 {
2819     CPUListState s = {
2820         .file = f,
2821         .cpu_fprintf = cpu_fprintf,
2822     };
2823     GSList *list;
2824
2825     list = object_class_get_list(TYPE_ARM_CPU, false);
2826     list = g_slist_sort(list, arm_cpu_list_compare);
2827     (*cpu_fprintf)(f, "Available CPUs:\n");
2828     g_slist_foreach(list, arm_cpu_list_entry, &s);
2829     g_slist_free(list);
2830 #ifdef CONFIG_KVM
2831     /* The 'host' CPU type is dynamically registered only if KVM is
2832      * enabled, so we have to special-case it here:
2833      */
2834     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2835 #endif
2836 }
2837
2838 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2839 {
2840     ObjectClass *oc = data;
2841     CpuDefinitionInfoList **cpu_list = user_data;
2842     CpuDefinitionInfoList *entry;
2843     CpuDefinitionInfo *info;
2844     const char *typename;
2845
2846     typename = object_class_get_name(oc);
2847     info = g_malloc0(sizeof(*info));
2848     info->name = g_strndup(typename,
2849                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2850
2851     entry = g_malloc0(sizeof(*entry));
2852     entry->value = info;
2853     entry->next = *cpu_list;
2854     *cpu_list = entry;
2855 }
2856
2857 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2858 {
2859     CpuDefinitionInfoList *cpu_list = NULL;
2860     GSList *list;
2861
2862     list = object_class_get_list(TYPE_ARM_CPU, false);
2863     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2864     g_slist_free(list);
2865
2866     return cpu_list;
2867 }
2868
2869 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2870                                    void *opaque, int state,
2871                                    int crm, int opc1, int opc2)
2872 {
2873     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2874      * add a single reginfo struct to the hash table.
2875      */
2876     uint32_t *key = g_new(uint32_t, 1);
2877     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2878     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2879     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2880         /* The AArch32 view of a shared register sees the lower 32 bits
2881          * of a 64 bit backing field. It is not migratable as the AArch64
2882          * view handles that. AArch64 also handles reset.
2883          * We assume it is a cp15 register if the .cp field is left unset.
2884          */
2885         if (r2->cp == 0) {
2886             r2->cp = 15;
2887         }
2888         r2->type |= ARM_CP_NO_MIGRATE;
2889         r2->resetfn = arm_cp_reset_ignore;
2890 #ifdef HOST_WORDS_BIGENDIAN
2891         if (r2->fieldoffset) {
2892             r2->fieldoffset += sizeof(uint32_t);
2893         }
2894 #endif
2895     }
2896     if (state == ARM_CP_STATE_AA64) {
2897         /* To allow abbreviation of ARMCPRegInfo
2898          * definitions, we treat cp == 0 as equivalent to
2899          * the value for "standard guest-visible sysreg".
2900          * STATE_BOTH definitions are also always "standard
2901          * sysreg" in their AArch64 view (the .cp value may
2902          * be non-zero for the benefit of the AArch32 view).
2903          */
2904         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
2905             r2->cp = CP_REG_ARM64_SYSREG_CP;
2906         }
2907         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2908                                   r2->opc0, opc1, opc2);
2909     } else {
2910         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2911     }
2912     if (opaque) {
2913         r2->opaque = opaque;
2914     }
2915     /* reginfo passed to helpers is correct for the actual access,
2916      * and is never ARM_CP_STATE_BOTH:
2917      */
2918     r2->state = state;
2919     /* Make sure reginfo passed to helpers for wildcarded regs
2920      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2921      */
2922     r2->crm = crm;
2923     r2->opc1 = opc1;
2924     r2->opc2 = opc2;
2925     /* By convention, for wildcarded registers only the first
2926      * entry is used for migration; the others are marked as
2927      * NO_MIGRATE so we don't try to transfer the register
2928      * multiple times. Special registers (ie NOP/WFI) are
2929      * never migratable.
2930      */
2931     if ((r->type & ARM_CP_SPECIAL) ||
2932         ((r->crm == CP_ANY) && crm != 0) ||
2933         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2934         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2935         r2->type |= ARM_CP_NO_MIGRATE;
2936     }
2937
2938     /* Overriding of an existing definition must be explicitly
2939      * requested.
2940      */
2941     if (!(r->type & ARM_CP_OVERRIDE)) {
2942         ARMCPRegInfo *oldreg;
2943         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2944         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2945             fprintf(stderr, "Register redefined: cp=%d %d bit "
2946                     "crn=%d crm=%d opc1=%d opc2=%d, "
2947                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2948                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2949                     oldreg->name, r2->name);
2950             g_assert_not_reached();
2951         }
2952     }
2953     g_hash_table_insert(cpu->cp_regs, key, r2);
2954 }
2955
2956
2957 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2958                                        const ARMCPRegInfo *r, void *opaque)
2959 {
2960     /* Define implementations of coprocessor registers.
2961      * We store these in a hashtable because typically
2962      * there are less than 150 registers in a space which
2963      * is 16*16*16*8*8 = 262144 in size.
2964      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2965      * If a register is defined twice then the second definition is
2966      * used, so this can be used to define some generic registers and
2967      * then override them with implementation specific variations.
2968      * At least one of the original and the second definition should
2969      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2970      * against accidental use.
2971      *
2972      * The state field defines whether the register is to be
2973      * visible in the AArch32 or AArch64 execution state. If the
2974      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2975      * reginfo structure for the AArch32 view, which sees the lower
2976      * 32 bits of the 64 bit register.
2977      *
2978      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2979      * be wildcarded. AArch64 registers are always considered to be 64
2980      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2981      * the register, if any.
2982      */
2983     int crm, opc1, opc2, state;
2984     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2985     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2986     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2987     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2988     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2989     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2990     /* 64 bit registers have only CRm and Opc1 fields */
2991     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2992     /* op0 only exists in the AArch64 encodings */
2993     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2994     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2995     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2996     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2997      * encodes a minimum access level for the register. We roll this
2998      * runtime check into our general permission check code, so check
2999      * here that the reginfo's specified permissions are strict enough
3000      * to encompass the generic architectural permission check.
3001      */
3002     if (r->state != ARM_CP_STATE_AA32) {
3003         int mask = 0;
3004         switch (r->opc1) {
3005         case 0: case 1: case 2:
3006             /* min_EL EL1 */
3007             mask = PL1_RW;
3008             break;
3009         case 3:
3010             /* min_EL EL0 */
3011             mask = PL0_RW;
3012             break;
3013         case 4:
3014             /* min_EL EL2 */
3015             mask = PL2_RW;
3016             break;
3017         case 5:
3018             /* unallocated encoding, so not possible */
3019             assert(false);
3020             break;
3021         case 6:
3022             /* min_EL EL3 */
3023             mask = PL3_RW;
3024             break;
3025         case 7:
3026             /* min_EL EL1, secure mode only (we don't check the latter) */
3027             mask = PL1_RW;
3028             break;
3029         default:
3030             /* broken reginfo with out-of-range opc1 */
3031             assert(false);
3032             break;
3033         }
3034         /* assert our permissions are not too lax (stricter is fine) */
3035         assert((r->access & ~mask) == 0);
3036     }
3037
3038     /* Check that the register definition has enough info to handle
3039      * reads and writes if they are permitted.
3040      */
3041     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
3042         if (r->access & PL3_R) {
3043             assert(r->fieldoffset || r->readfn);
3044         }
3045         if (r->access & PL3_W) {
3046             assert(r->fieldoffset || r->writefn);
3047         }
3048     }
3049     /* Bad type field probably means missing sentinel at end of reg list */
3050     assert(cptype_valid(r->type));
3051     for (crm = crmmin; crm <= crmmax; crm++) {
3052         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
3053             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
3054                 for (state = ARM_CP_STATE_AA32;
3055                      state <= ARM_CP_STATE_AA64; state++) {
3056                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
3057                         continue;
3058                     }
3059                     add_cpreg_to_hashtable(cpu, r, opaque, state,
3060                                            crm, opc1, opc2);
3061                 }
3062             }
3063         }
3064     }
3065 }
3066
3067 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
3068                                     const ARMCPRegInfo *regs, void *opaque)
3069 {
3070     /* Define a whole list of registers */
3071     const ARMCPRegInfo *r;
3072     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
3073         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
3074     }
3075 }
3076
3077 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
3078 {
3079     return g_hash_table_lookup(cpregs, &encoded_cp);
3080 }
3081
3082 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
3083                          uint64_t value)
3084 {
3085     /* Helper coprocessor write function for write-ignore registers */
3086 }
3087
3088 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
3089 {
3090     /* Helper coprocessor write function for read-as-zero registers */
3091     return 0;
3092 }
3093
3094 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
3095 {
3096     /* Helper coprocessor reset function for do-nothing-on-reset registers */
3097 }
3098
3099 static int bad_mode_switch(CPUARMState *env, int mode)
3100 {
3101     /* Return true if it is not valid for us to switch to
3102      * this CPU mode (ie all the UNPREDICTABLE cases in
3103      * the ARM ARM CPSRWriteByInstr pseudocode).
3104      */
3105     switch (mode) {
3106     case ARM_CPU_MODE_USR:
3107     case ARM_CPU_MODE_SYS:
3108     case ARM_CPU_MODE_SVC:
3109     case ARM_CPU_MODE_ABT:
3110     case ARM_CPU_MODE_UND:
3111     case ARM_CPU_MODE_IRQ:
3112     case ARM_CPU_MODE_FIQ:
3113         return 0;
3114     default:
3115         return 1;
3116     }
3117 }
3118
3119 uint32_t cpsr_read(CPUARMState *env)
3120 {
3121     int ZF;
3122     ZF = (env->ZF == 0);
3123     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
3124         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
3125         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
3126         | ((env->condexec_bits & 0xfc) << 8)
3127         | (env->GE << 16) | (env->daif & CPSR_AIF);
3128 }
3129
3130 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
3131 {
3132     if (mask & CPSR_NZCV) {
3133         env->ZF = (~val) & CPSR_Z;
3134         env->NF = val;
3135         env->CF = (val >> 29) & 1;
3136         env->VF = (val << 3) & 0x80000000;
3137     }
3138     if (mask & CPSR_Q)
3139         env->QF = ((val & CPSR_Q) != 0);
3140     if (mask & CPSR_T)
3141         env->thumb = ((val & CPSR_T) != 0);
3142     if (mask & CPSR_IT_0_1) {
3143         env->condexec_bits &= ~3;
3144         env->condexec_bits |= (val >> 25) & 3;
3145     }
3146     if (mask & CPSR_IT_2_7) {
3147         env->condexec_bits &= 3;
3148         env->condexec_bits |= (val >> 8) & 0xfc;
3149     }
3150     if (mask & CPSR_GE) {
3151         env->GE = (val >> 16) & 0xf;
3152     }
3153
3154     env->daif &= ~(CPSR_AIF & mask);
3155     env->daif |= val & CPSR_AIF & mask;
3156
3157     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
3158         if (bad_mode_switch(env, val & CPSR_M)) {
3159             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
3160              * We choose to ignore the attempt and leave the CPSR M field
3161              * untouched.
3162              */
3163             mask &= ~CPSR_M;
3164         } else {
3165             switch_mode(env, val & CPSR_M);
3166         }
3167     }
3168     mask &= ~CACHED_CPSR_BITS;
3169     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
3170 }
3171
3172 /* Sign/zero extend */
3173 uint32_t HELPER(sxtb16)(uint32_t x)
3174 {
3175     uint32_t res;
3176     res = (uint16_t)(int8_t)x;
3177     res |= (uint32_t)(int8_t)(x >> 16) << 16;
3178     return res;
3179 }
3180
3181 uint32_t HELPER(uxtb16)(uint32_t x)
3182 {
3183     uint32_t res;
3184     res = (uint16_t)(uint8_t)x;
3185     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
3186     return res;
3187 }
3188
3189 uint32_t HELPER(clz)(uint32_t x)
3190 {
3191     return clz32(x);
3192 }
3193
3194 int32_t HELPER(sdiv)(int32_t num, int32_t den)
3195 {
3196     if (den == 0)
3197       return 0;
3198     if (num == INT_MIN && den == -1)
3199       return INT_MIN;
3200     return num / den;
3201 }
3202
3203 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
3204 {
3205     if (den == 0)
3206       return 0;
3207     return num / den;
3208 }
3209
3210 uint32_t HELPER(rbit)(uint32_t x)
3211 {
3212     x =  ((x & 0xff000000) >> 24)
3213        | ((x & 0x00ff0000) >> 8)
3214        | ((x & 0x0000ff00) << 8)
3215        | ((x & 0x000000ff) << 24);
3216     x =  ((x & 0xf0f0f0f0) >> 4)
3217        | ((x & 0x0f0f0f0f) << 4);
3218     x =  ((x & 0x88888888) >> 3)
3219        | ((x & 0x44444444) >> 1)
3220        | ((x & 0x22222222) << 1)
3221        | ((x & 0x11111111) << 3);
3222     return x;
3223 }
3224
3225 #if defined(CONFIG_USER_ONLY)
3226
3227 void arm_cpu_do_interrupt(CPUState *cs)
3228 {
3229     cs->exception_index = -1;
3230 }
3231
3232 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3233                              int mmu_idx)
3234 {
3235     ARMCPU *cpu = ARM_CPU(cs);
3236     CPUARMState *env = &cpu->env;
3237
3238     env->exception.vaddress = address;
3239     if (rw == 2) {
3240         cs->exception_index = EXCP_PREFETCH_ABORT;
3241     } else {
3242         cs->exception_index = EXCP_DATA_ABORT;
3243     }
3244     return 1;
3245 }
3246
3247 /* These should probably raise undefined insn exceptions.  */
3248 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3249 {
3250     ARMCPU *cpu = arm_env_get_cpu(env);
3251
3252     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3253 }
3254
3255 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3256 {
3257     ARMCPU *cpu = arm_env_get_cpu(env);
3258
3259     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3260     return 0;
3261 }
3262
3263 void switch_mode(CPUARMState *env, int mode)
3264 {
3265     ARMCPU *cpu = arm_env_get_cpu(env);
3266
3267     if (mode != ARM_CPU_MODE_USR) {
3268         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3269     }
3270 }
3271
3272 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3273 {
3274     ARMCPU *cpu = arm_env_get_cpu(env);
3275
3276     cpu_abort(CPU(cpu), "banked r13 write\n");
3277 }
3278
3279 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3280 {
3281     ARMCPU *cpu = arm_env_get_cpu(env);
3282
3283     cpu_abort(CPU(cpu), "banked r13 read\n");
3284     return 0;
3285 }
3286
3287 #else
3288
3289 /* Map CPU modes onto saved register banks.  */
3290 int bank_number(int mode)
3291 {
3292     switch (mode) {
3293     case ARM_CPU_MODE_USR:
3294     case ARM_CPU_MODE_SYS:
3295         return 0;
3296     case ARM_CPU_MODE_SVC:
3297         return 1;
3298     case ARM_CPU_MODE_ABT:
3299         return 2;
3300     case ARM_CPU_MODE_UND:
3301         return 3;
3302     case ARM_CPU_MODE_IRQ:
3303         return 4;
3304     case ARM_CPU_MODE_FIQ:
3305         return 5;
3306     case ARM_CPU_MODE_HYP:
3307         return 6;
3308     case ARM_CPU_MODE_MON:
3309         return 7;
3310     }
3311     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3312 }
3313
3314 void switch_mode(CPUARMState *env, int mode)
3315 {
3316     int old_mode;
3317     int i;
3318
3319     old_mode = env->uncached_cpsr & CPSR_M;
3320     if (mode == old_mode)
3321         return;
3322
3323     if (old_mode == ARM_CPU_MODE_FIQ) {
3324         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3325         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3326     } else if (mode == ARM_CPU_MODE_FIQ) {
3327         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3328         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3329     }
3330
3331     i = bank_number(old_mode);
3332     env->banked_r13[i] = env->regs[13];
3333     env->banked_r14[i] = env->regs[14];
3334     env->banked_spsr[i] = env->spsr;
3335
3336     i = bank_number(mode);
3337     env->regs[13] = env->banked_r13[i];
3338     env->regs[14] = env->banked_r14[i];
3339     env->spsr = env->banked_spsr[i];
3340 }
3341
3342 static void v7m_push(CPUARMState *env, uint32_t val)
3343 {
3344     CPUState *cs = CPU(arm_env_get_cpu(env));
3345
3346     env->regs[13] -= 4;
3347     stl_phys(cs->as, env->regs[13], val);
3348 }
3349
3350 static uint32_t v7m_pop(CPUARMState *env)
3351 {
3352     CPUState *cs = CPU(arm_env_get_cpu(env));
3353     uint32_t val;
3354
3355     val = ldl_phys(cs->as, env->regs[13]);
3356     env->regs[13] += 4;
3357     return val;
3358 }
3359
3360 /* Switch to V7M main or process stack pointer.  */
3361 static void switch_v7m_sp(CPUARMState *env, int process)
3362 {
3363     uint32_t tmp;
3364     if (env->v7m.current_sp != process) {
3365         tmp = env->v7m.other_sp;
3366         env->v7m.other_sp = env->regs[13];
3367         env->regs[13] = tmp;
3368         env->v7m.current_sp = process;
3369     }
3370 }
3371
3372 static void do_v7m_exception_exit(CPUARMState *env)
3373 {
3374     uint32_t type;
3375     uint32_t xpsr;
3376
3377     type = env->regs[15];
3378     if (env->v7m.exception != 0)
3379         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3380
3381     /* Switch to the target stack.  */
3382     switch_v7m_sp(env, (type & 4) != 0);
3383     /* Pop registers.  */
3384     env->regs[0] = v7m_pop(env);
3385     env->regs[1] = v7m_pop(env);
3386     env->regs[2] = v7m_pop(env);
3387     env->regs[3] = v7m_pop(env);
3388     env->regs[12] = v7m_pop(env);
3389     env->regs[14] = v7m_pop(env);
3390     env->regs[15] = v7m_pop(env);
3391     xpsr = v7m_pop(env);
3392     xpsr_write(env, xpsr, 0xfffffdff);
3393     /* Undo stack alignment.  */
3394     if (xpsr & 0x200)
3395         env->regs[13] |= 4;
3396     /* ??? The exception return type specifies Thread/Handler mode.  However
3397        this is also implied by the xPSR value. Not sure what to do
3398        if there is a mismatch.  */
3399     /* ??? Likewise for mismatches between the CONTROL register and the stack
3400        pointer.  */
3401 }
3402
3403 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3404 {
3405     ARMCPU *cpu = ARM_CPU(cs);
3406     CPUARMState *env = &cpu->env;
3407     uint32_t xpsr = xpsr_read(env);
3408     uint32_t lr;
3409     uint32_t addr;
3410
3411     arm_log_exception(cs->exception_index);
3412
3413     lr = 0xfffffff1;
3414     if (env->v7m.current_sp)
3415         lr |= 4;
3416     if (env->v7m.exception == 0)
3417         lr |= 8;
3418
3419     /* For exceptions we just mark as pending on the NVIC, and let that
3420        handle it.  */
3421     /* TODO: Need to escalate if the current priority is higher than the
3422        one we're raising.  */
3423     switch (cs->exception_index) {
3424     case EXCP_UDEF:
3425         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3426         return;
3427     case EXCP_SWI:
3428         /* The PC already points to the next instruction.  */
3429         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3430         return;
3431     case EXCP_PREFETCH_ABORT:
3432     case EXCP_DATA_ABORT:
3433         /* TODO: if we implemented the MPU registers, this is where we
3434          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3435          */
3436         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3437         return;
3438     case EXCP_BKPT:
3439         if (semihosting_enabled) {
3440             int nr;
3441             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3442             if (nr == 0xab) {
3443                 env->regs[15] += 2;
3444                 env->regs[0] = do_arm_semihosting(env);
3445                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3446                 return;
3447             }
3448         }
3449         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3450         return;
3451     case EXCP_IRQ:
3452         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3453         break;
3454     case EXCP_EXCEPTION_EXIT:
3455         do_v7m_exception_exit(env);
3456         return;
3457     default:
3458         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3459         return; /* Never happens.  Keep compiler happy.  */
3460     }
3461
3462     /* Align stack pointer.  */
3463     /* ??? Should only do this if Configuration Control Register
3464        STACKALIGN bit is set.  */
3465     if (env->regs[13] & 4) {
3466         env->regs[13] -= 4;
3467         xpsr |= 0x200;
3468     }
3469     /* Switch to the handler mode.  */
3470     v7m_push(env, xpsr);
3471     v7m_push(env, env->regs[15]);
3472     v7m_push(env, env->regs[14]);
3473     v7m_push(env, env->regs[12]);
3474     v7m_push(env, env->regs[3]);
3475     v7m_push(env, env->regs[2]);
3476     v7m_push(env, env->regs[1]);
3477     v7m_push(env, env->regs[0]);
3478     switch_v7m_sp(env, 0);
3479     /* Clear IT bits */
3480     env->condexec_bits = 0;
3481     env->regs[14] = lr;
3482     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3483     env->regs[15] = addr & 0xfffffffe;
3484     env->thumb = addr & 1;
3485 }
3486
3487 /* Handle a CPU exception.  */
3488 void arm_cpu_do_interrupt(CPUState *cs)
3489 {
3490     ARMCPU *cpu = ARM_CPU(cs);
3491     CPUARMState *env = &cpu->env;
3492     uint32_t addr;
3493     uint32_t mask;
3494     int new_mode;
3495     uint32_t offset;
3496
3497     assert(!IS_M(env));
3498
3499     arm_log_exception(cs->exception_index);
3500
3501     /* TODO: Vectored interrupt controller.  */
3502     switch (cs->exception_index) {
3503     case EXCP_UDEF:
3504         new_mode = ARM_CPU_MODE_UND;
3505         addr = 0x04;
3506         mask = CPSR_I;
3507         if (env->thumb)
3508             offset = 2;
3509         else
3510             offset = 4;
3511         break;
3512     case EXCP_SWI:
3513         if (semihosting_enabled) {
3514             /* Check for semihosting interrupt.  */
3515             if (env->thumb) {
3516                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3517                     & 0xff;
3518             } else {
3519                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3520                     & 0xffffff;
3521             }
3522             /* Only intercept calls from privileged modes, to provide some
3523                semblance of security.  */
3524             if (((mask == 0x123456 && !env->thumb)
3525                     || (mask == 0xab && env->thumb))
3526                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3527                 env->regs[0] = do_arm_semihosting(env);
3528                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3529                 return;
3530             }
3531         }
3532         new_mode = ARM_CPU_MODE_SVC;
3533         addr = 0x08;
3534         mask = CPSR_I;
3535         /* The PC already points to the next instruction.  */
3536         offset = 0;
3537         break;
3538     case EXCP_BKPT:
3539         /* See if this is a semihosting syscall.  */
3540         if (env->thumb && semihosting_enabled) {
3541             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3542             if (mask == 0xab
3543                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3544                 env->regs[15] += 2;
3545                 env->regs[0] = do_arm_semihosting(env);
3546                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3547                 return;
3548             }
3549         }
3550         env->exception.fsr = 2;
3551         /* Fall through to prefetch abort.  */
3552     case EXCP_PREFETCH_ABORT:
3553         env->cp15.ifsr_el2 = env->exception.fsr;
3554         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
3555                                         env->exception.vaddress);
3556         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3557                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3558         new_mode = ARM_CPU_MODE_ABT;
3559         addr = 0x0c;
3560         mask = CPSR_A | CPSR_I;
3561         offset = 4;
3562         break;
3563     case EXCP_DATA_ABORT:
3564         env->cp15.esr_el[1] = env->exception.fsr;
3565         env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
3566                                         env->exception.vaddress);
3567         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3568                       (uint32_t)env->cp15.esr_el[1],
3569                       (uint32_t)env->exception.vaddress);
3570         new_mode = ARM_CPU_MODE_ABT;
3571         addr = 0x10;
3572         mask = CPSR_A | CPSR_I;
3573         offset = 8;
3574         break;
3575     case EXCP_IRQ:
3576         new_mode = ARM_CPU_MODE_IRQ;
3577         addr = 0x18;
3578         /* Disable IRQ and imprecise data aborts.  */
3579         mask = CPSR_A | CPSR_I;
3580         offset = 4;
3581         break;
3582     case EXCP_FIQ:
3583         new_mode = ARM_CPU_MODE_FIQ;
3584         addr = 0x1c;
3585         /* Disable FIQ, IRQ and imprecise data aborts.  */
3586         mask = CPSR_A | CPSR_I | CPSR_F;
3587         offset = 4;
3588         break;
3589     default:
3590         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3591         return; /* Never happens.  Keep compiler happy.  */
3592     }
3593     /* High vectors.  */
3594     if (env->cp15.c1_sys & SCTLR_V) {
3595         /* when enabled, base address cannot be remapped.  */
3596         addr += 0xffff0000;
3597     } else {
3598         /* ARM v7 architectures provide a vector base address register to remap
3599          * the interrupt vector table.
3600          * This register is only followed in non-monitor mode, and has a secure
3601          * and un-secure copy. Since the cpu is always in a un-secure operation
3602          * and is never in monitor mode this feature is always active.
3603          * Note: only bits 31:5 are valid.
3604          */
3605         addr += env->cp15.vbar_el[1];
3606     }
3607     switch_mode (env, new_mode);
3608     /* For exceptions taken to AArch32 we must clear the SS bit in both
3609      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
3610      */
3611     env->uncached_cpsr &= ~PSTATE_SS;
3612     env->spsr = cpsr_read(env);
3613     /* Clear IT bits.  */
3614     env->condexec_bits = 0;
3615     /* Switch to the new mode, and to the correct instruction set.  */
3616     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3617     env->daif |= mask;
3618     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3619      * and we should just guard the thumb mode on V4 */
3620     if (arm_feature(env, ARM_FEATURE_V4T)) {
3621         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3622     }
3623     env->regs[14] = env->regs[15] + offset;
3624     env->regs[15] = addr;
3625     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3626 }
3627
3628 /* Check section/page access permissions.
3629    Returns the page protection flags, or zero if the access is not
3630    permitted.  */
3631 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3632                            int access_type, int is_user)
3633 {
3634   int prot_ro;
3635
3636   if (domain_prot == 3) {
3637     return PAGE_READ | PAGE_WRITE;
3638   }
3639
3640   if (access_type == 1)
3641       prot_ro = 0;
3642   else
3643       prot_ro = PAGE_READ;
3644
3645   switch (ap) {
3646   case 0:
3647       if (arm_feature(env, ARM_FEATURE_V7)) {
3648           return 0;
3649       }
3650       if (access_type == 1)
3651           return 0;
3652       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3653       case SCTLR_S:
3654           return is_user ? 0 : PAGE_READ;
3655       case SCTLR_R:
3656           return PAGE_READ;
3657       default:
3658           return 0;
3659       }
3660   case 1:
3661       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3662   case 2:
3663       if (is_user)
3664           return prot_ro;
3665       else
3666           return PAGE_READ | PAGE_WRITE;
3667   case 3:
3668       return PAGE_READ | PAGE_WRITE;
3669   case 4: /* Reserved.  */
3670       return 0;
3671   case 5:
3672       return is_user ? 0 : prot_ro;
3673   case 6:
3674       return prot_ro;
3675   case 7:
3676       if (!arm_feature (env, ARM_FEATURE_V6K))
3677           return 0;
3678       return prot_ro;
3679   default:
3680       abort();
3681   }
3682 }
3683
3684 static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
3685                                          uint32_t address)
3686 {
3687     if (address & env->cp15.c2_mask) {
3688         if ((env->cp15.c2_control & TTBCR_PD1)) {
3689             /* Translation table walk disabled for TTBR1 */
3690             return false;
3691         }
3692         *table = env->cp15.ttbr1_el1 & 0xffffc000;
3693     } else {
3694         if ((env->cp15.c2_control & TTBCR_PD0)) {
3695             /* Translation table walk disabled for TTBR0 */
3696             return false;
3697         }
3698         *table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3699     }
3700     *table |= (address >> 18) & 0x3ffc;
3701     return true;
3702 }
3703
3704 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3705                             int is_user, hwaddr *phys_ptr,
3706                             int *prot, target_ulong *page_size)
3707 {
3708     CPUState *cs = CPU(arm_env_get_cpu(env));
3709     int code;
3710     uint32_t table;
3711     uint32_t desc;
3712     int type;
3713     int ap;
3714     int domain = 0;
3715     int domain_prot;
3716     hwaddr phys_addr;
3717
3718     /* Pagetable walk.  */
3719     /* Lookup l1 descriptor.  */
3720     if (!get_level1_table_address(env, &table, address)) {
3721         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3722         code = 5;
3723         goto do_fault;
3724     }
3725     desc = ldl_phys(cs->as, table);
3726     type = (desc & 3);
3727     domain = (desc >> 5) & 0x0f;
3728     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3729     if (type == 0) {
3730         /* Section translation fault.  */
3731         code = 5;
3732         goto do_fault;
3733     }
3734     if (domain_prot == 0 || domain_prot == 2) {
3735         if (type == 2)
3736             code = 9; /* Section domain fault.  */
3737         else
3738             code = 11; /* Page domain fault.  */
3739         goto do_fault;
3740     }
3741     if (type == 2) {
3742         /* 1Mb section.  */
3743         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3744         ap = (desc >> 10) & 3;
3745         code = 13;
3746         *page_size = 1024 * 1024;
3747     } else {
3748         /* Lookup l2 entry.  */
3749         if (type == 1) {
3750             /* Coarse pagetable.  */
3751             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3752         } else {
3753             /* Fine pagetable.  */
3754             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3755         }
3756         desc = ldl_phys(cs->as, table);
3757         switch (desc & 3) {
3758         case 0: /* Page translation fault.  */
3759             code = 7;
3760             goto do_fault;
3761         case 1: /* 64k page.  */
3762             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3763             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3764             *page_size = 0x10000;
3765             break;
3766         case 2: /* 4k page.  */
3767             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3768             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3769             *page_size = 0x1000;
3770             break;
3771         case 3: /* 1k page.  */
3772             if (type == 1) {
3773                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3774                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3775                 } else {
3776                     /* Page translation fault.  */
3777                     code = 7;
3778                     goto do_fault;
3779                 }
3780             } else {
3781                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3782             }
3783             ap = (desc >> 4) & 3;
3784             *page_size = 0x400;
3785             break;
3786         default:
3787             /* Never happens, but compiler isn't smart enough to tell.  */
3788             abort();
3789         }
3790         code = 15;
3791     }
3792     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3793     if (!*prot) {
3794         /* Access permission fault.  */
3795         goto do_fault;
3796     }
3797     *prot |= PAGE_EXEC;
3798     *phys_ptr = phys_addr;
3799     return 0;
3800 do_fault:
3801     return code | (domain << 4);
3802 }
3803
3804 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3805                             int is_user, hwaddr *phys_ptr,
3806                             int *prot, target_ulong *page_size)
3807 {
3808     CPUState *cs = CPU(arm_env_get_cpu(env));
3809     int code;
3810     uint32_t table;
3811     uint32_t desc;
3812     uint32_t xn;
3813     uint32_t pxn = 0;
3814     int type;
3815     int ap;
3816     int domain = 0;
3817     int domain_prot;
3818     hwaddr phys_addr;
3819
3820     /* Pagetable walk.  */
3821     /* Lookup l1 descriptor.  */
3822     if (!get_level1_table_address(env, &table, address)) {
3823         /* Section translation fault if page walk is disabled by PD0 or PD1 */
3824         code = 5;
3825         goto do_fault;
3826     }
3827     desc = ldl_phys(cs->as, table);
3828     type = (desc & 3);
3829     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3830         /* Section translation fault, or attempt to use the encoding
3831          * which is Reserved on implementations without PXN.
3832          */
3833         code = 5;
3834         goto do_fault;
3835     }
3836     if ((type == 1) || !(desc & (1 << 18))) {
3837         /* Page or Section.  */
3838         domain = (desc >> 5) & 0x0f;
3839     }
3840     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3841     if (domain_prot == 0 || domain_prot == 2) {
3842         if (type != 1) {
3843             code = 9; /* Section domain fault.  */
3844         } else {
3845             code = 11; /* Page domain fault.  */
3846         }
3847         goto do_fault;
3848     }
3849     if (type != 1) {
3850         if (desc & (1 << 18)) {
3851             /* Supersection.  */
3852             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3853             *page_size = 0x1000000;
3854         } else {
3855             /* Section.  */
3856             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3857             *page_size = 0x100000;
3858         }
3859         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3860         xn = desc & (1 << 4);
3861         pxn = desc & 1;
3862         code = 13;
3863     } else {
3864         if (arm_feature(env, ARM_FEATURE_PXN)) {
3865             pxn = (desc >> 2) & 1;
3866         }
3867         /* Lookup l2 entry.  */
3868         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3869         desc = ldl_phys(cs->as, table);
3870         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3871         switch (desc & 3) {
3872         case 0: /* Page translation fault.  */
3873             code = 7;
3874             goto do_fault;
3875         case 1: /* 64k page.  */
3876             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3877             xn = desc & (1 << 15);
3878             *page_size = 0x10000;
3879             break;
3880         case 2: case 3: /* 4k page.  */
3881             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3882             xn = desc & 1;
3883             *page_size = 0x1000;
3884             break;
3885         default:
3886             /* Never happens, but compiler isn't smart enough to tell.  */
3887             abort();
3888         }
3889         code = 15;
3890     }
3891     if (domain_prot == 3) {
3892         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3893     } else {
3894         if (pxn && !is_user) {
3895             xn = 1;
3896         }
3897         if (xn && access_type == 2)
3898             goto do_fault;
3899
3900         /* The simplified model uses AP[0] as an access control bit.  */
3901         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3902             /* Access flag fault.  */
3903             code = (code == 15) ? 6 : 3;
3904             goto do_fault;
3905         }
3906         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3907         if (!*prot) {
3908             /* Access permission fault.  */
3909             goto do_fault;
3910         }
3911         if (!xn) {
3912             *prot |= PAGE_EXEC;
3913         }
3914     }
3915     *phys_ptr = phys_addr;
3916     return 0;
3917 do_fault:
3918     return code | (domain << 4);
3919 }
3920
3921 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3922  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3923  */
3924 typedef enum {
3925     translation_fault = 1,
3926     access_fault = 2,
3927     permission_fault = 3,
3928 } MMUFaultType;
3929
3930 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3931                               int access_type, int is_user,
3932                               hwaddr *phys_ptr, int *prot,
3933                               target_ulong *page_size_ptr)
3934 {
3935     CPUState *cs = CPU(arm_env_get_cpu(env));
3936     /* Read an LPAE long-descriptor translation table. */
3937     MMUFaultType fault_type = translation_fault;
3938     uint32_t level = 1;
3939     uint32_t epd;
3940     int32_t tsz;
3941     uint32_t tg;
3942     uint64_t ttbr;
3943     int ttbr_select;
3944     hwaddr descaddr, descmask;
3945     uint32_t tableattrs;
3946     target_ulong page_size;
3947     uint32_t attrs;
3948     int32_t granule_sz = 9;
3949     int32_t va_size = 32;
3950     int32_t tbi = 0;
3951
3952     if (arm_el_is_aa64(env, 1)) {
3953         va_size = 64;
3954         if (extract64(address, 55, 1))
3955             tbi = extract64(env->cp15.c2_control, 38, 1);
3956         else
3957             tbi = extract64(env->cp15.c2_control, 37, 1);
3958         tbi *= 8;
3959     }
3960
3961     /* Determine whether this address is in the region controlled by
3962      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3963      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3964      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3965      */
3966     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3967     if (arm_el_is_aa64(env, 1)) {
3968         t0sz = MIN(t0sz, 39);
3969         t0sz = MAX(t0sz, 16);
3970     }
3971     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3972     if (arm_el_is_aa64(env, 1)) {
3973         t1sz = MIN(t1sz, 39);
3974         t1sz = MAX(t1sz, 16);
3975     }
3976     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3977         /* there is a ttbr0 region and we are in it (high bits all zero) */
3978         ttbr_select = 0;
3979     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3980         /* there is a ttbr1 region and we are in it (high bits all one) */
3981         ttbr_select = 1;
3982     } else if (!t0sz) {
3983         /* ttbr0 region is "everything not in the ttbr1 region" */
3984         ttbr_select = 0;
3985     } else if (!t1sz) {
3986         /* ttbr1 region is "everything not in the ttbr0 region" */
3987         ttbr_select = 1;
3988     } else {
3989         /* in the gap between the two regions, this is a Translation fault */
3990         fault_type = translation_fault;
3991         goto do_fault;
3992     }
3993
3994     /* Note that QEMU ignores shareability and cacheability attributes,
3995      * so we don't need to do anything with the SH, ORGN, IRGN fields
3996      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
3997      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3998      * implement any ASID-like capability so we can ignore it (instead
3999      * we will always flush the TLB any time the ASID is changed).
4000      */
4001     if (ttbr_select == 0) {
4002         ttbr = env->cp15.ttbr0_el1;
4003         epd = extract32(env->cp15.c2_control, 7, 1);
4004         tsz = t0sz;
4005
4006         tg = extract32(env->cp15.c2_control, 14, 2);
4007         if (tg == 1) { /* 64KB pages */
4008             granule_sz = 13;
4009         }
4010         if (tg == 2) { /* 16KB pages */
4011             granule_sz = 11;
4012         }
4013     } else {
4014         ttbr = env->cp15.ttbr1_el1;
4015         epd = extract32(env->cp15.c2_control, 23, 1);
4016         tsz = t1sz;
4017
4018         tg = extract32(env->cp15.c2_control, 30, 2);
4019         if (tg == 3)  { /* 64KB pages */
4020             granule_sz = 13;
4021         }
4022         if (tg == 1) { /* 16KB pages */
4023             granule_sz = 11;
4024         }
4025     }
4026
4027     if (epd) {
4028         /* Translation table walk disabled => Translation fault on TLB miss */
4029         goto do_fault;
4030     }
4031
4032     /* The starting level depends on the virtual address size which can be
4033      * up to 48-bits and the translation granule size.
4034      */
4035     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
4036         level = 0;
4037     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
4038         level = 1;
4039     } else {
4040         level = 2;
4041     }
4042
4043     /* Clear the vaddr bits which aren't part of the within-region address,
4044      * so that we don't have to special case things when calculating the
4045      * first descriptor address.
4046      */
4047     if (tsz) {
4048         address &= (1ULL << (va_size - tsz)) - 1;
4049     }
4050
4051     descmask = (1ULL << (granule_sz + 3)) - 1;
4052
4053     /* Now we can extract the actual base address from the TTBR */
4054     descaddr = extract64(ttbr, 0, 48);
4055     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
4056
4057     tableattrs = 0;
4058     for (;;) {
4059         uint64_t descriptor;
4060
4061         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
4062         descaddr &= ~7ULL;
4063         descriptor = ldq_phys(cs->as, descaddr);
4064         if (!(descriptor & 1) ||
4065             (!(descriptor & 2) && (level == 3))) {
4066             /* Invalid, or the Reserved level 3 encoding */
4067             goto do_fault;
4068         }
4069         descaddr = descriptor & 0xfffffff000ULL;
4070
4071         if ((descriptor & 2) && (level < 3)) {
4072             /* Table entry. The top five bits are attributes which  may
4073              * propagate down through lower levels of the table (and
4074              * which are all arranged so that 0 means "no effect", so
4075              * we can gather them up by ORing in the bits at each level).
4076              */
4077             tableattrs |= extract64(descriptor, 59, 5);
4078             level++;
4079             continue;
4080         }
4081         /* Block entry at level 1 or 2, or page entry at level 3.
4082          * These are basically the same thing, although the number
4083          * of bits we pull in from the vaddr varies.
4084          */
4085         page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
4086         descaddr |= (address & (page_size - 1));
4087         /* Extract attributes from the descriptor and merge with table attrs */
4088         attrs = extract64(descriptor, 2, 10)
4089             | (extract64(descriptor, 52, 12) << 10);
4090         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
4091         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
4092         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
4093          * means "force PL1 access only", which means forcing AP[1] to 0.
4094          */
4095         if (extract32(tableattrs, 2, 1)) {
4096             attrs &= ~(1 << 4);
4097         }
4098         /* Since we're always in the Non-secure state, NSTable is ignored. */
4099         break;
4100     }
4101     /* Here descaddr is the final physical address, and attributes
4102      * are all in attrs.
4103      */
4104     fault_type = access_fault;
4105     if ((attrs & (1 << 8)) == 0) {
4106         /* Access flag */
4107         goto do_fault;
4108     }
4109     fault_type = permission_fault;
4110     if (is_user && !(attrs & (1 << 4))) {
4111         /* Unprivileged access not enabled */
4112         goto do_fault;
4113     }
4114     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4115     if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) ||
4116         (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) ||
4117         (!is_user && (attrs & (1 << 11)))) {
4118         /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally
4119          * treat XN/UXN as UXN for v8.
4120          */
4121         if (access_type == 2) {
4122             goto do_fault;
4123         }
4124         *prot &= ~PAGE_EXEC;
4125     }
4126     if (attrs & (1 << 5)) {
4127         /* Write access forbidden */
4128         if (access_type == 1) {
4129             goto do_fault;
4130         }
4131         *prot &= ~PAGE_WRITE;
4132     }
4133
4134     *phys_ptr = descaddr;
4135     *page_size_ptr = page_size;
4136     return 0;
4137
4138 do_fault:
4139     /* Long-descriptor format IFSR/DFSR value */
4140     return (1 << 9) | (fault_type << 2) | level;
4141 }
4142
4143 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
4144                              int access_type, int is_user,
4145                              hwaddr *phys_ptr, int *prot)
4146 {
4147     int n;
4148     uint32_t mask;
4149     uint32_t base;
4150
4151     *phys_ptr = address;
4152     for (n = 7; n >= 0; n--) {
4153         base = env->cp15.c6_region[n];
4154         if ((base & 1) == 0)
4155             continue;
4156         mask = 1 << ((base >> 1) & 0x1f);
4157         /* Keep this shift separate from the above to avoid an
4158            (undefined) << 32.  */
4159         mask = (mask << 1) - 1;
4160         if (((base ^ address) & ~mask) == 0)
4161             break;
4162     }
4163     if (n < 0)
4164         return 2;
4165
4166     if (access_type == 2) {
4167         mask = env->cp15.pmsav5_insn_ap;
4168     } else {
4169         mask = env->cp15.pmsav5_data_ap;
4170     }
4171     mask = (mask >> (n * 4)) & 0xf;
4172     switch (mask) {
4173     case 0:
4174         return 1;
4175     case 1:
4176         if (is_user)
4177           return 1;
4178         *prot = PAGE_READ | PAGE_WRITE;
4179         break;
4180     case 2:
4181         *prot = PAGE_READ;
4182         if (!is_user)
4183             *prot |= PAGE_WRITE;
4184         break;
4185     case 3:
4186         *prot = PAGE_READ | PAGE_WRITE;
4187         break;
4188     case 5:
4189         if (is_user)
4190             return 1;
4191         *prot = PAGE_READ;
4192         break;
4193     case 6:
4194         *prot = PAGE_READ;
4195         break;
4196     default:
4197         /* Bad permission.  */
4198         return 1;
4199     }
4200     *prot |= PAGE_EXEC;
4201     return 0;
4202 }
4203
4204 /* get_phys_addr - get the physical address for this virtual address
4205  *
4206  * Find the physical address corresponding to the given virtual address,
4207  * by doing a translation table walk on MMU based systems or using the
4208  * MPU state on MPU based systems.
4209  *
4210  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
4211  * prot and page_size are not filled in, and the return value provides
4212  * information on why the translation aborted, in the format of a
4213  * DFSR/IFSR fault register, with the following caveats:
4214  *  * we honour the short vs long DFSR format differences.
4215  *  * the WnR bit is never set (the caller must do this).
4216  *  * for MPU based systems we don't bother to return a full FSR format
4217  *    value.
4218  *
4219  * @env: CPUARMState
4220  * @address: virtual address to get physical address for
4221  * @access_type: 0 for read, 1 for write, 2 for execute
4222  * @is_user: 0 for privileged access, 1 for user
4223  * @phys_ptr: set to the physical address corresponding to the virtual address
4224  * @prot: set to the permissions for the page containing phys_ptr
4225  * @page_size: set to the size of the page containing phys_ptr
4226  */
4227 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
4228                                 int access_type, int is_user,
4229                                 hwaddr *phys_ptr, int *prot,
4230                                 target_ulong *page_size)
4231 {
4232     /* Fast Context Switch Extension.  */
4233     if (address < 0x02000000)
4234         address += env->cp15.c13_fcse;
4235
4236     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
4237         /* MMU/MPU disabled.  */
4238         *phys_ptr = address;
4239         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
4240         *page_size = TARGET_PAGE_SIZE;
4241         return 0;
4242     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4243         *page_size = TARGET_PAGE_SIZE;
4244         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4245                                  prot);
4246     } else if (extended_addresses_enabled(env)) {
4247         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4248                                   prot, page_size);
4249     } else if (env->cp15.c1_sys & SCTLR_XP) {
4250         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4251                                 prot, page_size);
4252     } else {
4253         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4254                                 prot, page_size);
4255     }
4256 }
4257
4258 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4259                              int access_type, int mmu_idx)
4260 {
4261     ARMCPU *cpu = ARM_CPU(cs);
4262     CPUARMState *env = &cpu->env;
4263     hwaddr phys_addr;
4264     target_ulong page_size;
4265     int prot;
4266     int ret, is_user;
4267     uint32_t syn;
4268     bool same_el = (arm_current_pl(env) != 0);
4269
4270     is_user = mmu_idx == MMU_USER_IDX;
4271     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4272                         &page_size);
4273     if (ret == 0) {
4274         /* Map a single [sub]page.  */
4275         phys_addr &= TARGET_PAGE_MASK;
4276         address &= TARGET_PAGE_MASK;
4277         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4278         return 0;
4279     }
4280
4281     /* AArch64 syndrome does not have an LPAE bit */
4282     syn = ret & ~(1 << 9);
4283
4284     /* For insn and data aborts we assume there is no instruction syndrome
4285      * information; this is always true for exceptions reported to EL1.
4286      */
4287     if (access_type == 2) {
4288         syn = syn_insn_abort(same_el, 0, 0, syn);
4289         cs->exception_index = EXCP_PREFETCH_ABORT;
4290     } else {
4291         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4292         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4293             ret |= (1 << 11);
4294         }
4295         cs->exception_index = EXCP_DATA_ABORT;
4296     }
4297
4298     env->exception.syndrome = syn;
4299     env->exception.vaddress = address;
4300     env->exception.fsr = ret;
4301     return 1;
4302 }
4303
4304 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4305 {
4306     ARMCPU *cpu = ARM_CPU(cs);
4307     hwaddr phys_addr;
4308     target_ulong page_size;
4309     int prot;
4310     int ret;
4311
4312     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4313
4314     if (ret != 0) {
4315         return -1;
4316     }
4317
4318     return phys_addr;
4319 }
4320
4321 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4322 {
4323     if ((env->uncached_cpsr & CPSR_M) == mode) {
4324         env->regs[13] = val;
4325     } else {
4326         env->banked_r13[bank_number(mode)] = val;
4327     }
4328 }
4329
4330 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4331 {
4332     if ((env->uncached_cpsr & CPSR_M) == mode) {
4333         return env->regs[13];
4334     } else {
4335         return env->banked_r13[bank_number(mode)];
4336     }
4337 }
4338
4339 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4340 {
4341     ARMCPU *cpu = arm_env_get_cpu(env);
4342
4343     switch (reg) {
4344     case 0: /* APSR */
4345         return xpsr_read(env) & 0xf8000000;
4346     case 1: /* IAPSR */
4347         return xpsr_read(env) & 0xf80001ff;
4348     case 2: /* EAPSR */
4349         return xpsr_read(env) & 0xff00fc00;
4350     case 3: /* xPSR */
4351         return xpsr_read(env) & 0xff00fdff;
4352     case 5: /* IPSR */
4353         return xpsr_read(env) & 0x000001ff;
4354     case 6: /* EPSR */
4355         return xpsr_read(env) & 0x0700fc00;
4356     case 7: /* IEPSR */
4357         return xpsr_read(env) & 0x0700edff;
4358     case 8: /* MSP */
4359         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4360     case 9: /* PSP */
4361         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4362     case 16: /* PRIMASK */
4363         return (env->daif & PSTATE_I) != 0;
4364     case 17: /* BASEPRI */
4365     case 18: /* BASEPRI_MAX */
4366         return env->v7m.basepri;
4367     case 19: /* FAULTMASK */
4368         return (env->daif & PSTATE_F) != 0;
4369     case 20: /* CONTROL */
4370         return env->v7m.control;
4371     default:
4372         /* ??? For debugging only.  */
4373         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4374         return 0;
4375     }
4376 }
4377
4378 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4379 {
4380     ARMCPU *cpu = arm_env_get_cpu(env);
4381
4382     switch (reg) {
4383     case 0: /* APSR */
4384         xpsr_write(env, val, 0xf8000000);
4385         break;
4386     case 1: /* IAPSR */
4387         xpsr_write(env, val, 0xf8000000);
4388         break;
4389     case 2: /* EAPSR */
4390         xpsr_write(env, val, 0xfe00fc00);
4391         break;
4392     case 3: /* xPSR */
4393         xpsr_write(env, val, 0xfe00fc00);
4394         break;
4395     case 5: /* IPSR */
4396         /* IPSR bits are readonly.  */
4397         break;
4398     case 6: /* EPSR */
4399         xpsr_write(env, val, 0x0600fc00);
4400         break;
4401     case 7: /* IEPSR */
4402         xpsr_write(env, val, 0x0600fc00);
4403         break;
4404     case 8: /* MSP */
4405         if (env->v7m.current_sp)
4406             env->v7m.other_sp = val;
4407         else
4408             env->regs[13] = val;
4409         break;
4410     case 9: /* PSP */
4411         if (env->v7m.current_sp)
4412             env->regs[13] = val;
4413         else
4414             env->v7m.other_sp = val;
4415         break;
4416     case 16: /* PRIMASK */
4417         if (val & 1) {
4418             env->daif |= PSTATE_I;
4419         } else {
4420             env->daif &= ~PSTATE_I;
4421         }
4422         break;
4423     case 17: /* BASEPRI */
4424         env->v7m.basepri = val & 0xff;
4425         break;
4426     case 18: /* BASEPRI_MAX */
4427         val &= 0xff;
4428         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4429             env->v7m.basepri = val;
4430         break;
4431     case 19: /* FAULTMASK */
4432         if (val & 1) {
4433             env->daif |= PSTATE_F;
4434         } else {
4435             env->daif &= ~PSTATE_F;
4436         }
4437         break;
4438     case 20: /* CONTROL */
4439         env->v7m.control = val & 3;
4440         switch_v7m_sp(env, (val & 2) != 0);
4441         break;
4442     default:
4443         /* ??? For debugging only.  */
4444         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4445         return;
4446     }
4447 }
4448
4449 #endif
4450
4451 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4452 {
4453     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4454      * Note that we do not implement the (architecturally mandated)
4455      * alignment fault for attempts to use this on Device memory
4456      * (which matches the usual QEMU behaviour of not implementing either
4457      * alignment faults or any memory attribute handling).
4458      */
4459
4460     ARMCPU *cpu = arm_env_get_cpu(env);
4461     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4462     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4463
4464 #ifndef CONFIG_USER_ONLY
4465     {
4466         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4467          * the block size so we might have to do more than one TLB lookup.
4468          * We know that in fact for any v8 CPU the page size is at least 4K
4469          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4470          * 1K as an artefact of legacy v5 subpage support being present in the
4471          * same QEMU executable.
4472          */
4473         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4474         void *hostaddr[maxidx];
4475         int try, i;
4476
4477         for (try = 0; try < 2; try++) {
4478
4479             for (i = 0; i < maxidx; i++) {
4480                 hostaddr[i] = tlb_vaddr_to_host(env,
4481                                                 vaddr + TARGET_PAGE_SIZE * i,
4482                                                 1, cpu_mmu_index(env));
4483                 if (!hostaddr[i]) {
4484                     break;
4485                 }
4486             }
4487             if (i == maxidx) {
4488                 /* If it's all in the TLB it's fair game for just writing to;
4489                  * we know we don't need to update dirty status, etc.
4490                  */
4491                 for (i = 0; i < maxidx - 1; i++) {
4492                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4493                 }
4494                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4495                 return;
4496             }
4497             /* OK, try a store and see if we can populate the tlb. This
4498              * might cause an exception if the memory isn't writable,
4499              * in which case we will longjmp out of here. We must for
4500              * this purpose use the actual register value passed to us
4501              * so that we get the fault address right.
4502              */
4503             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4504             /* Now we can populate the other TLB entries, if any */
4505             for (i = 0; i < maxidx; i++) {
4506                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4507                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4508                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4509                 }
4510             }
4511         }
4512
4513         /* Slow path (probably attempt to do this to an I/O device or
4514          * similar, or clearing of a block of code we have translations
4515          * cached for). Just do a series of byte writes as the architecture
4516          * demands. It's not worth trying to use a cpu_physical_memory_map(),
4517          * memset(), unmap() sequence here because:
4518          *  + we'd need to account for the blocksize being larger than a page
4519          *  + the direct-RAM access case is almost always going to be dealt
4520          *    with in the fastpath code above, so there's no speed benefit
4521          *  + we would have to deal with the map returning NULL because the
4522          *    bounce buffer was in use
4523          */
4524         for (i = 0; i < blocklen; i++) {
4525             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4526         }
4527     }
4528 #else
4529     memset(g2h(vaddr), 0, blocklen);
4530 #endif
4531 }
4532
4533 /* Note that signed overflow is undefined in C.  The following routines are
4534    careful to use unsigned types where modulo arithmetic is required.
4535    Failure to do so _will_ break on newer gcc.  */
4536
4537 /* Signed saturating arithmetic.  */
4538
4539 /* Perform 16-bit signed saturating addition.  */
4540 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4541 {
4542     uint16_t res;
4543
4544     res = a + b;
4545     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4546         if (a & 0x8000)
4547             res = 0x8000;
4548         else
4549             res = 0x7fff;
4550     }
4551     return res;
4552 }
4553
4554 /* Perform 8-bit signed saturating addition.  */
4555 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4556 {
4557     uint8_t res;
4558
4559     res = a + b;
4560     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4561         if (a & 0x80)
4562             res = 0x80;
4563         else
4564             res = 0x7f;
4565     }
4566     return res;
4567 }
4568
4569 /* Perform 16-bit signed saturating subtraction.  */
4570 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4571 {
4572     uint16_t res;
4573
4574     res = a - b;
4575     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4576         if (a & 0x8000)
4577             res = 0x8000;
4578         else
4579             res = 0x7fff;
4580     }
4581     return res;
4582 }
4583
4584 /* Perform 8-bit signed saturating subtraction.  */
4585 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4586 {
4587     uint8_t res;
4588
4589     res = a - b;
4590     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4591         if (a & 0x80)
4592             res = 0x80;
4593         else
4594             res = 0x7f;
4595     }
4596     return res;
4597 }
4598
4599 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4600 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4601 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
4602 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
4603 #define PFX q
4604
4605 #include "op_addsub.h"
4606
4607 /* Unsigned saturating arithmetic.  */
4608 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4609 {
4610     uint16_t res;
4611     res = a + b;
4612     if (res < a)
4613         res = 0xffff;
4614     return res;
4615 }
4616
4617 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4618 {
4619     if (a > b)
4620         return a - b;
4621     else
4622         return 0;
4623 }
4624
4625 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4626 {
4627     uint8_t res;
4628     res = a + b;
4629     if (res < a)
4630         res = 0xff;
4631     return res;
4632 }
4633
4634 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4635 {
4636     if (a > b)
4637         return a - b;
4638     else
4639         return 0;
4640 }
4641
4642 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4643 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4644 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
4645 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
4646 #define PFX uq
4647
4648 #include "op_addsub.h"
4649
4650 /* Signed modulo arithmetic.  */
4651 #define SARITH16(a, b, n, op) do { \
4652     int32_t sum; \
4653     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4654     RESULT(sum, n, 16); \
4655     if (sum >= 0) \
4656         ge |= 3 << (n * 2); \
4657     } while(0)
4658
4659 #define SARITH8(a, b, n, op) do { \
4660     int32_t sum; \
4661     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4662     RESULT(sum, n, 8); \
4663     if (sum >= 0) \
4664         ge |= 1 << n; \
4665     } while(0)
4666
4667
4668 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4669 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4670 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
4671 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
4672 #define PFX s
4673 #define ARITH_GE
4674
4675 #include "op_addsub.h"
4676
4677 /* Unsigned modulo arithmetic.  */
4678 #define ADD16(a, b, n) do { \
4679     uint32_t sum; \
4680     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4681     RESULT(sum, n, 16); \
4682     if ((sum >> 16) == 1) \
4683         ge |= 3 << (n * 2); \
4684     } while(0)
4685
4686 #define ADD8(a, b, n) do { \
4687     uint32_t sum; \
4688     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4689     RESULT(sum, n, 8); \
4690     if ((sum >> 8) == 1) \
4691         ge |= 1 << n; \
4692     } while(0)
4693
4694 #define SUB16(a, b, n) do { \
4695     uint32_t sum; \
4696     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4697     RESULT(sum, n, 16); \
4698     if ((sum >> 16) == 0) \
4699         ge |= 3 << (n * 2); \
4700     } while(0)
4701
4702 #define SUB8(a, b, n) do { \
4703     uint32_t sum; \
4704     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4705     RESULT(sum, n, 8); \
4706     if ((sum >> 8) == 0) \
4707         ge |= 1 << n; \
4708     } while(0)
4709
4710 #define PFX u
4711 #define ARITH_GE
4712
4713 #include "op_addsub.h"
4714
4715 /* Halved signed arithmetic.  */
4716 #define ADD16(a, b, n) \
4717   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4718 #define SUB16(a, b, n) \
4719   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4720 #define ADD8(a, b, n) \
4721   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4722 #define SUB8(a, b, n) \
4723   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4724 #define PFX sh
4725
4726 #include "op_addsub.h"
4727
4728 /* Halved unsigned arithmetic.  */
4729 #define ADD16(a, b, n) \
4730   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4731 #define SUB16(a, b, n) \
4732   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4733 #define ADD8(a, b, n) \
4734   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4735 #define SUB8(a, b, n) \
4736   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4737 #define PFX uh
4738
4739 #include "op_addsub.h"
4740
4741 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4742 {
4743     if (a > b)
4744         return a - b;
4745     else
4746         return b - a;
4747 }
4748
4749 /* Unsigned sum of absolute byte differences.  */
4750 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4751 {
4752     uint32_t sum;
4753     sum = do_usad(a, b);
4754     sum += do_usad(a >> 8, b >> 8);
4755     sum += do_usad(a >> 16, b >>16);
4756     sum += do_usad(a >> 24, b >> 24);
4757     return sum;
4758 }
4759
4760 /* For ARMv6 SEL instruction.  */
4761 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4762 {
4763     uint32_t mask;
4764
4765     mask = 0;
4766     if (flags & 1)
4767         mask |= 0xff;
4768     if (flags & 2)
4769         mask |= 0xff00;
4770     if (flags & 4)
4771         mask |= 0xff0000;
4772     if (flags & 8)
4773         mask |= 0xff000000;
4774     return (a & mask) | (b & ~mask);
4775 }
4776
4777 /* VFP support.  We follow the convention used for VFP instructions:
4778    Single precision routines have a "s" suffix, double precision a
4779    "d" suffix.  */
4780
4781 /* Convert host exception flags to vfp form.  */
4782 static inline int vfp_exceptbits_from_host(int host_bits)
4783 {
4784     int target_bits = 0;
4785
4786     if (host_bits & float_flag_invalid)
4787         target_bits |= 1;
4788     if (host_bits & float_flag_divbyzero)
4789         target_bits |= 2;
4790     if (host_bits & float_flag_overflow)
4791         target_bits |= 4;
4792     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4793         target_bits |= 8;
4794     if (host_bits & float_flag_inexact)
4795         target_bits |= 0x10;
4796     if (host_bits & float_flag_input_denormal)
4797         target_bits |= 0x80;
4798     return target_bits;
4799 }
4800
4801 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4802 {
4803     int i;
4804     uint32_t fpscr;
4805
4806     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4807             | (env->vfp.vec_len << 16)
4808             | (env->vfp.vec_stride << 20);
4809     i = get_float_exception_flags(&env->vfp.fp_status);
4810     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4811     fpscr |= vfp_exceptbits_from_host(i);
4812     return fpscr;
4813 }
4814
4815 uint32_t vfp_get_fpscr(CPUARMState *env)
4816 {
4817     return HELPER(vfp_get_fpscr)(env);
4818 }
4819
4820 /* Convert vfp exception flags to target form.  */
4821 static inline int vfp_exceptbits_to_host(int target_bits)
4822 {
4823     int host_bits = 0;
4824
4825     if (target_bits & 1)
4826         host_bits |= float_flag_invalid;
4827     if (target_bits & 2)
4828         host_bits |= float_flag_divbyzero;
4829     if (target_bits & 4)
4830         host_bits |= float_flag_overflow;
4831     if (target_bits & 8)
4832         host_bits |= float_flag_underflow;
4833     if (target_bits & 0x10)
4834         host_bits |= float_flag_inexact;
4835     if (target_bits & 0x80)
4836         host_bits |= float_flag_input_denormal;
4837     return host_bits;
4838 }
4839
4840 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4841 {
4842     int i;
4843     uint32_t changed;
4844
4845     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4846     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4847     env->vfp.vec_len = (val >> 16) & 7;
4848     env->vfp.vec_stride = (val >> 20) & 3;
4849
4850     changed ^= val;
4851     if (changed & (3 << 22)) {
4852         i = (val >> 22) & 3;
4853         switch (i) {
4854         case FPROUNDING_TIEEVEN:
4855             i = float_round_nearest_even;
4856             break;
4857         case FPROUNDING_POSINF:
4858             i = float_round_up;
4859             break;
4860         case FPROUNDING_NEGINF:
4861             i = float_round_down;
4862             break;
4863         case FPROUNDING_ZERO:
4864             i = float_round_to_zero;
4865             break;
4866         }
4867         set_float_rounding_mode(i, &env->vfp.fp_status);
4868     }
4869     if (changed & (1 << 24)) {
4870         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4871         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4872     }
4873     if (changed & (1 << 25))
4874         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4875
4876     i = vfp_exceptbits_to_host(val);
4877     set_float_exception_flags(i, &env->vfp.fp_status);
4878     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4879 }
4880
4881 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4882 {
4883     HELPER(vfp_set_fpscr)(env, val);
4884 }
4885
4886 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4887
4888 #define VFP_BINOP(name) \
4889 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4890 { \
4891     float_status *fpst = fpstp; \
4892     return float32_ ## name(a, b, fpst); \
4893 } \
4894 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4895 { \
4896     float_status *fpst = fpstp; \
4897     return float64_ ## name(a, b, fpst); \
4898 }
4899 VFP_BINOP(add)
4900 VFP_BINOP(sub)
4901 VFP_BINOP(mul)
4902 VFP_BINOP(div)
4903 VFP_BINOP(min)
4904 VFP_BINOP(max)
4905 VFP_BINOP(minnum)
4906 VFP_BINOP(maxnum)
4907 #undef VFP_BINOP
4908
4909 float32 VFP_HELPER(neg, s)(float32 a)
4910 {
4911     return float32_chs(a);
4912 }
4913
4914 float64 VFP_HELPER(neg, d)(float64 a)
4915 {
4916     return float64_chs(a);
4917 }
4918
4919 float32 VFP_HELPER(abs, s)(float32 a)
4920 {
4921     return float32_abs(a);
4922 }
4923
4924 float64 VFP_HELPER(abs, d)(float64 a)
4925 {
4926     return float64_abs(a);
4927 }
4928
4929 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4930 {
4931     return float32_sqrt(a, &env->vfp.fp_status);
4932 }
4933
4934 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4935 {
4936     return float64_sqrt(a, &env->vfp.fp_status);
4937 }
4938
4939 /* XXX: check quiet/signaling case */
4940 #define DO_VFP_cmp(p, type) \
4941 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4942 { \
4943     uint32_t flags; \
4944     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4945     case 0: flags = 0x6; break; \
4946     case -1: flags = 0x8; break; \
4947     case 1: flags = 0x2; break; \
4948     default: case 2: flags = 0x3; break; \
4949     } \
4950     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4951         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4952 } \
4953 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4954 { \
4955     uint32_t flags; \
4956     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4957     case 0: flags = 0x6; break; \
4958     case -1: flags = 0x8; break; \
4959     case 1: flags = 0x2; break; \
4960     default: case 2: flags = 0x3; break; \
4961     } \
4962     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4963         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4964 }
4965 DO_VFP_cmp(s, float32)
4966 DO_VFP_cmp(d, float64)
4967 #undef DO_VFP_cmp
4968
4969 /* Integer to float and float to integer conversions */
4970
4971 #define CONV_ITOF(name, fsz, sign) \
4972     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4973 { \
4974     float_status *fpst = fpstp; \
4975     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4976 }
4977
4978 #define CONV_FTOI(name, fsz, sign, round) \
4979 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4980 { \
4981     float_status *fpst = fpstp; \
4982     if (float##fsz##_is_any_nan(x)) { \
4983         float_raise(float_flag_invalid, fpst); \
4984         return 0; \
4985     } \
4986     return float##fsz##_to_##sign##int32##round(x, fpst); \
4987 }
4988
4989 #define FLOAT_CONVS(name, p, fsz, sign) \
4990 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4991 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4992 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4993
4994 FLOAT_CONVS(si, s, 32, )
4995 FLOAT_CONVS(si, d, 64, )
4996 FLOAT_CONVS(ui, s, 32, u)
4997 FLOAT_CONVS(ui, d, 64, u)
4998
4999 #undef CONV_ITOF
5000 #undef CONV_FTOI
5001 #undef FLOAT_CONVS
5002
5003 /* floating point conversion */
5004 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
5005 {
5006     float64 r = float32_to_float64(x, &env->vfp.fp_status);
5007     /* ARM requires that S<->D conversion of any kind of NaN generates
5008      * a quiet NaN by forcing the most significant frac bit to 1.
5009      */
5010     return float64_maybe_silence_nan(r);
5011 }
5012
5013 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
5014 {
5015     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
5016     /* ARM requires that S<->D conversion of any kind of NaN generates
5017      * a quiet NaN by forcing the most significant frac bit to 1.
5018      */
5019     return float32_maybe_silence_nan(r);
5020 }
5021
5022 /* VFP3 fixed point conversion.  */
5023 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
5024 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
5025                                      void *fpstp) \
5026 { \
5027     float_status *fpst = fpstp; \
5028     float##fsz tmp; \
5029     tmp = itype##_to_##float##fsz(x, fpst); \
5030     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
5031 }
5032
5033 /* Notice that we want only input-denormal exception flags from the
5034  * scalbn operation: the other possible flags (overflow+inexact if
5035  * we overflow to infinity, output-denormal) aren't correct for the
5036  * complete scale-and-convert operation.
5037  */
5038 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
5039 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
5040                                              uint32_t shift, \
5041                                              void *fpstp) \
5042 { \
5043     float_status *fpst = fpstp; \
5044     int old_exc_flags = get_float_exception_flags(fpst); \
5045     float##fsz tmp; \
5046     if (float##fsz##_is_any_nan(x)) { \
5047         float_raise(float_flag_invalid, fpst); \
5048         return 0; \
5049     } \
5050     tmp = float##fsz##_scalbn(x, shift, fpst); \
5051     old_exc_flags |= get_float_exception_flags(fpst) \
5052         & float_flag_input_denormal; \
5053     set_float_exception_flags(old_exc_flags, fpst); \
5054     return float##fsz##_to_##itype##round(tmp, fpst); \
5055 }
5056
5057 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
5058 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5059 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
5060 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5061
5062 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
5063 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
5064 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
5065
5066 VFP_CONV_FIX(sh, d, 64, 64, int16)
5067 VFP_CONV_FIX(sl, d, 64, 64, int32)
5068 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
5069 VFP_CONV_FIX(uh, d, 64, 64, uint16)
5070 VFP_CONV_FIX(ul, d, 64, 64, uint32)
5071 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
5072 VFP_CONV_FIX(sh, s, 32, 32, int16)
5073 VFP_CONV_FIX(sl, s, 32, 32, int32)
5074 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
5075 VFP_CONV_FIX(uh, s, 32, 32, uint16)
5076 VFP_CONV_FIX(ul, s, 32, 32, uint32)
5077 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
5078 #undef VFP_CONV_FIX
5079 #undef VFP_CONV_FIX_FLOAT
5080 #undef VFP_CONV_FLOAT_FIX_ROUND
5081
5082 /* Set the current fp rounding mode and return the old one.
5083  * The argument is a softfloat float_round_ value.
5084  */
5085 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
5086 {
5087     float_status *fp_status = &env->vfp.fp_status;
5088
5089     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5090     set_float_rounding_mode(rmode, fp_status);
5091
5092     return prev_rmode;
5093 }
5094
5095 /* Set the current fp rounding mode in the standard fp status and return
5096  * the old one. This is for NEON instructions that need to change the
5097  * rounding mode but wish to use the standard FPSCR values for everything
5098  * else. Always set the rounding mode back to the correct value after
5099  * modifying it.
5100  * The argument is a softfloat float_round_ value.
5101  */
5102 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
5103 {
5104     float_status *fp_status = &env->vfp.standard_fp_status;
5105
5106     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
5107     set_float_rounding_mode(rmode, fp_status);
5108
5109     return prev_rmode;
5110 }
5111
5112 /* Half precision conversions.  */
5113 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
5114 {
5115     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5116     float32 r = float16_to_float32(make_float16(a), ieee, s);
5117     if (ieee) {
5118         return float32_maybe_silence_nan(r);
5119     }
5120     return r;
5121 }
5122
5123 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
5124 {
5125     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5126     float16 r = float32_to_float16(a, ieee, s);
5127     if (ieee) {
5128         r = float16_maybe_silence_nan(r);
5129     }
5130     return float16_val(r);
5131 }
5132
5133 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5134 {
5135     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
5136 }
5137
5138 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5139 {
5140     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
5141 }
5142
5143 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
5144 {
5145     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
5146 }
5147
5148 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
5149 {
5150     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
5151 }
5152
5153 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
5154 {
5155     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5156     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
5157     if (ieee) {
5158         return float64_maybe_silence_nan(r);
5159     }
5160     return r;
5161 }
5162
5163 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
5164 {
5165     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
5166     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
5167     if (ieee) {
5168         r = float16_maybe_silence_nan(r);
5169     }
5170     return float16_val(r);
5171 }
5172
5173 #define float32_two make_float32(0x40000000)
5174 #define float32_three make_float32(0x40400000)
5175 #define float32_one_point_five make_float32(0x3fc00000)
5176
5177 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
5178 {
5179     float_status *s = &env->vfp.standard_fp_status;
5180     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5181         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5182         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5183             float_raise(float_flag_input_denormal, s);
5184         }
5185         return float32_two;
5186     }
5187     return float32_sub(float32_two, float32_mul(a, b, s), s);
5188 }
5189
5190 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
5191 {
5192     float_status *s = &env->vfp.standard_fp_status;
5193     float32 product;
5194     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
5195         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
5196         if (!(float32_is_zero(a) || float32_is_zero(b))) {
5197             float_raise(float_flag_input_denormal, s);
5198         }
5199         return float32_one_point_five;
5200     }
5201     product = float32_mul(a, b, s);
5202     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
5203 }
5204
5205 /* NEON helpers.  */
5206
5207 /* Constants 256 and 512 are used in some helpers; we avoid relying on
5208  * int->float conversions at run-time.  */
5209 #define float64_256 make_float64(0x4070000000000000LL)
5210 #define float64_512 make_float64(0x4080000000000000LL)
5211 #define float32_maxnorm make_float32(0x7f7fffff)
5212 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
5213
5214 /* Reciprocal functions
5215  *
5216  * The algorithm that must be used to calculate the estimate
5217  * is specified by the ARM ARM, see FPRecipEstimate()
5218  */
5219
5220 static float64 recip_estimate(float64 a, float_status *real_fp_status)
5221 {
5222     /* These calculations mustn't set any fp exception flags,
5223      * so we use a local copy of the fp_status.
5224      */
5225     float_status dummy_status = *real_fp_status;
5226     float_status *s = &dummy_status;
5227     /* q = (int)(a * 512.0) */
5228     float64 q = float64_mul(float64_512, a, s);
5229     int64_t q_int = float64_to_int64_round_to_zero(q, s);
5230
5231     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
5232     q = int64_to_float64(q_int, s);
5233     q = float64_add(q, float64_half, s);
5234     q = float64_div(q, float64_512, s);
5235     q = float64_div(float64_one, q, s);
5236
5237     /* s = (int)(256.0 * r + 0.5) */
5238     q = float64_mul(q, float64_256, s);
5239     q = float64_add(q, float64_half, s);
5240     q_int = float64_to_int64_round_to_zero(q, s);
5241
5242     /* return (double)s / 256.0 */
5243     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5244 }
5245
5246 /* Common wrapper to call recip_estimate */
5247 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5248 {
5249     uint64_t val64 = float64_val(num);
5250     uint64_t frac = extract64(val64, 0, 52);
5251     int64_t exp = extract64(val64, 52, 11);
5252     uint64_t sbit;
5253     float64 scaled, estimate;
5254
5255     /* Generate the scaled number for the estimate function */
5256     if (exp == 0) {
5257         if (extract64(frac, 51, 1) == 0) {
5258             exp = -1;
5259             frac = extract64(frac, 0, 50) << 2;
5260         } else {
5261             frac = extract64(frac, 0, 51) << 1;
5262         }
5263     }
5264
5265     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5266     scaled = make_float64((0x3feULL << 52)
5267                           | extract64(frac, 44, 8) << 44);
5268
5269     estimate = recip_estimate(scaled, fpst);
5270
5271     /* Build new result */
5272     val64 = float64_val(estimate);
5273     sbit = 0x8000000000000000ULL & val64;
5274     exp = off - exp;
5275     frac = extract64(val64, 0, 52);
5276
5277     if (exp == 0) {
5278         frac = 1ULL << 51 | extract64(frac, 1, 51);
5279     } else if (exp == -1) {
5280         frac = 1ULL << 50 | extract64(frac, 2, 50);
5281         exp = 0;
5282     }
5283
5284     return make_float64(sbit | (exp << 52) | frac);
5285 }
5286
5287 static bool round_to_inf(float_status *fpst, bool sign_bit)
5288 {
5289     switch (fpst->float_rounding_mode) {
5290     case float_round_nearest_even: /* Round to Nearest */
5291         return true;
5292     case float_round_up: /* Round to +Inf */
5293         return !sign_bit;
5294     case float_round_down: /* Round to -Inf */
5295         return sign_bit;
5296     case float_round_to_zero: /* Round to Zero */
5297         return false;
5298     }
5299
5300     g_assert_not_reached();
5301 }
5302
5303 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5304 {
5305     float_status *fpst = fpstp;
5306     float32 f32 = float32_squash_input_denormal(input, fpst);
5307     uint32_t f32_val = float32_val(f32);
5308     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5309     int32_t f32_exp = extract32(f32_val, 23, 8);
5310     uint32_t f32_frac = extract32(f32_val, 0, 23);
5311     float64 f64, r64;
5312     uint64_t r64_val;
5313     int64_t r64_exp;
5314     uint64_t r64_frac;
5315
5316     if (float32_is_any_nan(f32)) {
5317         float32 nan = f32;
5318         if (float32_is_signaling_nan(f32)) {
5319             float_raise(float_flag_invalid, fpst);
5320             nan = float32_maybe_silence_nan(f32);
5321         }
5322         if (fpst->default_nan_mode) {
5323             nan =  float32_default_nan;
5324         }
5325         return nan;
5326     } else if (float32_is_infinity(f32)) {
5327         return float32_set_sign(float32_zero, float32_is_neg(f32));
5328     } else if (float32_is_zero(f32)) {
5329         float_raise(float_flag_divbyzero, fpst);
5330         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5331     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5332         /* Abs(value) < 2.0^-128 */
5333         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5334         if (round_to_inf(fpst, f32_sbit)) {
5335             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5336         } else {
5337             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5338         }
5339     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5340         float_raise(float_flag_underflow, fpst);
5341         return float32_set_sign(float32_zero, float32_is_neg(f32));
5342     }
5343
5344
5345     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5346     r64 = call_recip_estimate(f64, 253, fpst);
5347     r64_val = float64_val(r64);
5348     r64_exp = extract64(r64_val, 52, 11);
5349     r64_frac = extract64(r64_val, 0, 52);
5350
5351     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5352     return make_float32(f32_sbit |
5353                         (r64_exp & 0xff) << 23 |
5354                         extract64(r64_frac, 29, 24));
5355 }
5356
5357 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5358 {
5359     float_status *fpst = fpstp;
5360     float64 f64 = float64_squash_input_denormal(input, fpst);
5361     uint64_t f64_val = float64_val(f64);
5362     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5363     int64_t f64_exp = extract64(f64_val, 52, 11);
5364     float64 r64;
5365     uint64_t r64_val;
5366     int64_t r64_exp;
5367     uint64_t r64_frac;
5368
5369     /* Deal with any special cases */
5370     if (float64_is_any_nan(f64)) {
5371         float64 nan = f64;
5372         if (float64_is_signaling_nan(f64)) {
5373             float_raise(float_flag_invalid, fpst);
5374             nan = float64_maybe_silence_nan(f64);
5375         }
5376         if (fpst->default_nan_mode) {
5377             nan =  float64_default_nan;
5378         }
5379         return nan;
5380     } else if (float64_is_infinity(f64)) {
5381         return float64_set_sign(float64_zero, float64_is_neg(f64));
5382     } else if (float64_is_zero(f64)) {
5383         float_raise(float_flag_divbyzero, fpst);
5384         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5385     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5386         /* Abs(value) < 2.0^-1024 */
5387         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5388         if (round_to_inf(fpst, f64_sbit)) {
5389             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5390         } else {
5391             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5392         }
5393     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5394         float_raise(float_flag_underflow, fpst);
5395         return float64_set_sign(float64_zero, float64_is_neg(f64));
5396     }
5397
5398     r64 = call_recip_estimate(f64, 2045, fpst);
5399     r64_val = float64_val(r64);
5400     r64_exp = extract64(r64_val, 52, 11);
5401     r64_frac = extract64(r64_val, 0, 52);
5402
5403     /* result = sign : result_exp<10:0> : fraction<51:0> */
5404     return make_float64(f64_sbit |
5405                         ((r64_exp & 0x7ff) << 52) |
5406                         r64_frac);
5407 }
5408
5409 /* The algorithm that must be used to calculate the estimate
5410  * is specified by the ARM ARM.
5411  */
5412 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5413 {
5414     /* These calculations mustn't set any fp exception flags,
5415      * so we use a local copy of the fp_status.
5416      */
5417     float_status dummy_status = *real_fp_status;
5418     float_status *s = &dummy_status;
5419     float64 q;
5420     int64_t q_int;
5421
5422     if (float64_lt(a, float64_half, s)) {
5423         /* range 0.25 <= a < 0.5 */
5424
5425         /* a in units of 1/512 rounded down */
5426         /* q0 = (int)(a * 512.0);  */
5427         q = float64_mul(float64_512, a, s);
5428         q_int = float64_to_int64_round_to_zero(q, s);
5429
5430         /* reciprocal root r */
5431         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5432         q = int64_to_float64(q_int, s);
5433         q = float64_add(q, float64_half, s);
5434         q = float64_div(q, float64_512, s);
5435         q = float64_sqrt(q, s);
5436         q = float64_div(float64_one, q, s);
5437     } else {
5438         /* range 0.5 <= a < 1.0 */
5439
5440         /* a in units of 1/256 rounded down */
5441         /* q1 = (int)(a * 256.0); */
5442         q = float64_mul(float64_256, a, s);
5443         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5444
5445         /* reciprocal root r */
5446         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5447         q = int64_to_float64(q_int, s);
5448         q = float64_add(q, float64_half, s);
5449         q = float64_div(q, float64_256, s);
5450         q = float64_sqrt(q, s);
5451         q = float64_div(float64_one, q, s);
5452     }
5453     /* r in units of 1/256 rounded to nearest */
5454     /* s = (int)(256.0 * r + 0.5); */
5455
5456     q = float64_mul(q, float64_256,s );
5457     q = float64_add(q, float64_half, s);
5458     q_int = float64_to_int64_round_to_zero(q, s);
5459
5460     /* return (double)s / 256.0;*/
5461     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5462 }
5463
5464 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5465 {
5466     float_status *s = fpstp;
5467     float32 f32 = float32_squash_input_denormal(input, s);
5468     uint32_t val = float32_val(f32);
5469     uint32_t f32_sbit = 0x80000000 & val;
5470     int32_t f32_exp = extract32(val, 23, 8);
5471     uint32_t f32_frac = extract32(val, 0, 23);
5472     uint64_t f64_frac;
5473     uint64_t val64;
5474     int result_exp;
5475     float64 f64;
5476
5477     if (float32_is_any_nan(f32)) {
5478         float32 nan = f32;
5479         if (float32_is_signaling_nan(f32)) {
5480             float_raise(float_flag_invalid, s);
5481             nan = float32_maybe_silence_nan(f32);
5482         }
5483         if (s->default_nan_mode) {
5484             nan =  float32_default_nan;
5485         }
5486         return nan;
5487     } else if (float32_is_zero(f32)) {
5488         float_raise(float_flag_divbyzero, s);
5489         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5490     } else if (float32_is_neg(f32)) {
5491         float_raise(float_flag_invalid, s);
5492         return float32_default_nan;
5493     } else if (float32_is_infinity(f32)) {
5494         return float32_zero;
5495     }
5496
5497     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5498      * preserving the parity of the exponent.  */
5499
5500     f64_frac = ((uint64_t) f32_frac) << 29;
5501     if (f32_exp == 0) {
5502         while (extract64(f64_frac, 51, 1) == 0) {
5503             f64_frac = f64_frac << 1;
5504             f32_exp = f32_exp-1;
5505         }
5506         f64_frac = extract64(f64_frac, 0, 51) << 1;
5507     }
5508
5509     if (extract64(f32_exp, 0, 1) == 0) {
5510         f64 = make_float64(((uint64_t) f32_sbit) << 32
5511                            | (0x3feULL << 52)
5512                            | f64_frac);
5513     } else {
5514         f64 = make_float64(((uint64_t) f32_sbit) << 32
5515                            | (0x3fdULL << 52)
5516                            | f64_frac);
5517     }
5518
5519     result_exp = (380 - f32_exp) / 2;
5520
5521     f64 = recip_sqrt_estimate(f64, s);
5522
5523     val64 = float64_val(f64);
5524
5525     val = ((result_exp & 0xff) << 23)
5526         | ((val64 >> 29)  & 0x7fffff);
5527     return make_float32(val);
5528 }
5529
5530 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5531 {
5532     float_status *s = fpstp;
5533     float64 f64 = float64_squash_input_denormal(input, s);
5534     uint64_t val = float64_val(f64);
5535     uint64_t f64_sbit = 0x8000000000000000ULL & val;
5536     int64_t f64_exp = extract64(val, 52, 11);
5537     uint64_t f64_frac = extract64(val, 0, 52);
5538     int64_t result_exp;
5539     uint64_t result_frac;
5540
5541     if (float64_is_any_nan(f64)) {
5542         float64 nan = f64;
5543         if (float64_is_signaling_nan(f64)) {
5544             float_raise(float_flag_invalid, s);
5545             nan = float64_maybe_silence_nan(f64);
5546         }
5547         if (s->default_nan_mode) {
5548             nan =  float64_default_nan;
5549         }
5550         return nan;
5551     } else if (float64_is_zero(f64)) {
5552         float_raise(float_flag_divbyzero, s);
5553         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5554     } else if (float64_is_neg(f64)) {
5555         float_raise(float_flag_invalid, s);
5556         return float64_default_nan;
5557     } else if (float64_is_infinity(f64)) {
5558         return float64_zero;
5559     }
5560
5561     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5562      * preserving the parity of the exponent.  */
5563
5564     if (f64_exp == 0) {
5565         while (extract64(f64_frac, 51, 1) == 0) {
5566             f64_frac = f64_frac << 1;
5567             f64_exp = f64_exp - 1;
5568         }
5569         f64_frac = extract64(f64_frac, 0, 51) << 1;
5570     }
5571
5572     if (extract64(f64_exp, 0, 1) == 0) {
5573         f64 = make_float64(f64_sbit
5574                            | (0x3feULL << 52)
5575                            | f64_frac);
5576     } else {
5577         f64 = make_float64(f64_sbit
5578                            | (0x3fdULL << 52)
5579                            | f64_frac);
5580     }
5581
5582     result_exp = (3068 - f64_exp) / 2;
5583
5584     f64 = recip_sqrt_estimate(f64, s);
5585
5586     result_frac = extract64(float64_val(f64), 0, 52);
5587
5588     return make_float64(f64_sbit |
5589                         ((result_exp & 0x7ff) << 52) |
5590                         result_frac);
5591 }
5592
5593 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5594 {
5595     float_status *s = fpstp;
5596     float64 f64;
5597
5598     if ((a & 0x80000000) == 0) {
5599         return 0xffffffff;
5600     }
5601
5602     f64 = make_float64((0x3feULL << 52)
5603                        | ((int64_t)(a & 0x7fffffff) << 21));
5604
5605     f64 = recip_estimate(f64, s);
5606
5607     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5608 }
5609
5610 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5611 {
5612     float_status *fpst = fpstp;
5613     float64 f64;
5614
5615     if ((a & 0xc0000000) == 0) {
5616         return 0xffffffff;
5617     }
5618
5619     if (a & 0x80000000) {
5620         f64 = make_float64((0x3feULL << 52)
5621                            | ((uint64_t)(a & 0x7fffffff) << 21));
5622     } else { /* bits 31-30 == '01' */
5623         f64 = make_float64((0x3fdULL << 52)
5624                            | ((uint64_t)(a & 0x3fffffff) << 22));
5625     }
5626
5627     f64 = recip_sqrt_estimate(f64, fpst);
5628
5629     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5630 }
5631
5632 /* VFPv4 fused multiply-accumulate */
5633 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5634 {
5635     float_status *fpst = fpstp;
5636     return float32_muladd(a, b, c, 0, fpst);
5637 }
5638
5639 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5640 {
5641     float_status *fpst = fpstp;
5642     return float64_muladd(a, b, c, 0, fpst);
5643 }
5644
5645 /* ARMv8 round to integral */
5646 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5647 {
5648     return float32_round_to_int(x, fp_status);
5649 }
5650
5651 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5652 {
5653     return float64_round_to_int(x, fp_status);
5654 }
5655
5656 float32 HELPER(rints)(float32 x, void *fp_status)
5657 {
5658     int old_flags = get_float_exception_flags(fp_status), new_flags;
5659     float32 ret;
5660
5661     ret = float32_round_to_int(x, fp_status);
5662
5663     /* Suppress any inexact exceptions the conversion produced */
5664     if (!(old_flags & float_flag_inexact)) {
5665         new_flags = get_float_exception_flags(fp_status);
5666         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5667     }
5668
5669     return ret;
5670 }
5671
5672 float64 HELPER(rintd)(float64 x, void *fp_status)
5673 {
5674     int old_flags = get_float_exception_flags(fp_status), new_flags;
5675     float64 ret;
5676
5677     ret = float64_round_to_int(x, fp_status);
5678
5679     new_flags = get_float_exception_flags(fp_status);
5680
5681     /* Suppress any inexact exceptions the conversion produced */
5682     if (!(old_flags & float_flag_inexact)) {
5683         new_flags = get_float_exception_flags(fp_status);
5684         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5685     }
5686
5687     return ret;
5688 }
5689
5690 /* Convert ARM rounding mode to softfloat */
5691 int arm_rmode_to_sf(int rmode)
5692 {
5693     switch (rmode) {
5694     case FPROUNDING_TIEAWAY:
5695         rmode = float_round_ties_away;
5696         break;
5697     case FPROUNDING_ODD:
5698         /* FIXME: add support for TIEAWAY and ODD */
5699         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5700                       rmode);
5701     case FPROUNDING_TIEEVEN:
5702     default:
5703         rmode = float_round_nearest_even;
5704         break;
5705     case FPROUNDING_POSINF:
5706         rmode = float_round_up;
5707         break;
5708     case FPROUNDING_NEGINF:
5709         rmode = float_round_down;
5710         break;
5711     case FPROUNDING_ZERO:
5712         rmode = float_round_to_zero;
5713         break;
5714     }
5715     return rmode;
5716 }
5717
5718 /* CRC helpers.
5719  * The upper bytes of val (above the number specified by 'bytes') must have
5720  * been zeroed out by the caller.
5721  */
5722 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5723 {
5724     uint8_t buf[4];
5725
5726     stl_le_p(buf, val);
5727
5728     /* zlib crc32 converts the accumulator and output to one's complement.  */
5729     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5730 }
5731
5732 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5733 {
5734     uint8_t buf[4];
5735
5736     stl_le_p(buf, val);
5737
5738     /* Linux crc32c converts the output to one's complement.  */
5739     return crc32c(acc, buf, bytes) ^ 0xffffffff;
5740 }