hw/intc/arm_gicv3_common.c

   1 /*
   2  * ARM GICv3 support - common bits of emulated and KVM kernel model
   3  *
   4  * Copyright (c) 2012 Linaro Limited
   5  * Copyright (c) 2015 Huawei.
   6  * Written by Peter Maydell
   7  * Extended to 64 cores by Shlomo Pongratz
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation, either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw/intc/arm_gicv3_common.h"
  24
  25 static void gicv3_pre_save(void *opaque)
  26 {
  27     GICv3State *s = (GICv3State *)opaque;
  28     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
  29
  30     if (c->pre_save) {
  31         c->pre_save(s);
  32     }
  33 }
  34
  35 static int gicv3_post_load(void *opaque, int version_id)
  36 {
  37     GICv3State *s = (GICv3State *)opaque;
  38     ARMGICv3CommonClass *c = ARM_GICV3_COMMON_GET_CLASS(s);
  39
  40     if (c->post_load) {
  41         c->post_load(s);
  42     }
  43     return 0;
  44 }
  45
  46 static const VMStateDescription vmstate_gicv3 = {
  47     .name = "arm_gicv3",
  48     .unmigratable = 1,
  49     .pre_save = gicv3_pre_save,
  50     .post_load = gicv3_post_load,
  51 };
  52
  53 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
  54                               const MemoryRegionOps *ops)
  55 {
  56     SysBusDevice *sbd = SYS_BUS_DEVICE(s);
  57     int i;
  58
  59     /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
  60      * GPIO array layout is thus:
  61      *  [0..N-1] spi
  62      *  [N..N+31] PPIs for CPU 0
  63      *  [N+32..N+63] PPIs for CPU 1
  64      *   ...
  65      */
  66     i = s->num_irq - GIC_INTERNAL + GIC_INTERNAL * s->num_cpu;
  67     qdev_init_gpio_in(DEVICE(s), handler, i);
  68
  69     s->parent_irq = g_malloc(s->num_cpu * sizeof(qemu_irq));
  70     s->parent_fiq = g_malloc(s->num_cpu * sizeof(qemu_irq));
  71
  72     for (i = 0; i < s->num_cpu; i++) {
  73         sysbus_init_irq(sbd, &s->parent_irq[i]);
  74     }
  75     for (i = 0; i < s->num_cpu; i++) {
  76         sysbus_init_irq(sbd, &s->parent_fiq[i]);
  77     }
  78
  79     memory_region_init_io(&s->iomem_dist, OBJECT(s), ops, s,
  80                           "gicv3_dist", 0x10000);
  81     memory_region_init_io(&s->iomem_redist, OBJECT(s), ops ? &ops[1] : NULL, s,
  82                           "gicv3_redist", 0x20000 * s->num_cpu);
  83
  84     sysbus_init_mmio(sbd, &s->iomem_dist);
  85     sysbus_init_mmio(sbd, &s->iomem_redist);
  86 }
  87
  88 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
  89 {
  90     GICv3State *s = ARM_GICV3_COMMON(dev);
  91
  92     /* revision property is actually reserved and currently used only in order
  93      * to keep the interface compatible with GICv2 code, avoiding extra
  94      * conditions. However, in future it could be used, for example, if we
  95      * implement GICv4.
  96      */
  97     if (s->revision != 3) {
  98         error_setg(errp, "unsupported GIC revision %d", s->revision);
  99         return;
 100     }
 101 }
 102
 103 static void arm_gicv3_common_reset(DeviceState *dev)
 104 {
 105     /* TODO */
 106 }
 107
 108 static Property arm_gicv3_common_properties[] = {
 109     DEFINE_PROP_UINT32("num-cpu", GICv3State, num_cpu, 1),
 110     DEFINE_PROP_UINT32("num-irq", GICv3State, num_irq, 32),
 111     DEFINE_PROP_UINT32("revision", GICv3State, revision, 3),
 112     DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn, 0),
 113     DEFINE_PROP_END_OF_LIST(),
 114 };
 115
 116 static void arm_gicv3_common_class_init(ObjectClass *klass, void *data)
 117 {
 118     DeviceClass *dc = DEVICE_CLASS(klass);
 119
 120     dc->reset = arm_gicv3_common_reset;
 121     dc->realize = arm_gicv3_common_realize;
 122     dc->props = arm_gicv3_common_properties;
 123     dc->vmsd = &vmstate_gicv3;
 124 }
 125
 126 static const TypeInfo arm_gicv3_common_type = {
 127     .name = TYPE_ARM_GICV3_COMMON,
 128     .parent = TYPE_SYS_BUS_DEVICE,
 129     .instance_size = sizeof(GICv3State),
 130     .class_size = sizeof(ARMGICv3CommonClass),
 131     .class_init = arm_gicv3_common_class_init,
 132     .abstract = true,
 133 };
 134
 135 static void register_types(void)
 136 {
 137     type_register_static(&arm_gicv3_common_type);
 138 }
 139
 140 type_init(register_types)