hw/arm/virt-acpi-build.c

   1 /* Support for generating ACPI tables and passing them to Guests
   2  *
   3  * ARM virt ACPI generation
   4  *
   5  * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
   6  * Copyright (C) 2006 Fabrice Bellard
   7  * Copyright (C) 2013 Red Hat Inc
   8  *
   9  * Author: Michael S. Tsirkin <mst@redhat.com>
  10  *
  11  * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
  12  *
  13  * Author: Shannon Zhao <zhaoshenglong@huawei.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24
  25  * You should have received a copy of the GNU General Public License along
  26  * with this program; if not, see <http://www.gnu.org/licenses/>.
  27  */
  28
  29 #include "qemu-common.h"
  30 #include "hw/arm/virt-acpi-build.h"
  31 #include "qemu/bitmap.h"
  32 #include "trace.h"
  33 #include "qom/cpu.h"
  34 #include "target-arm/cpu.h"
  35 #include "hw/acpi/acpi-defs.h"
  36 #include "hw/acpi/acpi.h"
  37 #include "hw/nvram/fw_cfg.h"
  38 #include "hw/acpi/bios-linker-loader.h"
  39 #include "hw/loader.h"
  40 #include "hw/hw.h"
  41 #include "hw/acpi/aml-build.h"
  42 #include "hw/pci/pcie_host.h"
  43 #include "hw/pci/pci.h"
  44
  45 #define ARM_SPI_BASE 32
  46
  47 typedef struct VirtAcpiCpuInfo {
  48     DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
  49 } VirtAcpiCpuInfo;
  50
  51 static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
  52 {
  53     CPUState *cpu;
  54
  55     memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
  56     CPU_FOREACH(cpu) {
  57         set_bit(cpu->cpu_index, cpuinfo->found_cpus);
  58     }
  59 }
  60
  61 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
  62 {
  63     uint16_t i;
  64
  65     for (i = 0; i < smp_cpus; i++) {
  66         Aml *dev = aml_device("C%03x", i);
  67         aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
  68         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
  69         aml_append(scope, dev);
  70     }
  71 }
  72
  73 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
  74                                            int uart_irq)
  75 {
  76     Aml *dev = aml_device("COM0");
  77     aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
  78     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
  79
  80     Aml *crs = aml_resource_template();
  81     aml_append(crs, aml_memory32_fixed(uart_memmap->base,
  82                                        uart_memmap->size, AML_READ_WRITE));
  83     aml_append(crs,
  84                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
  85                              AML_EXCLUSIVE, uart_irq));
  86     aml_append(dev, aml_name_decl("_CRS", crs));
  87
  88     /* The _ADR entry is used to link this device to the UART described
  89      * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
  90      */
  91     aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
  92
  93     aml_append(scope, dev);
  94 }
  95
  96 static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap,
  97                                           int rtc_irq)
  98 {
  99     Aml *dev = aml_device("RTC0");
 100     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
 101     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 102
 103     Aml *crs = aml_resource_template();
 104     aml_append(crs, aml_memory32_fixed(rtc_memmap->base,
 105                                        rtc_memmap->size, AML_READ_WRITE));
 106     aml_append(crs,
 107                aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 108                              AML_EXCLUSIVE, rtc_irq));
 109     aml_append(dev, aml_name_decl("_CRS", crs));
 110     aml_append(scope, dev);
 111 }
 112
 113 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
 114 {
 115     Aml *dev, *crs;
 116     hwaddr base = flash_memmap->base;
 117     hwaddr size = flash_memmap->size / 2;
 118
 119     dev = aml_device("FLS0");
 120     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 121     aml_append(dev, aml_name_decl("_UID", aml_int(0)));
 122
 123     crs = aml_resource_template();
 124     aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 125     aml_append(dev, aml_name_decl("_CRS", crs));
 126     aml_append(scope, dev);
 127
 128     dev = aml_device("FLS1");
 129     aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
 130     aml_append(dev, aml_name_decl("_UID", aml_int(1)));
 131     crs = aml_resource_template();
 132     aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
 133     aml_append(dev, aml_name_decl("_CRS", crs));
 134     aml_append(scope, dev);
 135 }
 136
 137 static void acpi_dsdt_add_virtio(Aml *scope,
 138                                  const MemMapEntry *virtio_mmio_memmap,
 139                                  int mmio_irq, int num)
 140 {
 141     hwaddr base = virtio_mmio_memmap->base;
 142     hwaddr size = virtio_mmio_memmap->size;
 143     int irq = mmio_irq;
 144     int i;
 145
 146     for (i = 0; i < num; i++) {
 147         Aml *dev = aml_device("VR%02u", i);
 148         aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
 149         aml_append(dev, aml_name_decl("_UID", aml_int(i)));
 150
 151         Aml *crs = aml_resource_template();
 152         aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
 153         aml_append(crs,
 154                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 155                                  AML_EXCLUSIVE, irq + i));
 156         aml_append(dev, aml_name_decl("_CRS", crs));
 157         aml_append(scope, dev);
 158         base += size;
 159     }
 160 }
 161
 162 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq,
 163                               bool use_highmem)
 164 {
 165     Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
 166     int i, bus_no;
 167     hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
 168     hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
 169     hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
 170     hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
 171     hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
 172     hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
 173     int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
 174
 175     Aml *dev = aml_device("%s", "PCI0");
 176     aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
 177     aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
 178     aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
 179     aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
 180     aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
 181     aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
 182     aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
 183
 184     /* Declare the PCI Routing Table. */
 185     Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
 186     for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
 187         for (i = 0; i < PCI_NUM_PINS; i++) {
 188             int gsi = (i + bus_no) % PCI_NUM_PINS;
 189             Aml *pkg = aml_package(4);
 190             aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
 191             aml_append(pkg, aml_int(i));
 192             aml_append(pkg, aml_name("GSI%d", gsi));
 193             aml_append(pkg, aml_int(0));
 194             aml_append(rt_pkg, pkg);
 195         }
 196     }
 197     aml_append(dev, aml_name_decl("_PRT", rt_pkg));
 198
 199     /* Create GSI link device */
 200     for (i = 0; i < PCI_NUM_PINS; i++) {
 201         Aml *dev_gsi = aml_device("GSI%d", i);
 202         aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
 203         aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
 204         crs = aml_resource_template();
 205         aml_append(crs,
 206                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 207                                  AML_EXCLUSIVE, irq + i));
 208         aml_append(dev_gsi, aml_name_decl("_PRS", crs));
 209         crs = aml_resource_template();
 210         aml_append(crs,
 211                    aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
 212                                  AML_EXCLUSIVE, irq + i));
 213         aml_append(dev_gsi, aml_name_decl("_CRS", crs));
 214         method = aml_method("_SRS", 1);
 215         aml_append(dev_gsi, method);
 216         aml_append(dev, dev_gsi);
 217     }
 218
 219     method = aml_method("_CBA", 0);
 220     aml_append(method, aml_return(aml_int(base_ecam)));
 221     aml_append(dev, method);
 222
 223     method = aml_method("_CRS", 0);
 224     Aml *rbuf = aml_resource_template();
 225     aml_append(rbuf,
 226         aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 227                             0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
 228                             nr_pcie_buses));
 229     aml_append(rbuf,
 230         aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 231                          AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
 232                          base_mmio + size_mmio - 1, 0x0000, size_mmio));
 233     aml_append(rbuf,
 234         aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
 235                      AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
 236                      size_pio));
 237
 238     if (use_highmem) {
 239         hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
 240         hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
 241
 242         aml_append(rbuf,
 243             aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
 244                              AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
 245                              base_mmio_high, base_mmio_high, 0x0000,
 246                              size_mmio_high));
 247     }
 248
 249     aml_append(method, aml_name_decl("RBUF", rbuf));
 250     aml_append(method, aml_return(rbuf));
 251     aml_append(dev, method);
 252
 253     /* Declare an _OSC (OS Control Handoff) method */
 254     aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
 255     aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
 256     method = aml_method("_OSC", 4);
 257     aml_append(method,
 258         aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
 259
 260     /* PCI Firmware Specification 3.0
 261      * 4.5.1. _OSC Interface for PCI Host Bridge Devices
 262      * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
 263      * identified by the Universal Unique IDentifier (UUID)
 264      * 33DB4D5B-1FF7-401C-9657-7441C03DD766
 265      */
 266     UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
 267     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 268     aml_append(ifctx,
 269         aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
 270     aml_append(ifctx,
 271         aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
 272     aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
 273     aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
 274     aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
 275                                 aml_name("CTRL")));
 276
 277     ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
 278     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
 279                                  aml_name("CDW1")));
 280     aml_append(ifctx, ifctx1);
 281
 282     ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
 283     aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
 284                                  aml_name("CDW1")));
 285     aml_append(ifctx, ifctx1);
 286
 287     aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
 288     aml_append(ifctx, aml_return(aml_arg(3)));
 289     aml_append(method, ifctx);
 290
 291     elsectx = aml_else();
 292     aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
 293                                   aml_name("CDW1")));
 294     aml_append(elsectx, aml_return(aml_arg(3)));
 295     aml_append(method, elsectx);
 296     aml_append(dev, method);
 297
 298     method = aml_method("_DSM", 4);
 299
 300     /* PCI Firmware Specification 3.0
 301      * 4.6.1. _DSM for PCI Express Slot Information
 302      * The UUID in _DSM in this context is
 303      * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
 304      */
 305     UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
 306     ifctx = aml_if(aml_equal(aml_arg(0), UUID));
 307     ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
 308     uint8_t byte_list[1] = {1};
 309     buf = aml_buffer(1, byte_list);
 310     aml_append(ifctx1, aml_return(buf));
 311     aml_append(ifctx, ifctx1);
 312     aml_append(method, ifctx);
 313
 314     byte_list[0] = 0;
 315     buf = aml_buffer(1, byte_list);
 316     aml_append(method, aml_return(buf));
 317     aml_append(dev, method);
 318
 319     Aml *dev_rp0 = aml_device("%s", "RP0");
 320     aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
 321     aml_append(dev, dev_rp0);
 322     aml_append(scope, dev);
 323 }
 324
 325 /* RSDP */
 326 static GArray *
 327 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
 328 {
 329     AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
 330
 331     bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
 332                              true /* fseg memory */);
 333
 334     memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
 335     memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
 336     rsdp->length = cpu_to_le32(sizeof(*rsdp));
 337     rsdp->revision = 0x02;
 338
 339     /* Point to RSDT */
 340     rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
 341     /* Address to be filled by Guest linker */
 342     bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
 343                                    ACPI_BUILD_TABLE_FILE,
 344                                    rsdp_table, &rsdp->rsdt_physical_address,
 345                                    sizeof rsdp->rsdt_physical_address);
 346     rsdp->checksum = 0;
 347     /* Checksum to be filled by Guest linker */
 348     bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
 349                                     rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
 350
 351     return rsdp_table;
 352 }
 353
 354 static void
 355 build_spcr(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 356 {
 357     AcpiSerialPortConsoleRedirection *spcr;
 358     const MemMapEntry *uart_memmap = &guest_info->memmap[VIRT_UART];
 359     int irq = guest_info->irqmap[VIRT_UART] + ARM_SPI_BASE;
 360
 361     spcr = acpi_data_push(table_data, sizeof(*spcr));
 362
 363     spcr->interface_type = 0x3;    /* ARM PL011 UART */
 364
 365     spcr->base_address.space_id = AML_SYSTEM_MEMORY;
 366     spcr->base_address.bit_width = 8;
 367     spcr->base_address.bit_offset = 0;
 368     spcr->base_address.access_width = 1;
 369     spcr->base_address.address = cpu_to_le64(uart_memmap->base);
 370
 371     spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
 372     spcr->gsi = cpu_to_le32(irq);  /* Global System Interrupt */
 373
 374     spcr->baud = 3;                /* Baud Rate: 3 = 9600 */
 375     spcr->parity = 0;              /* No Parity */
 376     spcr->stopbits = 1;            /* 1 Stop bit */
 377     spcr->flowctrl = (1 << 1);     /* Bit[1] = RTS/CTS hardware flow control */
 378     spcr->term_type = 0;           /* Terminal Type: 0 = VT100 */
 379
 380     spcr->pci_device_id = 0xffff;  /* PCI Device ID: not a PCI device */
 381     spcr->pci_vendor_id = 0xffff;  /* PCI Vendor ID: not a PCI device */
 382
 383     build_header(linker, table_data, (void *)spcr, "SPCR", sizeof(*spcr), 2);
 384 }
 385
 386 static void
 387 build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 388 {
 389     AcpiTableMcfg *mcfg;
 390     const MemMapEntry *memmap = guest_info->memmap;
 391     int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
 392
 393     mcfg = acpi_data_push(table_data, len);
 394     mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
 395
 396     /* Only a single allocation so no need to play with segments */
 397     mcfg->allocation[0].pci_segment = cpu_to_le16(0);
 398     mcfg->allocation[0].start_bus_number = 0;
 399     mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
 400                                           / PCIE_MMCFG_SIZE_MIN) - 1;
 401
 402     build_header(linker, table_data, (void *)mcfg, "MCFG", len, 1);
 403 }
 404
 405 /* GTDT */
 406 static void
 407 build_gtdt(GArray *table_data, GArray *linker)
 408 {
 409     int gtdt_start = table_data->len;
 410     AcpiGenericTimerTable *gtdt;
 411
 412     gtdt = acpi_data_push(table_data, sizeof *gtdt);
 413     /* The interrupt values are the same with the device tree when adding 16 */
 414     gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16;
 415     gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
 416
 417     gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16;
 418     gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
 419
 420     gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16;
 421     gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
 422
 423     gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16;
 424     gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
 425
 426     build_header(linker, table_data,
 427                  (void *)(table_data->data + gtdt_start), "GTDT",
 428                  table_data->len - gtdt_start, 2);
 429 }
 430
 431 /* MADT */
 432 static void
 433 build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
 434            VirtAcpiCpuInfo *cpuinfo)
 435 {
 436     int madt_start = table_data->len;
 437     const MemMapEntry *memmap = guest_info->memmap;
 438     const int *irqmap = guest_info->irqmap;
 439     AcpiMultipleApicTable *madt;
 440     AcpiMadtGenericDistributor *gicd;
 441     AcpiMadtGenericMsiFrame *gic_msi;
 442     int i;
 443
 444     madt = acpi_data_push(table_data, sizeof *madt);
 445
 446     gicd = acpi_data_push(table_data, sizeof *gicd);
 447     gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
 448     gicd->length = sizeof(*gicd);
 449     gicd->base_address = memmap[VIRT_GIC_DIST].base;
 450
 451     if (guest_info->gic_version == 3) {
 452         AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
 453                                                          sizeof *gicr);
 454
 455         gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
 456         gicr->length = sizeof(*gicr);
 457         gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
 458         gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
 459     } else {
 460         for (i = 0; i < guest_info->smp_cpus; i++) {
 461             AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
 462                                                          sizeof *gicc);
 463             gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
 464             gicc->length = sizeof(*gicc);
 465             gicc->base_address = memmap[VIRT_GIC_CPU].base;
 466             gicc->cpu_interface_number = i;
 467             gicc->arm_mpidr = i;
 468             gicc->uid = i;
 469             if (test_bit(i, cpuinfo->found_cpus)) {
 470                 gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
 471             }
 472         }
 473
 474         gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
 475         gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
 476         gic_msi->length = sizeof(*gic_msi);
 477         gic_msi->gic_msi_frame_id = 0;
 478         gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
 479         gic_msi->flags = cpu_to_le32(1);
 480         gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
 481         gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
 482     }
 483
 484     build_header(linker, table_data,
 485                  (void *)(table_data->data + madt_start), "APIC",
 486                  table_data->len - madt_start, 3);
 487 }
 488
 489 /* FADT */
 490 static void
 491 build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
 492 {
 493     AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
 494
 495     /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
 496     fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
 497     fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
 498                                        (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
 499
 500     /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
 501     fadt->minor_revision = 0x1;
 502
 503     fadt->dsdt = cpu_to_le32(dsdt);
 504     /* DSDT address to be filled by Guest linker */
 505     bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
 506                                    ACPI_BUILD_TABLE_FILE,
 507                                    table_data, &fadt->dsdt,
 508                                    sizeof fadt->dsdt);
 509
 510     build_header(linker, table_data,
 511                  (void *)fadt, "FACP", sizeof(*fadt), 5);
 512 }
 513
 514 /* DSDT */
 515 static void
 516 build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
 517 {
 518     Aml *scope, *dsdt;
 519     const MemMapEntry *memmap = guest_info->memmap;
 520     const int *irqmap = guest_info->irqmap;
 521
 522     dsdt = init_aml_allocator();
 523     /* Reserve space for header */
 524     acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
 525
 526     scope = aml_scope("\\_SB");
 527     acpi_dsdt_add_cpus(scope, guest_info->smp_cpus);
 528     acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
 529                        (irqmap[VIRT_UART] + ARM_SPI_BASE));
 530     acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC],
 531                       (irqmap[VIRT_RTC] + ARM_SPI_BASE));
 532     acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
 533     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
 534                     (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
 535     acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
 536                       guest_info->use_highmem);
 537
 538     aml_append(dsdt, scope);
 539
 540     /* copy AML table into ACPI tables blob and patch header there */
 541     g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
 542     build_header(linker, table_data,
 543         (void *)(table_data->data + table_data->len - dsdt->buf->len),
 544         "DSDT", dsdt->buf->len, 2);
 545     free_aml_allocator();
 546 }
 547
 548 typedef
 549 struct AcpiBuildState {
 550     /* Copy of table in RAM (for patching). */
 551     MemoryRegion *table_mr;
 552     MemoryRegion *rsdp_mr;
 553     MemoryRegion *linker_mr;
 554     /* Is table patched? */
 555     bool patched;
 556     VirtGuestInfo *guest_info;
 557 } AcpiBuildState;
 558
 559 static
 560 void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
 561 {
 562     GArray *table_offsets;
 563     unsigned dsdt, rsdt;
 564     VirtAcpiCpuInfo cpuinfo;
 565     GArray *tables_blob = tables->table_data;
 566
 567     virt_acpi_get_cpu_info(&cpuinfo);
 568
 569     table_offsets = g_array_new(false, true /* clear */,
 570                                         sizeof(uint32_t));
 571
 572     bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
 573                              64, false /* high memory */);
 574
 575     /*
 576      * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
 577      * RSDP
 578      * RSDT
 579      * FADT
 580      * GTDT
 581      * MADT
 582      * MCFG
 583      * DSDT
 584      */
 585
 586     /* DSDT is pointed to by FADT */
 587     dsdt = tables_blob->len;
 588     build_dsdt(tables_blob, tables->linker, guest_info);
 589
 590     /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
 591     acpi_add_table(table_offsets, tables_blob);
 592     build_fadt(tables_blob, tables->linker, dsdt);
 593
 594     acpi_add_table(table_offsets, tables_blob);
 595     build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
 596
 597     acpi_add_table(table_offsets, tables_blob);
 598     build_gtdt(tables_blob, tables->linker);
 599
 600     acpi_add_table(table_offsets, tables_blob);
 601     build_mcfg(tables_blob, tables->linker, guest_info);
 602
 603     acpi_add_table(table_offsets, tables_blob);
 604     build_spcr(tables_blob, tables->linker, guest_info);
 605
 606     /* RSDT is pointed to by RSDP */
 607     rsdt = tables_blob->len;
 608     build_rsdt(tables_blob, tables->linker, table_offsets);
 609
 610     /* RSDP is in FSEG memory, so allocate it separately */
 611     build_rsdp(tables->rsdp, tables->linker, rsdt);
 612
 613     /* Cleanup memory that's no longer used. */
 614     g_array_free(table_offsets, true);
 615 }
 616
 617 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
 618 {
 619     uint32_t size = acpi_data_len(data);
 620
 621     /* Make sure RAM size is correct - in case it got changed
 622      * e.g. by migration */
 623     memory_region_ram_resize(mr, size, &error_abort);
 624
 625     memcpy(memory_region_get_ram_ptr(mr), data->data, size);
 626     memory_region_set_dirty(mr, 0, size);
 627 }
 628
 629 static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
 630 {
 631     AcpiBuildState *build_state = build_opaque;
 632     AcpiBuildTables tables;
 633
 634     /* No state to update or already patched? Nothing to do. */
 635     if (!build_state || build_state->patched) {
 636         return;
 637     }
 638     build_state->patched = true;
 639
 640     acpi_build_tables_init(&tables);
 641
 642     virt_acpi_build(build_state->guest_info, &tables);
 643
 644     acpi_ram_update(build_state->table_mr, tables.table_data);
 645     acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
 646     acpi_ram_update(build_state->linker_mr, tables.linker);
 647
 648
 649     acpi_build_tables_cleanup(&tables, true);
 650 }
 651
 652 static void virt_acpi_build_reset(void *build_opaque)
 653 {
 654     AcpiBuildState *build_state = build_opaque;
 655     build_state->patched = false;
 656 }
 657
 658 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
 659                                        GArray *blob, const char *name,
 660                                        uint64_t max_size)
 661 {
 662     return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
 663                         name, virt_acpi_build_update, build_state);
 664 }
 665
 666 static const VMStateDescription vmstate_virt_acpi_build = {
 667     .name = "virt_acpi_build",
 668     .version_id = 1,
 669     .minimum_version_id = 1,
 670     .fields = (VMStateField[]) {
 671         VMSTATE_BOOL(patched, AcpiBuildState),
 672         VMSTATE_END_OF_LIST()
 673     },
 674 };
 675
 676 void virt_acpi_setup(VirtGuestInfo *guest_info)
 677 {
 678     AcpiBuildTables tables;
 679     AcpiBuildState *build_state;
 680
 681     if (!guest_info->fw_cfg) {
 682         trace_virt_acpi_setup();
 683         return;
 684     }
 685
 686     if (!acpi_enabled) {
 687         trace_virt_acpi_setup();
 688         return;
 689     }
 690
 691     build_state = g_malloc0(sizeof *build_state);
 692     build_state->guest_info = guest_info;
 693
 694     acpi_build_tables_init(&tables);
 695     virt_acpi_build(build_state->guest_info, &tables);
 696
 697     /* Now expose it all to Guest */
 698     build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
 699                                                ACPI_BUILD_TABLE_FILE,
 700                                                ACPI_BUILD_TABLE_MAX_SIZE);
 701     assert(build_state->table_mr != NULL);
 702
 703     build_state->linker_mr =
 704         acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
 705
 706     fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
 707                     tables.tcpalog->data, acpi_data_len(tables.tcpalog));
 708
 709     build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
 710                                               ACPI_BUILD_RSDP_FILE, 0);
 711
 712     qemu_register_reset(virt_acpi_build_reset, build_state);
 713     virt_acpi_build_reset(build_state);
 714     vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
 715
 716     /* Cleanup tables but don't free the memory: we track it
 717      * in build_state.
 718      */
 719     acpi_build_tables_cleanup(&tables, false);
 720 }