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pc: acpi-build: drop template patching and memory hotplug objects dynamically
[qemu/ar7.git] / hw / i386 / acpi-build.c
blob377dd72ea6fbca94ca26695fe158cb38ea8d497b
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/range.h"
30 #include "qemu/error-report.h"
31 #include "hw/pci/pci.h"
32 #include "qom/cpu.h"
33 #include "hw/i386/pc.h"
34 #include "target-i386/cpu.h"
35 #include "hw/timer/hpet.h"
36 #include "hw/i386/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/isa/isa.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45
46 /* Supported chipsets: */
47 #include "hw/acpi/piix4.h"
48 #include "hw/acpi/pcihp.h"
49 #include "hw/i386/ich9.h"
50 #include "hw/pci/pci_bus.h"
51 #include "hw/pci-host/q35.h"
52 #include "hw/i386/intel_iommu.h"
53
54 #include "hw/i386/q35-acpi-dsdt.hex"
55 #include "hw/i386/acpi-dsdt.hex"
56
57 #include "hw/acpi/aml-build.h"
58
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
61 #include "exec/ram_addr.h"
62
63 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
64 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
65 * a little bit, there should be plenty of free space since the DSDT
66 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 */
68 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
69 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70
71 #define ACPI_BUILD_TABLE_SIZE 0x20000
72
73 /* Reserve RAM space for tables: add another order of magnitude. */
74 #define ACPI_BUILD_TABLE_MAX_SIZE 0x200000
75
76 /* #define DEBUG_ACPI_BUILD */
77 #ifdef DEBUG_ACPI_BUILD
78 #define ACPI_BUILD_DPRINTF(fmt, ...) \
79 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
80 #else
81 #define ACPI_BUILD_DPRINTF(fmt, ...)
82 #endif
83
84 typedef struct AcpiCpuInfo {
85 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
86 } AcpiCpuInfo;
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t cpu_hp_io_len;
106 } AcpiPmInfo;
107
108 typedef struct AcpiMiscInfo {
109 bool has_hpet;
110 bool has_tpm;
111 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
112 const unsigned char *dsdt_code;
113 unsigned dsdt_size;
114 uint16_t pvpanic_port;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 static void acpi_get_dsdt(AcpiMiscInfo *info)
125 {
126 uint16_t *applesmc_sta;
127 Object *piix = piix4_pm_find();
128 Object *lpc = ich9_lpc_find();
129 assert(!!piix != !!lpc);
130
131 if (piix) {
132 info->dsdt_code = AcpiDsdtAmlCode;
133 info->dsdt_size = sizeof AcpiDsdtAmlCode;
134 applesmc_sta = piix_dsdt_applesmc_sta;
135 }
136 if (lpc) {
137 info->dsdt_code = Q35AcpiDsdtAmlCode;
138 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
139 applesmc_sta = q35_dsdt_applesmc_sta;
140 }
141
142 /* Patch in appropriate value for AppleSMC _STA */
143 *(uint8_t *)(info->dsdt_code + *applesmc_sta) =
144 applesmc_find() ? 0x0b : 0x00;
145 }
146
147 static
148 int acpi_add_cpu_info(Object *o, void *opaque)
149 {
150 AcpiCpuInfo *cpu = opaque;
151 uint64_t apic_id;
152
153 if (object_dynamic_cast(o, TYPE_CPU)) {
154 apic_id = object_property_get_int(o, "apic-id", NULL);
155 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
156
157 set_bit(apic_id, cpu->found_cpus);
158 }
159
160 object_child_foreach(o, acpi_add_cpu_info, opaque);
161 return 0;
162 }
163
164 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
165 {
166 Object *root = object_get_root();
167
168 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
169 object_child_foreach(root, acpi_add_cpu_info, cpu);
170 }
171
172 static void acpi_get_pm_info(AcpiPmInfo *pm)
173 {
174 Object *piix = piix4_pm_find();
175 Object *lpc = ich9_lpc_find();
176 Object *obj = NULL;
177 QObject *o;
178
179 if (piix) {
180 obj = piix;
181 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
182 }
183 if (lpc) {
184 obj = lpc;
185 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
186 }
187 assert(obj);
188
189 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
190 /* Fill in optional s3/s4 related properties */
191 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
192 if (o) {
193 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
194 } else {
195 pm->s3_disabled = false;
196 }
197 qobject_decref(o);
198 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
199 if (o) {
200 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
201 } else {
202 pm->s4_disabled = false;
203 }
204 qobject_decref(o);
205 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
206 if (o) {
207 pm->s4_val = qint_get_int(qobject_to_qint(o));
208 } else {
209 pm->s4_val = false;
210 }
211 qobject_decref(o);
212
213 /* Fill in mandatory properties */
214 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
215
216 pm->acpi_enable_cmd = object_property_get_int(obj,
217 ACPI_PM_PROP_ACPI_ENABLE_CMD,
218 NULL);
219 pm->acpi_disable_cmd = object_property_get_int(obj,
220 ACPI_PM_PROP_ACPI_DISABLE_CMD,
221 NULL);
222 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
223 NULL);
224 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
225 NULL);
226 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
227 NULL);
228 pm->pcihp_bridge_en =
229 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
230 NULL);
231 }
232
233 static void acpi_get_misc_info(AcpiMiscInfo *info)
234 {
235 info->has_hpet = hpet_find();
236 info->has_tpm = tpm_find();
237 info->pvpanic_port = pvpanic_port();
238 }
239
240 static void acpi_get_pci_info(PcPciInfo *info)
241 {
242 Object *pci_host;
243 bool ambiguous;
244
245 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
246 g_assert(!ambiguous);
247 g_assert(pci_host);
248
249 info->w32.begin = object_property_get_int(pci_host,
250 PCI_HOST_PROP_PCI_HOLE_START,
251 NULL);
252 info->w32.end = object_property_get_int(pci_host,
253 PCI_HOST_PROP_PCI_HOLE_END,
254 NULL);
255 info->w64.begin = object_property_get_int(pci_host,
256 PCI_HOST_PROP_PCI_HOLE64_START,
257 NULL);
258 info->w64.end = object_property_get_int(pci_host,
259 PCI_HOST_PROP_PCI_HOLE64_END,
260 NULL);
261 }
262
263 #define ACPI_BUILD_APPNAME "Bochs"
264 #define ACPI_BUILD_APPNAME6 "BOCHS "
265 #define ACPI_BUILD_APPNAME4 "BXPC"
266
267 #define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
268 #define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
269 #define ACPI_BUILD_TPMLOG_FILE "etc/tpm/log"
270
271 static void
272 build_header(GArray *linker, GArray *table_data,
273 AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
274 {
275 memcpy(&h->signature, sig, 4);
276 h->length = cpu_to_le32(len);
277 h->revision = rev;
278 memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
279 memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
280 memcpy(h->oem_table_id + 4, sig, 4);
281 h->oem_revision = cpu_to_le32(1);
282 memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
283 h->asl_compiler_revision = cpu_to_le32(1);
284 h->checksum = 0;
285 /* Checksum to be filled in by Guest linker */
286 bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
287 table_data->data, h, len, &h->checksum);
288 }
289
290 static GArray *build_alloc_method(const char *name, uint8_t arg_count)
291 {
292 GArray *method = build_alloc_array();
293
294 build_append_namestring(method, "%s", name);
295 build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
296
297 return method;
298 }
299
300 static void build_append_and_cleanup_method(GArray *device, GArray *method)
301 {
302 uint8_t op = 0x14; /* MethodOp */
303
304 build_package(method, op);
305
306 build_append_array(device, method);
307 build_free_array(method);
308 }
309
310 /* End here */
311 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
312
313 static inline void *acpi_data_push(GArray *table_data, unsigned size)
314 {
315 unsigned off = table_data->len;
316 g_array_set_size(table_data, off + size);
317 return table_data->data + off;
318 }
319
320 static unsigned acpi_data_len(GArray *table)
321 {
322 #if GLIB_CHECK_VERSION(2, 22, 0)
323 assert(g_array_get_element_size(table) == 1);
324 #endif
325 return table->len;
326 }
327
328 static void acpi_align_size(GArray *blob, unsigned align)
329 {
330 /* Align size to multiple of given size. This reduces the chance
331 * we need to change size in the future (breaking cross version migration).
332 */
333 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
334 }
335
336 /* Set a value within table in a safe manner */
337 #define ACPI_BUILD_SET_LE(table, size, off, bits, val) \
338 do { \
339 uint64_t ACPI_BUILD_SET_LE_val = cpu_to_le64(val); \
340 memcpy(acpi_data_get_ptr(table, size, off, \
341 (bits) / BITS_PER_BYTE), \
342 &ACPI_BUILD_SET_LE_val, \
343 (bits) / BITS_PER_BYTE); \
344 } while (0)
345
346 static inline void *acpi_data_get_ptr(uint8_t *table_data, unsigned table_size,
347 unsigned off, unsigned size)
348 {
349 assert(off + size > off);
350 assert(off + size <= table_size);
351 return table_data + off;
352 }
353
354 static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
355 {
356 uint32_t offset = cpu_to_le32(table_data->len);
357 g_array_append_val(table_offsets, offset);
358 }
359
360 /* FACS */
361 static void
362 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
363 {
364 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
365 memcpy(&facs->signature, "FACS", 4);
366 facs->length = cpu_to_le32(sizeof(*facs));
367 }
368
369 /* Load chipset information in FADT */
370 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
371 {
372 fadt->model = 1;
373 fadt->reserved1 = 0;
374 fadt->sci_int = cpu_to_le16(pm->sci_int);
375 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
376 fadt->acpi_enable = pm->acpi_enable_cmd;
377 fadt->acpi_disable = pm->acpi_disable_cmd;
378 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
379 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
380 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
381 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
382 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
383 /* EVT, CNT, TMR length matches hw/acpi/core.c */
384 fadt->pm1_evt_len = 4;
385 fadt->pm1_cnt_len = 2;
386 fadt->pm_tmr_len = 4;
387 fadt->gpe0_blk_len = pm->gpe0_blk_len;
388 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
389 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
390 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
391 (1 << ACPI_FADT_F_PROC_C1) |
392 (1 << ACPI_FADT_F_SLP_BUTTON) |
393 (1 << ACPI_FADT_F_RTC_S4));
394 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
395 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
396 * For more than 8 CPUs, "Clustered Logical" mode has to be used
397 */
398 if (max_cpus > 8) {
399 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
400 }
401 }
402
403
404 /* FADT */
405 static void
406 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
407 unsigned facs, unsigned dsdt)
408 {
409 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
410
411 fadt->firmware_ctrl = cpu_to_le32(facs);
412 /* FACS address to be filled by Guest linker */
413 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
414 ACPI_BUILD_TABLE_FILE,
415 table_data, &fadt->firmware_ctrl,
416 sizeof fadt->firmware_ctrl);
417
418 fadt->dsdt = cpu_to_le32(dsdt);
419 /* DSDT address to be filled by Guest linker */
420 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
421 ACPI_BUILD_TABLE_FILE,
422 table_data, &fadt->dsdt,
423 sizeof fadt->dsdt);
424
425 fadt_setup(fadt, pm);
426
427 build_header(linker, table_data,
428 (void *)fadt, "FACP", sizeof(*fadt), 1);
429 }
430
431 static void
432 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
433 PcGuestInfo *guest_info)
434 {
435 int madt_start = table_data->len;
436
437 AcpiMultipleApicTable *madt;
438 AcpiMadtIoApic *io_apic;
439 AcpiMadtIntsrcovr *intsrcovr;
440 AcpiMadtLocalNmi *local_nmi;
441 int i;
442
443 madt = acpi_data_push(table_data, sizeof *madt);
444 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
445 madt->flags = cpu_to_le32(1);
446
447 for (i = 0; i < guest_info->apic_id_limit; i++) {
448 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
449 apic->type = ACPI_APIC_PROCESSOR;
450 apic->length = sizeof(*apic);
451 apic->processor_id = i;
452 apic->local_apic_id = i;
453 if (test_bit(i, cpu->found_cpus)) {
454 apic->flags = cpu_to_le32(1);
455 } else {
456 apic->flags = cpu_to_le32(0);
457 }
458 }
459 io_apic = acpi_data_push(table_data, sizeof *io_apic);
460 io_apic->type = ACPI_APIC_IO;
461 io_apic->length = sizeof(*io_apic);
462 #define ACPI_BUILD_IOAPIC_ID 0x0
463 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
464 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
465 io_apic->interrupt = cpu_to_le32(0);
466
467 if (guest_info->apic_xrupt_override) {
468 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
469 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
470 intsrcovr->length = sizeof(*intsrcovr);
471 intsrcovr->source = 0;
472 intsrcovr->gsi = cpu_to_le32(2);
473 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
474 }
475 for (i = 1; i < 16; i++) {
476 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
477 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
478 /* No need for a INT source override structure. */
479 continue;
480 }
481 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
482 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
483 intsrcovr->length = sizeof(*intsrcovr);
484 intsrcovr->source = i;
485 intsrcovr->gsi = cpu_to_le32(i);
486 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
487 }
488
489 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
490 local_nmi->type = ACPI_APIC_LOCAL_NMI;
491 local_nmi->length = sizeof(*local_nmi);
492 local_nmi->processor_id = 0xff; /* all processors */
493 local_nmi->flags = cpu_to_le16(0);
494 local_nmi->lint = 1; /* ACPI_LINT1 */
495
496 build_header(linker, table_data,
497 (void *)(table_data->data + madt_start), "APIC",
498 table_data->len - madt_start, 1);
499 }
500
501 /* Encode a hex value */
502 static inline char acpi_get_hex(uint32_t val)
503 {
504 val &= 0x0f;
505 return (val <= 9) ? ('0' + val) : ('A' + val - 10);
506 }
507
508 /* 0x5B 0x82 DeviceOp PkgLength NameString */
509 #define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
510 #define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
511 #define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
512 #define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
513 #define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
514 #define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
515
516 #define ACPI_PCINOHP_OFFSET_HEX (*ssdt_pcinohp_name - *ssdt_pcinohp_start + 1)
517 #define ACPI_PCINOHP_OFFSET_ADR (*ssdt_pcinohp_adr - *ssdt_pcinohp_start)
518 #define ACPI_PCINOHP_SIZEOF (*ssdt_pcinohp_end - *ssdt_pcinohp_start)
519 #define ACPI_PCINOHP_AML (ssdp_pcihp_aml + *ssdt_pcinohp_start)
520
521 #define ACPI_PCIVGA_OFFSET_HEX (*ssdt_pcivga_name - *ssdt_pcivga_start + 1)
522 #define ACPI_PCIVGA_OFFSET_ADR (*ssdt_pcivga_adr - *ssdt_pcivga_start)
523 #define ACPI_PCIVGA_SIZEOF (*ssdt_pcivga_end - *ssdt_pcivga_start)
524 #define ACPI_PCIVGA_AML (ssdp_pcihp_aml + *ssdt_pcivga_start)
525
526 #define ACPI_PCIQXL_OFFSET_HEX (*ssdt_pciqxl_name - *ssdt_pciqxl_start + 1)
527 #define ACPI_PCIQXL_OFFSET_ADR (*ssdt_pciqxl_adr - *ssdt_pciqxl_start)
528 #define ACPI_PCIQXL_SIZEOF (*ssdt_pciqxl_end - *ssdt_pciqxl_start)
529 #define ACPI_PCIQXL_AML (ssdp_pcihp_aml + *ssdt_pciqxl_start)
530
531 #define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
532 #define ACPI_SSDT_HEADER_LENGTH 36
533
534 #include "hw/i386/ssdt-misc.hex"
535 #include "hw/i386/ssdt-pcihp.hex"
536 #include "hw/i386/ssdt-tpm.hex"
537
538 static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
539 {
540 unsigned devfn = PCI_DEVFN(slot, 0);
541
542 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
543 ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
544 ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
545 ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
546 }
547
548 static void patch_pcinohp(int slot, uint8_t *ssdt_ptr)
549 {
550 unsigned devfn = PCI_DEVFN(slot, 0);
551
552 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
553 ssdt_ptr[ACPI_PCINOHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
554 ssdt_ptr[ACPI_PCINOHP_OFFSET_ADR + 2] = slot;
555 }
556
557 static void patch_pcivga(int slot, uint8_t *ssdt_ptr)
558 {
559 unsigned devfn = PCI_DEVFN(slot, 0);
560
561 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
562 ssdt_ptr[ACPI_PCIVGA_OFFSET_HEX + 1] = acpi_get_hex(devfn);
563 ssdt_ptr[ACPI_PCIVGA_OFFSET_ADR + 2] = slot;
564 }
565
566 static void patch_pciqxl(int slot, uint8_t *ssdt_ptr)
567 {
568 unsigned devfn = PCI_DEVFN(slot, 0);
569
570 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
571 ssdt_ptr[ACPI_PCIQXL_OFFSET_HEX + 1] = acpi_get_hex(devfn);
572 ssdt_ptr[ACPI_PCIQXL_OFFSET_ADR + 2] = slot;
573 }
574
575 /* Assign BSEL property to all buses. In the future, this can be changed
576 * to only assign to buses that support hotplug.
577 */
578 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
579 {
580 unsigned *bsel_alloc = opaque;
581 unsigned *bus_bsel;
582
583 if (qbus_is_hotpluggable(BUS(bus))) {
584 bus_bsel = g_malloc(sizeof *bus_bsel);
585
586 *bus_bsel = (*bsel_alloc)++;
587 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
588 bus_bsel, NULL);
589 }
590
591 return bsel_alloc;
592 }
593
594 static void acpi_set_pci_info(void)
595 {
596 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
597 unsigned bsel_alloc = 0;
598
599 if (bus) {
600 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
601 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
602 }
603 }
604
605 static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
606 AcpiBuildPciBusHotplugState *parent,
607 bool pcihp_bridge_en)
608 {
609 state->parent = parent;
610 state->device_table = build_alloc_array();
611 state->notify_table = build_alloc_array();
612 state->pcihp_bridge_en = pcihp_bridge_en;
613 }
614
615 static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
616 {
617 build_free_array(state->device_table);
618 build_free_array(state->notify_table);
619 }
620
621 static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
622 {
623 AcpiBuildPciBusHotplugState *parent = parent_state;
624 AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
625
626 build_pci_bus_state_init(child, parent, parent->pcihp_bridge_en);
627
628 return child;
629 }
630
631 static void build_pci_bus_end(PCIBus *bus, void *bus_state)
632 {
633 AcpiBuildPciBusHotplugState *child = bus_state;
634 AcpiBuildPciBusHotplugState *parent = child->parent;
635 GArray *bus_table = build_alloc_array();
636 DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
637 DECLARE_BITMAP(slot_device_present, PCI_SLOT_MAX);
638 DECLARE_BITMAP(slot_device_system, PCI_SLOT_MAX);
639 DECLARE_BITMAP(slot_device_vga, PCI_SLOT_MAX);
640 DECLARE_BITMAP(slot_device_qxl, PCI_SLOT_MAX);
641 uint8_t op;
642 int i;
643 QObject *bsel;
644 GArray *method;
645 bool bus_hotplug_support = false;
646
647 /*
648 * Skip bridge subtree creation if bridge hotplug is disabled
649 * to make acpi tables compatible with legacy machine types.
650 * Skip creation for hotplugged bridges as well.
651 */
652 if (bus->parent_dev && (!child->pcihp_bridge_en ||
653 DEVICE(bus->parent_dev)->hotplugged)) {
654 build_free_array(bus_table);
655 build_pci_bus_state_cleanup(child);
656 g_free(child);
657 return;
658 }
659
660 if (bus->parent_dev) {
661 op = 0x82; /* DeviceOp */
662 build_append_namestring(bus_table, "S%.02X",
663 bus->parent_dev->devfn);
664 build_append_byte(bus_table, 0x08); /* NameOp */
665 build_append_namestring(bus_table, "_SUN");
666 build_append_int(bus_table, PCI_SLOT(bus->parent_dev->devfn));
667 build_append_byte(bus_table, 0x08); /* NameOp */
668 build_append_namestring(bus_table, "_ADR");
669 build_append_int(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
670 PCI_FUNC(bus->parent_dev->devfn));
671 } else {
672 op = 0x10; /* ScopeOp */;
673 build_append_namestring(bus_table, "PCI0");
674 }
675
676 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
677 if (bsel) {
678 build_append_byte(bus_table, 0x08); /* NameOp */
679 build_append_namestring(bus_table, "BSEL");
680 build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
681 memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
682 } else {
683 /* No bsel - no slots are hot-pluggable */
684 memset(slot_hotplug_enable, 0x00, sizeof slot_hotplug_enable);
685 }
686
687 memset(slot_device_present, 0x00, sizeof slot_device_present);
688 memset(slot_device_system, 0x00, sizeof slot_device_present);
689 memset(slot_device_vga, 0x00, sizeof slot_device_vga);
690 memset(slot_device_qxl, 0x00, sizeof slot_device_qxl);
691
692 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
693 DeviceClass *dc;
694 PCIDeviceClass *pc;
695 PCIDevice *pdev = bus->devices[i];
696 int slot = PCI_SLOT(i);
697 bool bridge_in_acpi;
698
699 if (!pdev) {
700 continue;
701 }
702
703 set_bit(slot, slot_device_present);
704 pc = PCI_DEVICE_GET_CLASS(pdev);
705 dc = DEVICE_GET_CLASS(pdev);
706
707 /* When hotplug for bridges is enabled, bridges are
708 * described in ACPI separately (see build_pci_bus_end).
709 * In this case they aren't themselves hot-pluggable.
710 * Hotplugged bridges *are* hot-pluggable.
711 */
712 bridge_in_acpi = pc->is_bridge && child->pcihp_bridge_en &&
713 !DEVICE(pdev)->hotplugged;
714
715 if (pc->class_id == PCI_CLASS_BRIDGE_ISA || bridge_in_acpi) {
716 set_bit(slot, slot_device_system);
717 }
718
719 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
720 set_bit(slot, slot_device_vga);
721
722 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
723 set_bit(slot, slot_device_qxl);
724 }
725 }
726
727 if (!dc->hotpluggable || bridge_in_acpi) {
728 clear_bit(slot, slot_hotplug_enable);
729 }
730 }
731
732 /* Append Device object for each slot */
733 for (i = 0; i < PCI_SLOT_MAX; i++) {
734 bool can_eject = test_bit(i, slot_hotplug_enable);
735 bool present = test_bit(i, slot_device_present);
736 bool vga = test_bit(i, slot_device_vga);
737 bool qxl = test_bit(i, slot_device_qxl);
738 bool system = test_bit(i, slot_device_system);
739 if (can_eject) {
740 void *pcihp = acpi_data_push(bus_table,
741 ACPI_PCIHP_SIZEOF);
742 memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
743 patch_pcihp(i, pcihp);
744 bus_hotplug_support = true;
745 } else if (qxl) {
746 void *pcihp = acpi_data_push(bus_table,
747 ACPI_PCIQXL_SIZEOF);
748 memcpy(pcihp, ACPI_PCIQXL_AML, ACPI_PCIQXL_SIZEOF);
749 patch_pciqxl(i, pcihp);
750 } else if (vga) {
751 void *pcihp = acpi_data_push(bus_table,
752 ACPI_PCIVGA_SIZEOF);
753 memcpy(pcihp, ACPI_PCIVGA_AML, ACPI_PCIVGA_SIZEOF);
754 patch_pcivga(i, pcihp);
755 } else if (system) {
756 /* Nothing to do: system devices are in DSDT or in SSDT above. */
757 } else if (present) {
758 void *pcihp = acpi_data_push(bus_table,
759 ACPI_PCINOHP_SIZEOF);
760 memcpy(pcihp, ACPI_PCINOHP_AML, ACPI_PCINOHP_SIZEOF);
761 patch_pcinohp(i, pcihp);
762 }
763 }
764
765 if (bsel) {
766 method = build_alloc_method("DVNT", 2);
767
768 for (i = 0; i < PCI_SLOT_MAX; i++) {
769 GArray *notify;
770 uint8_t op;
771
772 if (!test_bit(i, slot_hotplug_enable)) {
773 continue;
774 }
775
776 notify = build_alloc_array();
777 op = 0xA0; /* IfOp */
778
779 build_append_byte(notify, 0x7B); /* AndOp */
780 build_append_byte(notify, 0x68); /* Arg0Op */
781 build_append_int(notify, 0x1U << i);
782 build_append_byte(notify, 0x00); /* NullName */
783 build_append_byte(notify, 0x86); /* NotifyOp */
784 build_append_namestring(notify, "S%.02X", PCI_DEVFN(i, 0));
785 build_append_byte(notify, 0x69); /* Arg1Op */
786
787 /* Pack it up */
788 build_package(notify, op);
789
790 build_append_array(method, notify);
791
792 build_free_array(notify);
793 }
794
795 build_append_and_cleanup_method(bus_table, method);
796 }
797
798 /* Append PCNT method to notify about events on local and child buses.
799 * Add unconditionally for root since DSDT expects it.
800 */
801 if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
802 method = build_alloc_method("PCNT", 0);
803
804 /* If bus supports hotplug select it and notify about local events */
805 if (bsel) {
806 build_append_byte(method, 0x70); /* StoreOp */
807 build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
808 build_append_namestring(method, "BNUM");
809 build_append_namestring(method, "DVNT");
810 build_append_namestring(method, "PCIU");
811 build_append_int(method, 1); /* Device Check */
812 build_append_namestring(method, "DVNT");
813 build_append_namestring(method, "PCID");
814 build_append_int(method, 3); /* Eject Request */
815 }
816
817 /* Notify about child bus events in any case */
818 build_append_array(method, child->notify_table);
819
820 build_append_and_cleanup_method(bus_table, method);
821
822 /* Append description of child buses */
823 build_append_array(bus_table, child->device_table);
824
825 /* Pack it up */
826 if (bus->parent_dev) {
827 build_extop_package(bus_table, op);
828 } else {
829 build_package(bus_table, op);
830 }
831
832 /* Append our bus description to parent table */
833 build_append_array(parent->device_table, bus_table);
834
835 /* Also tell parent how to notify us, invoking PCNT method.
836 * At the moment this is not needed for root as we have a single root.
837 */
838 if (bus->parent_dev) {
839 build_append_namestring(parent->notify_table, "^PCNT.S%.02X",
840 bus->parent_dev->devfn);
841 }
842 }
843
844 qobject_decref(bsel);
845 build_free_array(bus_table);
846 build_pci_bus_state_cleanup(child);
847 g_free(child);
848 }
849
850 static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
851 {
852 ACPI_BUILD_SET_LE(start, size, acpi_pci32_start[0], 32, pci->w32.begin);
853
854 ACPI_BUILD_SET_LE(start, size, acpi_pci32_end[0], 32, pci->w32.end - 1);
855
856 if (pci->w64.end || pci->w64.begin) {
857 ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 1);
858 ACPI_BUILD_SET_LE(start, size, acpi_pci64_start[0], 64, pci->w64.begin);
859 ACPI_BUILD_SET_LE(start, size, acpi_pci64_end[0], 64, pci->w64.end - 1);
860 ACPI_BUILD_SET_LE(start, size, acpi_pci64_length[0], 64, pci->w64.end - pci->w64.begin);
861 } else {
862 ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 0);
863 }
864 }
865
866 static void
867 build_ssdt(GArray *table_data, GArray *linker,
868 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
869 PcPciInfo *pci, PcGuestInfo *guest_info)
870 {
871 MachineState *machine = MACHINE(qdev_get_machine());
872 uint32_t nr_mem = machine->ram_slots;
873 unsigned acpi_cpus = guest_info->apic_id_limit;
874 uint8_t *ssdt_ptr;
875 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field, *ifctx;
876 int i;
877
878 ssdt = init_aml_allocator();
879 /* The current AML generator can cover the APIC ID range [0..255],
880 * inclusive, for VCPU hotplug. */
881 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
882 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
883
884 /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
885 ssdt_ptr = acpi_data_push(ssdt->buf, sizeof(ssdp_misc_aml));
886 memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
887
888 patch_pci_windows(pci, ssdt_ptr, sizeof(ssdp_misc_aml));
889
890 ACPI_BUILD_SET_LE(ssdt_ptr, sizeof(ssdp_misc_aml),
891 ssdt_mctrl_nr_slots[0], 32, nr_mem);
892
893 /* create S3_ / S4_ / S5_ packages if necessary */
894 scope = aml_scope("\\");
895 if (!pm->s3_disabled) {
896 pkg = aml_package(4);
897 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
898 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
899 aml_append(pkg, aml_int(0)); /* reserved */
900 aml_append(pkg, aml_int(0)); /* reserved */
901 aml_append(scope, aml_name_decl("_S3", pkg));
902 }
903
904 if (!pm->s4_disabled) {
905 pkg = aml_package(4);
906 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
907 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
908 aml_append(pkg, aml_int(pm->s4_val));
909 aml_append(pkg, aml_int(0)); /* reserved */
910 aml_append(pkg, aml_int(0)); /* reserved */
911 aml_append(scope, aml_name_decl("_S4", pkg));
912 }
913
914 pkg = aml_package(4);
915 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
916 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
917 aml_append(pkg, aml_int(0)); /* reserved */
918 aml_append(pkg, aml_int(0)); /* reserved */
919 aml_append(scope, aml_name_decl("_S5", pkg));
920 aml_append(ssdt, scope);
921
922 if (misc->pvpanic_port) {
923 scope = aml_scope("\\_SB.PCI0.ISA");
924
925 dev = aml_device("PEVR");
926 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
927
928 crs = aml_resource_template();
929 aml_append(crs,
930 aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
931 );
932 aml_append(dev, aml_name_decl("_CRS", crs));
933
934 aml_append(dev, aml_operation_region("PEOR", aml_system_io,
935 misc->pvpanic_port, 1));
936 field = aml_field("PEOR", aml_byte_acc);
937 aml_append(field, aml_named_field("PEPT", 8));
938 aml_append(dev, field);
939
940 method = aml_method("RDPT", 0);
941 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
942 aml_append(method, aml_return(aml_local(0)));
943 aml_append(dev, method);
944
945 method = aml_method("WRPT", 1);
946 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
947 aml_append(dev, method);
948
949 aml_append(scope, dev);
950 aml_append(ssdt, scope);
951 }
952
953 sb_scope = aml_scope("_SB");
954 {
955 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
956 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
957 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
958 aml_append(dev,
959 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
960 );
961 /* device present, functioning, decoding, not shown in UI */
962 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
963 crs = aml_resource_template();
964 aml_append(crs,
965 aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
966 pm->cpu_hp_io_len)
967 );
968 aml_append(dev, aml_name_decl("_CRS", crs));
969 aml_append(sb_scope, dev);
970 /* declare CPU hotplug MMIO region and PRS field to access it */
971 aml_append(sb_scope, aml_operation_region(
972 "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
973 field = aml_field("PRST", aml_byte_acc);
974 aml_append(field, aml_named_field("PRS", 256));
975 aml_append(sb_scope, field);
976
977 /* build Processor object for each processor */
978 for (i = 0; i < acpi_cpus; i++) {
979 dev = aml_processor(i, 0, 0, "CP%.02X", i);
980
981 method = aml_method("_MAT", 0);
982 aml_append(method, aml_return(aml_call1("CPMA", aml_int(i))));
983 aml_append(dev, method);
984
985 method = aml_method("_STA", 0);
986 aml_append(method, aml_return(aml_call1("CPST", aml_int(i))));
987 aml_append(dev, method);
988
989 method = aml_method("_EJ0", 1);
990 aml_append(method,
991 aml_return(aml_call2("CPEJ", aml_int(i), aml_arg(0)))
992 );
993 aml_append(dev, method);
994
995 aml_append(sb_scope, dev);
996 }
997
998 /* build this code:
999 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1000 */
1001 /* Arg0 = Processor ID = APIC ID */
1002 method = aml_method("NTFY", 2);
1003 for (i = 0; i < acpi_cpus; i++) {
1004 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1005 aml_append(ifctx,
1006 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1007 );
1008 aml_append(method, ifctx);
1009 }
1010 aml_append(sb_scope, method);
1011
1012 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1013 *
1014 * Note: The ability to create variable-sized packages was first
1015 * ntroduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1016 * ith up to 255 elements. Windows guests up to win2k8 fail when
1017 * VarPackageOp is used.
1018 */
1019 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1020 aml_varpackage(acpi_cpus);
1021
1022 for (i = 0; i < acpi_cpus; i++) {
1023 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1024 aml_append(pkg, aml_int(b));
1025 }
1026 aml_append(sb_scope, aml_name_decl("CPON", pkg));
1027
1028 /* build memory devices */
1029 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1030
1031 for (i = 0; i < nr_mem; i++) {
1032 #define BASEPATH "\\_SB.PCI0." stringify(MEMORY_HOTPLUG_DEVICE) "."
1033 const char *s;
1034
1035 dev = aml_device("MP%02X", i);
1036 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1037 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1038
1039 method = aml_method("_CRS", 0);
1040 s = BASEPATH stringify(MEMORY_SLOT_CRS_METHOD);
1041 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1042 aml_append(dev, method);
1043
1044 method = aml_method("_STA", 0);
1045 s = BASEPATH stringify(MEMORY_SLOT_STATUS_METHOD);
1046 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1047 aml_append(dev, method);
1048
1049 method = aml_method("_PXM", 0);
1050 s = BASEPATH stringify(MEMORY_SLOT_PROXIMITY_METHOD);
1051 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1052 aml_append(dev, method);
1053
1054 method = aml_method("_OST", 3);
1055 s = BASEPATH stringify(MEMORY_SLOT_OST_METHOD);
1056 aml_append(method, aml_return(aml_call4(
1057 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1058 )));
1059 aml_append(dev, method);
1060
1061 aml_append(sb_scope, dev);
1062 }
1063
1064 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1065 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ...
1066 */
1067 method = aml_method(stringify(MEMORY_SLOT_NOTIFY_METHOD), 2);
1068 for (i = 0; i < nr_mem; i++) {
1069 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1070 aml_append(ifctx,
1071 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1072 );
1073 aml_append(method, ifctx);
1074 }
1075 aml_append(sb_scope, method);
1076
1077 {
1078 AcpiBuildPciBusHotplugState hotplug_state;
1079 Object *pci_host;
1080 PCIBus *bus = NULL;
1081 bool ambiguous;
1082
1083 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1084 if (!ambiguous && pci_host) {
1085 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1086 }
1087
1088 build_pci_bus_state_init(&hotplug_state, NULL, pm->pcihp_bridge_en);
1089
1090 if (bus) {
1091 /* Scan all PCI buses. Generate tables to support hotplug. */
1092 pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
1093 build_pci_bus_end, &hotplug_state);
1094 }
1095
1096 build_append_array(sb_scope->buf, hotplug_state.device_table);
1097 build_pci_bus_state_cleanup(&hotplug_state);
1098 }
1099 aml_append(ssdt, sb_scope);
1100 }
1101
1102 /* copy AML table into ACPI tables blob and patch header there */
1103 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
1104 build_header(linker, table_data,
1105 (void *)(table_data->data + table_data->len - ssdt->buf->len),
1106 "SSDT", ssdt->buf->len, 1);
1107 free_aml_allocator();
1108 }
1109
1110 static void
1111 build_hpet(GArray *table_data, GArray *linker)
1112 {
1113 Acpi20Hpet *hpet;
1114
1115 hpet = acpi_data_push(table_data, sizeof(*hpet));
1116 /* Note timer_block_id value must be kept in sync with value advertised by
1117 * emulated hpet
1118 */
1119 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1120 hpet->addr.address = cpu_to_le64(HPET_BASE);
1121 build_header(linker, table_data,
1122 (void *)hpet, "HPET", sizeof(*hpet), 1);
1123 }
1124
1125 static void
1126 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
1127 {
1128 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1129 uint64_t log_area_start_address = acpi_data_len(tcpalog);
1130
1131 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1132 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1133 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
1134
1135 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
1136 false /* high memory */);
1137
1138 /* log area start address to be filled by Guest linker */
1139 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
1140 ACPI_BUILD_TPMLOG_FILE,
1141 table_data, &tcpa->log_area_start_address,
1142 sizeof(tcpa->log_area_start_address));
1143
1144 build_header(linker, table_data,
1145 (void *)tcpa, "TCPA", sizeof(*tcpa), 2);
1146
1147 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
1148 }
1149
1150 static void
1151 build_tpm_ssdt(GArray *table_data, GArray *linker)
1152 {
1153 void *tpm_ptr;
1154
1155 tpm_ptr = acpi_data_push(table_data, sizeof(ssdt_tpm_aml));
1156 memcpy(tpm_ptr, ssdt_tpm_aml, sizeof(ssdt_tpm_aml));
1157 }
1158
1159 typedef enum {
1160 MEM_AFFINITY_NOFLAGS = 0,
1161 MEM_AFFINITY_ENABLED = (1 << 0),
1162 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
1163 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
1164 } MemoryAffinityFlags;
1165
1166 static void
1167 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
1168 uint64_t len, int node, MemoryAffinityFlags flags)
1169 {
1170 numamem->type = ACPI_SRAT_MEMORY;
1171 numamem->length = sizeof(*numamem);
1172 memset(numamem->proximity, 0, 4);
1173 numamem->proximity[0] = node;
1174 numamem->flags = cpu_to_le32(flags);
1175 numamem->base_addr = cpu_to_le64(base);
1176 numamem->range_length = cpu_to_le64(len);
1177 }
1178
1179 static void
1180 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
1181 {
1182 AcpiSystemResourceAffinityTable *srat;
1183 AcpiSratProcessorAffinity *core;
1184 AcpiSratMemoryAffinity *numamem;
1185
1186 int i;
1187 uint64_t curnode;
1188 int srat_start, numa_start, slots;
1189 uint64_t mem_len, mem_base, next_base;
1190 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
1191 ram_addr_t hotplugabble_address_space_size =
1192 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
1193 NULL);
1194
1195 srat_start = table_data->len;
1196
1197 srat = acpi_data_push(table_data, sizeof *srat);
1198 srat->reserved1 = cpu_to_le32(1);
1199 core = (void *)(srat + 1);
1200
1201 for (i = 0; i < guest_info->apic_id_limit; ++i) {
1202 core = acpi_data_push(table_data, sizeof *core);
1203 core->type = ACPI_SRAT_PROCESSOR;
1204 core->length = sizeof(*core);
1205 core->local_apic_id = i;
1206 curnode = guest_info->node_cpu[i];
1207 core->proximity_lo = curnode;
1208 memset(core->proximity_hi, 0, 3);
1209 core->local_sapic_eid = 0;
1210 core->flags = cpu_to_le32(1);
1211 }
1212
1213
1214 /* the memory map is a bit tricky, it contains at least one hole
1215 * from 640k-1M and possibly another one from 3.5G-4G.
1216 */
1217 next_base = 0;
1218 numa_start = table_data->len;
1219
1220 numamem = acpi_data_push(table_data, sizeof *numamem);
1221 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
1222 next_base = 1024 * 1024;
1223 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
1224 mem_base = next_base;
1225 mem_len = guest_info->node_mem[i - 1];
1226 if (i == 1) {
1227 mem_len -= 1024 * 1024;
1228 }
1229 next_base = mem_base + mem_len;
1230
1231 /* Cut out the ACPI_PCI hole */
1232 if (mem_base <= guest_info->ram_size_below_4g &&
1233 next_base > guest_info->ram_size_below_4g) {
1234 mem_len -= next_base - guest_info->ram_size_below_4g;
1235 if (mem_len > 0) {
1236 numamem = acpi_data_push(table_data, sizeof *numamem);
1237 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1238 MEM_AFFINITY_ENABLED);
1239 }
1240 mem_base = 1ULL << 32;
1241 mem_len = next_base - guest_info->ram_size_below_4g;
1242 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
1243 }
1244 numamem = acpi_data_push(table_data, sizeof *numamem);
1245 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
1246 MEM_AFFINITY_ENABLED);
1247 }
1248 slots = (table_data->len - numa_start) / sizeof *numamem;
1249 for (; slots < guest_info->numa_nodes + 2; slots++) {
1250 numamem = acpi_data_push(table_data, sizeof *numamem);
1251 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1252 }
1253
1254 /*
1255 * Entry is required for Windows to enable memory hotplug in OS.
1256 * Memory devices may override proximity set by this entry,
1257 * providing _PXM method if necessary.
1258 */
1259 if (hotplugabble_address_space_size) {
1260 numamem = acpi_data_push(table_data, sizeof *numamem);
1261 acpi_build_srat_memory(numamem, pcms->hotplug_memory_base,
1262 hotplugabble_address_space_size, 0,
1263 MEM_AFFINITY_HOTPLUGGABLE |
1264 MEM_AFFINITY_ENABLED);
1265 }
1266
1267 build_header(linker, table_data,
1268 (void *)(table_data->data + srat_start),
1269 "SRAT",
1270 table_data->len - srat_start, 1);
1271 }
1272
1273 static void
1274 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
1275 {
1276 AcpiTableMcfg *mcfg;
1277 const char *sig;
1278 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
1279
1280 mcfg = acpi_data_push(table_data, len);
1281 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
1282 /* Only a single allocation so no need to play with segments */
1283 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
1284 mcfg->allocation[0].start_bus_number = 0;
1285 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
1286
1287 /* MCFG is used for ECAM which can be enabled or disabled by guest.
1288 * To avoid table size changes (which create migration issues),
1289 * always create the table even if there are no allocations,
1290 * but set the signature to a reserved value in this case.
1291 * ACPI spec requires OSPMs to ignore such tables.
1292 */
1293 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
1294 /* Reserved signature: ignored by OSPM */
1295 sig = "QEMU";
1296 } else {
1297 sig = "MCFG";
1298 }
1299 build_header(linker, table_data, (void *)mcfg, sig, len, 1);
1300 }
1301
1302 static void
1303 build_dmar_q35(GArray *table_data, GArray *linker)
1304 {
1305 int dmar_start = table_data->len;
1306
1307 AcpiTableDmar *dmar;
1308 AcpiDmarHardwareUnit *drhd;
1309
1310 dmar = acpi_data_push(table_data, sizeof(*dmar));
1311 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
1312 dmar->flags = 0; /* No intr_remap for now */
1313
1314 /* DMAR Remapping Hardware Unit Definition structure */
1315 drhd = acpi_data_push(table_data, sizeof(*drhd));
1316 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1317 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
1318 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1319 drhd->pci_segment = cpu_to_le16(0);
1320 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1321
1322 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1323 "DMAR", table_data->len - dmar_start, 1);
1324 }
1325
1326 static void
1327 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
1328 {
1329 AcpiTableHeader *dsdt;
1330
1331 assert(misc->dsdt_code && misc->dsdt_size);
1332
1333 dsdt = acpi_data_push(table_data, misc->dsdt_size);
1334 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
1335
1336 memset(dsdt, 0, sizeof *dsdt);
1337 build_header(linker, table_data, dsdt, "DSDT",
1338 misc->dsdt_size, 1);
1339 }
1340
1341 /* Build final rsdt table */
1342 static void
1343 build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
1344 {
1345 AcpiRsdtDescriptorRev1 *rsdt;
1346 size_t rsdt_len;
1347 int i;
1348
1349 rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
1350 rsdt = acpi_data_push(table_data, rsdt_len);
1351 memcpy(rsdt->table_offset_entry, table_offsets->data,
1352 sizeof(uint32_t) * table_offsets->len);
1353 for (i = 0; i < table_offsets->len; ++i) {
1354 /* rsdt->table_offset_entry to be filled by Guest linker */
1355 bios_linker_loader_add_pointer(linker,
1356 ACPI_BUILD_TABLE_FILE,
1357 ACPI_BUILD_TABLE_FILE,
1358 table_data, &rsdt->table_offset_entry[i],
1359 sizeof(uint32_t));
1360 }
1361 build_header(linker, table_data,
1362 (void *)rsdt, "RSDT", rsdt_len, 1);
1363 }
1364
1365 static GArray *
1366 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
1367 {
1368 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
1369
1370 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
1371 true /* fseg memory */);
1372
1373 memcpy(&rsdp->signature, "RSD PTR ", 8);
1374 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
1375 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
1376 /* Address to be filled by Guest linker */
1377 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
1378 ACPI_BUILD_TABLE_FILE,
1379 rsdp_table, &rsdp->rsdt_physical_address,
1380 sizeof rsdp->rsdt_physical_address);
1381 rsdp->checksum = 0;
1382 /* Checksum to be filled by Guest linker */
1383 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
1384 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
1385
1386 return rsdp_table;
1387 }
1388
1389 typedef
1390 struct AcpiBuildTables {
1391 GArray *table_data;
1392 GArray *rsdp;
1393 GArray *tcpalog;
1394 GArray *linker;
1395 } AcpiBuildTables;
1396
1397 static inline void acpi_build_tables_init(AcpiBuildTables *tables)
1398 {
1399 tables->rsdp = g_array_new(false, true /* clear */, 1);
1400 tables->table_data = g_array_new(false, true /* clear */, 1);
1401 tables->tcpalog = g_array_new(false, true /* clear */, 1);
1402 tables->linker = bios_linker_loader_init();
1403 }
1404
1405 static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
1406 {
1407 void *linker_data = bios_linker_loader_cleanup(tables->linker);
1408 g_free(linker_data);
1409 g_array_free(tables->rsdp, true);
1410 g_array_free(tables->table_data, true);
1411 g_array_free(tables->tcpalog, mfre);
1412 }
1413
1414 typedef
1415 struct AcpiBuildState {
1416 /* Copy of table in RAM (for patching). */
1417 ram_addr_t table_ram;
1418 /* Is table patched? */
1419 uint8_t patched;
1420 PcGuestInfo *guest_info;
1421 void *rsdp;
1422 ram_addr_t rsdp_ram;
1423 ram_addr_t linker_ram;
1424 } AcpiBuildState;
1425
1426 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
1427 {
1428 Object *pci_host;
1429 QObject *o;
1430 bool ambiguous;
1431
1432 pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
1433 g_assert(!ambiguous);
1434 g_assert(pci_host);
1435
1436 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
1437 if (!o) {
1438 return false;
1439 }
1440 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
1441 qobject_decref(o);
1442
1443 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
1444 assert(o);
1445 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
1446 qobject_decref(o);
1447 return true;
1448 }
1449
1450 static bool acpi_has_iommu(void)
1451 {
1452 bool ambiguous;
1453 Object *intel_iommu;
1454
1455 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
1456 &ambiguous);
1457 return intel_iommu && !ambiguous;
1458 }
1459
1460 static
1461 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
1462 {
1463 GArray *table_offsets;
1464 unsigned facs, ssdt, dsdt, rsdt;
1465 AcpiCpuInfo cpu;
1466 AcpiPmInfo pm;
1467 AcpiMiscInfo misc;
1468 AcpiMcfgInfo mcfg;
1469 PcPciInfo pci;
1470 uint8_t *u;
1471 size_t aml_len = 0;
1472 GArray *tables_blob = tables->table_data;
1473
1474 acpi_get_cpu_info(&cpu);
1475 acpi_get_pm_info(&pm);
1476 acpi_get_dsdt(&misc);
1477 acpi_get_misc_info(&misc);
1478 acpi_get_pci_info(&pci);
1479
1480 table_offsets = g_array_new(false, true /* clear */,
1481 sizeof(uint32_t));
1482 ACPI_BUILD_DPRINTF("init ACPI tables\n");
1483
1484 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
1485 64 /* Ensure FACS is aligned */,
1486 false /* high memory */);
1487
1488 /*
1489 * FACS is pointed to by FADT.
1490 * We place it first since it's the only table that has alignment
1491 * requirements.
1492 */
1493 facs = tables_blob->len;
1494 build_facs(tables_blob, tables->linker, guest_info);
1495
1496 /* DSDT is pointed to by FADT */
1497 dsdt = tables_blob->len;
1498 build_dsdt(tables_blob, tables->linker, &misc);
1499
1500 /* Count the size of the DSDT and SSDT, we will need it for legacy
1501 * sizing of ACPI tables.
1502 */
1503 aml_len += tables_blob->len - dsdt;
1504
1505 /* ACPI tables pointed to by RSDT */
1506 acpi_add_table(table_offsets, tables_blob);
1507 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
1508
1509 ssdt = tables_blob->len;
1510 acpi_add_table(table_offsets, tables_blob);
1511 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
1512 guest_info);
1513 aml_len += tables_blob->len - ssdt;
1514
1515 acpi_add_table(table_offsets, tables_blob);
1516 build_madt(tables_blob, tables->linker, &cpu, guest_info);
1517
1518 if (misc.has_hpet) {
1519 acpi_add_table(table_offsets, tables_blob);
1520 build_hpet(tables_blob, tables->linker);
1521 }
1522 if (misc.has_tpm) {
1523 acpi_add_table(table_offsets, tables_blob);
1524 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
1525
1526 acpi_add_table(table_offsets, tables_blob);
1527 build_tpm_ssdt(tables_blob, tables->linker);
1528 }
1529 if (guest_info->numa_nodes) {
1530 acpi_add_table(table_offsets, tables_blob);
1531 build_srat(tables_blob, tables->linker, guest_info);
1532 }
1533 if (acpi_get_mcfg(&mcfg)) {
1534 acpi_add_table(table_offsets, tables_blob);
1535 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
1536 }
1537 if (acpi_has_iommu()) {
1538 acpi_add_table(table_offsets, tables_blob);
1539 build_dmar_q35(tables_blob, tables->linker);
1540 }
1541
1542 /* Add tables supplied by user (if any) */
1543 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
1544 unsigned len = acpi_table_len(u);
1545
1546 acpi_add_table(table_offsets, tables_blob);
1547 g_array_append_vals(tables_blob, u, len);
1548 }
1549
1550 /* RSDT is pointed to by RSDP */
1551 rsdt = tables_blob->len;
1552 build_rsdt(tables_blob, tables->linker, table_offsets);
1553
1554 /* RSDP is in FSEG memory, so allocate it separately */
1555 build_rsdp(tables->rsdp, tables->linker, rsdt);
1556
1557 /* We'll expose it all to Guest so we want to reduce
1558 * chance of size changes.
1559 *
1560 * We used to align the tables to 4k, but of course this would
1561 * too simple to be enough. 4k turned out to be too small an
1562 * alignment very soon, and in fact it is almost impossible to
1563 * keep the table size stable for all (max_cpus, max_memory_slots)
1564 * combinations. So the table size is always 64k for pc-i440fx-2.1
1565 * and we give an error if the table grows beyond that limit.
1566 *
1567 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
1568 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
1569 * than 2.0 and we can always pad the smaller tables with zeros. We can
1570 * then use the exact size of the 2.0 tables.
1571 *
1572 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
1573 */
1574 if (guest_info->legacy_acpi_table_size) {
1575 /* Subtracting aml_len gives the size of fixed tables. Then add the
1576 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
1577 */
1578 int legacy_aml_len =
1579 guest_info->legacy_acpi_table_size +
1580 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
1581 int legacy_table_size =
1582 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
1583 ACPI_BUILD_ALIGN_SIZE);
1584 if (tables_blob->len > legacy_table_size) {
1585 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
1586 error_report("Warning: migration may not work.");
1587 }
1588 g_array_set_size(tables_blob, legacy_table_size);
1589 } else {
1590 /* Make sure we have a buffer in case we need to resize the tables. */
1591 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1592 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
1593 error_report("Warning: ACPI tables are larger than 64k.");
1594 error_report("Warning: migration may not work.");
1595 error_report("Warning: please remove CPUs, NUMA nodes, "
1596 "memory slots or PCI bridges.");
1597 }
1598 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1599 }
1600
1601 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
1602
1603 /* Cleanup memory that's no longer used. */
1604 g_array_free(table_offsets, true);
1605 }
1606
1607 static void acpi_ram_update(ram_addr_t ram, GArray *data)
1608 {
1609 uint32_t size = acpi_data_len(data);
1610
1611 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
1612 qemu_ram_resize(ram, size, &error_abort);
1613
1614 memcpy(qemu_get_ram_ptr(ram), data->data, size);
1615 cpu_physical_memory_set_dirty_range_nocode(ram, size);
1616 }
1617
1618 static void acpi_build_update(void *build_opaque, uint32_t offset)
1619 {
1620 AcpiBuildState *build_state = build_opaque;
1621 AcpiBuildTables tables;
1622
1623 /* No state to update or already patched? Nothing to do. */
1624 if (!build_state || build_state->patched) {
1625 return;
1626 }
1627 build_state->patched = 1;
1628
1629 acpi_build_tables_init(&tables);
1630
1631 acpi_build(build_state->guest_info, &tables);
1632
1633 acpi_ram_update(build_state->table_ram, tables.table_data);
1634
1635 if (build_state->rsdp) {
1636 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
1637 } else {
1638 acpi_ram_update(build_state->rsdp_ram, tables.rsdp);
1639 }
1640
1641 acpi_ram_update(build_state->linker_ram, tables.linker);
1642 acpi_build_tables_cleanup(&tables, true);
1643 }
1644
1645 static void acpi_build_reset(void *build_opaque)
1646 {
1647 AcpiBuildState *build_state = build_opaque;
1648 build_state->patched = 0;
1649 }
1650
1651 static ram_addr_t acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
1652 const char *name, uint64_t max_size)
1653 {
1654 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
1655 name, acpi_build_update, build_state);
1656 }
1657
1658 static const VMStateDescription vmstate_acpi_build = {
1659 .name = "acpi_build",
1660 .version_id = 1,
1661 .minimum_version_id = 1,
1662 .fields = (VMStateField[]) {
1663 VMSTATE_UINT8(patched, AcpiBuildState),
1664 VMSTATE_END_OF_LIST()
1665 },
1666 };
1667
1668 void acpi_setup(PcGuestInfo *guest_info)
1669 {
1670 AcpiBuildTables tables;
1671 AcpiBuildState *build_state;
1672
1673 if (!guest_info->fw_cfg) {
1674 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
1675 return;
1676 }
1677
1678 if (!guest_info->has_acpi_build) {
1679 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
1680 return;
1681 }
1682
1683 if (!acpi_enabled) {
1684 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
1685 return;
1686 }
1687
1688 build_state = g_malloc0(sizeof *build_state);
1689
1690 build_state->guest_info = guest_info;
1691
1692 acpi_set_pci_info();
1693
1694 acpi_build_tables_init(&tables);
1695 acpi_build(build_state->guest_info, &tables);
1696
1697 /* Now expose it all to Guest */
1698 build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
1699 ACPI_BUILD_TABLE_FILE,
1700 ACPI_BUILD_TABLE_MAX_SIZE);
1701 assert(build_state->table_ram != RAM_ADDR_MAX);
1702
1703 build_state->linker_ram =
1704 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
1705
1706 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
1707 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
1708
1709 if (!guest_info->rsdp_in_ram) {
1710 /*
1711 * Keep for compatibility with old machine types.
1712 * Though RSDP is small, its contents isn't immutable, so
1713 * we'll update it along with the rest of tables on guest access.
1714 */
1715 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
1716
1717 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
1718 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
1719 acpi_build_update, build_state,
1720 build_state->rsdp, rsdp_size);
1721 build_state->rsdp_ram = (ram_addr_t)-1;
1722 } else {
1723 build_state->rsdp = NULL;
1724 build_state->rsdp_ram = acpi_add_rom_blob(build_state, tables.rsdp,
1725 ACPI_BUILD_RSDP_FILE, 0);
1726 }
1727
1728 qemu_register_reset(acpi_build_reset, build_state);
1729 acpi_build_reset(build_state);
1730 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
1731
1732 /* Cleanup tables but don't free the memory: we track it
1733 * in build_state.
1734 */
1735 acpi_build_tables_cleanup(&tables, false);
1736 }
AR7 emulation for QEMU