2 * QEMU Sun4u/Sun4v System Emulator common routines
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/char/serial.h"
29 #include "hw/sparc/sparc64.h"
30 #include "qemu/timer.h"
37 #define CPUIRQ_DPRINTF(fmt, ...) \
38 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
40 #define CPUIRQ_DPRINTF(fmt, ...)
44 #define TIMER_DPRINTF(fmt, ...) \
45 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
47 #define TIMER_DPRINTF(fmt, ...)
50 #define TICK_MAX 0x7fffffffffffffffULL
52 void cpu_check_irqs(CPUSPARCState
*env
)
55 uint32_t pil
= env
->pil_in
|
56 (env
->softint
& ~(SOFTINT_TIMER
| SOFTINT_STIMER
));
58 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
59 if (env
->ivec_status
& 0x20) {
62 cs
= CPU(sparc_env_get_cpu(env
));
63 /* check if TM or SM in SOFTINT are set
64 setting these also causes interrupt 14 */
65 if (env
->softint
& (SOFTINT_TIMER
| SOFTINT_STIMER
)) {
69 /* The bit corresponding to psrpil is (1<< psrpil), the next bit
71 if (pil
< (2 << env
->psrpil
)) {
72 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
73 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
74 env
->interrupt_index
);
75 env
->interrupt_index
= 0;
76 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
81 if (cpu_interrupts_enabled(env
)) {
85 for (i
= 15; i
> env
->psrpil
; i
--) {
87 int old_interrupt
= env
->interrupt_index
;
88 int new_interrupt
= TT_EXTINT
| i
;
90 if (unlikely(env
->tl
> 0 && cpu_tsptr(env
)->tt
> new_interrupt
91 && ((cpu_tsptr(env
)->tt
& 0x1f0) == TT_EXTINT
))) {
92 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
93 "current %x >= pending %x\n",
94 env
->tl
, cpu_tsptr(env
)->tt
, new_interrupt
);
95 } else if (old_interrupt
!= new_interrupt
) {
96 env
->interrupt_index
= new_interrupt
;
97 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i
,
98 old_interrupt
, new_interrupt
);
99 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
104 } else if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
105 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
106 "current interrupt %x\n",
107 pil
, env
->pil_in
, env
->softint
, env
->interrupt_index
);
108 env
->interrupt_index
= 0;
109 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
113 static void cpu_kick_irq(SPARCCPU
*cpu
)
115 CPUState
*cs
= CPU(cpu
);
116 CPUSPARCState
*env
= &cpu
->env
;
123 void sparc64_cpu_set_ivec_irq(void *opaque
, int irq
, int level
)
125 SPARCCPU
*cpu
= opaque
;
126 CPUSPARCState
*env
= &cpu
->env
;
130 if (!(env
->ivec_status
& 0x20)) {
131 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq
);
134 env
->interrupt_index
= TT_IVEC
;
135 env
->ivec_status
|= 0x20;
136 env
->ivec_data
[0] = (0x1f << 6) | irq
;
137 env
->ivec_data
[1] = 0;
138 env
->ivec_data
[2] = 0;
139 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
142 if (env
->ivec_status
& 0x20) {
143 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq
);
145 env
->ivec_status
&= ~0x20;
146 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
151 typedef struct ResetData
{
156 static CPUTimer
*cpu_timer_create(const char *name
, SPARCCPU
*cpu
,
157 QEMUBHFunc
*cb
, uint32_t frequency
,
158 uint64_t disabled_mask
, uint64_t npt_mask
)
160 CPUTimer
*timer
= g_malloc0(sizeof(CPUTimer
));
163 timer
->frequency
= frequency
;
164 timer
->disabled_mask
= disabled_mask
;
165 timer
->npt_mask
= npt_mask
;
169 timer
->clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
171 timer
->qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cb
, cpu
);
176 static void cpu_timer_reset(CPUTimer
*timer
)
179 timer
->clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
181 timer_del(timer
->qtimer
);
184 static void main_cpu_reset(void *opaque
)
186 ResetData
*s
= (ResetData
*)opaque
;
187 CPUSPARCState
*env
= &s
->cpu
->env
;
188 static unsigned int nr_resets
;
190 cpu_reset(CPU(s
->cpu
));
192 cpu_timer_reset(env
->tick
);
193 cpu_timer_reset(env
->stick
);
194 cpu_timer_reset(env
->hstick
);
196 env
->gregs
[1] = 0; /* Memory start */
197 env
->gregs
[2] = ram_size
; /* Memory size */
198 env
->gregs
[3] = 0; /* Machine description XXX */
199 if (nr_resets
++ == 0) {
201 env
->pc
= s
->prom_addr
+ 0x20ULL
;
203 env
->pc
= s
->prom_addr
+ 0x40ULL
;
205 env
->npc
= env
->pc
+ 4;
208 static void tick_irq(void *opaque
)
210 SPARCCPU
*cpu
= opaque
;
211 CPUSPARCState
*env
= &cpu
->env
;
213 CPUTimer
*timer
= env
->tick
;
215 if (timer
->disabled
) {
216 CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
219 CPUIRQ_DPRINTF("tick: fire\n");
222 env
->softint
|= SOFTINT_TIMER
;
226 static void stick_irq(void *opaque
)
228 SPARCCPU
*cpu
= opaque
;
229 CPUSPARCState
*env
= &cpu
->env
;
231 CPUTimer
*timer
= env
->stick
;
233 if (timer
->disabled
) {
234 CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
237 CPUIRQ_DPRINTF("stick: fire\n");
240 env
->softint
|= SOFTINT_STIMER
;
244 static void hstick_irq(void *opaque
)
246 SPARCCPU
*cpu
= opaque
;
247 CPUSPARCState
*env
= &cpu
->env
;
249 CPUTimer
*timer
= env
->hstick
;
251 if (timer
->disabled
) {
252 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
255 CPUIRQ_DPRINTF("hstick: fire\n");
258 env
->softint
|= SOFTINT_STIMER
;
262 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks
, uint32_t frequency
)
264 return muldiv64(cpu_ticks
, NANOSECONDS_PER_SECOND
, frequency
);
267 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks
, uint32_t frequency
)
269 return muldiv64(timer_ticks
, frequency
, NANOSECONDS_PER_SECOND
);
272 void cpu_tick_set_count(CPUTimer
*timer
, uint64_t count
)
274 uint64_t real_count
= count
& ~timer
->npt_mask
;
275 uint64_t npt_bit
= count
& timer
->npt_mask
;
277 int64_t vm_clock_offset
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
278 cpu_to_timer_ticks(real_count
, timer
->frequency
);
280 TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n",
281 timer
->name
, real_count
,
282 timer
->npt
? "disabled" : "enabled", timer
);
284 timer
->npt
= npt_bit
? 1 : 0;
285 timer
->clock_offset
= vm_clock_offset
;
288 uint64_t cpu_tick_get_count(CPUTimer
*timer
)
290 uint64_t real_count
= timer_to_cpu_ticks(
291 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) - timer
->clock_offset
,
294 TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n",
295 timer
->name
, real_count
,
296 timer
->npt
? "disabled" : "enabled", timer
);
299 real_count
|= timer
->npt_mask
;
305 void cpu_tick_set_limit(CPUTimer
*timer
, uint64_t limit
)
307 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
309 uint64_t real_limit
= limit
& ~timer
->disabled_mask
;
310 timer
->disabled
= (limit
& timer
->disabled_mask
) ? 1 : 0;
312 int64_t expires
= cpu_to_timer_ticks(real_limit
, timer
->frequency
) +
319 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
320 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
321 timer
->name
, real_limit
,
322 timer
->disabled
? "disabled" : "enabled",
324 timer_to_cpu_ticks(now
- timer
->clock_offset
,
326 timer_to_cpu_ticks(expires
- now
, timer
->frequency
));
329 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
331 timer_del(timer
->qtimer
);
332 } else if (timer
->disabled
) {
333 timer_del(timer
->qtimer
);
335 timer_mod(timer
->qtimer
, expires
);
339 SPARCCPU
*sparc64_cpu_devinit(const char *cpu_model
,
340 const char *default_cpu_model
, uint64_t prom_addr
)
344 ResetData
*reset_info
;
346 uint32_t tick_frequency
= 100 * 1000000;
347 uint32_t stick_frequency
= 100 * 1000000;
348 uint32_t hstick_frequency
= 100 * 1000000;
350 if (cpu_model
== NULL
) {
351 cpu_model
= default_cpu_model
;
353 cpu
= cpu_sparc_init(cpu_model
);
355 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
360 env
->tick
= cpu_timer_create("tick", cpu
, tick_irq
,
361 tick_frequency
, TICK_INT_DIS
,
364 env
->stick
= cpu_timer_create("stick", cpu
, stick_irq
,
365 stick_frequency
, TICK_INT_DIS
,
368 env
->hstick
= cpu_timer_create("hstick", cpu
, hstick_irq
,
369 hstick_frequency
, TICK_INT_DIS
,
372 reset_info
= g_malloc0(sizeof(ResetData
));
373 reset_info
->cpu
= cpu
;
374 reset_info
->prom_addr
= prom_addr
;
375 qemu_register_reset(main_cpu_reset
, reset_info
);