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Update version for v4.1.0-rc4 release
[qemu/ar7.git] / disas / cris.c
blob2f43c9b2095a722e9b2d9914414e024e819af1ef
1 /* Disassembler code for CRIS.
2 Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Written by Hans-Peter Nilsson.
5
6 This file is part of the GNU binutils and GDB, the GNU debugger.
7
8 This program is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by the
10 Free Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
20
21 #include "qemu/osdep.h"
22 #include "disas/dis-asm.h"
23 #include "target/cris/opcode-cris.h"
24
25 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
26
27 /* cris-opc.c -- Table of opcodes for the CRIS processor.
28 Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
29 Contributed by Axis Communications AB, Lund, Sweden.
30 Originally written for GAS 1.38.1 by Mikael Asker.
31 Reorganized by Hans-Peter Nilsson.
32
33 This file is part of GAS, GDB and the GNU binutils.
34
35 GAS, GDB, and GNU binutils is free software; you can redistribute it
36 and/or modify it under the terms of the GNU General Public License as
37 published by the Free Software Foundation; either version 2, or (at your
38 option) any later version.
39
40 GAS, GDB, and GNU binutils are distributed in the hope that they will be
41 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
42 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
43 GNU General Public License for more details.
44
45 You should have received a copy of the GNU General Public License
46 along with this program; if not, see <http://www.gnu.org/licenses/>. */
47
48 #ifndef NULL
49 #define NULL (0)
50 #endif
51
52 /* This table isn't used for CRISv32 and the size of immediate operands. */
53 const struct cris_spec_reg
54 cris_spec_regs[] =
55 {
56 {"bz", 0, 1, cris_ver_v32p, NULL},
57 {"p0", 0, 1, 0, NULL},
58 {"vr", 1, 1, 0, NULL},
59 {"p1", 1, 1, 0, NULL},
60 {"pid", 2, 1, cris_ver_v32p, NULL},
61 {"p2", 2, 1, cris_ver_v32p, NULL},
62 {"p2", 2, 1, cris_ver_warning, NULL},
63 {"srs", 3, 1, cris_ver_v32p, NULL},
64 {"p3", 3, 1, cris_ver_v32p, NULL},
65 {"p3", 3, 1, cris_ver_warning, NULL},
66 {"wz", 4, 2, cris_ver_v32p, NULL},
67 {"p4", 4, 2, 0, NULL},
68 {"ccr", 5, 2, cris_ver_v0_10, NULL},
69 {"exs", 5, 4, cris_ver_v32p, NULL},
70 {"p5", 5, 2, cris_ver_v0_10, NULL},
71 {"p5", 5, 4, cris_ver_v32p, NULL},
72 {"dcr0",6, 2, cris_ver_v0_3, NULL},
73 {"eda", 6, 4, cris_ver_v32p, NULL},
74 {"p6", 6, 2, cris_ver_v0_3, NULL},
75 {"p6", 6, 4, cris_ver_v32p, NULL},
76 {"dcr1/mof", 7, 4, cris_ver_v10p,
77 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
78 {"dcr1/mof", 7, 2, cris_ver_v0_3,
79 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
80 {"mof", 7, 4, cris_ver_v10p, NULL},
81 {"dcr1",7, 2, cris_ver_v0_3, NULL},
82 {"p7", 7, 4, cris_ver_v10p, NULL},
83 {"p7", 7, 2, cris_ver_v0_3, NULL},
84 {"dz", 8, 4, cris_ver_v32p, NULL},
85 {"p8", 8, 4, 0, NULL},
86 {"ibr", 9, 4, cris_ver_v0_10, NULL},
87 {"ebp", 9, 4, cris_ver_v32p, NULL},
88 {"p9", 9, 4, 0, NULL},
89 {"irp", 10, 4, cris_ver_v0_10, NULL},
90 {"erp", 10, 4, cris_ver_v32p, NULL},
91 {"p10", 10, 4, 0, NULL},
92 {"srp", 11, 4, 0, NULL},
93 {"p11", 11, 4, 0, NULL},
94 /* For disassembly use only. Accept at assembly with a warning. */
95 {"bar/dtp0", 12, 4, cris_ver_warning,
96 "Ambiguous register `bar/dtp0' specified"},
97 {"nrp", 12, 4, cris_ver_v32p, NULL},
98 {"bar", 12, 4, cris_ver_v8_10, NULL},
99 {"dtp0",12, 4, cris_ver_v0_3, NULL},
100 {"p12", 12, 4, 0, NULL},
101 /* For disassembly use only. Accept at assembly with a warning. */
102 {"dccr/dtp1",13, 4, cris_ver_warning,
103 "Ambiguous register `dccr/dtp1' specified"},
104 {"ccs", 13, 4, cris_ver_v32p, NULL},
105 {"dccr",13, 4, cris_ver_v8_10, NULL},
106 {"dtp1",13, 4, cris_ver_v0_3, NULL},
107 {"p13", 13, 4, 0, NULL},
108 {"brp", 14, 4, cris_ver_v3_10, NULL},
109 {"usp", 14, 4, cris_ver_v32p, NULL},
110 {"p14", 14, 4, cris_ver_v3p, NULL},
111 {"usp", 15, 4, cris_ver_v10, NULL},
112 {"spc", 15, 4, cris_ver_v32p, NULL},
113 {"p15", 15, 4, cris_ver_v10p, NULL},
114 {NULL, 0, 0, cris_ver_version_all, NULL}
115 };
116
117 /* Add version specifiers to this table when necessary.
118 The (now) regular coding of register names suggests a simpler
119 implementation. */
120 const struct cris_support_reg cris_support_regs[] =
121 {
122 {"s0", 0},
123 {"s1", 1},
124 {"s2", 2},
125 {"s3", 3},
126 {"s4", 4},
127 {"s5", 5},
128 {"s6", 6},
129 {"s7", 7},
130 {"s8", 8},
131 {"s9", 9},
132 {"s10", 10},
133 {"s11", 11},
134 {"s12", 12},
135 {"s13", 13},
136 {"s14", 14},
137 {"s15", 15},
138 {NULL, 0}
139 };
140
141 /* All CRIS opcodes are 16 bits.
142
143 - The match component is a mask saying which bits must match a
144 particular opcode in order for an instruction to be an instance
145 of that opcode.
146
147 - The args component is a string containing characters symbolically
148 matching the operands of an instruction. Used for both assembly
149 and disassembly.
150
151 Operand-matching characters:
152 [ ] , space
153 Verbatim.
154 A The string "ACR" (case-insensitive).
155 B Not really an operand. It causes a "BDAP -size,SP" prefix to be
156 output for the PUSH alias-instructions and recognizes a push-
157 prefix at disassembly. This letter isn't recognized for v32.
158 Must be followed by a R or P letter.
159 ! Non-match pattern, will not match if there's a prefix insn.
160 b Non-matching operand, used for branches with 16-bit
161 displacement. Only recognized by the disassembler.
162 c 5-bit unsigned immediate in bits <4:0>.
163 C 4-bit unsigned immediate in bits <3:0>.
164 d At assembly, optionally (as in put other cases before this one)
165 ".d" or ".D" at the start of the operands, followed by one space
166 character. At disassembly, nothing.
167 D General register in bits <15:12> and <3:0>.
168 f List of flags in bits <15:12> and <3:0>.
169 i 6-bit signed immediate in bits <5:0>.
170 I 6-bit unsigned immediate in bits <5:0>.
171 M Size modifier (B, W or D) for CLEAR instructions.
172 m Size modifier (B, W or D) in bits <5:4>
173 N A 32-bit dword, like in the difference between s and y.
174 This has no effect on bits in the opcode. Can also be expressed
175 as "[pc+]" in input.
176 n As N, but PC-relative (to the start of the instruction).
177 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
178 branch instructions.
179 O [-128..127] offset in bits <7:0>. Also matches a comma and a
180 general register after the expression, in bits <15:12>. Used
181 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
182 P Special register in bits <15:12>.
183 p Indicates that the insn is a prefix insn. Must be first
184 character.
185 Q As O, but don't relax; force an 8-bit offset.
186 R General register in bits <15:12>.
187 r General register in bits <3:0>.
188 S Source operand in bit <10> and a prefix; a 3-operand prefix
189 without side-effect.
190 s Source operand in bits <10> and <3:0>, optionally with a
191 side-effect prefix, except [pc] (the name, not R15 as in ACR)
192 isn't allowed for v32 and higher.
193 T Support register in bits <15:12>.
194 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
195 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
196 Not recognized at disassembly.
197 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
198 y Like 's' but do not allow an integer at assembly.
199 Y The difference s-y; only an integer is allowed.
200 z Size modifier (B or W) in bit <4>. */
201
202
203 /* Please note the order of the opcodes in this table is significant.
204 The assembler requires that all instances of the same mnemonic must
205 be consecutive. If they aren't, the assembler might not recognize
206 them, or may indicate an internal error.
207
208 The disassembler should not normally care about the order of the
209 opcodes, but will prefer an earlier alternative if the "match-score"
210 (see cris-dis.c) is computed as equal.
211
212 It should not be significant for proper execution that this table is
213 in alphabetical order, but please follow that convention for an easy
214 overview. */
215
216 const struct cris_opcode
217 cris_opcodes[] =
218 {
219 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
220 cris_abs_op},
221
222 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
223 cris_reg_mode_add_sub_cmp_and_or_move_op},
224
225 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
226 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
227
228 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
229 cris_ver_v0_10,
230 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
231
232 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
233 cris_ver_v0_10,
234 cris_three_operand_add_sub_cmp_and_or_op},
235
236 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
237 cris_ver_v32p,
238 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
239
240 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
241 cris_ver_v32p,
242 cris_not_implemented_op},
243
244 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
245 cris_ver_v32p,
246 cris_not_implemented_op},
247
248 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
249 cris_ver_v32p,
250 cris_addi_op},
251
252 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
253 cris_addi_op},
254
255 /* This collates after "addo", but we want to disassemble as "addoq",
256 not "addo". */
257 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
258 cris_ver_v32p,
259 cris_not_implemented_op},
260
261 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
262 cris_ver_v32p,
263 cris_not_implemented_op},
264
265 /* This must be located after the insn above, lest we misinterpret
266 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
267 parser bug. */
268 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
269 cris_ver_v32p,
270 cris_not_implemented_op},
271
272 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
273 cris_quick_mode_add_sub_op},
274
275 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
276 cris_reg_mode_add_sub_cmp_and_or_move_op},
277
278 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
279 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
280 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
281
282 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
283 cris_ver_v0_10,
284 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
285
286 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
287 cris_ver_v0_10,
288 cris_three_operand_add_sub_cmp_and_or_op},
289
290 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
291 cris_reg_mode_add_sub_cmp_and_or_move_op},
292
293 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
294 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
295 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
296
297 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
298 cris_ver_v0_10,
299 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
300
301 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
302 cris_ver_v0_10,
303 cris_three_operand_add_sub_cmp_and_or_op},
304
305 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
306 cris_reg_mode_add_sub_cmp_and_or_move_op},
307
308 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
309 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
310
311 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
312 cris_ver_v0_10,
313 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
314
315 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
316 cris_ver_v0_10,
317 cris_three_operand_add_sub_cmp_and_or_op},
318
319 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
320 cris_quick_mode_and_cmp_move_or_op},
321
322 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
323 cris_asr_op},
324
325 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
326 cris_asrq_op},
327
328 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
329 cris_ax_ei_setf_op},
330
331 /* FIXME: Should use branch #defines. */
332 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
333 cris_sixteen_bit_offset_branch_op},
334
335 {"ba",
336 BA_QUICK_OPCODE,
337 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
338 cris_eight_bit_offset_branch_op},
339
340 /* Needs to come after the usual "ba o", which might be relaxed to
341 this one. */
342 {"ba", BA_DWORD_OPCODE,
343 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
344 cris_ver_v32p,
345 cris_none_reg_mode_jump_op},
346
347 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
348 cris_ver_v32p,
349 cris_none_reg_mode_jump_op},
350
351 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
352 cris_ver_v32p,
353 cris_none_reg_mode_jump_op},
354
355 {"bcc",
356 BRANCH_QUICK_OPCODE+CC_CC*0x1000,
357 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
358 cris_eight_bit_offset_branch_op},
359
360 {"bcs",
361 BRANCH_QUICK_OPCODE+CC_CS*0x1000,
362 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
363 cris_eight_bit_offset_branch_op},
364
365 {"bdap",
366 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
367 cris_ver_v0_10,
368 cris_bdap_prefix},
369
370 {"bdap",
371 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
372 cris_ver_v0_10,
373 cris_quick_mode_bdap_prefix},
374
375 {"beq",
376 BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
377 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
378 cris_eight_bit_offset_branch_op},
379
380 /* This is deliberately put before "bext" to trump it, even though not
381 in alphabetical order, since we don't do excluding version checks
382 for v0..v10. */
383 {"bwf",
384 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
385 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
386 cris_ver_v10,
387 cris_eight_bit_offset_branch_op},
388
389 {"bext",
390 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
391 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
392 cris_ver_v0_3,
393 cris_eight_bit_offset_branch_op},
394
395 {"bge",
396 BRANCH_QUICK_OPCODE+CC_GE*0x1000,
397 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
398 cris_eight_bit_offset_branch_op},
399
400 {"bgt",
401 BRANCH_QUICK_OPCODE+CC_GT*0x1000,
402 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
403 cris_eight_bit_offset_branch_op},
404
405 {"bhi",
406 BRANCH_QUICK_OPCODE+CC_HI*0x1000,
407 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
408 cris_eight_bit_offset_branch_op},
409
410 {"bhs",
411 BRANCH_QUICK_OPCODE+CC_HS*0x1000,
412 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
413 cris_eight_bit_offset_branch_op},
414
415 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
416 cris_ver_v0_10,
417 cris_biap_prefix},
418
419 {"ble",
420 BRANCH_QUICK_OPCODE+CC_LE*0x1000,
421 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
422 cris_eight_bit_offset_branch_op},
423
424 {"blo",
425 BRANCH_QUICK_OPCODE+CC_LO*0x1000,
426 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
427 cris_eight_bit_offset_branch_op},
428
429 {"bls",
430 BRANCH_QUICK_OPCODE+CC_LS*0x1000,
431 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
432 cris_eight_bit_offset_branch_op},
433
434 {"blt",
435 BRANCH_QUICK_OPCODE+CC_LT*0x1000,
436 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
437 cris_eight_bit_offset_branch_op},
438
439 {"bmi",
440 BRANCH_QUICK_OPCODE+CC_MI*0x1000,
441 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
442 cris_eight_bit_offset_branch_op},
443
444 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
445 cris_ver_sim_v0_10,
446 cris_not_implemented_op},
447
448 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
449 cris_ver_sim_v0_10,
450 cris_not_implemented_op},
451
452 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
453 cris_ver_sim_v0_10,
454 cris_not_implemented_op},
455
456 {"bne",
457 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
458 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
459 cris_eight_bit_offset_branch_op},
460
461 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
462 cris_two_operand_bound_op},
463 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
464 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
465 cris_ver_v0_10,
466 cris_two_operand_bound_op},
467 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
468 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
469 cris_two_operand_bound_op},
470 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
471 cris_ver_v0_10,
472 cris_two_operand_bound_op},
473 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
474 cris_ver_v0_10,
475 cris_three_operand_bound_op},
476
477 {"bpl",
478 BRANCH_QUICK_OPCODE+CC_PL*0x1000,
479 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
480 cris_eight_bit_offset_branch_op},
481
482 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
483 cris_ver_v3p,
484 cris_break_op},
485
486 {"bsb",
487 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
488 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
489 cris_ver_v32p,
490 cris_eight_bit_offset_branch_op},
491
492 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
493 cris_ver_v32p,
494 cris_none_reg_mode_jump_op},
495
496 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
497 cris_ver_v32p,
498 cris_none_reg_mode_jump_op},
499
500 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
501 cris_ver_warning,
502 cris_not_implemented_op},
503
504 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
505 cris_ver_warning,
506 cris_not_implemented_op},
507
508 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
509 cris_ver_warning,
510 cris_not_implemented_op},
511
512 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
513 cris_btst_nop_op},
514 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
515 cris_btst_nop_op},
516
517 {"bvc",
518 BRANCH_QUICK_OPCODE+CC_VC*0x1000,
519 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
520 cris_eight_bit_offset_branch_op},
521
522 {"bvs",
523 BRANCH_QUICK_OPCODE+CC_VS*0x1000,
524 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
525 cris_eight_bit_offset_branch_op},
526
527 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
528 cris_reg_mode_clear_op},
529
530 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
531 cris_none_reg_mode_clear_test_op},
532
533 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
534 cris_ver_v0_10,
535 cris_none_reg_mode_clear_test_op},
536
537 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
538 cris_clearf_di_op},
539
540 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
541 cris_reg_mode_add_sub_cmp_and_or_move_op},
542
543 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
544 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
545
546 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
547 cris_ver_v0_10,
548 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
549
550 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
551 cris_quick_mode_and_cmp_move_or_op},
552
553 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
554 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
555 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
556
557 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
558 cris_ver_v0_10,
559 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
560
561 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
562 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
563 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
564
565 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
566 cris_ver_v0_10,
567 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
568
569 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
570 cris_clearf_di_op},
571
572 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
573 cris_ver_v0_10,
574 cris_dip_prefix},
575
576 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
577 cris_not_implemented_op},
578
579 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
580 cris_dstep_logshift_mstep_neg_not_op},
581
582 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
583 cris_ax_ei_setf_op},
584
585 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
586 cris_ver_v32p,
587 cris_not_implemented_op},
588
589 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
590 cris_ver_v32p,
591 cris_not_implemented_op},
592
593 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
594 cris_ver_v32p,
595 cris_not_implemented_op},
596
597 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
598 cris_ver_v32p,
599 cris_not_implemented_op},
600
601 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
602 cris_ver_v32p,
603 cris_not_implemented_op},
604
605 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
606 cris_ver_v32p,
607 cris_reg_mode_jump_op},
608
609 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
610 cris_ver_v32p,
611 cris_reg_mode_jump_op},
612
613 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
614 cris_ver_v32p,
615 cris_reg_mode_jump_op},
616
617 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
618 cris_ver_v32p,
619 cris_reg_mode_jump_op},
620
621 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
622 cris_ver_v8_10,
623 cris_reg_mode_jump_op},
624
625 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
626 cris_ver_v8_10,
627 cris_none_reg_mode_jump_op},
628
629 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
630 cris_ver_v8_10,
631 cris_none_reg_mode_jump_op},
632
633 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
634 cris_ver_v8_10,
635 cris_reg_mode_jump_op},
636
637 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
638 cris_ver_v8_10,
639 cris_none_reg_mode_jump_op},
640
641 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
642 cris_ver_v8_10,
643 cris_none_reg_mode_jump_op},
644
645 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
646 cris_ver_v8_10,
647 cris_reg_mode_jump_op},
648
649 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
650 cris_ver_v8_10,
651 cris_none_reg_mode_jump_op},
652
653 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
654 cris_ver_v8_10,
655 cris_none_reg_mode_jump_op},
656
657 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
658 cris_reg_mode_jump_op},
659
660 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
661 cris_ver_v0_10,
662 cris_none_reg_mode_jump_op},
663
664 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
665 cris_ver_v32p,
666 cris_none_reg_mode_jump_op},
667
668 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
669 cris_ver_v0_10,
670 cris_none_reg_mode_jump_op},
671
672 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
673 cris_ver_v8_10,
674 cris_reg_mode_jump_op},
675
676 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
677 cris_ver_v8_10,
678 cris_none_reg_mode_jump_op},
679
680 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
681 cris_ver_v8_10,
682 cris_none_reg_mode_jump_op},
683
684 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
685 cris_ver_v32p,
686 cris_reg_mode_jump_op},
687
688 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
689 cris_ver_v32p,
690 cris_reg_mode_jump_op},
691
692 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
693 cris_reg_mode_jump_op},
694
695 {"jump",
696 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
697 cris_ver_v0_10,
698 cris_none_reg_mode_jump_op},
699
700 {"jump",
701 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
702 cris_ver_v0_10,
703 cris_none_reg_mode_jump_op},
704
705 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
706 cris_ver_v32p,
707 cris_none_reg_mode_jump_op},
708
709 {"jump",
710 JUMP_PC_INCR_OPCODE_V32,
711 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
712 cris_ver_v32p,
713 cris_none_reg_mode_jump_op},
714
715 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
716 cris_ver_v10,
717 cris_none_reg_mode_jump_op},
718
719 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
720 cris_ver_v10,
721 cris_none_reg_mode_jump_op},
722
723 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
724 cris_ver_v32p,
725 cris_not_implemented_op},
726
727 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
728 cris_ver_v32p,
729 cris_not_implemented_op},
730
731 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
732 cris_ver_v32p,
733 cris_addi_op},
734
735 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
736 cris_dstep_logshift_mstep_neg_not_op},
737
738 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
739 cris_dstep_logshift_mstep_neg_not_op},
740
741 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
742 cris_dstep_logshift_mstep_neg_not_op},
743
744 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
745 cris_dstep_logshift_mstep_neg_not_op},
746
747 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
748 cris_ver_v3p,
749 cris_not_implemented_op},
750
751 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
752 cris_ver_v32p,
753 cris_not_implemented_op},
754
755 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
756 cris_reg_mode_add_sub_cmp_and_or_move_op},
757
758 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
759 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
760
761 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
762 cris_ver_v0_10,
763 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
764
765 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
766 cris_move_to_preg_op},
767
768 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
769 cris_reg_mode_move_from_preg_op},
770
771 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
772 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
773
774 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
775 cris_ver_v0_10,
776 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
777
778 {"move",
779 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
780 "s,P", 0, SIZE_SPEC_REG, 0,
781 cris_move_to_preg_op},
782
783 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
784 cris_ver_v0_10,
785 cris_move_to_preg_op},
786
787 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
788 cris_none_reg_mode_move_from_preg_op},
789
790 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
791 cris_ver_v0_10,
792 cris_none_reg_mode_move_from_preg_op},
793
794 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
795 cris_ver_v32p,
796 cris_not_implemented_op},
797
798 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
799 cris_ver_v32p,
800 cris_not_implemented_op},
801
802 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
803 cris_move_reg_to_mem_movem_op},
804
805 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
806 cris_ver_v0_10,
807 cris_move_reg_to_mem_movem_op},
808
809 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
810 cris_move_mem_to_reg_movem_op},
811
812 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
813 cris_ver_v0_10,
814 cris_move_mem_to_reg_movem_op},
815
816 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
817 cris_quick_mode_and_cmp_move_or_op},
818
819 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
820 cris_reg_mode_add_sub_cmp_and_or_move_op},
821
822 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
823 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
824 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
825
826 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
827 cris_ver_v0_10,
828 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
829
830 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
831 cris_reg_mode_add_sub_cmp_and_or_move_op},
832
833 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
834 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
835 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
836
837 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
838 cris_ver_v0_10,
839 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
840
841 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
842 cris_ver_v0_10,
843 cris_dstep_logshift_mstep_neg_not_op},
844
845 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
846 cris_ver_v10p,
847 cris_muls_op},
848
849 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
850 cris_ver_v10p,
851 cris_mulu_op},
852
853 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
854 cris_dstep_logshift_mstep_neg_not_op},
855
856 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
857 cris_ver_v0_10,
858 cris_btst_nop_op},
859
860 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
861 cris_ver_v32p,
862 cris_btst_nop_op},
863
864 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
865 cris_dstep_logshift_mstep_neg_not_op},
866
867 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
868 cris_reg_mode_add_sub_cmp_and_or_move_op},
869
870 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
871 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
872
873 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
874 cris_ver_v0_10,
875 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
876
877 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
878 cris_ver_v0_10,
879 cris_three_operand_add_sub_cmp_and_or_op},
880
881 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
882 cris_quick_mode_and_cmp_move_or_op},
883
884 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
885 cris_ver_v0_10,
886 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
887
888 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
889 cris_ver_v0_10,
890 cris_none_reg_mode_move_from_preg_op},
891
892 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
893 cris_ver_v0_10,
894 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
895
896 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
897 cris_ver_v0_10,
898 cris_move_to_preg_op},
899
900 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
901 cris_ver_v10,
902 cris_not_implemented_op},
903
904 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
905 cris_ver_v10,
906 cris_not_implemented_op},
907
908 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
909 cris_ver_v32p,
910 cris_not_implemented_op},
911
912 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
913 cris_ver_v32p,
914 cris_not_implemented_op},
915
916 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
917 cris_ver_v32p,
918 cris_not_implemented_op},
919
920 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
921 cris_ver_v0_10,
922 cris_reg_mode_move_from_preg_op},
923
924 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
925 cris_ver_v32p,
926 cris_reg_mode_move_from_preg_op},
927
928 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
929 cris_ver_v0_10,
930 cris_reg_mode_move_from_preg_op},
931
932 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
933 cris_ver_v32p,
934 cris_reg_mode_move_from_preg_op},
935
936 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
937 cris_ver_v0_10,
938 cris_reg_mode_move_from_preg_op},
939
940 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
941 cris_ver_v32p,
942 cris_reg_mode_move_from_preg_op},
943
944 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
945 cris_ver_v10,
946 cris_not_implemented_op},
947
948 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
949 cris_ver_v10,
950 cris_not_implemented_op},
951
952 {"sa",
953 0x0530+CC_A*0x1000,
954 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
955 cris_scc_op},
956
957 {"ssb",
958 0x0530+CC_EXT*0x1000,
959 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
960 cris_ver_v32p,
961 cris_scc_op},
962
963 {"scc",
964 0x0530+CC_CC*0x1000,
965 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
966 cris_scc_op},
967
968 {"scs",
969 0x0530+CC_CS*0x1000,
970 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
971 cris_scc_op},
972
973 {"seq",
974 0x0530+CC_EQ*0x1000,
975 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
976 cris_scc_op},
977
978 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
979 cris_ax_ei_setf_op},
980
981 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
982 cris_ver_v32p,
983 cris_not_implemented_op},
984
985 /* Need to have "swf" in front of "sext" so it is the one displayed in
986 disassembly. */
987 {"swf",
988 0x0530+CC_EXT*0x1000,
989 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
990 cris_ver_v10,
991 cris_scc_op},
992
993 {"sext",
994 0x0530+CC_EXT*0x1000,
995 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
996 cris_ver_v0_3,
997 cris_scc_op},
998
999 {"sge",
1000 0x0530+CC_GE*0x1000,
1001 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
1002 cris_scc_op},
1003
1004 {"sgt",
1005 0x0530+CC_GT*0x1000,
1006 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
1007 cris_scc_op},
1008
1009 {"shi",
1010 0x0530+CC_HI*0x1000,
1011 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
1012 cris_scc_op},
1013
1014 {"shs",
1015 0x0530+CC_HS*0x1000,
1016 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
1017 cris_scc_op},
1018
1019 {"sle",
1020 0x0530+CC_LE*0x1000,
1021 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
1022 cris_scc_op},
1023
1024 {"slo",
1025 0x0530+CC_LO*0x1000,
1026 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
1027 cris_scc_op},
1028
1029 {"sls",
1030 0x0530+CC_LS*0x1000,
1031 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
1032 cris_scc_op},
1033
1034 {"slt",
1035 0x0530+CC_LT*0x1000,
1036 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
1037 cris_scc_op},
1038
1039 {"smi",
1040 0x0530+CC_MI*0x1000,
1041 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
1042 cris_scc_op},
1043
1044 {"sne",
1045 0x0530+CC_NE*0x1000,
1046 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
1047 cris_scc_op},
1048
1049 {"spl",
1050 0x0530+CC_PL*0x1000,
1051 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
1052 cris_scc_op},
1053
1054 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
1055 cris_reg_mode_add_sub_cmp_and_or_move_op},
1056
1057 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
1058 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1059
1060 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
1061 cris_ver_v0_10,
1062 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1063
1064 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
1065 cris_ver_v0_10,
1066 cris_three_operand_add_sub_cmp_and_or_op},
1067
1068 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
1069 cris_quick_mode_add_sub_op},
1070
1071 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
1072 cris_reg_mode_add_sub_cmp_and_or_move_op},
1073
1074 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
1075 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
1076 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1077
1078 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
1079 cris_ver_v0_10,
1080 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1081
1082 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
1083 cris_ver_v0_10,
1084 cris_three_operand_add_sub_cmp_and_or_op},
1085
1086 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
1087 cris_reg_mode_add_sub_cmp_and_or_move_op},
1088
1089 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
1090 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
1091 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1092
1093 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
1094 cris_ver_v0_10,
1095 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1096
1097 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
1098 cris_ver_v0_10,
1099 cris_three_operand_add_sub_cmp_and_or_op},
1100
1101 {"svc",
1102 0x0530+CC_VC*0x1000,
1103 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
1104 cris_scc_op},
1105
1106 {"svs",
1107 0x0530+CC_VS*0x1000,
1108 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
1109 cris_scc_op},
1110
1111 /* The insn "swapn" is the same as "not" and will be disassembled as
1112 such, but the swap* family of mnmonics are generally v8-and-higher
1113 only, so count it in. */
1114 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
1115 cris_ver_v8p,
1116 cris_not_implemented_op},
1117
1118 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
1119 cris_ver_v8p,
1120 cris_not_implemented_op},
1121
1122 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
1123 cris_ver_v8p,
1124 cris_not_implemented_op},
1125
1126 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
1127 cris_ver_v8p,
1128 cris_not_implemented_op},
1129
1130 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
1131 cris_ver_v8p,
1132 cris_not_implemented_op},
1133
1134 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
1135 cris_ver_v8p,
1136 cris_not_implemented_op},
1137
1138 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
1139 cris_ver_v8p,
1140 cris_not_implemented_op},
1141
1142 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
1143 cris_ver_v8p,
1144 cris_not_implemented_op},
1145
1146 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
1147 cris_ver_v8p,
1148 cris_not_implemented_op},
1149
1150 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
1151 cris_ver_v8p,
1152 cris_not_implemented_op},
1153
1154 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
1155 cris_ver_v8p,
1156 cris_not_implemented_op},
1157
1158 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
1159 cris_ver_v8p,
1160 cris_not_implemented_op},
1161
1162 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
1163 cris_ver_v8p,
1164 cris_not_implemented_op},
1165
1166 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
1167 cris_ver_v8p,
1168 cris_not_implemented_op},
1169
1170 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
1171 cris_ver_v8p,
1172 cris_not_implemented_op},
1173
1174 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
1175 cris_ver_v0_10,
1176 cris_reg_mode_test_op},
1177
1178 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
1179 cris_none_reg_mode_clear_test_op},
1180
1181 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
1182 cris_ver_v0_10,
1183 cris_none_reg_mode_clear_test_op},
1184
1185 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
1186 cris_xor_op},
1187
1188 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1189 };
1190
1191 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1192 const char * const
1193 cris_cc_strings[] =
1194 {
1195 "hs",
1196 "lo",
1197 "ne",
1198 "eq",
1199 "vc",
1200 "vs",
1201 "pl",
1202 "mi",
1203 "ls",
1204 "hi",
1205 "ge",
1206 "lt",
1207 "gt",
1208 "le",
1209 "a",
1210 /* This is a placeholder. In v0, this would be "ext". In v32, this
1211 is "sb". */
1212 "wf"
1213 };
1214
1215 /*
1216 * Local variables:
1217 * eval: (c-set-style "gnu")
1218 * indent-tabs-mode: t
1219 * End:
1220 */
1221
1222
1223 /* No instruction will be disassembled longer than this. In theory, and
1224 in silicon, address prefixes can be cascaded. In practice, cascading
1225 is not used by GCC, and not supported by the assembler. */
1226 #ifndef MAX_BYTES_PER_CRIS_INSN
1227 #define MAX_BYTES_PER_CRIS_INSN 8
1228 #endif
1229
1230 /* Whether or not to decode prefixes, folding it into the following
1231 instruction. FIXME: Make this optional later. */
1232 #ifndef PARSE_PREFIX
1233 #define PARSE_PREFIX 1
1234 #endif
1235
1236 /* Sometimes we prefix all registers with this character. */
1237 #define REGISTER_PREFIX_CHAR '$'
1238
1239 /* Whether or not to trace the following sequence:
1240 sub* X,r%d
1241 bound* Y,r%d
1242 adds.w [pc+r%d.w],pc
1243
1244 This is the assembly form of a switch-statement in C.
1245 The "sub is optional. If there is none, then X will be zero.
1246 X is the value of the first case,
1247 Y is the number of cases (including default).
1248
1249 This results in case offsets printed on the form:
1250 case N: -> case_address
1251 where N is an estimation on the corresponding 'case' operand in C,
1252 and case_address is where execution of that case continues after the
1253 sequence presented above.
1254
1255 The old style of output was to print the offsets as instructions,
1256 which made it hard to follow "case"-constructs in the disassembly,
1257 and caused a lot of annoying warnings about undefined instructions.
1258
1259 FIXME: Make this optional later. */
1260 #ifndef TRACE_CASE
1261 #define TRACE_CASE (disdata->trace_case)
1262 #endif
1263
1264 enum cris_disass_family
1265 { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
1266
1267 /* Stored in the disasm_info->private_data member. */
1268 struct cris_disasm_data
1269 {
1270 /* Whether to print something less confusing if we find something
1271 matching a switch-construct. */
1272 bfd_boolean trace_case;
1273
1274 /* Whether this code is flagged as crisv32. FIXME: Should be an enum
1275 that includes "compatible". */
1276 enum cris_disass_family distype;
1277 };
1278
1279 /* Value of first element in switch. */
1280 static long case_offset = 0;
1281
1282 /* How many more case-offsets to print. */
1283 static long case_offset_counter = 0;
1284
1285 /* Number of case offsets. */
1286 static long no_of_case_offsets = 0;
1287
1288 /* Candidate for next case_offset. */
1289 static long last_immediate = 0;
1290
1291 static int cris_constraint
1292 (const char *, unsigned, unsigned, struct cris_disasm_data *);
1293
1294 /* Parse disassembler options and store state in info. FIXME: For the
1295 time being, we abuse static variables. */
1296
1297 static bfd_boolean
1298 cris_parse_disassembler_options (disassemble_info *info,
1299 enum cris_disass_family distype)
1300 {
1301 struct cris_disasm_data *disdata;
1302
1303 info->private_data = calloc (1, sizeof (struct cris_disasm_data));
1304 disdata = (struct cris_disasm_data *) info->private_data;
1305 if (disdata == NULL)
1306 return false;
1307
1308 /* Default true. */
1309 disdata->trace_case
1310 = (info->disassembler_options == NULL
1311 || (strcmp (info->disassembler_options, "nocase") != 0));
1312
1313 disdata->distype = distype;
1314 return true;
1315 }
1316
1317 static const struct cris_spec_reg *
1318 spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
1319 {
1320 int i;
1321
1322 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1323 {
1324 if (cris_spec_regs[i].number == sreg)
1325 {
1326 if (distype == cris_dis_v32)
1327 switch (cris_spec_regs[i].applicable_version)
1328 {
1329 case cris_ver_warning:
1330 case cris_ver_version_all:
1331 case cris_ver_v3p:
1332 case cris_ver_v8p:
1333 case cris_ver_v10p:
1334 case cris_ver_v32p:
1335 /* No ambiguous sizes or register names with CRISv32. */
1336 if (cris_spec_regs[i].warning == NULL)
1337 return &cris_spec_regs[i];
1338 default:
1339 ;
1340 }
1341 else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
1342 return &cris_spec_regs[i];
1343 }
1344 }
1345
1346 return NULL;
1347 }
1348
1349 /* Return the number of bits in the argument. */
1350
1351 static int
1352 number_of_bits (unsigned int val)
1353 {
1354 int bits;
1355
1356 for (bits = 0; val != 0; val &= val - 1)
1357 bits++;
1358
1359 return bits;
1360 }
1361
1362 /* Get an entry in the opcode-table. */
1363
1364 static const struct cris_opcode *
1365 get_opcode_entry (unsigned int insn,
1366 unsigned int prefix_insn,
1367 struct cris_disasm_data *disdata)
1368 {
1369 /* For non-prefixed insns, we keep a table of pointers, indexed by the
1370 insn code. Each entry is initialized when found to be NULL. */
1371 static const struct cris_opcode **opc_table = NULL;
1372
1373 const struct cris_opcode *max_matchedp = NULL;
1374 const struct cris_opcode **prefix_opc_table = NULL;
1375
1376 /* We hold a table for each prefix that need to be handled differently. */
1377 static const struct cris_opcode **dip_prefixes = NULL;
1378 static const struct cris_opcode **bdapq_m1_prefixes = NULL;
1379 static const struct cris_opcode **bdapq_m2_prefixes = NULL;
1380 static const struct cris_opcode **bdapq_m4_prefixes = NULL;
1381 static const struct cris_opcode **rest_prefixes = NULL;
1382
1383 /* Allocate and clear the opcode-table. */
1384 if (opc_table == NULL)
1385 {
1386 opc_table = g_new0(const struct cris_opcode *, 65536);
1387 dip_prefixes = g_new0(const struct cris_opcode *, 65536);
1388 bdapq_m1_prefixes = g_new0(const struct cris_opcode *, 65536);
1389 bdapq_m2_prefixes = g_new0(const struct cris_opcode *, 65536);
1390 bdapq_m4_prefixes = g_new0(const struct cris_opcode *, 65536);
1391 rest_prefixes = g_new0(const struct cris_opcode *, 65536);
1392 }
1393
1394 /* Get the right table if this is a prefix.
1395 This code is connected to cris_constraints in that it knows what
1396 prefixes play a role in recognition of patterns; the necessary
1397 state is reflected by which table is used. If constraints
1398 involving match or non-match of prefix insns are changed, then this
1399 probably needs changing too. */
1400 if (prefix_insn != NO_CRIS_PREFIX)
1401 {
1402 const struct cris_opcode *popcodep
1403 = (opc_table[prefix_insn] != NULL
1404 ? opc_table[prefix_insn]
1405 : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
1406
1407 if (popcodep == NULL)
1408 return NULL;
1409
1410 if (popcodep->match == BDAP_QUICK_OPCODE)
1411 {
1412 /* Since some offsets are recognized with "push" macros, we
1413 have to have different tables for them. */
1414 int offset = (prefix_insn & 255);
1415
1416 if (offset > 127)
1417 offset -= 256;
1418
1419 switch (offset)
1420 {
1421 case -4:
1422 prefix_opc_table = bdapq_m4_prefixes;
1423 break;
1424
1425 case -2:
1426 prefix_opc_table = bdapq_m2_prefixes;
1427 break;
1428
1429 case -1:
1430 prefix_opc_table = bdapq_m1_prefixes;
1431 break;
1432
1433 default:
1434 prefix_opc_table = rest_prefixes;
1435 break;
1436 }
1437 }
1438 else if (popcodep->match == DIP_OPCODE)
1439 /* We don't allow postincrement when the prefix is DIP, so use a
1440 different table for DIP. */
1441 prefix_opc_table = dip_prefixes;
1442 else
1443 prefix_opc_table = rest_prefixes;
1444 }
1445
1446 if (prefix_insn != NO_CRIS_PREFIX
1447 && prefix_opc_table[insn] != NULL)
1448 max_matchedp = prefix_opc_table[insn];
1449 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
1450 max_matchedp = opc_table[insn];
1451 else
1452 {
1453 const struct cris_opcode *opcodep;
1454 int max_level_of_match = -1;
1455
1456 for (opcodep = cris_opcodes;
1457 opcodep->name != NULL;
1458 opcodep++)
1459 {
1460 int level_of_match;
1461
1462 if (disdata->distype == cris_dis_v32)
1463 {
1464 switch (opcodep->applicable_version)
1465 {
1466 case cris_ver_version_all:
1467 break;
1468
1469 case cris_ver_v0_3:
1470 case cris_ver_v0_10:
1471 case cris_ver_v3_10:
1472 case cris_ver_sim_v0_10:
1473 case cris_ver_v8_10:
1474 case cris_ver_v10:
1475 case cris_ver_warning:
1476 continue;
1477
1478 case cris_ver_v3p:
1479 case cris_ver_v8p:
1480 case cris_ver_v10p:
1481 case cris_ver_v32p:
1482 break;
1483
1484 case cris_ver_v8:
1485 abort ();
1486 default:
1487 abort ();
1488 }
1489 }
1490 else
1491 {
1492 switch (opcodep->applicable_version)
1493 {
1494 case cris_ver_version_all:
1495 case cris_ver_v0_3:
1496 case cris_ver_v3p:
1497 case cris_ver_v0_10:
1498 case cris_ver_v8p:
1499 case cris_ver_v8_10:
1500 case cris_ver_v10:
1501 case cris_ver_sim_v0_10:
1502 case cris_ver_v10p:
1503 case cris_ver_warning:
1504 break;
1505
1506 case cris_ver_v32p:
1507 continue;
1508
1509 case cris_ver_v8:
1510 abort ();
1511 default:
1512 abort ();
1513 }
1514 }
1515
1516 /* We give a double lead for bits matching the template in
1517 cris_opcodes. Not even, because then "move p8,r10" would
1518 be given 2 bits lead over "clear.d r10". When there's a
1519 tie, the first entry in the table wins. This is
1520 deliberate, to avoid a more complicated recognition
1521 formula. */
1522 if ((opcodep->match & insn) == opcodep->match
1523 && (opcodep->lose & insn) == 0
1524 && ((level_of_match
1525 = cris_constraint (opcodep->args,
1526 insn,
1527 prefix_insn,
1528 disdata))
1529 >= 0)
1530 && ((level_of_match
1531 += 2 * number_of_bits (opcodep->match
1532 | opcodep->lose))
1533 > max_level_of_match))
1534 {
1535 max_matchedp = opcodep;
1536 max_level_of_match = level_of_match;
1537
1538 /* If there was a full match, never mind looking
1539 further. */
1540 if (level_of_match >= 2 * 16)
1541 break;
1542 }
1543 }
1544 /* Fill in the new entry.
1545
1546 If there are changes to the opcode-table involving prefixes, and
1547 disassembly then does not work correctly, try removing the
1548 else-clause below that fills in the prefix-table. If that
1549 helps, you need to change the prefix_opc_table setting above, or
1550 something related. */
1551 if (prefix_insn == NO_CRIS_PREFIX)
1552 opc_table[insn] = max_matchedp;
1553 else
1554 prefix_opc_table[insn] = max_matchedp;
1555 }
1556
1557 return max_matchedp;
1558 }
1559
1560 /* Return -1 if the constraints of a bitwise-matched instruction say
1561 that there is no match. Otherwise return a nonnegative number
1562 indicating the confidence in the match (higher is better). */
1563
1564 static int
1565 cris_constraint (const char *cs,
1566 unsigned int insn,
1567 unsigned int prefix_insn,
1568 struct cris_disasm_data *disdata)
1569 {
1570 int retval = 0;
1571 int tmp;
1572 int prefix_ok = 0;
1573 const char *s;
1574
1575 for (s = cs; *s; s++)
1576 switch (*s)
1577 {
1578 case '!':
1579 /* Do not recognize "pop" if there's a prefix and then only for
1580 v0..v10. */
1581 if (prefix_insn != NO_CRIS_PREFIX
1582 || disdata->distype != cris_dis_v0_v10)
1583 return -1;
1584 break;
1585
1586 case 'U':
1587 /* Not recognized at disassembly. */
1588 return -1;
1589
1590 case 'M':
1591 /* Size modifier for "clear", i.e. special register 0, 4 or 8.
1592 Check that it is one of them. Only special register 12 could
1593 be mismatched, but checking for matches is more logical than
1594 checking for mismatches when there are only a few cases. */
1595 tmp = ((insn >> 12) & 0xf);
1596 if (tmp != 0 && tmp != 4 && tmp != 8)
1597 return -1;
1598 break;
1599
1600 case 'm':
1601 if ((insn & 0x30) == 0x30)
1602 return -1;
1603 break;
1604
1605 case 'S':
1606 /* A prefix operand without side-effect. */
1607 if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
1608 {
1609 prefix_ok = 1;
1610 break;
1611 }
1612 else
1613 return -1;
1614
1615 case 's':
1616 case 'y':
1617 case 'Y':
1618 /* If this is a prefixed insn with postincrement (side-effect),
1619 the prefix must not be DIP. */
1620 if (prefix_insn != NO_CRIS_PREFIX)
1621 {
1622 if (insn & 0x400)
1623 {
1624 const struct cris_opcode *prefix_opcodep
1625 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1626
1627 if (prefix_opcodep->match == DIP_OPCODE)
1628 return -1;
1629 }
1630
1631 prefix_ok = 1;
1632 }
1633 break;
1634
1635 case 'B':
1636 /* If we don't fall through, then the prefix is ok. */
1637 prefix_ok = 1;
1638
1639 /* A "push" prefix. Check for valid "push" size.
1640 In case of special register, it may be != 4. */
1641 if (prefix_insn != NO_CRIS_PREFIX)
1642 {
1643 /* Match the prefix insn to BDAPQ. */
1644 const struct cris_opcode *prefix_opcodep
1645 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1646
1647 if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
1648 {
1649 int pushsize = (prefix_insn & 255);
1650
1651 if (pushsize > 127)
1652 pushsize -= 256;
1653
1654 if (s[1] == 'P')
1655 {
1656 unsigned int spec_reg = (insn >> 12) & 15;
1657 const struct cris_spec_reg *sregp
1658 = spec_reg_info (spec_reg, disdata->distype);
1659
1660 /* For a special-register, the "prefix size" must
1661 match the size of the register. */
1662 if (sregp && sregp->reg_size == (unsigned int) -pushsize)
1663 break;
1664 }
1665 else if (s[1] == 'R')
1666 {
1667 if ((insn & 0x30) == 0x20 && pushsize == -4)
1668 break;
1669 }
1670 /* FIXME: Should abort here; next constraint letter
1671 *must* be 'P' or 'R'. */
1672 }
1673 }
1674 return -1;
1675
1676 case 'D':
1677 retval = (((insn >> 12) & 15) == (insn & 15));
1678 if (!retval)
1679 return -1;
1680 else
1681 retval += 4;
1682 break;
1683
1684 case 'P':
1685 {
1686 const struct cris_spec_reg *sregp
1687 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
1688
1689 /* Since we match four bits, we will give a value of 4-1 = 3
1690 in a match. If there is a corresponding exact match of a
1691 special register in another pattern, it will get a value of
1692 4, which will be higher. This should be correct in that an
1693 exact pattern would match better than a general pattern.
1694
1695 Note that there is a reason for not returning zero; the
1696 pattern for "clear" is partly matched in the bit-pattern
1697 (the two lower bits must be zero), while the bit-pattern
1698 for a move from a special register is matched in the
1699 register constraint. */
1700
1701 if (sregp != NULL)
1702 {
1703 retval += 3;
1704 break;
1705 }
1706 else
1707 return -1;
1708 }
1709 }
1710
1711 if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
1712 return -1;
1713
1714 return retval;
1715 }
1716
1717 /* Format number as hex with a leading "0x" into outbuffer. */
1718
1719 static char *
1720 format_hex (unsigned long number,
1721 char *outbuffer,
1722 struct cris_disasm_data *disdata)
1723 {
1724 /* Truncate negative numbers on >32-bit hosts. */
1725 number &= 0xffffffff;
1726
1727 sprintf (outbuffer, "0x%lx", number);
1728
1729 /* Save this value for the "case" support. */
1730 if (TRACE_CASE)
1731 last_immediate = number;
1732
1733 return outbuffer + strlen (outbuffer);
1734 }
1735
1736 /* Format number as decimal into outbuffer. Parameter signedp says
1737 whether the number should be formatted as signed (!= 0) or
1738 unsigned (== 0). */
1739
1740 static char *
1741 format_dec (long number, char *outbuffer, int signedp)
1742 {
1743 last_immediate = number;
1744 sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
1745
1746 return outbuffer + strlen (outbuffer);
1747 }
1748
1749 /* Format the name of the general register regno into outbuffer. */
1750
1751 static char *
1752 format_reg (struct cris_disasm_data *disdata,
1753 int regno,
1754 char *outbuffer_start,
1755 bfd_boolean with_reg_prefix)
1756 {
1757 char *outbuffer = outbuffer_start;
1758
1759 if (with_reg_prefix)
1760 *outbuffer++ = REGISTER_PREFIX_CHAR;
1761
1762 switch (regno)
1763 {
1764 case 15:
1765 /* For v32, there is no context in which we output PC. */
1766 if (disdata->distype == cris_dis_v32)
1767 strcpy (outbuffer, "acr");
1768 else
1769 strcpy (outbuffer, "pc");
1770 break;
1771
1772 case 14:
1773 strcpy (outbuffer, "sp");
1774 break;
1775
1776 default:
1777 sprintf (outbuffer, "r%d", regno);
1778 break;
1779 }
1780
1781 return outbuffer_start + strlen (outbuffer_start);
1782 }
1783
1784 /* Format the name of a support register into outbuffer. */
1785
1786 static char *
1787 format_sup_reg (unsigned int regno,
1788 char *outbuffer_start,
1789 bfd_boolean with_reg_prefix)
1790 {
1791 char *outbuffer = outbuffer_start;
1792 int i;
1793
1794 if (with_reg_prefix)
1795 *outbuffer++ = REGISTER_PREFIX_CHAR;
1796
1797 for (i = 0; cris_support_regs[i].name != NULL; i++)
1798 if (cris_support_regs[i].number == regno)
1799 {
1800 sprintf (outbuffer, "%s", cris_support_regs[i].name);
1801 return outbuffer_start + strlen (outbuffer_start);
1802 }
1803
1804 /* There's supposed to be register names covering all numbers, though
1805 some may be generic names. */
1806 sprintf (outbuffer, "format_sup_reg-BUG");
1807 return outbuffer_start + strlen (outbuffer_start);
1808 }
1809
1810 /* Return the length of an instruction. */
1811
1812 static unsigned
1813 bytes_to_skip (unsigned int insn,
1814 const struct cris_opcode *matchedp,
1815 enum cris_disass_family distype,
1816 const struct cris_opcode *prefix_matchedp)
1817 {
1818 /* Each insn is a word plus "immediate" operands. */
1819 unsigned to_skip = 2;
1820 const char *template = matchedp->args;
1821 const char *s;
1822
1823 for (s = template; *s; s++)
1824 if ((*s == 's' || *s == 'N' || *s == 'Y')
1825 && (insn & 0x400) && (insn & 15) == 15
1826 && prefix_matchedp == NULL)
1827 {
1828 /* Immediate via [pc+], so we have to check the size of the
1829 operand. */
1830 int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
1831
1832 if (matchedp->imm_oprnd_size == SIZE_FIX_32)
1833 to_skip += 4;
1834 else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
1835 {
1836 const struct cris_spec_reg *sregp
1837 = spec_reg_info ((insn >> 12) & 15, distype);
1838
1839 /* FIXME: Improve error handling; should have been caught
1840 earlier. */
1841 if (sregp == NULL)
1842 return 2;
1843
1844 /* PC is incremented by two, not one, for a byte. Except on
1845 CRISv32, where constants are always DWORD-size for
1846 special registers. */
1847 to_skip +=
1848 distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
1849 }
1850 else
1851 to_skip += (mode_size + 1) & ~1;
1852 }
1853 else if (*s == 'n')
1854 to_skip += 4;
1855 else if (*s == 'b')
1856 to_skip += 2;
1857
1858 return to_skip;
1859 }
1860
1861 /* Print condition code flags. */
1862
1863 static char *
1864 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
1865 {
1866 /* Use the v8 (Etrax 100) flag definitions for disassembly.
1867 The differences with v0 (Etrax 1..4) vs. Svinto are:
1868 v0 'd' <=> v8 'm'
1869 v0 'e' <=> v8 'b'.
1870 FIXME: Emit v0..v3 flag names somehow. */
1871 static const char v8_fnames[] = "cvznxibm";
1872 static const char v32_fnames[] = "cvznxiup";
1873 const char *fnames
1874 = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
1875
1876 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
1877 int i;
1878
1879 for (i = 0; i < 8; i++)
1880 if (flagbits & (1 << i))
1881 *cp++ = fnames[i];
1882
1883 return cp;
1884 }
1885
1886 /* Print out an insn with its operands, and update the info->insn_type
1887 fields. The prefix_opcodep and the rest hold a prefix insn that is
1888 supposed to be output as an address mode. */
1889
1890 static void
1891 print_with_operands (const struct cris_opcode *opcodep,
1892 unsigned int insn,
1893 unsigned char *buffer,
1894 bfd_vma addr,
1895 disassemble_info *info,
1896 /* If a prefix insn was before this insn (and is supposed
1897 to be output as an address), here is a description of
1898 it. */
1899 const struct cris_opcode *prefix_opcodep,
1900 unsigned int prefix_insn,
1901 unsigned char *prefix_buffer,
1902 bfd_boolean with_reg_prefix)
1903 {
1904 /* Get a buffer of somewhat reasonable size where we store
1905 intermediate parts of the insn. */
1906 char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
1907 char *tp = temp;
1908 static const char mode_char[] = "bwd?";
1909 const char *s;
1910 const char *cs;
1911 struct cris_disasm_data *disdata
1912 = (struct cris_disasm_data *) info->private_data;
1913
1914 /* Print out the name first thing we do. */
1915 (*info->fprintf_func) (info->stream, "%s", opcodep->name);
1916
1917 cs = opcodep->args;
1918 s = cs;
1919
1920 /* Ignore any prefix indicator. */
1921 if (*s == 'p')
1922 s++;
1923
1924 if (*s == 'm' || *s == 'M' || *s == 'z')
1925 {
1926 *tp++ = '.';
1927
1928 /* Get the size-letter. */
1929 *tp++ = *s == 'M'
1930 ? (insn & 0x8000 ? 'd'
1931 : insn & 0x4000 ? 'w' : 'b')
1932 : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
1933
1934 /* Ignore the size and the space character that follows. */
1935 s += 2;
1936 }
1937
1938 /* Add a space if this isn't a long-branch, because for those will add
1939 the condition part of the name later. */
1940 if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
1941 *tp++ = ' ';
1942
1943 /* Fill in the insn-type if deducible from the name (and there's no
1944 better way). */
1945 if (opcodep->name[0] == 'j')
1946 {
1947 if (CONST_STRNEQ (opcodep->name, "jsr"))
1948 /* It's "jsr" or "jsrc". */
1949 info->insn_type = dis_jsr;
1950 else
1951 /* Any other jump-type insn is considered a branch. */
1952 info->insn_type = dis_branch;
1953 }
1954
1955 /* We might know some more fields right now. */
1956 info->branch_delay_insns = opcodep->delayed;
1957
1958 /* Handle operands. */
1959 for (; *s; s++)
1960 {
1961 switch (*s)
1962 {
1963 case 'T':
1964 tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
1965 break;
1966
1967 case 'A':
1968 if (with_reg_prefix)
1969 *tp++ = REGISTER_PREFIX_CHAR;
1970 *tp++ = 'a';
1971 *tp++ = 'c';
1972 *tp++ = 'r';
1973 break;
1974
1975 case '[':
1976 case ']':
1977 case ',':
1978 *tp++ = *s;
1979 break;
1980
1981 case '!':
1982 /* Ignore at this point; used at earlier stages to avoid
1983 recognition if there's a prefix at something that in other
1984 ways looks like a "pop". */
1985 break;
1986
1987 case 'd':
1988 /* Ignore. This is an optional ".d " on the large one of
1989 relaxable insns. */
1990 break;
1991
1992 case 'B':
1993 /* This was the prefix that made this a "push". We've already
1994 handled it by recognizing it, so signal that the prefix is
1995 handled by setting it to NULL. */
1996 prefix_opcodep = NULL;
1997 break;
1998
1999 case 'D':
2000 case 'r':
2001 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2002 break;
2003
2004 case 'R':
2005 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2006 break;
2007
2008 case 'n':
2009 {
2010 /* Like N but pc-relative to the start of the insn. */
2011 uint32_t number
2012 = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2013 + buffer[5] * 0x1000000 + addr);
2014
2015 /* Finish off and output previous formatted bytes. */
2016 *tp = 0;
2017 if (temp[0])
2018 (*info->fprintf_func) (info->stream, "%s", temp);
2019 tp = temp;
2020
2021 (*info->print_address_func) ((bfd_vma) number, info);
2022 }
2023 break;
2024
2025 case 'u':
2026 {
2027 /* Like n but the offset is bits <3:0> in the instruction. */
2028 unsigned long number = (buffer[0] & 0xf) * 2 + addr;
2029
2030 /* Finish off and output previous formatted bytes. */
2031 *tp = 0;
2032 if (temp[0])
2033 (*info->fprintf_func) (info->stream, "%s", temp);
2034 tp = temp;
2035
2036 (*info->print_address_func) ((bfd_vma) number, info);
2037 }
2038 break;
2039
2040 case 'N':
2041 case 'y':
2042 case 'Y':
2043 case 'S':
2044 case 's':
2045 /* Any "normal" memory operand. */
2046 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
2047 {
2048 /* We're looking at [pc+], i.e. we need to output an immediate
2049 number, where the size can depend on different things. */
2050 int32_t number;
2051 int signedp
2052 = ((*cs == 'z' && (insn & 0x20))
2053 || opcodep->match == BDAP_QUICK_OPCODE);
2054 int nbytes;
2055
2056 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2057 nbytes = 4;
2058 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2059 {
2060 const struct cris_spec_reg *sregp
2061 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2062
2063 /* A NULL return should have been as a non-match earlier,
2064 so catch it as an internal error in the error-case
2065 below. */
2066 if (sregp == NULL)
2067 /* Whatever non-valid size. */
2068 nbytes = 42;
2069 else
2070 /* PC is always incremented by a multiple of two.
2071 For CRISv32, immediates are always 4 bytes for
2072 special registers. */
2073 nbytes = disdata->distype == cris_dis_v32
2074 ? 4 : (sregp->reg_size + 1) & ~1;
2075 }
2076 else
2077 {
2078 int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
2079
2080 if (mode_size == 1)
2081 nbytes = 2;
2082 else
2083 nbytes = mode_size;
2084 }
2085
2086 switch (nbytes)
2087 {
2088 case 1:
2089 number = buffer[2];
2090 if (signedp && number > 127)
2091 number -= 256;
2092 break;
2093
2094 case 2:
2095 number = buffer[2] + buffer[3] * 256;
2096 if (signedp && number > 32767)
2097 number -= 65536;
2098 break;
2099
2100 case 4:
2101 number
2102 = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2103 + buffer[5] * 0x1000000;
2104 break;
2105
2106 default:
2107 strcpy (tp, "bug");
2108 tp += 3;
2109 number = 42;
2110 }
2111
2112 if ((*cs == 'z' && (insn & 0x20))
2113 || (opcodep->match == BDAP_QUICK_OPCODE
2114 && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
2115 tp = format_dec (number, tp, signedp);
2116 else
2117 {
2118 unsigned int highbyte = (number >> 24) & 0xff;
2119
2120 /* Either output this as an address or as a number. If it's
2121 a dword with the same high-byte as the address of the
2122 insn, assume it's an address, and also if it's a non-zero
2123 non-0xff high-byte. If this is a jsr or a jump, then
2124 it's definitely an address. */
2125 if (nbytes == 4
2126 && (highbyte == ((addr >> 24) & 0xff)
2127 || (highbyte != 0 && highbyte != 0xff)
2128 || info->insn_type == dis_branch
2129 || info->insn_type == dis_jsr))
2130 {
2131 /* Finish off and output previous formatted bytes. */
2132 *tp = 0;
2133 tp = temp;
2134 if (temp[0])
2135 (*info->fprintf_func) (info->stream, "%s", temp);
2136
2137 (*info->print_address_func) ((bfd_vma) number, info);
2138
2139 info->target = number;
2140 }
2141 else
2142 tp = format_hex (number, tp, disdata);
2143 }
2144 }
2145 else
2146 {
2147 /* Not an immediate number. Then this is a (possibly
2148 prefixed) memory operand. */
2149 if (info->insn_type != dis_nonbranch)
2150 {
2151 int mode_size
2152 = 1 << ((insn >> 4)
2153 & (opcodep->args[0] == 'z' ? 1 : 3));
2154 int size;
2155 info->insn_type = dis_dref;
2156 info->flags |= CRIS_DIS_FLAG_MEMREF;
2157
2158 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2159 size = 4;
2160 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2161 {
2162 const struct cris_spec_reg *sregp
2163 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2164
2165 /* FIXME: Improve error handling; should have been caught
2166 earlier. */
2167 if (sregp == NULL)
2168 size = 4;
2169 else
2170 size = sregp->reg_size;
2171 }
2172 else
2173 size = mode_size;
2174
2175 info->data_size = size;
2176 }
2177
2178 *tp++ = '[';
2179
2180 if (prefix_opcodep
2181 /* We don't match dip with a postincremented field
2182 as a side-effect address mode. */
2183 && ((insn & 0x400) == 0
2184 || prefix_opcodep->match != DIP_OPCODE))
2185 {
2186 if (insn & 0x400)
2187 {
2188 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2189 *tp++ = '=';
2190 }
2191
2192
2193 /* We mainly ignore the prefix format string when the
2194 address-mode syntax is output. */
2195 switch (prefix_opcodep->match)
2196 {
2197 case DIP_OPCODE:
2198 /* It's [r], [r+] or [pc+]. */
2199 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2200 {
2201 /* It's [pc+]. This cannot possibly be anything
2202 but an address. */
2203 uint32_t number
2204 = prefix_buffer[2] + prefix_buffer[3] * 256
2205 + prefix_buffer[4] * 65536
2206 + prefix_buffer[5] * 0x1000000;
2207
2208 info->target = (bfd_vma) number;
2209
2210 /* Finish off and output previous formatted
2211 data. */
2212 *tp = 0;
2213 tp = temp;
2214 if (temp[0])
2215 (*info->fprintf_func) (info->stream, "%s", temp);
2216
2217 (*info->print_address_func) ((bfd_vma) number, info);
2218 }
2219 else
2220 {
2221 /* For a memref in an address, we use target2.
2222 In this case, target is zero. */
2223 info->flags
2224 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2225 | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
2226
2227 info->target2 = prefix_insn & 15;
2228
2229 *tp++ = '[';
2230 tp = format_reg (disdata, prefix_insn & 15, tp,
2231 with_reg_prefix);
2232 if (prefix_insn & 0x400)
2233 *tp++ = '+';
2234 *tp++ = ']';
2235 }
2236 break;
2237
2238 case BDAP_QUICK_OPCODE:
2239 {
2240 int number;
2241
2242 number = prefix_buffer[0];
2243 if (number > 127)
2244 number -= 256;
2245
2246 /* Output "reg+num" or, if num < 0, "reg-num". */
2247 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2248 with_reg_prefix);
2249 if (number >= 0)
2250 *tp++ = '+';
2251 tp = format_dec (number, tp, 1);
2252
2253 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2254 info->target = (prefix_insn >> 12) & 15;
2255 info->target2 = (bfd_vma) number;
2256 break;
2257 }
2258
2259 case BIAP_OPCODE:
2260 /* Output "r+R.m". */
2261 tp = format_reg (disdata, prefix_insn & 15, tp,
2262 with_reg_prefix);
2263 *tp++ = '+';
2264 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2265 with_reg_prefix);
2266 *tp++ = '.';
2267 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2268
2269 info->flags
2270 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2271 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2272
2273 | ((prefix_insn & 0x8000)
2274 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
2275 : ((prefix_insn & 0x8000)
2276 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
2277
2278 /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
2279 if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
2280 /* Then start interpreting data as offsets. */
2281 case_offset_counter = no_of_case_offsets;
2282 break;
2283
2284 case BDAP_INDIR_OPCODE:
2285 /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
2286 "r-s". */
2287 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2288 with_reg_prefix);
2289
2290 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2291 {
2292 int32_t number;
2293 unsigned int nbytes;
2294
2295 /* It's a value. Get its size. */
2296 int mode_size = 1 << ((prefix_insn >> 4) & 3);
2297
2298 if (mode_size == 1)
2299 nbytes = 2;
2300 else
2301 nbytes = mode_size;
2302
2303 switch (nbytes)
2304 {
2305 case 1:
2306 number = prefix_buffer[2];
2307 if (number > 127)
2308 number -= 256;
2309 break;
2310
2311 case 2:
2312 number = prefix_buffer[2] + prefix_buffer[3] * 256;
2313 if (number > 32767)
2314 number -= 65536;
2315 break;
2316
2317 case 4:
2318 number
2319 = prefix_buffer[2] + prefix_buffer[3] * 256
2320 + prefix_buffer[4] * 65536
2321 + prefix_buffer[5] * 0x1000000;
2322 break;
2323
2324 default:
2325 strcpy (tp, "bug");
2326 tp += 3;
2327 number = 42;
2328 }
2329
2330 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2331 info->target2 = (bfd_vma) number;
2332
2333 /* If the size is dword, then assume it's an
2334 address. */
2335 if (nbytes == 4)
2336 {
2337 /* Finish off and output previous formatted
2338 bytes. */
2339 *tp++ = '+';
2340 *tp = 0;
2341 tp = temp;
2342 (*info->fprintf_func) (info->stream, "%s", temp);
2343
2344 (*info->print_address_func) ((bfd_vma) number, info);
2345 }
2346 else
2347 {
2348 if (number >= 0)
2349 *tp++ = '+';
2350 tp = format_dec (number, tp, 1);
2351 }
2352 }
2353 else
2354 {
2355 /* Output "r+[R].m" or "r+[R+].m". */
2356 *tp++ = '+';
2357 *tp++ = '[';
2358 tp = format_reg (disdata, prefix_insn & 15, tp,
2359 with_reg_prefix);
2360 if (prefix_insn & 0x400)
2361 *tp++ = '+';
2362 *tp++ = ']';
2363 *tp++ = '.';
2364 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2365
2366 info->flags
2367 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2368 | CRIS_DIS_FLAG_MEM_TARGET2_MEM
2369 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2370
2371 | (((prefix_insn >> 4) == 2)
2372 ? 0
2373 : (((prefix_insn >> 4) & 3) == 1
2374 ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
2375 : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
2376 }
2377 break;
2378
2379 default:
2380 (*info->fprintf_func) (info->stream, "?prefix-bug");
2381 }
2382
2383 /* To mark that the prefix is used, reset it. */
2384 prefix_opcodep = NULL;
2385 }
2386 else
2387 {
2388 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2389
2390 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2391 info->target = insn & 15;
2392
2393 if (insn & 0x400)
2394 *tp++ = '+';
2395 }
2396 *tp++ = ']';
2397 }
2398 break;
2399
2400 case 'x':
2401 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2402 *tp++ = '.';
2403 *tp++ = mode_char[(insn >> 4) & 3];
2404 break;
2405
2406 case 'I':
2407 tp = format_dec (insn & 63, tp, 0);
2408 break;
2409
2410 case 'b':
2411 {
2412 int where = buffer[2] + buffer[3] * 256;
2413
2414 if (where > 32767)
2415 where -= 65536;
2416
2417 where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
2418
2419 if (insn == BA_PC_INCR_OPCODE)
2420 info->insn_type = dis_branch;
2421 else
2422 info->insn_type = dis_condbranch;
2423
2424 info->target = (bfd_vma) where;
2425
2426 *tp = 0;
2427 tp = temp;
2428 (*info->fprintf_func) (info->stream, "%s%s ",
2429 temp, cris_cc_strings[insn >> 12]);
2430
2431 (*info->print_address_func) ((bfd_vma) where, info);
2432 }
2433 break;
2434
2435 case 'c':
2436 tp = format_dec (insn & 31, tp, 0);
2437 break;
2438
2439 case 'C':
2440 tp = format_dec (insn & 15, tp, 0);
2441 break;
2442
2443 case 'o':
2444 {
2445 long offset = insn & 0xfe;
2446 bfd_vma target;
2447
2448 if (insn & 1)
2449 offset |= ~0xff;
2450
2451 if (opcodep->match == BA_QUICK_OPCODE)
2452 info->insn_type = dis_branch;
2453 else
2454 info->insn_type = dis_condbranch;
2455
2456 target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
2457 info->target = target;
2458 *tp = 0;
2459 tp = temp;
2460 (*info->fprintf_func) (info->stream, "%s", temp);
2461 (*info->print_address_func) (target, info);
2462 }
2463 break;
2464
2465 case 'Q':
2466 case 'O':
2467 {
2468 long number = buffer[0];
2469
2470 if (number > 127)
2471 number = number - 256;
2472
2473 tp = format_dec (number, tp, 1);
2474 *tp++ = ',';
2475 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2476 }
2477 break;
2478
2479 case 'f':
2480 tp = print_flags (disdata, insn, tp);
2481 break;
2482
2483 case 'i':
2484 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
2485 break;
2486
2487 case 'P':
2488 {
2489 const struct cris_spec_reg *sregp
2490 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2491
2492 if (sregp == NULL || sregp->name == NULL)
2493 /* Should have been caught as a non-match earlier. */
2494 *tp++ = '?';
2495 else
2496 {
2497 if (with_reg_prefix)
2498 *tp++ = REGISTER_PREFIX_CHAR;
2499 strcpy (tp, sregp->name);
2500 tp += strlen (tp);
2501 }
2502 }
2503 break;
2504
2505 default:
2506 strcpy (tp, "???");
2507 tp += 3;
2508 }
2509 }
2510
2511 *tp = 0;
2512
2513 if (prefix_opcodep)
2514 (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
2515 prefix_opcodep->name, prefix_opcodep->args);
2516
2517 (*info->fprintf_func) (info->stream, "%s", temp);
2518
2519 /* Get info for matching case-tables, if we don't have any active.
2520 We assume that the last constant seen is used; either in the insn
2521 itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
2522 if (TRACE_CASE && case_offset_counter == 0)
2523 {
2524 if (CONST_STRNEQ (opcodep->name, "sub"))
2525 case_offset = last_immediate;
2526
2527 /* It could also be an "add", if there are negative case-values. */
2528 else if (CONST_STRNEQ (opcodep->name, "add"))
2529 /* The first case is the negated operand to the add. */
2530 case_offset = -last_immediate;
2531
2532 /* A bound insn will tell us the number of cases. */
2533 else if (CONST_STRNEQ (opcodep->name, "bound"))
2534 no_of_case_offsets = last_immediate + 1;
2535
2536 /* A jump or jsr or branch breaks the chain of insns for a
2537 case-table, so assume default first-case again. */
2538 else if (info->insn_type == dis_jsr
2539 || info->insn_type == dis_branch
2540 || info->insn_type == dis_condbranch)
2541 case_offset = 0;
2542 }
2543 }
2544
2545
2546 /* Print the CRIS instruction at address memaddr on stream. Returns
2547 length of the instruction, in bytes. Prefix register names with `$' if
2548 WITH_REG_PREFIX. */
2549
2550 static int
2551 print_insn_cris_generic (bfd_vma memaddr,
2552 disassemble_info *info,
2553 bfd_boolean with_reg_prefix)
2554 {
2555 int nbytes;
2556 unsigned int insn;
2557 const struct cris_opcode *matchedp;
2558 int advance = 0;
2559 struct cris_disasm_data *disdata
2560 = (struct cris_disasm_data *) info->private_data;
2561
2562 /* No instruction will be disassembled as longer than this number of
2563 bytes; stacked prefixes will not be expanded. */
2564 unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
2565 unsigned char *bufp;
2566 int status = 0;
2567 bfd_vma addr;
2568
2569 /* There will be an "out of range" error after the last instruction.
2570 Reading pairs of bytes in decreasing number, we hope that we will get
2571 at least the amount that we will consume.
2572
2573 If we can't get any data, or we do not get enough data, we print
2574 the error message. */
2575
2576 nbytes = info->buffer_length ? info->buffer_length
2577 : MAX_BYTES_PER_CRIS_INSN;
2578 nbytes = MIN(nbytes, MAX_BYTES_PER_CRIS_INSN);
2579 status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);
2580
2581 /* If we did not get all we asked for, then clear the rest.
2582 Hopefully this makes a reproducible result in case of errors. */
2583 if (nbytes != MAX_BYTES_PER_CRIS_INSN)
2584 memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
2585
2586 addr = memaddr;
2587 bufp = buffer;
2588
2589 /* Set some defaults for the insn info. */
2590 info->insn_info_valid = 1;
2591 info->branch_delay_insns = 0;
2592 info->data_size = 0;
2593 info->insn_type = dis_nonbranch;
2594 info->flags = 0;
2595 info->target = 0;
2596 info->target2 = 0;
2597
2598 /* If we got any data, disassemble it. */
2599 if (nbytes != 0)
2600 {
2601 matchedp = NULL;
2602
2603 insn = bufp[0] + bufp[1] * 256;
2604
2605 /* If we're in a case-table, don't disassemble the offsets. */
2606 if (TRACE_CASE && case_offset_counter != 0)
2607 {
2608 info->insn_type = dis_noninsn;
2609 advance += 2;
2610
2611 /* If to print data as offsets, then shortcut here. */
2612 (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
2613 case_offset + no_of_case_offsets
2614 - case_offset_counter,
2615 case_offset_counter == 1 ? "/default" :
2616 "");
2617
2618 (*info->print_address_func) ((bfd_vma)
2619 ((short) (insn)
2620 + (long) (addr
2621 - (no_of_case_offsets
2622 - case_offset_counter)
2623 * 2)), info);
2624 case_offset_counter--;
2625
2626 /* The default case start (without a "sub" or "add") must be
2627 zero. */
2628 if (case_offset_counter == 0)
2629 case_offset = 0;
2630 }
2631 else if (insn == 0)
2632 {
2633 /* We're often called to disassemble zeroes. While this is a
2634 valid "bcc .+2" insn, it is also useless enough and enough
2635 of a nuiscance that we will just output "bcc .+2" for it
2636 and signal it as a noninsn. */
2637 (*info->fprintf_func) (info->stream,
2638 disdata->distype == cris_dis_v32
2639 ? "bcc ." : "bcc .+2");
2640 info->insn_type = dis_noninsn;
2641 advance += 2;
2642 }
2643 else
2644 {
2645 const struct cris_opcode *prefix_opcodep = NULL;
2646 unsigned char *prefix_buffer = bufp;
2647 unsigned int prefix_insn = insn;
2648 int prefix_size = 0;
2649
2650 matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
2651
2652 /* Check if we're supposed to write out prefixes as address
2653 modes and if this was a prefix. */
2654 if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
2655 {
2656 /* If it's a prefix, put it into the prefix vars and get the
2657 main insn. */
2658 prefix_size = bytes_to_skip (prefix_insn, matchedp,
2659 disdata->distype, NULL);
2660 prefix_opcodep = matchedp;
2661
2662 insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
2663 matchedp = get_opcode_entry (insn, prefix_insn, disdata);
2664
2665 if (matchedp != NULL)
2666 {
2667 addr += prefix_size;
2668 bufp += prefix_size;
2669 advance += prefix_size;
2670 }
2671 else
2672 {
2673 /* The "main" insn wasn't valid, at least not when
2674 prefixed. Put back things enough to output the
2675 prefix insn only, as a normal insn. */
2676 matchedp = prefix_opcodep;
2677 insn = prefix_insn;
2678 prefix_opcodep = NULL;
2679 }
2680 }
2681
2682 if (matchedp == NULL)
2683 {
2684 (*info->fprintf_func) (info->stream, "??0x%x", insn);
2685 advance += 2;
2686
2687 info->insn_type = dis_noninsn;
2688 }
2689 else
2690 {
2691 advance
2692 += bytes_to_skip (insn, matchedp, disdata->distype,
2693 prefix_opcodep);
2694
2695 /* The info_type and assorted fields will be set according
2696 to the operands. */
2697 print_with_operands (matchedp, insn, bufp, addr, info,
2698 prefix_opcodep, prefix_insn,
2699 prefix_buffer, with_reg_prefix);
2700 }
2701 }
2702 }
2703 else
2704 info->insn_type = dis_noninsn;
2705
2706 /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
2707 status when reading that much, and the insn decoding indicated a
2708 length exceeding what we read, there is an error. */
2709 if (status != 0 && (nbytes == 0 || advance > nbytes))
2710 {
2711 (*info->memory_error_func) (status, memaddr, info);
2712 return -1;
2713 }
2714
2715 /* Max supported insn size with one folded prefix insn. */
2716 info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
2717
2718 /* I would like to set this to a fixed value larger than the actual
2719 number of bytes to print in order to avoid spaces between bytes,
2720 but objdump.c (2.9.1) does not like that, so we print 16-bit
2721 chunks, which is the next choice. */
2722 info->bytes_per_chunk = 2;
2723
2724 /* Printing bytes in order of increasing addresses makes sense,
2725 especially on a little-endian target.
2726 This is completely the opposite of what you think; setting this to
2727 BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
2728 we want. */
2729 info->display_endian = BFD_ENDIAN_BIG;
2730
2731 return advance;
2732 }
2733
2734 /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
2735 static int
2736 print_insn_cris_with_register_prefix (bfd_vma vma,
2737 disassemble_info *info)
2738 {
2739 if (info->private_data == NULL
2740 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2741 return -1;
2742 return print_insn_cris_generic (vma, info, true);
2743 }
2744 /* Disassemble, prefixing register names with `$'. CRIS v32. */
2745
2746 static int
2747 print_insn_crisv32_with_register_prefix (bfd_vma vma,
2748 disassemble_info *info)
2749 {
2750 if (info->private_data == NULL
2751 && !cris_parse_disassembler_options (info, cris_dis_v32))
2752 return -1;
2753 return print_insn_cris_generic (vma, info, true);
2754 }
2755
2756 #if 0
2757 /* Disassemble, prefixing register names with `$'.
2758 Common v10 and v32 subset. */
2759
2760 static int
2761 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
2762 disassemble_info *info)
2763 {
2764 if (info->private_data == NULL
2765 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2766 return -1;
2767 return print_insn_cris_generic (vma, info, true);
2768 }
2769
2770 /* Disassemble, no prefixes on register names. CRIS v0..v10. */
2771
2772 static int
2773 print_insn_cris_without_register_prefix (bfd_vma vma,
2774 disassemble_info *info)
2775 {
2776 if (info->private_data == NULL
2777 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2778 return -1;
2779 return print_insn_cris_generic (vma, info, false);
2780 }
2781
2782 /* Disassemble, no prefixes on register names. CRIS v32. */
2783
2784 static int
2785 print_insn_crisv32_without_register_prefix (bfd_vma vma,
2786 disassemble_info *info)
2787 {
2788 if (info->private_data == NULL
2789 && !cris_parse_disassembler_options (info, cris_dis_v32))
2790 return -1;
2791 return print_insn_cris_generic (vma, info, false);
2792 }
2793
2794 /* Disassemble, no prefixes on register names.
2795 Common v10 and v32 subset. */
2796
2797 static int
2798 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
2799 disassemble_info *info)
2800 {
2801 if (info->private_data == NULL
2802 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2803 return -1;
2804 return print_insn_cris_generic (vma, info, false);
2805 }
2806 #endif
2807
2808 int
2809 print_insn_crisv10 (bfd_vma vma,
2810 disassemble_info *info)
2811 {
2812 return print_insn_cris_with_register_prefix(vma, info);
2813 }
2814
2815 int
2816 print_insn_crisv32 (bfd_vma vma,
2817 disassemble_info *info)
2818 {
2819 return print_insn_crisv32_with_register_prefix(vma, info);
2820 }
2821
2822 /* Return a disassembler-function that prints registers with a `$' prefix,
2823 or one that prints registers without a prefix.
2824 FIXME: We should improve the solution to avoid the multitude of
2825 functions seen above. */
2826 #if 0
2827 disassembler_ftype
2828 cris_get_disassembler (bfd *abfd)
2829 {
2830 /* If there's no bfd in sight, we return what is valid as input in all
2831 contexts if fed back to the assembler: disassembly *with* register
2832 prefix. Unfortunately this will be totally wrong for v32. */
2833 if (abfd == NULL)
2834 return print_insn_cris_with_register_prefix;
2835
2836 if (bfd_get_symbol_leading_char (abfd) == 0)
2837 {
2838 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2839 return print_insn_crisv32_with_register_prefix;
2840 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2841 return print_insn_crisv10_v32_with_register_prefix;
2842
2843 /* We default to v10. This may be specifically specified in the
2844 bfd mach, but is also the default setting. */
2845 return print_insn_cris_with_register_prefix;
2846 }
2847
2848 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2849 return print_insn_crisv32_without_register_prefix;
2850 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2851 return print_insn_crisv10_v32_without_register_prefix;
2852 return print_insn_cris_without_register_prefix;
2853 }
2854 #endif
2855 /* Local variables:
2856 eval: (c-set-style "gnu")
2857 indent-tabs-mode: t
2858 End: */
AR7 emulation for QEMU