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target/arm: Move CPU state dumping routines to cpu.c
[qemu/ar7.git] / hw / scsi / esp-pci.c
blob342f500f823d13946f2fa6b2891f18030e28e4e7
1 /*
2 * QEMU ESP/NCR53C9x emulation
3 *
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/pci/pci.h"
28 #include "hw/nvram/eeprom93xx.h"
29 #include "hw/scsi/esp.h"
30 #include "trace.h"
31 #include "qapi/error.h"
32 #include "qemu/log.h"
33 #include "qemu/module.h"
34
35 #define TYPE_AM53C974_DEVICE "am53c974"
36
37 #define PCI_ESP(obj) \
38 OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
39
40 #define DMA_CMD 0x0
41 #define DMA_STC 0x1
42 #define DMA_SPA 0x2
43 #define DMA_WBC 0x3
44 #define DMA_WAC 0x4
45 #define DMA_STAT 0x5
46 #define DMA_SMDLA 0x6
47 #define DMA_WMAC 0x7
48
49 #define DMA_CMD_MASK 0x03
50 #define DMA_CMD_DIAG 0x04
51 #define DMA_CMD_MDL 0x10
52 #define DMA_CMD_INTE_P 0x20
53 #define DMA_CMD_INTE_D 0x40
54 #define DMA_CMD_DIR 0x80
55
56 #define DMA_STAT_PWDN 0x01
57 #define DMA_STAT_ERROR 0x02
58 #define DMA_STAT_ABORT 0x04
59 #define DMA_STAT_DONE 0x08
60 #define DMA_STAT_SCSIINT 0x10
61 #define DMA_STAT_BCMBLT 0x20
62
63 #define SBAC_STATUS (1 << 24)
64
65 typedef struct PCIESPState {
66 /*< private >*/
67 PCIDevice parent_obj;
68 /*< public >*/
69
70 MemoryRegion io;
71 uint32_t dma_regs[8];
72 uint32_t sbac;
73 ESPState esp;
74 } PCIESPState;
75
76 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
77 {
78 trace_esp_pci_dma_idle(val);
79 esp_dma_enable(&pci->esp, 0, 0);
80 }
81
82 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
83 {
84 trace_esp_pci_dma_blast(val);
85 qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
86 }
87
88 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
89 {
90 trace_esp_pci_dma_abort(val);
91 if (pci->esp.current_req) {
92 scsi_req_cancel(pci->esp.current_req);
93 }
94 }
95
96 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
97 {
98 trace_esp_pci_dma_start(val);
99
100 pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
101 pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
102 pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
103
104 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
105 | DMA_STAT_DONE | DMA_STAT_ABORT
106 | DMA_STAT_ERROR | DMA_STAT_PWDN);
107
108 esp_dma_enable(&pci->esp, 0, 1);
109 }
110
111 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
112 {
113 trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
114 switch (saddr) {
115 case DMA_CMD:
116 pci->dma_regs[saddr] = val;
117 switch (val & DMA_CMD_MASK) {
118 case 0x0: /* IDLE */
119 esp_pci_handle_idle(pci, val);
120 break;
121 case 0x1: /* BLAST */
122 esp_pci_handle_blast(pci, val);
123 break;
124 case 0x2: /* ABORT */
125 esp_pci_handle_abort(pci, val);
126 break;
127 case 0x3: /* START */
128 esp_pci_handle_start(pci, val);
129 break;
130 default: /* can't happen */
131 abort();
132 }
133 break;
134 case DMA_STC:
135 case DMA_SPA:
136 case DMA_SMDLA:
137 pci->dma_regs[saddr] = val;
138 break;
139 case DMA_STAT:
140 if (pci->sbac & SBAC_STATUS) {
141 /* clear some bits on write */
142 uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
143 pci->dma_regs[DMA_STAT] &= ~(val & mask);
144 }
145 break;
146 default:
147 trace_esp_pci_error_invalid_write_dma(val, saddr);
148 return;
149 }
150 }
151
152 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
153 {
154 uint32_t val;
155
156 val = pci->dma_regs[saddr];
157 if (saddr == DMA_STAT) {
158 if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
159 val |= DMA_STAT_SCSIINT;
160 }
161 if (!(pci->sbac & SBAC_STATUS)) {
162 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
163 DMA_STAT_DONE);
164 }
165 }
166
167 trace_esp_pci_dma_read(saddr, val);
168 return val;
169 }
170
171 static void esp_pci_io_write(void *opaque, hwaddr addr,
172 uint64_t val, unsigned int size)
173 {
174 PCIESPState *pci = opaque;
175
176 if (size < 4 || addr & 3) {
177 /* need to upgrade request: we only support 4-bytes accesses */
178 uint32_t current = 0, mask;
179 int shift;
180
181 if (addr < 0x40) {
182 current = pci->esp.wregs[addr >> 2];
183 } else if (addr < 0x60) {
184 current = pci->dma_regs[(addr - 0x40) >> 2];
185 } else if (addr < 0x74) {
186 current = pci->sbac;
187 }
188
189 shift = (4 - size) * 8;
190 mask = (~(uint32_t)0 << shift) >> shift;
191
192 shift = ((4 - (addr & 3)) & 3) * 8;
193 val <<= shift;
194 val |= current & ~(mask << shift);
195 addr &= ~3;
196 size = 4;
197 }
198
199 if (addr < 0x40) {
200 /* SCSI core reg */
201 esp_reg_write(&pci->esp, addr >> 2, val);
202 } else if (addr < 0x60) {
203 /* PCI DMA CCB */
204 esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
205 } else if (addr == 0x70) {
206 /* DMA SCSI Bus and control */
207 trace_esp_pci_sbac_write(pci->sbac, val);
208 pci->sbac = val;
209 } else {
210 trace_esp_pci_error_invalid_write((int)addr);
211 }
212 }
213
214 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
215 unsigned int size)
216 {
217 PCIESPState *pci = opaque;
218 uint32_t ret;
219
220 if (addr < 0x40) {
221 /* SCSI core reg */
222 ret = esp_reg_read(&pci->esp, addr >> 2);
223 } else if (addr < 0x60) {
224 /* PCI DMA CCB */
225 ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
226 } else if (addr == 0x70) {
227 /* DMA SCSI Bus and control */
228 trace_esp_pci_sbac_read(pci->sbac);
229 ret = pci->sbac;
230 } else {
231 /* Invalid region */
232 trace_esp_pci_error_invalid_read((int)addr);
233 ret = 0;
234 }
235
236 /* give only requested data */
237 ret >>= (addr & 3) * 8;
238 ret &= ~(~(uint64_t)0 << (8 * size));
239
240 return ret;
241 }
242
243 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
244 DMADirection dir)
245 {
246 dma_addr_t addr;
247 DMADirection expected_dir;
248
249 if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
250 expected_dir = DMA_DIRECTION_FROM_DEVICE;
251 } else {
252 expected_dir = DMA_DIRECTION_TO_DEVICE;
253 }
254
255 if (dir != expected_dir) {
256 trace_esp_pci_error_invalid_dma_direction();
257 return;
258 }
259
260 if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
261 qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
262 }
263
264 addr = pci->dma_regs[DMA_SPA];
265 if (pci->dma_regs[DMA_WBC] < len) {
266 len = pci->dma_regs[DMA_WBC];
267 }
268
269 pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
270
271 /* update status registers */
272 pci->dma_regs[DMA_WBC] -= len;
273 pci->dma_regs[DMA_WAC] += len;
274 if (pci->dma_regs[DMA_WBC] == 0) {
275 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
276 }
277 }
278
279 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
280 {
281 PCIESPState *pci = opaque;
282 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
283 }
284
285 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
286 {
287 PCIESPState *pci = opaque;
288 esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
289 }
290
291 static const MemoryRegionOps esp_pci_io_ops = {
292 .read = esp_pci_io_read,
293 .write = esp_pci_io_write,
294 .endianness = DEVICE_LITTLE_ENDIAN,
295 .impl = {
296 .min_access_size = 1,
297 .max_access_size = 4,
298 },
299 };
300
301 static void esp_pci_hard_reset(DeviceState *dev)
302 {
303 PCIESPState *pci = PCI_ESP(dev);
304 esp_hard_reset(&pci->esp);
305 pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
306 | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
307 pci->dma_regs[DMA_WBC] &= ~0xffff;
308 pci->dma_regs[DMA_WAC] = 0xffffffff;
309 pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
310 | DMA_STAT_DONE | DMA_STAT_ABORT
311 | DMA_STAT_ERROR);
312 pci->dma_regs[DMA_WMAC] = 0xfffffffd;
313 }
314
315 static const VMStateDescription vmstate_esp_pci_scsi = {
316 .name = "pciespscsi",
317 .version_id = 1,
318 .minimum_version_id = 1,
319 .fields = (VMStateField[]) {
320 VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
321 VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
322 VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
323 VMSTATE_END_OF_LIST()
324 }
325 };
326
327 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
328 size_t resid)
329 {
330 ESPState *s = req->hba_private;
331 PCIESPState *pci = container_of(s, PCIESPState, esp);
332
333 esp_command_complete(req, status, resid);
334 pci->dma_regs[DMA_WBC] = 0;
335 pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
336 }
337
338 static const struct SCSIBusInfo esp_pci_scsi_info = {
339 .tcq = false,
340 .max_target = ESP_MAX_DEVS,
341 .max_lun = 7,
342
343 .transfer_data = esp_transfer_data,
344 .complete = esp_pci_command_complete,
345 .cancel = esp_request_cancelled,
346 };
347
348 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
349 {
350 PCIESPState *pci = PCI_ESP(dev);
351 DeviceState *d = DEVICE(dev);
352 ESPState *s = &pci->esp;
353 uint8_t *pci_conf;
354
355 pci_conf = dev->config;
356
357 /* Interrupt pin A */
358 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
359
360 s->dma_memory_read = esp_pci_dma_memory_read;
361 s->dma_memory_write = esp_pci_dma_memory_write;
362 s->dma_opaque = pci;
363 s->chip_id = TCHI_AM53C974;
364 memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
365 "esp-io", 0x80);
366
367 pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
368 s->irq = pci_allocate_irq(dev);
369
370 scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
371 }
372
373 static void esp_pci_scsi_uninit(PCIDevice *d)
374 {
375 PCIESPState *pci = PCI_ESP(d);
376
377 qemu_free_irq(pci->esp.irq);
378 }
379
380 static void esp_pci_class_init(ObjectClass *klass, void *data)
381 {
382 DeviceClass *dc = DEVICE_CLASS(klass);
383 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
384
385 k->realize = esp_pci_scsi_realize;
386 k->exit = esp_pci_scsi_uninit;
387 k->vendor_id = PCI_VENDOR_ID_AMD;
388 k->device_id = PCI_DEVICE_ID_AMD_SCSI;
389 k->revision = 0x10;
390 k->class_id = PCI_CLASS_STORAGE_SCSI;
391 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
392 dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
393 dc->reset = esp_pci_hard_reset;
394 dc->vmsd = &vmstate_esp_pci_scsi;
395 }
396
397 static const TypeInfo esp_pci_info = {
398 .name = TYPE_AM53C974_DEVICE,
399 .parent = TYPE_PCI_DEVICE,
400 .instance_size = sizeof(PCIESPState),
401 .class_init = esp_pci_class_init,
402 .interfaces = (InterfaceInfo[]) {
403 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
404 { },
405 },
406 };
407
408 typedef struct {
409 PCIESPState pci;
410 eeprom_t *eeprom;
411 } DC390State;
412
413 #define TYPE_DC390_DEVICE "dc390"
414 #define DC390(obj) \
415 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
416
417 #define EE_ADAPT_SCSI_ID 64
418 #define EE_MODE2 65
419 #define EE_DELAY 66
420 #define EE_TAG_CMD_NUM 67
421 #define EE_ADAPT_OPTIONS 68
422 #define EE_BOOT_SCSI_ID 69
423 #define EE_BOOT_SCSI_LUN 70
424 #define EE_CHKSUM1 126
425 #define EE_CHKSUM2 127
426
427 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
428 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
429 #define EE_ADAPT_OPTION_INT13 0x04
430 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
431
432
433 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
434 {
435 DC390State *pci = DC390(dev);
436 uint32_t val;
437
438 val = pci_default_read_config(dev, addr, l);
439
440 if (addr == 0x00 && l == 1) {
441 /* First byte of address space is AND-ed with EEPROM DO line */
442 if (!eeprom93xx_read(pci->eeprom)) {
443 val &= ~0xff;
444 }
445 }
446
447 return val;
448 }
449
450 static void dc390_write_config(PCIDevice *dev,
451 uint32_t addr, uint32_t val, int l)
452 {
453 DC390State *pci = DC390(dev);
454 if (addr == 0x80) {
455 /* EEPROM write */
456 int eesk = val & 0x80 ? 1 : 0;
457 int eedi = val & 0x40 ? 1 : 0;
458 eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
459 } else if (addr == 0xc0) {
460 /* EEPROM CS low */
461 eeprom93xx_write(pci->eeprom, 0, 0, 0);
462 } else {
463 pci_default_write_config(dev, addr, val, l);
464 }
465 }
466
467 static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
468 {
469 DC390State *pci = DC390(dev);
470 Error *err = NULL;
471 uint8_t *contents;
472 uint16_t chksum = 0;
473 int i;
474
475 /* init base class */
476 esp_pci_scsi_realize(dev, &err);
477 if (err) {
478 error_propagate(errp, err);
479 return;
480 }
481
482 /* EEPROM */
483 pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
484
485 /* set default eeprom values */
486 contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
487
488 for (i = 0; i < 16; i++) {
489 contents[i * 2] = 0x57;
490 contents[i * 2 + 1] = 0x00;
491 }
492 contents[EE_ADAPT_SCSI_ID] = 7;
493 contents[EE_MODE2] = 0x0f;
494 contents[EE_TAG_CMD_NUM] = 0x04;
495 contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
496 | EE_ADAPT_OPTION_BOOT_FROM_CDROM
497 | EE_ADAPT_OPTION_INT13;
498
499 /* update eeprom checksum */
500 for (i = 0; i < EE_CHKSUM1; i += 2) {
501 chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
502 }
503 chksum = 0x1234 - chksum;
504 contents[EE_CHKSUM1] = chksum & 0xff;
505 contents[EE_CHKSUM2] = chksum >> 8;
506 }
507
508 static void dc390_class_init(ObjectClass *klass, void *data)
509 {
510 DeviceClass *dc = DEVICE_CLASS(klass);
511 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
512
513 k->realize = dc390_scsi_realize;
514 k->config_read = dc390_read_config;
515 k->config_write = dc390_write_config;
516 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
517 dc->desc = "Tekram DC-390 SCSI adapter";
518 }
519
520 static const TypeInfo dc390_info = {
521 .name = "dc390",
522 .parent = TYPE_AM53C974_DEVICE,
523 .instance_size = sizeof(DC390State),
524 .class_init = dc390_class_init,
525 };
526
527 static void esp_pci_register_types(void)
528 {
529 type_register_static(&esp_pci_info);
530 type_register_static(&dc390_info);
531 }
532
533 type_init(esp_pci_register_types)
AR7 emulation for QEMU