accel/tcg/user-exec.c

   1 /*
   2  *  User emulator execution
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "disas/disas.h"
  22 #include "exec/exec-all.h"
  23 #include "tcg.h"
  24 #include "qemu/bitops.h"
  25 #include "exec/cpu_ldst.h"
  26 #include "translate-all.h"
  27 #include "exec/helper-proto.h"
  28 #include "qemu/atomic128.h"
  29
  30 #undef EAX
  31 #undef ECX
  32 #undef EDX
  33 #undef EBX
  34 #undef ESP
  35 #undef EBP
  36 #undef ESI
  37 #undef EDI
  38 #undef EIP
  39 #ifdef __linux__
  40 #include <sys/ucontext.h>
  41 #endif
  42
  43 __thread uintptr_t helper_retaddr;
  44
  45 //#define DEBUG_SIGNAL
  46
  47 /* exit the current TB from a signal handler. The host registers are
  48    restored in a state compatible with the CPU emulator
  49  */
  50 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
  51 {
  52     /* XXX: use siglongjmp ? */
  53     sigprocmask(SIG_SETMASK, old_set, NULL);
  54     cpu_loop_exit_noexc(cpu);
  55 }
  56
  57 /* 'pc' is the host PC at which the exception was raised. 'address' is
  58    the effective address of the memory exception. 'is_write' is 1 if a
  59    write caused the exception and otherwise 0'. 'old_set' is the
  60    signal set which should be restored */
  61 static inline int handle_cpu_signal(uintptr_t pc, siginfo_t *info,
  62                                     int is_write, sigset_t *old_set)
  63 {
  64     CPUState *cpu = current_cpu;
  65     CPUClass *cc;
  66     unsigned long address = (unsigned long)info->si_addr;
  67     MMUAccessType access_type;
  68
  69     /* We must handle PC addresses from two different sources:
  70      * a call return address and a signal frame address.
  71      *
  72      * Within cpu_restore_state_from_tb we assume the former and adjust
  73      * the address by -GETPC_ADJ so that the address is within the call
  74      * insn so that addr does not accidentally match the beginning of the
  75      * next guest insn.
  76      *
  77      * However, when the PC comes from the signal frame, it points to
  78      * the actual faulting host insn and not a call insn.  Subtracting
  79      * GETPC_ADJ in that case may accidentally match the previous guest insn.
  80      *
  81      * So for the later case, adjust forward to compensate for what
  82      * will be done later by cpu_restore_state_from_tb.
  83      */
  84     if (helper_retaddr) {
  85         pc = helper_retaddr;
  86     } else {
  87         pc += GETPC_ADJ;
  88     }
  89
  90     /* For synchronous signals we expect to be coming from the vCPU
  91      * thread (so current_cpu should be valid) and either from running
  92      * code or during translation which can fault as we cross pages.
  93      *
  94      * If neither is true then something has gone wrong and we should
  95      * abort rather than try and restart the vCPU execution.
  96      */
  97     if (!cpu || !cpu->running) {
  98         printf("qemu:%s received signal outside vCPU context @ pc=0x%"
  99                PRIxPTR "\n",  __func__, pc);
 100         abort();
 101     }
 102
 103 #if defined(DEBUG_SIGNAL)
 104     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 105            pc, address, is_write, *(unsigned long *)old_set);
 106 #endif
 107     /* XXX: locking issue */
 108     /* Note that it is important that we don't call page_unprotect() unless
 109      * this is really a "write to nonwriteable page" fault, because
 110      * page_unprotect() assumes that if it is called for an access to
 111      * a page that's writeable this means we had two threads racing and
 112      * another thread got there first and already made the page writeable;
 113      * so we will retry the access. If we were to call page_unprotect()
 114      * for some other kind of fault that should really be passed to the
 115      * guest, we'd end up in an infinite loop of retrying the faulting
 116      * access.
 117      */
 118     if (is_write && info->si_signo == SIGSEGV && info->si_code == SEGV_ACCERR &&
 119         h2g_valid(address)) {
 120         switch (page_unprotect(h2g(address), pc)) {
 121         case 0:
 122             /* Fault not caused by a page marked unwritable to protect
 123              * cached translations, must be the guest binary's problem.
 124              */
 125             break;
 126         case 1:
 127             /* Fault caused by protection of cached translation; TBs
 128              * invalidated, so resume execution.  Retain helper_retaddr
 129              * for a possible second fault.
 130              */
 131             return 1;
 132         case 2:
 133             /* Fault caused by protection of cached translation, and the
 134              * currently executing TB was modified and must be exited
 135              * immediately.  Clear helper_retaddr for next execution.
 136              */
 137             helper_retaddr = 0;
 138             cpu_exit_tb_from_sighandler(cpu, old_set);
 139             /* NORETURN */
 140
 141         default:
 142             g_assert_not_reached();
 143         }
 144     }
 145
 146     /* Convert forcefully to guest address space, invalid addresses
 147        are still valid segv ones */
 148     address = h2g_nocheck(address);
 149
 150     /*
 151      * There is no way the target can handle this other than raising
 152      * an exception.  Undo signal and retaddr state prior to longjmp.
 153      */
 154     sigprocmask(SIG_SETMASK, old_set, NULL);
 155     helper_retaddr = 0;
 156
 157     cc = CPU_GET_CLASS(cpu);
 158     access_type = is_write ? MMU_DATA_STORE : MMU_DATA_LOAD;
 159     cc->tlb_fill(cpu, address, 0, access_type, MMU_USER_IDX, false, pc);
 160     g_assert_not_reached();
 161 }
 162
 163 #if defined(__i386__)
 164
 165 #if defined(__NetBSD__)
 166 #include <ucontext.h>
 167
 168 #define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
 169 #define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 170 #define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
 171 #define MASK_sig(context)    ((context)->uc_sigmask)
 172 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 173 #include <ucontext.h>
 174
 175 #define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
 176 #define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
 177 #define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
 178 #define MASK_sig(context)    ((context)->uc_sigmask)
 179 #elif defined(__OpenBSD__)
 180 #define EIP_sig(context)     ((context)->sc_eip)
 181 #define TRAP_sig(context)    ((context)->sc_trapno)
 182 #define ERROR_sig(context)   ((context)->sc_err)
 183 #define MASK_sig(context)    ((context)->sc_mask)
 184 #else
 185 #define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
 186 #define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
 187 #define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
 188 #define MASK_sig(context)    ((context)->uc_sigmask)
 189 #endif
 190
 191 int cpu_signal_handler(int host_signum, void *pinfo,
 192                        void *puc)
 193 {
 194     siginfo_t *info = pinfo;
 195 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 196     ucontext_t *uc = puc;
 197 #elif defined(__OpenBSD__)
 198     struct sigcontext *uc = puc;
 199 #else
 200     ucontext_t *uc = puc;
 201 #endif
 202     unsigned long pc;
 203     int trapno;
 204
 205 #ifndef REG_EIP
 206 /* for glibc 2.1 */
 207 #define REG_EIP    EIP
 208 #define REG_ERR    ERR
 209 #define REG_TRAPNO TRAPNO
 210 #endif
 211     pc = EIP_sig(uc);
 212     trapno = TRAP_sig(uc);
 213     return handle_cpu_signal(pc, info,
 214                              trapno == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
 215                              &MASK_sig(uc));
 216 }
 217
 218 #elif defined(__x86_64__)
 219
 220 #ifdef __NetBSD__
 221 #define PC_sig(context)       _UC_MACHINE_PC(context)
 222 #define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
 223 #define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
 224 #define MASK_sig(context)     ((context)->uc_sigmask)
 225 #elif defined(__OpenBSD__)
 226 #define PC_sig(context)       ((context)->sc_rip)
 227 #define TRAP_sig(context)     ((context)->sc_trapno)
 228 #define ERROR_sig(context)    ((context)->sc_err)
 229 #define MASK_sig(context)     ((context)->sc_mask)
 230 #elif defined(__FreeBSD__) || defined(__DragonFly__)
 231 #include <ucontext.h>
 232
 233 #define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
 234 #define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
 235 #define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
 236 #define MASK_sig(context)     ((context)->uc_sigmask)
 237 #else
 238 #define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
 239 #define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
 240 #define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
 241 #define MASK_sig(context)     ((context)->uc_sigmask)
 242 #endif
 243
 244 int cpu_signal_handler(int host_signum, void *pinfo,
 245                        void *puc)
 246 {
 247     siginfo_t *info = pinfo;
 248     unsigned long pc;
 249 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
 250     ucontext_t *uc = puc;
 251 #elif defined(__OpenBSD__)
 252     struct sigcontext *uc = puc;
 253 #else
 254     ucontext_t *uc = puc;
 255 #endif
 256
 257     pc = PC_sig(uc);
 258     return handle_cpu_signal(pc, info,
 259                              TRAP_sig(uc) == 0xe ? (ERROR_sig(uc) >> 1) & 1 : 0,
 260                              &MASK_sig(uc));
 261 }
 262
 263 #elif defined(_ARCH_PPC)
 264
 265 /***********************************************************************
 266  * signal context platform-specific definitions
 267  * From Wine
 268  */
 269 #ifdef linux
 270 /* All Registers access - only for local access */
 271 #define REG_sig(reg_name, context)              \
 272     ((context)->uc_mcontext.regs->reg_name)
 273 /* Gpr Registers access  */
 274 #define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
 275 /* Program counter */
 276 #define IAR_sig(context)                       REG_sig(nip, context)
 277 /* Machine State Register (Supervisor) */
 278 #define MSR_sig(context)                       REG_sig(msr, context)
 279 /* Count register */
 280 #define CTR_sig(context)                       REG_sig(ctr, context)
 281 /* User's integer exception register */
 282 #define XER_sig(context)                       REG_sig(xer, context)
 283 /* Link register */
 284 #define LR_sig(context)                        REG_sig(link, context)
 285 /* Condition register */
 286 #define CR_sig(context)                        REG_sig(ccr, context)
 287
 288 /* Float Registers access  */
 289 #define FLOAT_sig(reg_num, context)                                     \
 290     (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
 291 #define FPSCR_sig(context) \
 292     (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
 293 /* Exception Registers access */
 294 #define DAR_sig(context)                       REG_sig(dar, context)
 295 #define DSISR_sig(context)                     REG_sig(dsisr, context)
 296 #define TRAP_sig(context)                      REG_sig(trap, context)
 297 #endif /* linux */
 298
 299 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 300 #include <ucontext.h>
 301 #define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
 302 #define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
 303 #define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
 304 #define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
 305 #define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
 306 #define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
 307 /* Exception Registers access */
 308 #define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
 309 #define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
 310 #define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
 311 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
 312
 313 int cpu_signal_handler(int host_signum, void *pinfo,
 314                        void *puc)
 315 {
 316     siginfo_t *info = pinfo;
 317 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
 318     ucontext_t *uc = puc;
 319 #else
 320     ucontext_t *uc = puc;
 321 #endif
 322     unsigned long pc;
 323     int is_write;
 324
 325     pc = IAR_sig(uc);
 326     is_write = 0;
 327 #if 0
 328     /* ppc 4xx case */
 329     if (DSISR_sig(uc) & 0x00800000) {
 330         is_write = 1;
 331     }
 332 #else
 333     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
 334         is_write = 1;
 335     }
 336 #endif
 337     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 338 }
 339
 340 #elif defined(__alpha__)
 341
 342 int cpu_signal_handler(int host_signum, void *pinfo,
 343                            void *puc)
 344 {
 345     siginfo_t *info = pinfo;
 346     ucontext_t *uc = puc;
 347     uint32_t *pc = uc->uc_mcontext.sc_pc;
 348     uint32_t insn = *pc;
 349     int is_write = 0;
 350
 351     /* XXX: need kernel patch to get write flag faster */
 352     switch (insn >> 26) {
 353     case 0x0d: /* stw */
 354     case 0x0e: /* stb */
 355     case 0x0f: /* stq_u */
 356     case 0x24: /* stf */
 357     case 0x25: /* stg */
 358     case 0x26: /* sts */
 359     case 0x27: /* stt */
 360     case 0x2c: /* stl */
 361     case 0x2d: /* stq */
 362     case 0x2e: /* stl_c */
 363     case 0x2f: /* stq_c */
 364         is_write = 1;
 365     }
 366
 367     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 368 }
 369 #elif defined(__sparc__)
 370
 371 int cpu_signal_handler(int host_signum, void *pinfo,
 372                        void *puc)
 373 {
 374     siginfo_t *info = pinfo;
 375     int is_write;
 376     uint32_t insn;
 377 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
 378     uint32_t *regs = (uint32_t *)(info + 1);
 379     void *sigmask = (regs + 20);
 380     /* XXX: is there a standard glibc define ? */
 381     unsigned long pc = regs[1];
 382 #else
 383 #ifdef __linux__
 384     struct sigcontext *sc = puc;
 385     unsigned long pc = sc->sigc_regs.tpc;
 386     void *sigmask = (void *)sc->sigc_mask;
 387 #elif defined(__OpenBSD__)
 388     struct sigcontext *uc = puc;
 389     unsigned long pc = uc->sc_pc;
 390     void *sigmask = (void *)(long)uc->sc_mask;
 391 #elif defined(__NetBSD__)
 392     ucontext_t *uc = puc;
 393     unsigned long pc = _UC_MACHINE_PC(uc);
 394     void *sigmask = (void *)&uc->uc_sigmask;
 395 #endif
 396 #endif
 397
 398     /* XXX: need kernel patch to get write flag faster */
 399     is_write = 0;
 400     insn = *(uint32_t *)pc;
 401     if ((insn >> 30) == 3) {
 402         switch ((insn >> 19) & 0x3f) {
 403         case 0x05: /* stb */
 404         case 0x15: /* stba */
 405         case 0x06: /* sth */
 406         case 0x16: /* stha */
 407         case 0x04: /* st */
 408         case 0x14: /* sta */
 409         case 0x07: /* std */
 410         case 0x17: /* stda */
 411         case 0x0e: /* stx */
 412         case 0x1e: /* stxa */
 413         case 0x24: /* stf */
 414         case 0x34: /* stfa */
 415         case 0x27: /* stdf */
 416         case 0x37: /* stdfa */
 417         case 0x26: /* stqf */
 418         case 0x36: /* stqfa */
 419         case 0x25: /* stfsr */
 420         case 0x3c: /* casa */
 421         case 0x3e: /* casxa */
 422             is_write = 1;
 423             break;
 424         }
 425     }
 426     return handle_cpu_signal(pc, info, is_write, sigmask);
 427 }
 428
 429 #elif defined(__arm__)
 430
 431 #if defined(__NetBSD__)
 432 #include <ucontext.h>
 433 #endif
 434
 435 int cpu_signal_handler(int host_signum, void *pinfo,
 436                        void *puc)
 437 {
 438     siginfo_t *info = pinfo;
 439 #if defined(__NetBSD__)
 440     ucontext_t *uc = puc;
 441 #else
 442     ucontext_t *uc = puc;
 443 #endif
 444     unsigned long pc;
 445     int is_write;
 446
 447 #if defined(__NetBSD__)
 448     pc = uc->uc_mcontext.__gregs[_REG_R15];
 449 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
 450     pc = uc->uc_mcontext.gregs[R15];
 451 #else
 452     pc = uc->uc_mcontext.arm_pc;
 453 #endif
 454
 455     /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
 456      * later processor; on v5 we will always report this as a read).
 457      */
 458     is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
 459     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 460 }
 461
 462 #elif defined(__aarch64__)
 463
 464 #ifndef ESR_MAGIC
 465 /* Pre-3.16 kernel headers don't have these, so provide fallback definitions */
 466 #define ESR_MAGIC 0x45535201
 467 struct esr_context {
 468     struct _aarch64_ctx head;
 469     uint64_t esr;
 470 };
 471 #endif
 472
 473 static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc)
 474 {
 475     return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved;
 476 }
 477
 478 static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr)
 479 {
 480     return (struct _aarch64_ctx *)((char *)hdr + hdr->size);
 481 }
 482
 483 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
 484 {
 485     siginfo_t *info = pinfo;
 486     ucontext_t *uc = puc;
 487     uintptr_t pc = uc->uc_mcontext.pc;
 488     bool is_write;
 489     struct _aarch64_ctx *hdr;
 490     struct esr_context const *esrctx = NULL;
 491
 492     /* Find the esr_context, which has the WnR bit in it */
 493     for (hdr = first_ctx(uc); hdr->magic; hdr = next_ctx(hdr)) {
 494         if (hdr->magic == ESR_MAGIC) {
 495             esrctx = (struct esr_context const *)hdr;
 496             break;
 497         }
 498     }
 499
 500     if (esrctx) {
 501         /* For data aborts ESR.EC is 0b10010x: then bit 6 is the WnR bit */
 502         uint64_t esr = esrctx->esr;
 503         is_write = extract32(esr, 27, 5) == 0x12 && extract32(esr, 6, 1) == 1;
 504     } else {
 505         /*
 506          * Fall back to parsing instructions; will only be needed
 507          * for really ancient (pre-3.16) kernels.
 508          */
 509         uint32_t insn = *(uint32_t *)pc;
 510
 511         is_write = ((insn & 0xbfff0000) == 0x0c000000   /* C3.3.1 */
 512                     || (insn & 0xbfe00000) == 0x0c800000   /* C3.3.2 */
 513                     || (insn & 0xbfdf0000) == 0x0d000000   /* C3.3.3 */
 514                     || (insn & 0xbfc00000) == 0x0d800000   /* C3.3.4 */
 515                     || (insn & 0x3f400000) == 0x08000000   /* C3.3.6 */
 516                     || (insn & 0x3bc00000) == 0x39000000   /* C3.3.13 */
 517                     || (insn & 0x3fc00000) == 0x3d800000   /* ... 128bit */
 518                     /* Ignore bits 10, 11 & 21, controlling indexing.  */
 519                     || (insn & 0x3bc00000) == 0x38000000   /* C3.3.8-12 */
 520                     || (insn & 0x3fe00000) == 0x3c800000   /* ... 128bit */
 521                     /* Ignore bits 23 & 24, controlling indexing.  */
 522                     || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
 523     }
 524     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 525 }
 526
 527 #elif defined(__s390__)
 528
 529 int cpu_signal_handler(int host_signum, void *pinfo,
 530                        void *puc)
 531 {
 532     siginfo_t *info = pinfo;
 533     ucontext_t *uc = puc;
 534     unsigned long pc;
 535     uint16_t *pinsn;
 536     int is_write = 0;
 537
 538     pc = uc->uc_mcontext.psw.addr;
 539
 540     /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
 541        of the normal 2 arguments.  The 3rd argument contains the "int_code"
 542        from the hardware which does in fact contain the is_write value.
 543        The rt signal handler, as far as I can tell, does not give this value
 544        at all.  Not that we could get to it from here even if it were.  */
 545     /* ??? This is not even close to complete, since it ignores all
 546        of the read-modify-write instructions.  */
 547     pinsn = (uint16_t *)pc;
 548     switch (pinsn[0] >> 8) {
 549     case 0x50: /* ST */
 550     case 0x42: /* STC */
 551     case 0x40: /* STH */
 552         is_write = 1;
 553         break;
 554     case 0xc4: /* RIL format insns */
 555         switch (pinsn[0] & 0xf) {
 556         case 0xf: /* STRL */
 557         case 0xb: /* STGRL */
 558         case 0x7: /* STHRL */
 559             is_write = 1;
 560         }
 561         break;
 562     case 0xe3: /* RXY format insns */
 563         switch (pinsn[2] & 0xff) {
 564         case 0x50: /* STY */
 565         case 0x24: /* STG */
 566         case 0x72: /* STCY */
 567         case 0x70: /* STHY */
 568         case 0x8e: /* STPQ */
 569         case 0x3f: /* STRVH */
 570         case 0x3e: /* STRV */
 571         case 0x2f: /* STRVG */
 572             is_write = 1;
 573         }
 574         break;
 575     }
 576     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 577 }
 578
 579 #elif defined(__mips__)
 580
 581 int cpu_signal_handler(int host_signum, void *pinfo,
 582                        void *puc)
 583 {
 584     siginfo_t *info = pinfo;
 585     ucontext_t *uc = puc;
 586     greg_t pc = uc->uc_mcontext.pc;
 587     int is_write;
 588
 589     /* XXX: compute is_write */
 590     is_write = 0;
 591     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 592 }
 593
 594 #elif defined(__riscv)
 595
 596 int cpu_signal_handler(int host_signum, void *pinfo,
 597                        void *puc)
 598 {
 599     siginfo_t *info = pinfo;
 600     ucontext_t *uc = puc;
 601     greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
 602     uint32_t insn = *(uint32_t *)pc;
 603     int is_write = 0;
 604
 605     /* Detect store by reading the instruction at the program
 606        counter. Note: we currently only generate 32-bit
 607        instructions so we thus only detect 32-bit stores */
 608     switch (((insn >> 0) & 0b11)) {
 609     case 3:
 610         switch (((insn >> 2) & 0b11111)) {
 611         case 8:
 612             switch (((insn >> 12) & 0b111)) {
 613             case 0: /* sb */
 614             case 1: /* sh */
 615             case 2: /* sw */
 616             case 3: /* sd */
 617             case 4: /* sq */
 618                 is_write = 1;
 619                 break;
 620             default:
 621                 break;
 622             }
 623             break;
 624         case 9:
 625             switch (((insn >> 12) & 0b111)) {
 626             case 2: /* fsw */
 627             case 3: /* fsd */
 628             case 4: /* fsq */
 629                 is_write = 1;
 630                 break;
 631             default:
 632                 break;
 633             }
 634             break;
 635         default:
 636             break;
 637         }
 638     }
 639
 640     /* Check for compressed instructions */
 641     switch (((insn >> 13) & 0b111)) {
 642     case 7:
 643         switch (insn & 0b11) {
 644         case 0: /*c.sd */
 645         case 2: /* c.sdsp */
 646             is_write = 1;
 647             break;
 648         default:
 649             break;
 650         }
 651         break;
 652     case 6:
 653         switch (insn & 0b11) {
 654         case 0: /* c.sw */
 655         case 3: /* c.swsp */
 656             is_write = 1;
 657             break;
 658         default:
 659             break;
 660         }
 661         break;
 662     default:
 663         break;
 664     }
 665
 666     return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
 667 }
 668
 669 #else
 670
 671 #error host CPU specific signal handler needed
 672
 673 #endif
 674
 675 /* The softmmu versions of these helpers are in cputlb.c.  */
 676
 677 /* Do not allow unaligned operations to proceed.  Return the host address.  */
 678 static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
 679                                int size, uintptr_t retaddr)
 680 {
 681     /* Enforce qemu required alignment.  */
 682     if (unlikely(addr & (size - 1))) {
 683         cpu_loop_exit_atomic(env_cpu(env), retaddr);
 684     }
 685     helper_retaddr = retaddr;
 686     return g2h(addr);
 687 }
 688
 689 /* Macro to call the above, with local variables from the use context.  */
 690 #define ATOMIC_MMU_DECLS do {} while (0)
 691 #define ATOMIC_MMU_LOOKUP  atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
 692 #define ATOMIC_MMU_CLEANUP do { helper_retaddr = 0; } while (0)
 693
 694 #define ATOMIC_NAME(X)   HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
 695 #define EXTRA_ARGS
 696
 697 #define DATA_SIZE 1
 698 #include "atomic_template.h"
 699
 700 #define DATA_SIZE 2
 701 #include "atomic_template.h"
 702
 703 #define DATA_SIZE 4
 704 #include "atomic_template.h"
 705
 706 #ifdef CONFIG_ATOMIC64
 707 #define DATA_SIZE 8
 708 #include "atomic_template.h"
 709 #endif
 710
 711 /* The following is only callable from other helpers, and matches up
 712    with the softmmu version.  */
 713
 714 #if HAVE_ATOMIC128 || HAVE_CMPXCHG128
 715
 716 #undef EXTRA_ARGS
 717 #undef ATOMIC_NAME
 718 #undef ATOMIC_MMU_LOOKUP
 719
 720 #define EXTRA_ARGS     , TCGMemOpIdx oi, uintptr_t retaddr
 721 #define ATOMIC_NAME(X) \
 722     HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
 723 #define ATOMIC_MMU_LOOKUP  atomic_mmu_lookup(env, addr, DATA_SIZE, retaddr)
 724
 725 #define DATA_SIZE 16
 726 #include "atomic_template.h"
 727 #endif