target/openrisc/machine.c

   1 /*
   2  * OpenRISC Machine
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "migration/cpu.h"
  23
  24 static const VMStateDescription vmstate_tlb_entry = {
  25     .name = "tlb_entry",
  26     .version_id = 1,
  27     .minimum_version_id = 1,
  28     .minimum_version_id_old = 1,
  29     .fields = (VMStateField[]) {
  30         VMSTATE_UINTTL(mr, OpenRISCTLBEntry),
  31         VMSTATE_UINTTL(tr, OpenRISCTLBEntry),
  32         VMSTATE_END_OF_LIST()
  33     }
  34 };
  35
  36 static const VMStateDescription vmstate_cpu_tlb = {
  37     .name = "cpu_tlb",
  38     .version_id = 2,
  39     .minimum_version_id = 2,
  40     .fields = (VMStateField[]) {
  41         VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
  42                              vmstate_tlb_entry, OpenRISCTLBEntry),
  43         VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
  44                              vmstate_tlb_entry, OpenRISCTLBEntry),
  45         VMSTATE_END_OF_LIST()
  46     }
  47 };
  48
  49 static int get_sr(QEMUFile *f, void *opaque, size_t size,
  50                   const VMStateField *field)
  51 {
  52     CPUOpenRISCState *env = opaque;
  53     cpu_set_sr(env, qemu_get_be32(f));
  54     return 0;
  55 }
  56
  57 static int put_sr(QEMUFile *f, void *opaque, size_t size,
  58                   const VMStateField *field, QJSON *vmdesc)
  59 {
  60     CPUOpenRISCState *env = opaque;
  61     qemu_put_be32(f, cpu_get_sr(env));
  62     return 0;
  63 }
  64
  65 static const VMStateInfo vmstate_sr = {
  66     .name = "sr",
  67     .get = get_sr,
  68     .put = put_sr,
  69 };
  70
  71 static const VMStateDescription vmstate_env = {
  72     .name = "env",
  73     .version_id = 6,
  74     .minimum_version_id = 6,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
  77         VMSTATE_UINTTL(pc, CPUOpenRISCState),
  78         VMSTATE_UINTTL(ppc, CPUOpenRISCState),
  79         VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState),
  80         VMSTATE_UINTTL(lock_addr, CPUOpenRISCState),
  81         VMSTATE_UINTTL(lock_value, CPUOpenRISCState),
  82         VMSTATE_UINTTL(epcr, CPUOpenRISCState),
  83         VMSTATE_UINTTL(eear, CPUOpenRISCState),
  84
  85         /* Save the architecture value of the SR, not the internally
  86            expanded version.  Since this architecture value does not
  87            exist in memory to be stored, this requires a but of hoop
  88            jumping.  We want OFFSET=0 so that we effectively pass ENV
  89            to the helper functions, and we need to fill in the name by
  90            hand since there's no field of that name.  */
  91         {
  92             .name = "sr",
  93             .version_id = 0,
  94             .size = sizeof(uint32_t),
  95             .info = &vmstate_sr,
  96             .flags = VMS_SINGLE,
  97             .offset = 0
  98         },
  99
 100         VMSTATE_UINT32(vr, CPUOpenRISCState),
 101         VMSTATE_UINT32(upr, CPUOpenRISCState),
 102         VMSTATE_UINT32(cpucfgr, CPUOpenRISCState),
 103         VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState),
 104         VMSTATE_UINT32(immucfgr, CPUOpenRISCState),
 105         VMSTATE_UINT32(evbar, CPUOpenRISCState),
 106         VMSTATE_UINT32(pmr, CPUOpenRISCState),
 107         VMSTATE_UINT32(esr, CPUOpenRISCState),
 108         VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
 109         VMSTATE_UINT64(mac, CPUOpenRISCState),
 110
 111         VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1,
 112                        vmstate_cpu_tlb, CPUOpenRISCTLBContext),
 113
 114         VMSTATE_TIMER_PTR(timer, CPUOpenRISCState),
 115         VMSTATE_UINT32(ttmr, CPUOpenRISCState),
 116
 117         VMSTATE_UINT32(picmr, CPUOpenRISCState),
 118         VMSTATE_UINT32(picsr, CPUOpenRISCState),
 119
 120         VMSTATE_END_OF_LIST()
 121     }
 122 };
 123
 124 static int cpu_post_load(void *opaque, int version_id)
 125 {
 126     OpenRISCCPU *cpu = opaque;
 127     CPUOpenRISCState *env = &cpu->env;
 128
 129     /* Update env->fp_status to match env->fpcsr.  */
 130     cpu_set_fpcsr(env, env->fpcsr);
 131     return 0;
 132 }
 133
 134 const VMStateDescription vmstate_openrisc_cpu = {
 135     .name = "cpu",
 136     .version_id = 1,
 137     .minimum_version_id = 1,
 138     .post_load = cpu_post_load,
 139     .fields = (VMStateField[]) {
 140         VMSTATE_CPU(),
 141         VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
 142         VMSTATE_END_OF_LIST()
 143     }
 144 };