hw/i386/pc_q35.c

   1 /*
   2  * Q35 chipset based pc system emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2009, 2010
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   9  *
  10  * This is based on pc.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/loader.h"
  32 #include "sysemu/arch_init.h"
  33 #include "hw/i2c/smbus.h"
  34 #include "hw/boards.h"
  35 #include "hw/timer/mc146818rtc.h"
  36 #include "hw/xen/xen.h"
  37 #include "sysemu/kvm.h"
  38 #include "hw/kvm/clock.h"
  39 #include "hw/pci-host/q35.h"
  40 #include "exec/address-spaces.h"
  41 #include "hw/i386/ich9.h"
  42 #include "hw/smbios/smbios.h"
  43 #include "hw/ide/pci.h"
  44 #include "hw/ide/ahci.h"
  45 #include "hw/usb.h"
  46 #include "hw/cpu/icc_bus.h"
  47 #include "qemu/error-report.h"
  48 #include "migration/migration.h"
  49
  50 /* ICH9 AHCI has 6 ports */
  51 #define MAX_SATA_PORTS     6
  52
  53 static bool has_acpi_build = true;
  54 static bool rsdp_in_ram = true;
  55 static bool smbios_defaults = true;
  56 static bool smbios_legacy_mode;
  57 static bool smbios_uuid_encoded = true;
  58 /* Make sure that guest addresses aligned at 1Gbyte boundaries get mapped to
  59  * host addresses aligned at 1Gbyte boundaries.  This way we can use 1GByte
  60  * pages in the host.
  61  */
  62 static bool gigabyte_align = true;
  63 static bool has_reserved_memory = true;
  64
  65 /* PC hardware initialisation */
  66 static void pc_q35_init(MachineState *machine)
  67 {
  68     PCMachineState *pcms = PC_MACHINE(machine);
  69     Q35PCIHost *q35_host;
  70     PCIHostState *phb;
  71     PCIBus *host_bus;
  72     PCIDevice *lpc;
  73     BusState *idebus[MAX_SATA_PORTS];
  74     ISADevice *rtc_state;
  75     MemoryRegion *pci_memory;
  76     MemoryRegion *rom_memory;
  77     MemoryRegion *ram_memory;
  78     GSIState *gsi_state;
  79     ISABus *isa_bus;
  80     int pci_enabled = 1;
  81     qemu_irq *gsi;
  82     qemu_irq *i8259;
  83     int i;
  84     ICH9LPCState *ich9_lpc;
  85     PCIDevice *ahci;
  86     DeviceState *icc_bridge;
  87     PcGuestInfo *guest_info;
  88     ram_addr_t lowmem;
  89     DriveInfo *hd[MAX_SATA_PORTS];
  90     MachineClass *mc = MACHINE_GET_CLASS(machine);
  91
  92     /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
  93      * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
  94      * also known as MMCFG).
  95      * If it doesn't, we need to split it in chunks below and above 4G.
  96      * In any case, try to make sure that guest addresses aligned at
  97      * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
  98      * For old machine types, use whatever split we used historically to avoid
  99      * breaking migration.
 100      */
 101     if (machine->ram_size >= 0xb0000000) {
 102         lowmem = gigabyte_align ? 0x80000000 : 0xb0000000;
 103     } else {
 104         lowmem = 0xb0000000;
 105     }
 106
 107     /* Handle the machine opt max-ram-below-4g.  It is basically doing
 108      * min(qemu limit, user limit).
 109      */
 110     if (lowmem > pcms->max_ram_below_4g) {
 111         lowmem = pcms->max_ram_below_4g;
 112         if (machine->ram_size - lowmem > lowmem &&
 113             lowmem & ((1ULL << 30) - 1)) {
 114             error_report("Warning: Large machine and max_ram_below_4g(%"PRIu64
 115                          ") not a multiple of 1G; possible bad performance.",
 116                          pcms->max_ram_below_4g);
 117         }
 118     }
 119
 120     if (machine->ram_size >= lowmem) {
 121         pcms->above_4g_mem_size = machine->ram_size - lowmem;
 122         pcms->below_4g_mem_size = lowmem;
 123     } else {
 124         pcms->above_4g_mem_size = 0;
 125         pcms->below_4g_mem_size = machine->ram_size;
 126     }
 127
 128     if (xen_enabled() && xen_hvm_init(&pcms->below_4g_mem_size,
 129                                       &pcms->above_4g_mem_size,
 130                                       &ram_memory) != 0) {
 131         fprintf(stderr, "xen hardware virtual machine initialisation failed\n");
 132         exit(1);
 133     }
 134
 135     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
 136     object_property_add_child(qdev_get_machine(), "icc-bridge",
 137                               OBJECT(icc_bridge), NULL);
 138
 139     pc_cpus_init(machine->cpu_model, icc_bridge);
 140     pc_acpi_init("q35-acpi-dsdt.aml");
 141
 142     kvmclock_create();
 143
 144     /* pci enabled */
 145     if (pci_enabled) {
 146         pci_memory = g_new(MemoryRegion, 1);
 147         memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
 148         rom_memory = pci_memory;
 149     } else {
 150         pci_memory = NULL;
 151         rom_memory = get_system_memory();
 152     }
 153
 154     guest_info = pc_guest_info_init(pcms);
 155     guest_info->isapc_ram_fw = false;
 156     guest_info->has_acpi_build = has_acpi_build;
 157     guest_info->has_reserved_memory = has_reserved_memory;
 158     guest_info->rsdp_in_ram = rsdp_in_ram;
 159
 160     /* Migration was not supported in 2.0 for Q35, so do not bother
 161      * with this hack (see hw/i386/acpi-build.c).
 162      */
 163     guest_info->legacy_acpi_table_size = 0;
 164
 165     if (smbios_defaults) {
 166         /* These values are guest ABI, do not change */
 167         smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
 168                             mc->name, smbios_legacy_mode, smbios_uuid_encoded,
 169                             SMBIOS_ENTRY_POINT_21);
 170     }
 171
 172     /* allocate ram and load rom/bios */
 173     if (!xen_enabled()) {
 174         pc_memory_init(pcms, get_system_memory(),
 175                        rom_memory, &ram_memory, guest_info);
 176     }
 177
 178     /* irq lines */
 179     gsi_state = g_malloc0(sizeof(*gsi_state));
 180     if (kvm_irqchip_in_kernel()) {
 181         kvm_pc_setup_irq_routing(pci_enabled);
 182         gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
 183                                  GSI_NUM_PINS);
 184     } else {
 185         gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
 186     }
 187
 188     /* create pci host bus */
 189     q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
 190
 191     object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host), NULL);
 192     q35_host->mch.ram_memory = ram_memory;
 193     q35_host->mch.pci_address_space = pci_memory;
 194     q35_host->mch.system_memory = get_system_memory();
 195     q35_host->mch.address_space_io = get_system_io();
 196     q35_host->mch.below_4g_mem_size = pcms->below_4g_mem_size;
 197     q35_host->mch.above_4g_mem_size = pcms->above_4g_mem_size;
 198     q35_host->mch.guest_info = guest_info;
 199     /* pci */
 200     qdev_init_nofail(DEVICE(q35_host));
 201     phb = PCI_HOST_BRIDGE(q35_host);
 202     host_bus = phb->bus;
 203     /* create ISA bus */
 204     lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
 205                                           ICH9_LPC_FUNC), true,
 206                                           TYPE_ICH9_LPC_DEVICE);
 207
 208     object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
 209                              TYPE_HOTPLUG_HANDLER,
 210                              (Object **)&pcms->acpi_dev,
 211                              object_property_allow_set_link,
 212                              OBJ_PROP_LINK_UNREF_ON_RELEASE, &error_abort);
 213     object_property_set_link(OBJECT(machine), OBJECT(lpc),
 214                              PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
 215
 216     ich9_lpc = ICH9_LPC_DEVICE(lpc);
 217     ich9_lpc->pic = gsi;
 218     ich9_lpc->ioapic = gsi_state->ioapic_irq;
 219     pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
 220                  ICH9_LPC_NB_PIRQS);
 221     pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
 222     isa_bus = ich9_lpc->isa_bus;
 223
 224     /*end early*/
 225     isa_bus_irqs(isa_bus, gsi);
 226
 227     if (kvm_irqchip_in_kernel()) {
 228         i8259 = kvm_i8259_init(isa_bus);
 229     } else if (xen_enabled()) {
 230         i8259 = xen_interrupt_controller_init();
 231     } else {
 232         i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
 233     }
 234
 235     for (i = 0; i < ISA_NUM_IRQS; i++) {
 236         gsi_state->i8259_irq[i] = i8259[i];
 237     }
 238     if (pci_enabled) {
 239         ioapic_init_gsi(gsi_state, "q35");
 240     }
 241     qdev_init_nofail(icc_bridge);
 242
 243     pc_register_ferr_irq(gsi[13]);
 244
 245     assert(pcms->vmport != ON_OFF_AUTO_MAX);
 246     if (pcms->vmport == ON_OFF_AUTO_AUTO) {
 247         pcms->vmport = xen_enabled() ? ON_OFF_AUTO_OFF : ON_OFF_AUTO_ON;
 248     }
 249
 250     /* init basic PC hardware */
 251     pc_basic_device_init(isa_bus, gsi, &rtc_state, !mc->no_floppy,
 252                          (pcms->vmport != ON_OFF_AUTO_ON), 0xff0104);
 253
 254     /* connect pm stuff to lpc */
 255     ich9_lpc_pm_init(lpc, pc_machine_is_smm_enabled(pcms), !mc->no_tco);
 256
 257     /* ahci and SATA device, for q35 1 ahci controller is built-in */
 258     ahci = pci_create_simple_multifunction(host_bus,
 259                                            PCI_DEVFN(ICH9_SATA1_DEV,
 260                                                      ICH9_SATA1_FUNC),
 261                                            true, "ich9-ahci");
 262     idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
 263     idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
 264     g_assert(MAX_SATA_PORTS == ICH_AHCI(ahci)->ahci.ports);
 265     ide_drive_get(hd, ICH_AHCI(ahci)->ahci.ports);
 266     ahci_ide_create_devs(ahci, hd);
 267
 268     if (usb_enabled()) {
 269         /* Should we create 6 UHCI according to ich9 spec? */
 270         ehci_create_ich9_with_companions(host_bus, 0x1d);
 271     }
 272
 273     /* TODO: Populate SPD eeprom data.  */
 274     smbus_eeprom_init(ich9_smb_init(host_bus,
 275                                     PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
 276                                     0xb100),
 277                       8, NULL, 0);
 278
 279     pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
 280
 281     /* the rest devices to which pci devfn is automatically assigned */
 282     pc_vga_init(isa_bus, host_bus);
 283     pc_nic_init(isa_bus, host_bus);
 284     if (pci_enabled) {
 285         pc_pci_device_init(host_bus);
 286     }
 287 }
 288
 289 static void pc_compat_2_3(MachineState *machine)
 290 {
 291     PCMachineState *pcms = PC_MACHINE(machine);
 292     savevm_skip_section_footers();
 293     if (kvm_enabled()) {
 294         pcms->smm = ON_OFF_AUTO_OFF;
 295     }
 296     global_state_set_optional();
 297     savevm_skip_configuration();
 298 }
 299
 300 static void pc_compat_2_2(MachineState *machine)
 301 {
 302     pc_compat_2_3(machine);
 303     rsdp_in_ram = false;
 304     machine->suppress_vmdesc = true;
 305 }
 306
 307 static void pc_compat_2_1(MachineState *machine)
 308 {
 309     PCMachineState *pcms = PC_MACHINE(machine);
 310
 311     pc_compat_2_2(machine);
 312     pcms->enforce_aligned_dimm = false;
 313     smbios_uuid_encoded = false;
 314     x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM);
 315 }
 316
 317 static void pc_compat_2_0(MachineState *machine)
 318 {
 319     pc_compat_2_1(machine);
 320     smbios_legacy_mode = true;
 321     has_reserved_memory = false;
 322     pc_set_legacy_acpi_data_size();
 323 }
 324
 325 static void pc_compat_1_7(MachineState *machine)
 326 {
 327     pc_compat_2_0(machine);
 328     smbios_defaults = false;
 329     gigabyte_align = false;
 330     option_rom_has_mr = true;
 331     x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC);
 332 }
 333
 334 static void pc_compat_1_6(MachineState *machine)
 335 {
 336     pc_compat_1_7(machine);
 337     rom_file_has_mr = false;
 338     has_acpi_build = false;
 339 }
 340
 341 static void pc_compat_1_5(MachineState *machine)
 342 {
 343     pc_compat_1_6(machine);
 344 }
 345
 346 static void pc_compat_1_4(MachineState *machine)
 347 {
 348     pc_compat_1_5(machine);
 349 }
 350
 351 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
 352     static void pc_init_##suffix(MachineState *machine) \
 353     { \
 354         void (*compat)(MachineState *m) = (compatfn); \
 355         if (compat) { \
 356             compat(machine); \
 357         } \
 358         pc_q35_init(machine); \
 359     } \
 360     DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
 361
 362
 363 static void pc_q35_machine_options(MachineClass *m)
 364 {
 365     m->family = "pc_q35";
 366     m->desc = "Standard PC (Q35 + ICH9, 2009)";
 367     m->hot_add_cpu = pc_hot_add_cpu;
 368     m->units_per_default_bus = 1;
 369 }
 370
 371 static void pc_q35_2_4_machine_options(MachineClass *m)
 372 {
 373     pc_q35_machine_options(m);
 374     m->default_machine_opts = "firmware=bios-256k.bin";
 375     m->default_display = "std";
 376     m->no_floppy = 1;
 377     m->no_tco = 0;
 378     m->alias = "q35";
 379 }
 380
 381 DEFINE_Q35_MACHINE(v2_4, "pc-q35-2.4", NULL,
 382                    pc_q35_2_4_machine_options);
 383
 384
 385 static void pc_q35_2_3_machine_options(MachineClass *m)
 386 {
 387     pc_q35_2_4_machine_options(m);
 388     m->no_floppy = 0;
 389     m->no_tco = 1;
 390     m->alias = NULL;
 391     SET_MACHINE_COMPAT(m, PC_COMPAT_2_3);
 392 }
 393
 394 DEFINE_Q35_MACHINE(v2_3, "pc-q35-2.3", pc_compat_2_3,
 395                    pc_q35_2_3_machine_options);
 396
 397
 398 static void pc_q35_2_2_machine_options(MachineClass *m)
 399 {
 400     pc_q35_2_3_machine_options(m);
 401     SET_MACHINE_COMPAT(m, PC_COMPAT_2_2);
 402 }
 403
 404 DEFINE_Q35_MACHINE(v2_2, "pc-q35-2.2", pc_compat_2_2,
 405                    pc_q35_2_2_machine_options);
 406
 407
 408 static void pc_q35_2_1_machine_options(MachineClass *m)
 409 {
 410     pc_q35_2_2_machine_options(m);
 411     m->default_display = NULL;
 412     SET_MACHINE_COMPAT(m, PC_COMPAT_2_1);
 413 }
 414
 415 DEFINE_Q35_MACHINE(v2_1, "pc-q35-2.1", pc_compat_2_1,
 416                    pc_q35_2_1_machine_options);
 417
 418
 419 static void pc_q35_2_0_machine_options(MachineClass *m)
 420 {
 421     pc_q35_2_1_machine_options(m);
 422     SET_MACHINE_COMPAT(m, PC_COMPAT_2_0);
 423 }
 424
 425 DEFINE_Q35_MACHINE(v2_0, "pc-q35-2.0", pc_compat_2_0,
 426                    pc_q35_2_0_machine_options);
 427
 428
 429 static void pc_q35_1_7_machine_options(MachineClass *m)
 430 {
 431     pc_q35_2_0_machine_options(m);
 432     m->default_machine_opts = NULL;
 433     SET_MACHINE_COMPAT(m, PC_COMPAT_1_7);
 434 }
 435
 436 DEFINE_Q35_MACHINE(v1_7, "pc-q35-1.7", pc_compat_1_7,
 437                    pc_q35_1_7_machine_options);
 438
 439
 440 static void pc_q35_1_6_machine_options(MachineClass *m)
 441 {
 442     pc_q35_machine_options(m);
 443     SET_MACHINE_COMPAT(m, PC_COMPAT_1_6);
 444 }
 445
 446 DEFINE_Q35_MACHINE(v1_6, "pc-q35-1.6", pc_compat_1_6,
 447                    pc_q35_1_6_machine_options);
 448
 449
 450 static void pc_q35_1_5_machine_options(MachineClass *m)
 451 {
 452     pc_q35_1_6_machine_options(m);
 453     SET_MACHINE_COMPAT(m, PC_COMPAT_1_5);
 454 }
 455
 456 DEFINE_Q35_MACHINE(v1_5, "pc-q35-1.5", pc_compat_1_5,
 457                    pc_q35_1_5_machine_options);
 458
 459
 460 static void pc_q35_1_4_machine_options(MachineClass *m)
 461 {
 462     pc_q35_1_5_machine_options(m);
 463     m->hot_add_cpu = NULL;
 464     SET_MACHINE_COMPAT(m, PC_COMPAT_1_4);
 465 }
 466
 467 DEFINE_Q35_MACHINE(v1_4, "pc-q35-1.4", pc_compat_1_4,
 468                    pc_q35_1_4_machine_options);