hw/arm/xlnx-zcu102.c

   1 /*
   2  * Xilinx ZynqMP ZCU102 board
   3  *
   4  * Copyright (C) 2015 Xilinx Inc
   5  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  * for more details.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "hw/arm/xlnx-zynqmp.h"
  21 #include "hw/boards.h"
  22 #include "qemu/error-report.h"
  23 #include "qemu/log.h"
  24 #include "sysemu/device_tree.h"
  25 #include "qom/object.h"
  26 #include "net/can_emu.h"
  27
  28 struct XlnxZCU102 {
  29     MachineState parent_obj;
  30
  31     XlnxZynqMPState soc;
  32
  33     bool secure;
  34     bool virt;
  35
  36     CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
  37
  38     struct arm_boot_info binfo;
  39 };
  40
  41 #define TYPE_ZCU102_MACHINE   MACHINE_TYPE_NAME("xlnx-zcu102")
  42 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZCU102, ZCU102_MACHINE)
  43
  44
  45 static bool zcu102_get_secure(Object *obj, Error **errp)
  46 {
  47     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  48
  49     return s->secure;
  50 }
  51
  52 static void zcu102_set_secure(Object *obj, bool value, Error **errp)
  53 {
  54     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  55
  56     s->secure = value;
  57 }
  58
  59 static bool zcu102_get_virt(Object *obj, Error **errp)
  60 {
  61     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  62
  63     return s->virt;
  64 }
  65
  66 static void zcu102_set_virt(Object *obj, bool value, Error **errp)
  67 {
  68     XlnxZCU102 *s = ZCU102_MACHINE(obj);
  69
  70     s->virt = value;
  71 }
  72
  73 static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt)
  74 {
  75     XlnxZCU102 *s = container_of(binfo, XlnxZCU102, binfo);
  76     bool method_is_hvc;
  77     char **node_path;
  78     const char *r;
  79     int prop_len;
  80     int i;
  81
  82     /* If EL3 is enabled, we keep all firmware nodes active.  */
  83     if (!s->secure) {
  84         node_path = qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware",
  85                                        &error_fatal);
  86
  87         for (i = 0; node_path && node_path[i]; i++) {
  88             r = qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len, NULL);
  89             method_is_hvc = r && !strcmp("hvc", r);
  90
  91             /* Allow HVC based firmware if EL2 is enabled.  */
  92             if (method_is_hvc && s->virt) {
  93                 continue;
  94             }
  95             qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled");
  96         }
  97         g_strfreev(node_path);
  98     }
  99 }
 100
 101 static void xlnx_zcu102_init(MachineState *machine)
 102 {
 103     XlnxZCU102 *s = ZCU102_MACHINE(machine);
 104     int i;
 105     uint64_t ram_size = machine->ram_size;
 106
 107     /* Create the memory region to pass to the SoC */
 108     if (ram_size > XLNX_ZYNQMP_MAX_RAM_SIZE) {
 109         error_report("ERROR: RAM size 0x%" PRIx64 " above max supported of "
 110                      "0x%llx", ram_size,
 111                      XLNX_ZYNQMP_MAX_RAM_SIZE);
 112         exit(1);
 113     }
 114
 115     if (ram_size < 0x08000000) {
 116         qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102",
 117                  ram_size);
 118     }
 119
 120     object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_XLNX_ZYNQMP);
 121
 122     object_property_set_link(OBJECT(&s->soc), "ddr-ram", OBJECT(machine->ram),
 123                              &error_abort);
 124     object_property_set_bool(OBJECT(&s->soc), "secure", s->secure,
 125                              &error_fatal);
 126     object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
 127                              &error_fatal);
 128
 129     for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
 130         gchar *bus_name = g_strdup_printf("canbus%d", i);
 131
 132         object_property_set_link(OBJECT(&s->soc), bus_name,
 133                                  OBJECT(s->canbus[i]), &error_fatal);
 134         g_free(bus_name);
 135     }
 136
 137     qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
 138
 139     /* Create and plug in the SD cards */
 140     for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
 141         BusState *bus;
 142         DriveInfo *di = drive_get_next(IF_SD);
 143         BlockBackend *blk = di ? blk_by_legacy_dinfo(di) : NULL;
 144         DeviceState *carddev;
 145         char *bus_name;
 146
 147         bus_name = g_strdup_printf("sd-bus%d", i);
 148         bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
 149         g_free(bus_name);
 150         if (!bus) {
 151             error_report("No SD bus found for SD card %d", i);
 152             exit(1);
 153         }
 154         carddev = qdev_new(TYPE_SD_CARD);
 155         qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal);
 156         qdev_realize_and_unref(carddev, bus, &error_fatal);
 157     }
 158
 159     for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
 160         BusState *spi_bus;
 161         DeviceState *flash_dev;
 162         qemu_irq cs_line;
 163         DriveInfo *dinfo = drive_get_next(IF_MTD);
 164         gchar *bus_name = g_strdup_printf("spi%d", i);
 165
 166         spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
 167         g_free(bus_name);
 168
 169         flash_dev = qdev_new("sst25wf080");
 170         if (dinfo) {
 171             qdev_prop_set_drive_err(flash_dev, "drive",
 172                                     blk_by_legacy_dinfo(dinfo), &error_fatal);
 173         }
 174         qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
 175
 176         cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 177
 178         sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi[i]), 1, cs_line);
 179     }
 180
 181     for (i = 0; i < XLNX_ZYNQMP_NUM_QSPI_FLASH; i++) {
 182         BusState *spi_bus;
 183         DeviceState *flash_dev;
 184         qemu_irq cs_line;
 185         DriveInfo *dinfo = drive_get_next(IF_MTD);
 186         int bus = i / XLNX_ZYNQMP_NUM_QSPI_BUS_CS;
 187         gchar *bus_name = g_strdup_printf("qspi%d", bus);
 188
 189         spi_bus = qdev_get_child_bus(DEVICE(&s->soc), bus_name);
 190         g_free(bus_name);
 191
 192         flash_dev = qdev_new("n25q512a11");
 193         if (dinfo) {
 194             qdev_prop_set_drive_err(flash_dev, "drive",
 195                                     blk_by_legacy_dinfo(dinfo), &error_fatal);
 196         }
 197         qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal);
 198
 199         cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 200
 201         sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.qspi), i + 1, cs_line);
 202     }
 203
 204     /* TODO create and connect IDE devices for ide_drive_get() */
 205
 206     s->binfo.ram_size = ram_size;
 207     s->binfo.loader_start = 0;
 208     s->binfo.modify_dtb = zcu102_modify_dtb;
 209     arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo);
 210 }
 211
 212 static void xlnx_zcu102_machine_instance_init(Object *obj)
 213 {
 214     XlnxZCU102 *s = ZCU102_MACHINE(obj);
 215
 216     /* Default to secure mode being disabled */
 217     s->secure = false;
 218     /* Default to virt (EL2) being disabled */
 219     s->virt = false;
 220     object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
 221                              (Object **)&s->canbus[0],
 222                              object_property_allow_set_link,
 223                              0);
 224
 225     object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
 226                              (Object **)&s->canbus[1],
 227                              object_property_allow_set_link,
 228                              0);
 229 }
 230
 231 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
 232 {
 233     MachineClass *mc = MACHINE_CLASS(oc);
 234
 235     mc->desc = "Xilinx ZynqMP ZCU102 board with 4xA53s and 2xR5Fs based on " \
 236                "the value of smp";
 237     mc->init = xlnx_zcu102_init;
 238     mc->block_default_type = IF_IDE;
 239     mc->units_per_default_bus = 1;
 240     mc->ignore_memory_transaction_failures = true;
 241     mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;
 242     mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS;
 243     mc->default_ram_id = "ddr-ram";
 244
 245     object_class_property_add_bool(oc, "secure", zcu102_get_secure,
 246                                    zcu102_set_secure);
 247     object_class_property_set_description(oc, "secure",
 248                                           "Set on/off to enable/disable the ARM "
 249                                           "Security Extensions (TrustZone)");
 250
 251     object_class_property_add_bool(oc, "virtualization", zcu102_get_virt,
 252                                    zcu102_set_virt);
 253     object_class_property_set_description(oc, "virtualization",
 254                                           "Set on/off to enable/disable emulating a "
 255                                           "guest CPU which implements the ARM "
 256                                           "Virtualization Extensions");
 257 }
 258
 259 static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
 260     .name       = TYPE_ZCU102_MACHINE,
 261     .parent     = TYPE_MACHINE,
 262     .class_init = xlnx_zcu102_machine_class_init,
 263     .instance_init = xlnx_zcu102_machine_instance_init,
 264     .instance_size = sizeof(XlnxZCU102),
 265 };
 266
 267 static void xlnx_zcu102_machine_init_register_types(void)
 268 {
 269     type_register_static(&xlnx_zcu102_machine_init_typeinfo);
 270 }
 271
 272 type_init(xlnx_zcu102_machine_init_register_types)