target/mips/cpu.h

   1 #ifndef MIPS_CPU_H
   2 #define MIPS_CPU_H
   3
   4 #include "cpu-qom.h"
   5 #include "exec/cpu-defs.h"
   6 #include "fpu/softfloat-types.h"
   7 #include "mips-defs.h"
   8
   9 #define TCG_GUEST_DEFAULT_MO (0)
  10
  11 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
  12
  13 /* MSA Context */
  14 #define MSA_WRLEN (128)
  15
  16 typedef union wr_t wr_t;
  17 union wr_t {
  18     int8_t  b[MSA_WRLEN / 8];
  19     int16_t h[MSA_WRLEN / 16];
  20     int32_t w[MSA_WRLEN / 32];
  21     int64_t d[MSA_WRLEN / 64];
  22 };
  23
  24 typedef union fpr_t fpr_t;
  25 union fpr_t {
  26     float64  fd;   /* ieee double precision */
  27     float32  fs[2];/* ieee single precision */
  28     uint64_t d;    /* binary double fixed-point */
  29     uint32_t w[2]; /* binary single fixed-point */
  30 /* FPU/MSA register mapping is not tested on big-endian hosts. */
  31     wr_t     wr;   /* vector data */
  32 };
  33 /*
  34  *define FP_ENDIAN_IDX to access the same location
  35  * in the fpr_t union regardless of the host endianness
  36  */
  37 #if defined(HOST_WORDS_BIGENDIAN)
  38 #  define FP_ENDIAN_IDX 1
  39 #else
  40 #  define FP_ENDIAN_IDX 0
  41 #endif
  42
  43 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
  44 struct CPUMIPSFPUContext {
  45     /* Floating point registers */
  46     fpr_t fpr[32];
  47     float_status fp_status;
  48     /* fpu implementation/revision register (fir) */
  49     uint32_t fcr0;
  50 #define FCR0_FREP 29
  51 #define FCR0_UFRP 28
  52 #define FCR0_HAS2008 23
  53 #define FCR0_F64 22
  54 #define FCR0_L 21
  55 #define FCR0_W 20
  56 #define FCR0_3D 19
  57 #define FCR0_PS 18
  58 #define FCR0_D 17
  59 #define FCR0_S 16
  60 #define FCR0_PRID 8
  61 #define FCR0_REV 0
  62     /* fcsr */
  63     uint32_t fcr31_rw_bitmask;
  64     uint32_t fcr31;
  65 #define FCR31_FS 24
  66 #define FCR31_ABS2008 19
  67 #define FCR31_NAN2008 18
  68 #define SET_FP_COND(num, env)     do { ((env).fcr31) |=                 \
  69                                        ((num) ? (1 << ((num) + 24)) :   \
  70                                                 (1 << 23));             \
  71                                      } while (0)
  72 #define CLEAR_FP_COND(num, env)   do { ((env).fcr31) &=                 \
  73                                        ~((num) ? (1 << ((num) + 24)) :  \
  74                                                  (1 << 23));            \
  75                                      } while (0)
  76 #define GET_FP_COND(env)         ((((env).fcr31 >> 24) & 0xfe) |        \
  77                                  (((env).fcr31 >> 23) & 0x1))
  78 #define GET_FP_CAUSE(reg)        (((reg) >> 12) & 0x3f)
  79 #define GET_FP_ENABLE(reg)       (((reg) >>  7) & 0x1f)
  80 #define GET_FP_FLAGS(reg)        (((reg) >>  2) & 0x1f)
  81 #define SET_FP_CAUSE(reg, v)      do { (reg) = ((reg) & ~(0x3f << 12)) | \
  82                                                ((v & 0x3f) << 12);       \
  83                                      } while (0)
  84 #define SET_FP_ENABLE(reg, v)     do { (reg) = ((reg) & ~(0x1f <<  7)) | \
  85                                                ((v & 0x1f) << 7);        \
  86                                      } while (0)
  87 #define SET_FP_FLAGS(reg, v)      do { (reg) = ((reg) & ~(0x1f <<  2)) | \
  88                                                ((v & 0x1f) << 2);        \
  89                                      } while (0)
  90 #define UPDATE_FP_FLAGS(reg, v)   do { (reg) |= ((v & 0x1f) << 2); } while (0)
  91 #define FP_INEXACT        1
  92 #define FP_UNDERFLOW      2
  93 #define FP_OVERFLOW       4
  94 #define FP_DIV0           8
  95 #define FP_INVALID        16
  96 #define FP_UNIMPLEMENTED  32
  97 };
  98
  99 #define TARGET_INSN_START_EXTRA_WORDS 2
 100
 101 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
 102 struct CPUMIPSMVPContext {
 103     int32_t CP0_MVPControl;
 104 #define CP0MVPCo_CPA    3
 105 #define CP0MVPCo_STLB   2
 106 #define CP0MVPCo_VPC    1
 107 #define CP0MVPCo_EVP    0
 108     int32_t CP0_MVPConf0;
 109 #define CP0MVPC0_M      31
 110 #define CP0MVPC0_TLBS   29
 111 #define CP0MVPC0_GS     28
 112 #define CP0MVPC0_PCP    27
 113 #define CP0MVPC0_PTLBE  16
 114 #define CP0MVPC0_TCA    15
 115 #define CP0MVPC0_PVPE   10
 116 #define CP0MVPC0_PTC    0
 117     int32_t CP0_MVPConf1;
 118 #define CP0MVPC1_CIM    31
 119 #define CP0MVPC1_CIF    30
 120 #define CP0MVPC1_PCX    20
 121 #define CP0MVPC1_PCP2   10
 122 #define CP0MVPC1_PCP1   0
 123 };
 124
 125 typedef struct mips_def_t mips_def_t;
 126
 127 #define MIPS_SHADOW_SET_MAX 16
 128 #define MIPS_TC_MAX 5
 129 #define MIPS_FPU_MAX 1
 130 #define MIPS_DSP_ACC 4
 131 #define MIPS_KSCRATCH_NUM 6
 132 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
 133
 134
 135 /*
 136  *     Summary of CP0 registers
 137  *     ========================
 138  *
 139  *
 140  *     Register 0        Register 1        Register 2        Register 3
 141  *     ----------        ----------        ----------        ----------
 142  *
 143  * 0   Index             Random            EntryLo0          EntryLo1
 144  * 1   MVPControl        VPEControl        TCStatus          GlobalNumber
 145  * 2   MVPConf0          VPEConf0          TCBind
 146  * 3   MVPConf1          VPEConf1          TCRestart
 147  * 4   VPControl         YQMask            TCHalt
 148  * 5                     VPESchedule       TCContext
 149  * 6                     VPEScheFBack      TCSchedule
 150  * 7                     VPEOpt            TCScheFBack       TCOpt
 151  *
 152  *
 153  *     Register 4        Register 5        Register 6        Register 7
 154  *     ----------        ----------        ----------        ----------
 155  *
 156  * 0   Context           PageMask          Wired             HWREna
 157  * 1   ContextConfig     PageGrain         SRSConf0
 158  * 2   UserLocal         SegCtl0           SRSConf1
 159  * 3   XContextConfig    SegCtl1           SRSConf2
 160  * 4   DebugContextID    SegCtl2           SRSConf3
 161  * 5   MemoryMapID       PWBase            SRSConf4
 162  * 6                     PWField           PWCtl
 163  * 7                     PWSize
 164  *
 165  *
 166  *     Register 8        Register 9        Register 10       Register 11
 167  *     ----------        ----------        -----------       -----------
 168  *
 169  * 0   BadVAddr          Count             EntryHi           Compare
 170  * 1   BadInstr
 171  * 2   BadInstrP
 172  * 3   BadInstrX
 173  * 4                                       GuestCtl1         GuestCtl0Ext
 174  * 5                                       GuestCtl2
 175  * 6                     SAARI             GuestCtl3
 176  * 7                     SAAR
 177  *
 178  *
 179  *     Register 12       Register 13       Register 14       Register 15
 180  *     -----------       -----------       -----------       -----------
 181  *
 182  * 0   Status            Cause             EPC               PRId
 183  * 1   IntCtl                                                EBase
 184  * 2   SRSCtl                              NestedEPC         CDMMBase
 185  * 3   SRSMap                                                CMGCRBase
 186  * 4   View_IPL          View_RIPL                           BEVVA
 187  * 5   SRSMap2           NestedExc
 188  * 6   GuestCtl0
 189  * 7   GTOffset
 190  *
 191  *
 192  *     Register 16       Register 17       Register 18       Register 19
 193  *     -----------       -----------       -----------       -----------
 194  *
 195  * 0   Config            LLAddr            WatchLo           WatchHi
 196  * 1   Config1           MAAR              WatchLo           WatchHi
 197  * 2   Config2           MAARI             WatchLo           WatchHi
 198  * 3   Config3                             WatchLo           WatchHi
 199  * 4   Config4                             WatchLo           WatchHi
 200  * 5   Config5                             WatchLo           WatchHi
 201  * 6                                       WatchLo           WatchHi
 202  * 7                                       WatchLo           WatchHi
 203  *
 204  *
 205  *     Register 20       Register 21       Register 22       Register 23
 206  *     -----------       -----------       -----------       -----------
 207  *
 208  * 0   XContext                                              Debug
 209  * 1                                                         TraceControl
 210  * 2                                                         TraceControl2
 211  * 3                                                         UserTraceData1
 212  * 4                                                         TraceIBPC
 213  * 5                                                         TraceDBPC
 214  * 6                                                         Debug2
 215  * 7
 216  *
 217  *
 218  *     Register 24       Register 25       Register 26       Register 27
 219  *     -----------       -----------       -----------       -----------
 220  *
 221  * 0   DEPC              PerfCnt            ErrCtl          CacheErr
 222  * 1                     PerfCnt
 223  * 2   TraceControl3     PerfCnt
 224  * 3   UserTraceData2    PerfCnt
 225  * 4                     PerfCnt
 226  * 5                     PerfCnt
 227  * 6                     PerfCnt
 228  * 7                     PerfCnt
 229  *
 230  *
 231  *     Register 28       Register 29       Register 30       Register 31
 232  *     -----------       -----------       -----------       -----------
 233  *
 234  * 0   DataLo            DataHi            ErrorEPC          DESAVE
 235  * 1   TagLo             TagHi
 236  * 2   DataLo            DataHi                              KScratch<n>
 237  * 3   TagLo             TagHi                               KScratch<n>
 238  * 4   DataLo            DataHi                              KScratch<n>
 239  * 5   TagLo             TagHi                               KScratch<n>
 240  * 6   DataLo            DataHi                              KScratch<n>
 241  * 7   TagLo             TagHi                               KScratch<n>
 242  *
 243  */
 244 #define CP0_REGISTER_00     0
 245 #define CP0_REGISTER_01     1
 246 #define CP0_REGISTER_02     2
 247 #define CP0_REGISTER_03     3
 248 #define CP0_REGISTER_04     4
 249 #define CP0_REGISTER_05     5
 250 #define CP0_REGISTER_06     6
 251 #define CP0_REGISTER_07     7
 252 #define CP0_REGISTER_08     8
 253 #define CP0_REGISTER_09     9
 254 #define CP0_REGISTER_10    10
 255 #define CP0_REGISTER_11    11
 256 #define CP0_REGISTER_12    12
 257 #define CP0_REGISTER_13    13
 258 #define CP0_REGISTER_14    14
 259 #define CP0_REGISTER_15    15
 260 #define CP0_REGISTER_16    16
 261 #define CP0_REGISTER_17    17
 262 #define CP0_REGISTER_18    18
 263 #define CP0_REGISTER_19    19
 264 #define CP0_REGISTER_20    20
 265 #define CP0_REGISTER_21    21
 266 #define CP0_REGISTER_22    22
 267 #define CP0_REGISTER_23    23
 268 #define CP0_REGISTER_24    24
 269 #define CP0_REGISTER_25    25
 270 #define CP0_REGISTER_26    26
 271 #define CP0_REGISTER_27    27
 272 #define CP0_REGISTER_28    28
 273 #define CP0_REGISTER_29    29
 274 #define CP0_REGISTER_30    30
 275 #define CP0_REGISTER_31    31
 276
 277
 278 /* CP0 Register 00 */
 279 #define CP0_REG00__INDEX           0
 280 #define CP0_REG00__MVPCONTROL      1
 281 #define CP0_REG00__MVPCONF0        2
 282 #define CP0_REG00__MVPCONF1        3
 283 #define CP0_REG00__VPCONTROL       4
 284 /* CP0 Register 01 */
 285 #define CP0_REG01__RANDOM          0
 286 #define CP0_REG01__VPECONTROL      1
 287 #define CP0_REG01__VPECONF0        2
 288 #define CP0_REG01__VPECONF1        3
 289 #define CP0_REG01__YQMASK          4
 290 #define CP0_REG01__VPESCHEDULE     5
 291 #define CP0_REG01__VPESCHEFBACK    6
 292 #define CP0_REG01__VPEOPT          7
 293 /* CP0 Register 02 */
 294 #define CP0_REG02__ENTRYLO0        0
 295 #define CP0_REG02__TCSTATUS        1
 296 #define CP0_REG02__TCBIND          2
 297 #define CP0_REG02__TCRESTART       3
 298 #define CP0_REG02__TCHALT          4
 299 #define CP0_REG02__TCCONTEXT       5
 300 #define CP0_REG02__TCSCHEDULE      6
 301 #define CP0_REG02__TCSCHEFBACK     7
 302 /* CP0 Register 03 */
 303 #define CP0_REG03__ENTRYLO1        0
 304 #define CP0_REG03__GLOBALNUM       1
 305 #define CP0_REG03__TCOPT           7
 306 /* CP0 Register 04 */
 307 #define CP0_REG04__CONTEXT         0
 308 #define CP0_REG04__CONTEXTCONFIG   1
 309 #define CP0_REG04__USERLOCAL       2
 310 #define CP0_REG04__XCONTEXTCONFIG  3
 311 #define CP0_REG04__DBGCONTEXTID    4
 312 #define CP0_REG00__MMID            5
 313 /* CP0 Register 05 */
 314 #define CP0_REG05__PAGEMASK        0
 315 #define CP0_REG05__PAGEGRAIN       1
 316 #define CP0_REG05__SEGCTL0         2
 317 #define CP0_REG05__SEGCTL1         3
 318 #define CP0_REG05__SEGCTL2         4
 319 #define CP0_REG05__PWBASE          5
 320 #define CP0_REG05__PWFIELD         6
 321 #define CP0_REG05__PWSIZE          7
 322 /* CP0 Register 06 */
 323 #define CP0_REG06__WIRED           0
 324 #define CP0_REG06__SRSCONF0        1
 325 #define CP0_REG06__SRSCONF1        2
 326 #define CP0_REG06__SRSCONF2        3
 327 #define CP0_REG06__SRSCONF3        4
 328 #define CP0_REG06__SRSCONF4        5
 329 #define CP0_REG06__PWCTL           6
 330 /* CP0 Register 07 */
 331 #define CP0_REG07__HWRENA          0
 332 /* CP0 Register 08 */
 333 #define CP0_REG08__BADVADDR        0
 334 #define CP0_REG08__BADINSTR        1
 335 #define CP0_REG08__BADINSTRP       2
 336 #define CP0_REG08__BADINSTRX       3
 337 /* CP0 Register 09 */
 338 #define CP0_REG09__COUNT           0
 339 #define CP0_REG09__SAARI           6
 340 #define CP0_REG09__SAAR            7
 341 /* CP0 Register 10 */
 342 #define CP0_REG10__ENTRYHI         0
 343 #define CP0_REG10__GUESTCTL1       4
 344 #define CP0_REG10__GUESTCTL2       5
 345 #define CP0_REG10__GUESTCTL3       6
 346 /* CP0 Register 11 */
 347 #define CP0_REG11__COMPARE         0
 348 #define CP0_REG11__GUESTCTL0EXT    4
 349 /* CP0 Register 12 */
 350 #define CP0_REG12__STATUS          0
 351 #define CP0_REG12__INTCTL          1
 352 #define CP0_REG12__SRSCTL          2
 353 #define CP0_REG12__GUESTCTL0       6
 354 #define CP0_REG12__GTOFFSET        7
 355 /* CP0 Register 13 */
 356 #define CP0_REG13__CAUSE           0
 357 /* CP0 Register 14 */
 358 #define CP0_REG14__EPC             0
 359 /* CP0 Register 15 */
 360 #define CP0_REG15__PRID            0
 361 #define CP0_REG15__EBASE           1
 362 #define CP0_REG15__CDMMBASE        2
 363 #define CP0_REG15__CMGCRBASE       3
 364 /* CP0 Register 16 */
 365 #define CP0_REG16__CONFIG          0
 366 #define CP0_REG16__CONFIG1         1
 367 #define CP0_REG16__CONFIG2         2
 368 #define CP0_REG16__CONFIG3         3
 369 #define CP0_REG16__CONFIG4         4
 370 #define CP0_REG16__CONFIG5         5
 371 #define CP0_REG00__CONFIG7         7
 372 /* CP0 Register 17 */
 373 #define CP0_REG17__LLADDR          0
 374 #define CP0_REG17__MAAR            1
 375 #define CP0_REG17__MAARI           2
 376 /* CP0 Register 18 */
 377 #define CP0_REG18__WATCHLO0        0
 378 #define CP0_REG18__WATCHLO1        1
 379 #define CP0_REG18__WATCHLO2        2
 380 #define CP0_REG18__WATCHLO3        3
 381 /* CP0 Register 19 */
 382 #define CP0_REG19__WATCHHI0        0
 383 #define CP0_REG19__WATCHHI1        1
 384 #define CP0_REG19__WATCHHI2        2
 385 #define CP0_REG19__WATCHHI3        3
 386 /* CP0 Register 20 */
 387 #define CP0_REG20__XCONTEXT        0
 388 /* CP0 Register 21 */
 389 /* CP0 Register 22 */
 390 /* CP0 Register 23 */
 391 #define CP0_REG23__DEBUG           0
 392 /* CP0 Register 24 */
 393 #define CP0_REG24__DEPC            0
 394 /* CP0 Register 25 */
 395 #define CP0_REG25__PERFCTL0        0
 396 #define CP0_REG25__PERFCNT0        1
 397 #define CP0_REG25__PERFCTL1        2
 398 #define CP0_REG25__PERFCNT1        3
 399 #define CP0_REG25__PERFCTL2        4
 400 #define CP0_REG25__PERFCNT2        5
 401 #define CP0_REG25__PERFCTL3        6
 402 #define CP0_REG25__PERFCNT3        7
 403 /* CP0 Register 26 */
 404 #define CP0_REG00__ERRCTL          0
 405 /* CP0 Register 27 */
 406 #define CP0_REG27__CACHERR         0
 407 /* CP0 Register 28 */
 408 #define CP0_REG28__ITAGLO          0
 409 #define CP0_REG28__IDATALO         1
 410 #define CP0_REG28__DTAGLO          2
 411 #define CP0_REG28__DDATALO         3
 412 /* CP0 Register 29 */
 413 #define CP0_REG29__IDATAHI         1
 414 #define CP0_REG29__DDATAHI         3
 415 /* CP0 Register 30 */
 416 #define CP0_REG30__ERROREPC        0
 417 /* CP0 Register 31 */
 418 #define CP0_REG31__DESAVE          0
 419 #define CP0_REG31__KSCRATCH1       2
 420 #define CP0_REG31__KSCRATCH2       3
 421 #define CP0_REG31__KSCRATCH3       4
 422 #define CP0_REG31__KSCRATCH4       5
 423 #define CP0_REG31__KSCRATCH5       6
 424 #define CP0_REG31__KSCRATCH6       7
 425
 426
 427 typedef struct TCState TCState;
 428 struct TCState {
 429     target_ulong gpr[32];
 430     target_ulong PC;
 431     target_ulong HI[MIPS_DSP_ACC];
 432     target_ulong LO[MIPS_DSP_ACC];
 433     target_ulong ACX[MIPS_DSP_ACC];
 434     target_ulong DSPControl;
 435     int32_t CP0_TCStatus;
 436 #define CP0TCSt_TCU3    31
 437 #define CP0TCSt_TCU2    30
 438 #define CP0TCSt_TCU1    29
 439 #define CP0TCSt_TCU0    28
 440 #define CP0TCSt_TMX     27
 441 #define CP0TCSt_RNST    23
 442 #define CP0TCSt_TDS     21
 443 #define CP0TCSt_DT      20
 444 #define CP0TCSt_DA      15
 445 #define CP0TCSt_A       13
 446 #define CP0TCSt_TKSU    11
 447 #define CP0TCSt_IXMT    10
 448 #define CP0TCSt_TASID   0
 449     int32_t CP0_TCBind;
 450 #define CP0TCBd_CurTC   21
 451 #define CP0TCBd_TBE     17
 452 #define CP0TCBd_CurVPE  0
 453     target_ulong CP0_TCHalt;
 454     target_ulong CP0_TCContext;
 455     target_ulong CP0_TCSchedule;
 456     target_ulong CP0_TCScheFBack;
 457     int32_t CP0_Debug_tcstatus;
 458     target_ulong CP0_UserLocal;
 459
 460     int32_t msacsr;
 461
 462 #define MSACSR_FS       24
 463 #define MSACSR_FS_MASK  (1 << MSACSR_FS)
 464 #define MSACSR_NX       18
 465 #define MSACSR_NX_MASK  (1 << MSACSR_NX)
 466 #define MSACSR_CEF      2
 467 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
 468 #define MSACSR_RM       0
 469 #define MSACSR_RM_MASK  (0x3 << MSACSR_RM)
 470 #define MSACSR_MASK     (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
 471         MSACSR_FS_MASK)
 472
 473     float_status msa_fp_status;
 474
 475     /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
 476     uint64_t mmr[32];
 477
 478 #define NUMBER_OF_MXU_REGISTERS 16
 479     target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
 480     target_ulong mxu_cr;
 481 #define MXU_CR_LC       31
 482 #define MXU_CR_RC       30
 483 #define MXU_CR_BIAS     2
 484 #define MXU_CR_RD_EN    1
 485 #define MXU_CR_MXU_EN   0
 486
 487 };
 488
 489 struct MIPSITUState;
 490 typedef struct CPUMIPSState CPUMIPSState;
 491 struct CPUMIPSState {
 492     TCState active_tc;
 493     CPUMIPSFPUContext active_fpu;
 494
 495     uint32_t current_tc;
 496     uint32_t current_fpu;
 497
 498     uint32_t SEGBITS;
 499     uint32_t PABITS;
 500 #if defined(TARGET_MIPS64)
 501 # define PABITS_BASE 36
 502 #else
 503 # define PABITS_BASE 32
 504 #endif
 505     target_ulong SEGMask;
 506     uint64_t PAMask;
 507 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
 508
 509     int32_t msair;
 510 #define MSAIR_ProcID    8
 511 #define MSAIR_Rev       0
 512
 513 /*
 514  * CP0 Register 0
 515  */
 516     int32_t CP0_Index;
 517     /* CP0_MVP* are per MVP registers. */
 518     int32_t CP0_VPControl;
 519 #define CP0VPCtl_DIS    0
 520 /*
 521  * CP0 Register 1
 522  */
 523     int32_t CP0_Random;
 524     int32_t CP0_VPEControl;
 525 #define CP0VPECo_YSI    21
 526 #define CP0VPECo_GSI    20
 527 #define CP0VPECo_EXCPT  16
 528 #define CP0VPECo_TE     15
 529 #define CP0VPECo_TargTC 0
 530     int32_t CP0_VPEConf0;
 531 #define CP0VPEC0_M      31
 532 #define CP0VPEC0_XTC    21
 533 #define CP0VPEC0_TCS    19
 534 #define CP0VPEC0_SCS    18
 535 #define CP0VPEC0_DSC    17
 536 #define CP0VPEC0_ICS    16
 537 #define CP0VPEC0_MVP    1
 538 #define CP0VPEC0_VPA    0
 539     int32_t CP0_VPEConf1;
 540 #define CP0VPEC1_NCX    20
 541 #define CP0VPEC1_NCP2   10
 542 #define CP0VPEC1_NCP1   0
 543     target_ulong CP0_YQMask;
 544     target_ulong CP0_VPESchedule;
 545     target_ulong CP0_VPEScheFBack;
 546     int32_t CP0_VPEOpt;
 547 #define CP0VPEOpt_IWX7  15
 548 #define CP0VPEOpt_IWX6  14
 549 #define CP0VPEOpt_IWX5  13
 550 #define CP0VPEOpt_IWX4  12
 551 #define CP0VPEOpt_IWX3  11
 552 #define CP0VPEOpt_IWX2  10
 553 #define CP0VPEOpt_IWX1  9
 554 #define CP0VPEOpt_IWX0  8
 555 #define CP0VPEOpt_DWX7  7
 556 #define CP0VPEOpt_DWX6  6
 557 #define CP0VPEOpt_DWX5  5
 558 #define CP0VPEOpt_DWX4  4
 559 #define CP0VPEOpt_DWX3  3
 560 #define CP0VPEOpt_DWX2  2
 561 #define CP0VPEOpt_DWX1  1
 562 #define CP0VPEOpt_DWX0  0
 563 /*
 564  * CP0 Register 2
 565  */
 566     uint64_t CP0_EntryLo0;
 567 /*
 568  * CP0 Register 3
 569  */
 570     uint64_t CP0_EntryLo1;
 571 #if defined(TARGET_MIPS64)
 572 # define CP0EnLo_RI 63
 573 # define CP0EnLo_XI 62
 574 #else
 575 # define CP0EnLo_RI 31
 576 # define CP0EnLo_XI 30
 577 #endif
 578     int32_t CP0_GlobalNumber;
 579 #define CP0GN_VPId 0
 580 /*
 581  * CP0 Register 4
 582  */
 583     target_ulong CP0_Context;
 584     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
 585     int32_t CP0_MemoryMapID;
 586 /*
 587  * CP0 Register 5
 588  */
 589     int32_t CP0_PageMask;
 590     int32_t CP0_PageGrain_rw_bitmask;
 591     int32_t CP0_PageGrain;
 592 #define CP0PG_RIE 31
 593 #define CP0PG_XIE 30
 594 #define CP0PG_ELPA 29
 595 #define CP0PG_IEC 27
 596     target_ulong CP0_SegCtl0;
 597     target_ulong CP0_SegCtl1;
 598     target_ulong CP0_SegCtl2;
 599 #define CP0SC_PA        9
 600 #define CP0SC_PA_MASK   (0x7FULL << CP0SC_PA)
 601 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
 602 #define CP0SC_AM        4
 603 #define CP0SC_AM_MASK   (0x7ULL << CP0SC_AM)
 604 #define CP0SC_AM_UK     0ULL
 605 #define CP0SC_AM_MK     1ULL
 606 #define CP0SC_AM_MSK    2ULL
 607 #define CP0SC_AM_MUSK   3ULL
 608 #define CP0SC_AM_MUSUK  4ULL
 609 #define CP0SC_AM_USK    5ULL
 610 #define CP0SC_AM_UUSK   7ULL
 611 #define CP0SC_EU        3
 612 #define CP0SC_EU_MASK   (1ULL << CP0SC_EU)
 613 #define CP0SC_C         0
 614 #define CP0SC_C_MASK    (0x7ULL << CP0SC_C)
 615 #define CP0SC_MASK      (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 616                          CP0SC_PA_MASK)
 617 #define CP0SC_1GMASK    (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
 618                          CP0SC_PA_1GMASK)
 619 #define CP0SC0_MASK     (CP0SC_MASK | (CP0SC_MASK << 16))
 620 #define CP0SC1_XAM      59
 621 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
 622 #define CP0SC1_MASK     (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
 623 #define CP0SC2_XR       56
 624 #define CP0SC2_XR_MASK  (0xFFULL << CP0SC2_XR)
 625 #define CP0SC2_MASK     (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
 626     target_ulong CP0_PWBase;
 627     target_ulong CP0_PWField;
 628 #if defined(TARGET_MIPS64)
 629 #define CP0PF_BDI  32    /* 37..32 */
 630 #define CP0PF_GDI  24    /* 29..24 */
 631 #define CP0PF_UDI  18    /* 23..18 */
 632 #define CP0PF_MDI  12    /* 17..12 */
 633 #define CP0PF_PTI  6     /* 11..6  */
 634 #define CP0PF_PTEI 0     /*  5..0  */
 635 #else
 636 #define CP0PF_GDW  24    /* 29..24 */
 637 #define CP0PF_UDW  18    /* 23..18 */
 638 #define CP0PF_MDW  12    /* 17..12 */
 639 #define CP0PF_PTW  6     /* 11..6  */
 640 #define CP0PF_PTEW 0     /*  5..0  */
 641 #endif
 642     target_ulong CP0_PWSize;
 643 #if defined(TARGET_MIPS64)
 644 #define CP0PS_BDW  32    /* 37..32 */
 645 #endif
 646 #define CP0PS_PS   30
 647 #define CP0PS_GDW  24    /* 29..24 */
 648 #define CP0PS_UDW  18    /* 23..18 */
 649 #define CP0PS_MDW  12    /* 17..12 */
 650 #define CP0PS_PTW  6     /* 11..6  */
 651 #define CP0PS_PTEW 0     /*  5..0  */
 652 /*
 653  * CP0 Register 6
 654  */
 655     int32_t CP0_Wired;
 656     int32_t CP0_PWCtl;
 657 #define CP0PC_PWEN      31
 658 #if defined(TARGET_MIPS64)
 659 #define CP0PC_PWDIREXT  30
 660 #define CP0PC_XK        28
 661 #define CP0PC_XS        27
 662 #define CP0PC_XU        26
 663 #endif
 664 #define CP0PC_DPH       7
 665 #define CP0PC_HUGEPG    6
 666 #define CP0PC_PSN       0     /*  5..0  */
 667     int32_t CP0_SRSConf0_rw_bitmask;
 668     int32_t CP0_SRSConf0;
 669 #define CP0SRSC0_M      31
 670 #define CP0SRSC0_SRS3   20
 671 #define CP0SRSC0_SRS2   10
 672 #define CP0SRSC0_SRS1   0
 673     int32_t CP0_SRSConf1_rw_bitmask;
 674     int32_t CP0_SRSConf1;
 675 #define CP0SRSC1_M      31
 676 #define CP0SRSC1_SRS6   20
 677 #define CP0SRSC1_SRS5   10
 678 #define CP0SRSC1_SRS4   0
 679     int32_t CP0_SRSConf2_rw_bitmask;
 680     int32_t CP0_SRSConf2;
 681 #define CP0SRSC2_M      31
 682 #define CP0SRSC2_SRS9   20
 683 #define CP0SRSC2_SRS8   10
 684 #define CP0SRSC2_SRS7   0
 685     int32_t CP0_SRSConf3_rw_bitmask;
 686     int32_t CP0_SRSConf3;
 687 #define CP0SRSC3_M      31
 688 #define CP0SRSC3_SRS12  20
 689 #define CP0SRSC3_SRS11  10
 690 #define CP0SRSC3_SRS10  0
 691     int32_t CP0_SRSConf4_rw_bitmask;
 692     int32_t CP0_SRSConf4;
 693 #define CP0SRSC4_SRS15  20
 694 #define CP0SRSC4_SRS14  10
 695 #define CP0SRSC4_SRS13  0
 696 /*
 697  * CP0 Register 7
 698  */
 699     int32_t CP0_HWREna;
 700 /*
 701  * CP0 Register 8
 702  */
 703     target_ulong CP0_BadVAddr;
 704     uint32_t CP0_BadInstr;
 705     uint32_t CP0_BadInstrP;
 706     uint32_t CP0_BadInstrX;
 707 /*
 708  * CP0 Register 9
 709  */
 710     int32_t CP0_Count;
 711     uint32_t CP0_SAARI;
 712 #define CP0SAARI_TARGET 0    /*  5..0  */
 713     uint64_t CP0_SAAR[2];
 714 #define CP0SAAR_BASE    12   /* 43..12 */
 715 #define CP0SAAR_SIZE    1    /*  5..1  */
 716 #define CP0SAAR_EN      0
 717 /*
 718  * CP0 Register 10
 719  */
 720     target_ulong CP0_EntryHi;
 721 #define CP0EnHi_EHINV 10
 722     target_ulong CP0_EntryHi_ASID_mask;
 723 /*
 724  * CP0 Register 11
 725  */
 726     int32_t CP0_Compare;
 727 /*
 728  * CP0 Register 12
 729  */
 730     int32_t CP0_Status;
 731 #define CP0St_CU3   31
 732 #define CP0St_CU2   30
 733 #define CP0St_CU1   29
 734 #define CP0St_CU0   28
 735 #define CP0St_RP    27
 736 #define CP0St_FR    26
 737 #define CP0St_RE    25
 738 #define CP0St_MX    24
 739 #define CP0St_PX    23
 740 #define CP0St_BEV   22
 741 #define CP0St_TS    21
 742 #define CP0St_SR    20
 743 #define CP0St_NMI   19
 744 #define CP0St_IM    8
 745 #define CP0St_KX    7
 746 #define CP0St_SX    6
 747 #define CP0St_UX    5
 748 #define CP0St_KSU   3
 749 #define CP0St_ERL   2
 750 #define CP0St_EXL   1
 751 #define CP0St_IE    0
 752     int32_t CP0_IntCtl;
 753 #define CP0IntCtl_IPTI 29
 754 #define CP0IntCtl_IPPCI 26
 755 #define CP0IntCtl_VS 5
 756     int32_t CP0_SRSCtl;
 757 #define CP0SRSCtl_HSS 26
 758 #define CP0SRSCtl_EICSS 18
 759 #define CP0SRSCtl_ESS 12
 760 #define CP0SRSCtl_PSS 6
 761 #define CP0SRSCtl_CSS 0
 762     int32_t CP0_SRSMap;
 763 #define CP0SRSMap_SSV7 28
 764 #define CP0SRSMap_SSV6 24
 765 #define CP0SRSMap_SSV5 20
 766 #define CP0SRSMap_SSV4 16
 767 #define CP0SRSMap_SSV3 12
 768 #define CP0SRSMap_SSV2 8
 769 #define CP0SRSMap_SSV1 4
 770 #define CP0SRSMap_SSV0 0
 771 /*
 772  * CP0 Register 13
 773  */
 774     int32_t CP0_Cause;
 775 #define CP0Ca_BD   31
 776 #define CP0Ca_TI   30
 777 #define CP0Ca_CE   28
 778 #define CP0Ca_DC   27
 779 #define CP0Ca_PCI  26
 780 #define CP0Ca_IV   23
 781 #define CP0Ca_WP   22
 782 #define CP0Ca_IP    8
 783 #define CP0Ca_IP_mask 0x0000FF00
 784 #define CP0Ca_EC    2
 785 /*
 786  * CP0 Register 14
 787  */
 788     target_ulong CP0_EPC;
 789 /*
 790  * CP0 Register 15
 791  */
 792     int32_t CP0_PRid;
 793     target_ulong CP0_EBase;
 794     target_ulong CP0_EBaseWG_rw_bitmask;
 795 #define CP0EBase_WG 11
 796     target_ulong CP0_CMGCRBase;
 797 /*
 798  * CP0 Register 16
 799  */
 800     int32_t CP0_Config0;
 801 #define CP0C0_M    31
 802 #define CP0C0_K23  28    /* 30..28 */
 803 #define CP0C0_KU   25    /* 27..25 */
 804 #define CP0C0_MDU  20
 805 #define CP0C0_MM   18
 806 #define CP0C0_BM   16
 807 #define CP0C0_Impl 16    /* 24..16 */
 808 #define CP0C0_BE   15
 809 #define CP0C0_AT   13    /* 14..13 */
 810 #define CP0C0_AR   10    /* 12..10 */
 811 #define CP0C0_MT   7     /*  9..7  */
 812 #define CP0C0_VI   3
 813 #define CP0C0_K0   0     /*  2..0  */
 814     int32_t CP0_Config1;
 815 #define CP0C1_M    31
 816 #define CP0C1_MMU  25    /* 30..25 */
 817 #define CP0C1_IS   22    /* 24..22 */
 818 #define CP0C1_IL   19    /* 21..19 */
 819 #define CP0C1_IA   16    /* 18..16 */
 820 #define CP0C1_DS   13    /* 15..13 */
 821 #define CP0C1_DL   10    /* 12..10 */
 822 #define CP0C1_DA   7     /*  9..7  */
 823 #define CP0C1_C2   6
 824 #define CP0C1_MD   5
 825 #define CP0C1_PC   4
 826 #define CP0C1_WR   3
 827 #define CP0C1_CA   2
 828 #define CP0C1_EP   1
 829 #define CP0C1_FP   0
 830     int32_t CP0_Config2;
 831 #define CP0C2_M    31
 832 #define CP0C2_TU   28    /* 30..28 */
 833 #define CP0C2_TS   24    /* 27..24 */
 834 #define CP0C2_TL   20    /* 23..20 */
 835 #define CP0C2_TA   16    /* 19..16 */
 836 #define CP0C2_SU   12    /* 15..12 */
 837 #define CP0C2_SS   8     /* 11..8  */
 838 #define CP0C2_SL   4     /*  7..4  */
 839 #define CP0C2_SA   0     /*  3..0  */
 840     int32_t CP0_Config3;
 841 #define CP0C3_M            31
 842 #define CP0C3_BPG          30
 843 #define CP0C3_CMGCR        29
 844 #define CP0C3_MSAP         28
 845 #define CP0C3_BP           27
 846 #define CP0C3_BI           26
 847 #define CP0C3_SC           25
 848 #define CP0C3_PW           24
 849 #define CP0C3_VZ           23
 850 #define CP0C3_IPLV         21    /* 22..21 */
 851 #define CP0C3_MMAR         18    /* 20..18 */
 852 #define CP0C3_MCU          17
 853 #define CP0C3_ISA_ON_EXC   16
 854 #define CP0C3_ISA          14    /* 15..14 */
 855 #define CP0C3_ULRI         13
 856 #define CP0C3_RXI          12
 857 #define CP0C3_DSP2P        11
 858 #define CP0C3_DSPP         10
 859 #define CP0C3_CTXTC        9
 860 #define CP0C3_ITL          8
 861 #define CP0C3_LPA          7
 862 #define CP0C3_VEIC         6
 863 #define CP0C3_VInt         5
 864 #define CP0C3_SP           4
 865 #define CP0C3_CDMM         3
 866 #define CP0C3_MT           2
 867 #define CP0C3_SM           1
 868 #define CP0C3_TL           0
 869     int32_t CP0_Config4;
 870     int32_t CP0_Config4_rw_bitmask;
 871 #define CP0C4_M            31
 872 #define CP0C4_IE           29    /* 30..29 */
 873 #define CP0C4_AE           28
 874 #define CP0C4_VTLBSizeExt  24    /* 27..24 */
 875 #define CP0C4_KScrExist    16
 876 #define CP0C4_MMUExtDef    14
 877 #define CP0C4_FTLBPageSize 8     /* 12..8  */
 878 /* bit layout if MMUExtDef=1 */
 879 #define CP0C4_MMUSizeExt   0     /*  7..0  */
 880 /* bit layout if MMUExtDef=2 */
 881 #define CP0C4_FTLBWays     4     /*  7..4  */
 882 #define CP0C4_FTLBSets     0     /*  3..0  */
 883     int32_t CP0_Config5;
 884     int32_t CP0_Config5_rw_bitmask;
 885 #define CP0C5_M            31
 886 #define CP0C5_K            30
 887 #define CP0C5_CV           29
 888 #define CP0C5_EVA          28
 889 #define CP0C5_MSAEn        27
 890 #define CP0C5_PMJ          23    /* 25..23 */
 891 #define CP0C5_WR2          22
 892 #define CP0C5_NMS          21
 893 #define CP0C5_ULS          20
 894 #define CP0C5_XPA          19
 895 #define CP0C5_CRCP         18
 896 #define CP0C5_MI           17
 897 #define CP0C5_GI           15    /* 16..15 */
 898 #define CP0C5_CA2          14
 899 #define CP0C5_XNP          13
 900 #define CP0C5_DEC          11
 901 #define CP0C5_L2C          10
 902 #define CP0C5_UFE          9
 903 #define CP0C5_FRE          8
 904 #define CP0C5_VP           7
 905 #define CP0C5_SBRI         6
 906 #define CP0C5_MVH          5
 907 #define CP0C5_LLB          4
 908 #define CP0C5_MRP          3
 909 #define CP0C5_UFR          2
 910 #define CP0C5_NFExists     0
 911     int32_t CP0_Config6;
 912     int32_t CP0_Config7;
 913     uint64_t CP0_LLAddr;
 914     uint64_t CP0_MAAR[MIPS_MAAR_MAX];
 915     int32_t CP0_MAARI;
 916     /* XXX: Maybe make LLAddr per-TC? */
 917 /*
 918  * CP0 Register 17
 919  */
 920     target_ulong lladdr; /* LL virtual address compared against SC */
 921     target_ulong llval;
 922     uint64_t llval_wp;
 923     uint32_t llnewval_wp;
 924     uint64_t CP0_LLAddr_rw_bitmask;
 925     int CP0_LLAddr_shift;
 926 /*
 927  * CP0 Register 18
 928  */
 929     target_ulong CP0_WatchLo[8];
 930 /*
 931  * CP0 Register 19
 932  */
 933     int32_t CP0_WatchHi[8];
 934 #define CP0WH_ASID 16
 935 /*
 936  * CP0 Register 20
 937  */
 938     target_ulong CP0_XContext;
 939     int32_t CP0_Framemask;
 940 /*
 941  * CP0 Register 23
 942  */
 943     int32_t CP0_Debug;
 944 #define CP0DB_DBD  31
 945 #define CP0DB_DM   30
 946 #define CP0DB_LSNM 28
 947 #define CP0DB_Doze 27
 948 #define CP0DB_Halt 26
 949 #define CP0DB_CNT  25
 950 #define CP0DB_IBEP 24
 951 #define CP0DB_DBEP 21
 952 #define CP0DB_IEXI 20
 953 #define CP0DB_VER  15
 954 #define CP0DB_DEC  10
 955 #define CP0DB_SSt  8
 956 #define CP0DB_DINT 5
 957 #define CP0DB_DIB  4
 958 #define CP0DB_DDBS 3
 959 #define CP0DB_DDBL 2
 960 #define CP0DB_DBp  1
 961 #define CP0DB_DSS  0
 962 /*
 963  * CP0 Register 24
 964  */
 965     target_ulong CP0_DEPC;
 966 /*
 967  * CP0 Register 25
 968  */
 969     int32_t CP0_Performance0;
 970 /*
 971  * CP0 Register 26
 972  */
 973     int32_t CP0_ErrCtl;
 974 #define CP0EC_WST 29
 975 #define CP0EC_SPR 28
 976 #define CP0EC_ITC 26
 977 /*
 978  * CP0 Register 28
 979  */
 980     uint64_t CP0_TagLo;
 981     int32_t CP0_DataLo;
 982 /*
 983  * CP0 Register 29
 984  */
 985     int32_t CP0_TagHi;
 986     int32_t CP0_DataHi;
 987 /*
 988  * CP0 Register 30
 989  */
 990     target_ulong CP0_ErrorEPC;
 991 /*
 992  * CP0 Register 31
 993  */
 994     int32_t CP0_DESAVE;
 995
 996     /* We waste some space so we can handle shadow registers like TCs. */
 997     TCState tcs[MIPS_SHADOW_SET_MAX];
 998     CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
 999     /* QEMU */
1000     int error_code;
1001 #define EXCP_TLB_NOMATCH   0x1
1002 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
1003     uint32_t hflags;    /* CPU State */
1004     /* TMASK defines different execution modes */
1005 #define MIPS_HFLAG_TMASK  0x1F5807FF
1006 #define MIPS_HFLAG_MODE   0x00007 /* execution modes                    */
1007     /*
1008      * The KSU flags must be the lowest bits in hflags. The flag order
1009      * must be the same as defined for CP0 Status. This allows to use
1010      * the bits as the value of mmu_idx.
1011      */
1012 #define MIPS_HFLAG_KSU    0x00003 /* kernel/supervisor/user mode mask   */
1013 #define MIPS_HFLAG_UM     0x00002 /* user mode flag                     */
1014 #define MIPS_HFLAG_SM     0x00001 /* supervisor mode flag               */
1015 #define MIPS_HFLAG_KM     0x00000 /* kernel mode flag                   */
1016 #define MIPS_HFLAG_DM     0x00004 /* Debug mode                         */
1017 #define MIPS_HFLAG_64     0x00008 /* 64-bit instructions enabled        */
1018 #define MIPS_HFLAG_CP0    0x00010 /* CP0 enabled                        */
1019 #define MIPS_HFLAG_FPU    0x00020 /* FPU enabled                        */
1020 #define MIPS_HFLAG_F64    0x00040 /* 64-bit FPU enabled                 */
1021     /*
1022      * True if the MIPS IV COP1X instructions can be used.  This also
1023      * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
1024      * and RSQRT.D.
1025      */
1026 #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
1027 #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
1028 #define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
1029 #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
1030 #define MIPS_HFLAG_M16_SHIFT 10
1031     /*
1032      * If translation is interrupted between the branch instruction and
1033      * the delay slot, record what type of branch it is so that we can
1034      * resume translation properly.  It might be possible to reduce
1035      * this from three bits to two.
1036      */
1037 #define MIPS_HFLAG_BMASK_BASE  0x803800
1038 #define MIPS_HFLAG_B      0x00800 /* Unconditional branch               */
1039 #define MIPS_HFLAG_BC     0x01000 /* Conditional branch                 */
1040 #define MIPS_HFLAG_BL     0x01800 /* Likely branch                      */
1041 #define MIPS_HFLAG_BR     0x02000 /* branch to register (can't link TB) */
1042     /* Extra flags about the current pending branch.  */
1043 #define MIPS_HFLAG_BMASK_EXT 0x7C000
1044 #define MIPS_HFLAG_B16    0x04000 /* branch instruction was 16 bits     */
1045 #define MIPS_HFLAG_BDS16  0x08000 /* branch requires 16-bit delay slot  */
1046 #define MIPS_HFLAG_BDS32  0x10000 /* branch requires 32-bit delay slot  */
1047 #define MIPS_HFLAG_BDS_STRICT  0x20000 /* Strict delay slot size */
1048 #define MIPS_HFLAG_BX     0x40000 /* branch exchanges execution mode    */
1049 #define MIPS_HFLAG_BMASK  (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
1050     /* MIPS DSP resources access. */
1051 #define MIPS_HFLAG_DSP    0x080000   /* Enable access to DSP resources.    */
1052 #define MIPS_HFLAG_DSP_R2 0x100000   /* Enable access to DSP R2 resources. */
1053 #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
1054     /* Extra flag about HWREna register. */
1055 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
1056 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
1057 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot                   */
1058 #define MIPS_HFLAG_MSA   0x1000000
1059 #define MIPS_HFLAG_FRE   0x2000000 /* FRE enabled */
1060 #define MIPS_HFLAG_ELPA  0x4000000
1061 #define MIPS_HFLAG_ITC_CACHE  0x8000000 /* CACHE instr. operates on ITC tag */
1062 #define MIPS_HFLAG_ERL   0x10000000 /* error level flag */
1063     target_ulong btarget;        /* Jump / branch target               */
1064     target_ulong bcond;          /* Branch condition (if needed)       */
1065
1066     int SYNCI_Step; /* Address step size for SYNCI */
1067     int CCRes; /* Cycle count resolution/divisor */
1068     uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
1069     uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
1070     uint64_t insn_flags; /* Supported instruction set */
1071     int saarp;
1072
1073     /* Fields up to this point are cleared by a CPU reset */
1074     struct {} end_reset_fields;
1075
1076     /* Fields from here on are preserved across CPU reset. */
1077     CPUMIPSMVPContext *mvp;
1078 #if !defined(CONFIG_USER_ONLY)
1079     CPUMIPSTLBContext *tlb;
1080 #endif
1081
1082     const mips_def_t *cpu_model;
1083     void *irq[8];
1084     QEMUTimer *timer; /* Internal timer */
1085     struct MIPSITUState *itu;
1086     MemoryRegion *itc_tag; /* ITC Configuration Tags */
1087     target_ulong exception_base; /* ExceptionBase input to the core */
1088 };
1089
1090 /**
1091  * MIPSCPU:
1092  * @env: #CPUMIPSState
1093  *
1094  * A MIPS CPU.
1095  */
1096 struct MIPSCPU {
1097     /*< private >*/
1098     CPUState parent_obj;
1099     /*< public >*/
1100
1101     CPUNegativeOffsetState neg;
1102     CPUMIPSState env;
1103 };
1104
1105
1106 void mips_cpu_list(void);
1107
1108 #define cpu_signal_handler cpu_mips_signal_handler
1109 #define cpu_list mips_cpu_list
1110
1111 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
1112 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
1113
1114 /*
1115  * MMU modes definitions. We carefully match the indices with our
1116  * hflags layout.
1117  */
1118 #define MMU_MODE0_SUFFIX _kernel
1119 #define MMU_MODE1_SUFFIX _super
1120 #define MMU_MODE2_SUFFIX _user
1121 #define MMU_MODE3_SUFFIX _error
1122 #define MMU_USER_IDX 2
1123
1124 static inline int hflags_mmu_index(uint32_t hflags)
1125 {
1126     if (hflags & MIPS_HFLAG_ERL) {
1127         return 3; /* ERL */
1128     } else {
1129         return hflags & MIPS_HFLAG_KSU;
1130     }
1131 }
1132
1133 static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
1134 {
1135     return hflags_mmu_index(env->hflags);
1136 }
1137
1138 typedef CPUMIPSState CPUArchState;
1139 typedef MIPSCPU ArchCPU;
1140
1141 #include "exec/cpu-all.h"
1142
1143 /*
1144  * Memory access type :
1145  * may be needed for precise access rights control and precise exceptions.
1146  */
1147 enum {
1148     /* 1 bit to define user level / supervisor access */
1149     ACCESS_USER  = 0x00,
1150     ACCESS_SUPER = 0x01,
1151     /* 1 bit to indicate direction */
1152     ACCESS_STORE = 0x02,
1153     /* Type of instruction that generated the access */
1154     ACCESS_CODE  = 0x10, /* Code fetch access                */
1155     ACCESS_INT   = 0x20, /* Integer load/store access        */
1156     ACCESS_FLOAT = 0x30, /* floating point load/store access */
1157 };
1158
1159 /* Exceptions */
1160 enum {
1161     EXCP_NONE          = -1,
1162     EXCP_RESET         = 0,
1163     EXCP_SRESET,
1164     EXCP_DSS,
1165     EXCP_DINT,
1166     EXCP_DDBL,
1167     EXCP_DDBS,
1168     EXCP_NMI,
1169     EXCP_MCHECK,
1170     EXCP_EXT_INTERRUPT, /* 8 */
1171     EXCP_DFWATCH,
1172     EXCP_DIB,
1173     EXCP_IWATCH,
1174     EXCP_AdEL,
1175     EXCP_AdES,
1176     EXCP_TLBF,
1177     EXCP_IBE,
1178     EXCP_DBp, /* 16 */
1179     EXCP_SYSCALL,
1180     EXCP_BREAK,
1181     EXCP_CpU,
1182     EXCP_RI,
1183     EXCP_OVERFLOW,
1184     EXCP_TRAP,
1185     EXCP_FPE,
1186     EXCP_DWATCH, /* 24 */
1187     EXCP_LTLBL,
1188     EXCP_TLBL,
1189     EXCP_TLBS,
1190     EXCP_DBE,
1191     EXCP_THREAD,
1192     EXCP_MDMX,
1193     EXCP_C2E,
1194     EXCP_CACHE, /* 32 */
1195     EXCP_DSPDIS,
1196     EXCP_MSADIS,
1197     EXCP_MSAFPE,
1198     EXCP_TLBXI,
1199     EXCP_TLBRI,
1200
1201     EXCP_LAST = EXCP_TLBRI,
1202 };
1203
1204 /*
1205  * This is an internally generated WAKE request line.
1206  * It is driven by the CPU itself. Raised when the MT
1207  * block wants to wake a VPE from an inactive state and
1208  * cleared when VPE goes from active to inactive.
1209  */
1210 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
1211
1212 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
1213
1214 #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU
1215 #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
1216 #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
1217
1218 bool cpu_supports_cps_smp(const char *cpu_type);
1219 bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
1220 void cpu_set_exception_base(int vp_index, target_ulong address);
1221
1222 /* mips_int.c */
1223 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
1224
1225 /* mips_itu.c */
1226 void itc_reconfigure(struct MIPSITUState *tag);
1227
1228 /* helper.c */
1229 target_ulong exception_resume_pc(CPUMIPSState *env);
1230
1231 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
1232                                         target_ulong *cs_base, uint32_t *flags)
1233 {
1234     *pc = env->active_tc.PC;
1235     *cs_base = 0;
1236     *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
1237                             MIPS_HFLAG_HWRENA_ULR);
1238 }
1239
1240 #endif /* MIPS_CPU_H */