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hw/timer: Add NPCM7xx Timer device model
[qemu/ar7.git] / hw / sparc / sun4m.c
blob947b69d1597de2c0a16b9ac0486c51d9e3a07911
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qapi/error.h"
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "hw/sysbus.h"
31 #include "qemu/error-report.h"
32 #include "qemu/timer.h"
33 #include "hw/sparc/sun4m_iommu.h"
34 #include "hw/rtc/m48t59.h"
35 #include "migration/vmstate.h"
36 #include "hw/sparc/sparc32_dma.h"
37 #include "hw/block/fdc.h"
38 #include "sysemu/reset.h"
39 #include "sysemu/runstate.h"
40 #include "sysemu/sysemu.h"
41 #include "net/net.h"
42 #include "hw/boards.h"
43 #include "hw/scsi/esp.h"
44 #include "hw/nvram/sun_nvram.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/nvram/chrp_nvram.h"
47 #include "hw/nvram/fw_cfg.h"
48 #include "hw/char/escc.h"
49 #include "hw/misc/empty_slot.h"
50 #include "hw/misc/unimp.h"
51 #include "hw/irq.h"
52 #include "hw/loader.h"
53 #include "elf.h"
54 #include "trace.h"
55 #include "qom/object.h"
56
57 /*
58 * Sun4m architecture was used in the following machines:
59 *
60 * SPARCserver 6xxMP/xx
61 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
62 * SPARCclassic X (4/10)
63 * SPARCstation LX/ZX (4/30)
64 * SPARCstation Voyager
65 * SPARCstation 10/xx, SPARCserver 10/xx
66 * SPARCstation 5, SPARCserver 5
67 * SPARCstation 20/xx, SPARCserver 20
68 * SPARCstation 4
69 *
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
71 */
72
73 #define KERNEL_LOAD_ADDR 0x00004000
74 #define CMDLINE_ADDR 0x007ff000
75 #define INITRD_LOAD_ADDR 0x00800000
76 #define PROM_SIZE_MAX (1 * MiB)
77 #define PROM_VADDR 0xffd00000
78 #define PROM_FILENAME "openbios-sparc32"
79 #define CFG_ADDR 0xd00000510ULL
80 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
83
84 #define MAX_CPUS 16
85 #define MAX_PILS 16
86 #define MAX_VSIMMS 4
87
88 #define ESCC_CLOCK 4915200
89
90 struct sun4m_hwdef {
91 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
92 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
93 hwaddr serial_base, fd_base;
94 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
95 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
96 hwaddr bpp_base, dbri_base, sx_base;
97 struct {
98 hwaddr reg_base, vram_base;
99 } vsimm[MAX_VSIMMS];
100 hwaddr ecc_base;
101 uint64_t max_mem;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 const char *fw_cfg_arch_key_name(uint16_t key)
109 {
110 static const struct {
111 uint16_t key;
112 const char *name;
113 } fw_cfg_arch_wellknown_keys[] = {
114 {FW_CFG_SUN4M_DEPTH, "depth"},
115 {FW_CFG_SUN4M_WIDTH, "width"},
116 {FW_CFG_SUN4M_HEIGHT, "height"},
117 };
118
119 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
120 if (fw_cfg_arch_wellknown_keys[i].key == key) {
121 return fw_cfg_arch_wellknown_keys[i].name;
122 }
123 }
124 return NULL;
125 }
126
127 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
128 Error **errp)
129 {
130 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
131 }
132
133 static void nvram_init(Nvram *nvram, uint8_t *macaddr,
134 const char *cmdline, const char *boot_devices,
135 ram_addr_t RAM_size, uint32_t kernel_size,
136 int width, int height, int depth,
137 int nvram_machine_id, const char *arch)
138 {
139 unsigned int i;
140 int sysp_end;
141 uint8_t image[0x1ff0];
142 NvramClass *k = NVRAM_GET_CLASS(nvram);
143
144 memset(image, '\0', sizeof(image));
145
146 /* OpenBIOS nvram variables partition */
147 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
148
149 /* Free space partition */
150 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
151
152 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
153 nvram_machine_id);
154
155 for (i = 0; i < sizeof(image); i++) {
156 (k->write)(nvram, i, image[i]);
157 }
158 }
159
160 void cpu_check_irqs(CPUSPARCState *env)
161 {
162 CPUState *cs;
163
164 /* We should be holding the BQL before we mess with IRQs */
165 g_assert(qemu_mutex_iothread_locked());
166
167 if (env->pil_in && (env->interrupt_index == 0 ||
168 (env->interrupt_index & ~15) == TT_EXTINT)) {
169 unsigned int i;
170
171 for (i = 15; i > 0; i--) {
172 if (env->pil_in & (1 << i)) {
173 int old_interrupt = env->interrupt_index;
174
175 env->interrupt_index = TT_EXTINT | i;
176 if (old_interrupt != env->interrupt_index) {
177 cs = env_cpu(env);
178 trace_sun4m_cpu_interrupt(i);
179 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
180 }
181 break;
182 }
183 }
184 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
185 cs = env_cpu(env);
186 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
187 env->interrupt_index = 0;
188 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
189 }
190 }
191
192 static void cpu_kick_irq(SPARCCPU *cpu)
193 {
194 CPUSPARCState *env = &cpu->env;
195 CPUState *cs = CPU(cpu);
196
197 cs->halted = 0;
198 cpu_check_irqs(env);
199 qemu_cpu_kick(cs);
200 }
201
202 static void cpu_set_irq(void *opaque, int irq, int level)
203 {
204 SPARCCPU *cpu = opaque;
205 CPUSPARCState *env = &cpu->env;
206
207 if (level) {
208 trace_sun4m_cpu_set_irq_raise(irq);
209 env->pil_in |= 1 << irq;
210 cpu_kick_irq(cpu);
211 } else {
212 trace_sun4m_cpu_set_irq_lower(irq);
213 env->pil_in &= ~(1 << irq);
214 cpu_check_irqs(env);
215 }
216 }
217
218 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
219 {
220 }
221
222 static void sun4m_cpu_reset(void *opaque)
223 {
224 SPARCCPU *cpu = opaque;
225 CPUState *cs = CPU(cpu);
226
227 cpu_reset(cs);
228 }
229
230 static void cpu_halt_signal(void *opaque, int irq, int level)
231 {
232 if (level && current_cpu) {
233 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
234 }
235 }
236
237 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
238 {
239 return addr - 0xf0000000ULL;
240 }
241
242 static unsigned long sun4m_load_kernel(const char *kernel_filename,
243 const char *initrd_filename,
244 ram_addr_t RAM_size,
245 uint32_t *initrd_size)
246 {
247 int linux_boot;
248 unsigned int i;
249 long kernel_size;
250 uint8_t *ptr;
251
252 linux_boot = (kernel_filename != NULL);
253
254 kernel_size = 0;
255 if (linux_boot) {
256 int bswap_needed;
257
258 #ifdef BSWAP_NEEDED
259 bswap_needed = 1;
260 #else
261 bswap_needed = 0;
262 #endif
263 kernel_size = load_elf(kernel_filename, NULL,
264 translate_kernel_address, NULL,
265 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
266 if (kernel_size < 0)
267 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
268 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
269 TARGET_PAGE_SIZE);
270 if (kernel_size < 0)
271 kernel_size = load_image_targphys(kernel_filename,
272 KERNEL_LOAD_ADDR,
273 RAM_size - KERNEL_LOAD_ADDR);
274 if (kernel_size < 0) {
275 error_report("could not load kernel '%s'", kernel_filename);
276 exit(1);
277 }
278
279 /* load initrd */
280 *initrd_size = 0;
281 if (initrd_filename) {
282 *initrd_size = load_image_targphys(initrd_filename,
283 INITRD_LOAD_ADDR,
284 RAM_size - INITRD_LOAD_ADDR);
285 if ((int)*initrd_size < 0) {
286 error_report("could not load initial ram disk '%s'",
287 initrd_filename);
288 exit(1);
289 }
290 }
291 if (*initrd_size > 0) {
292 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
293 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24);
294 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */
295 stl_p(ptr + 16, INITRD_LOAD_ADDR);
296 stl_p(ptr + 20, *initrd_size);
297 break;
298 }
299 }
300 }
301 }
302 return kernel_size;
303 }
304
305 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
306 {
307 DeviceState *dev;
308 SysBusDevice *s;
309
310 dev = qdev_new(TYPE_SUN4M_IOMMU);
311 qdev_prop_set_uint32(dev, "version", version);
312 s = SYS_BUS_DEVICE(dev);
313 sysbus_realize_and_unref(s, &error_fatal);
314 sysbus_connect_irq(s, 0, irq);
315 sysbus_mmio_map(s, 0, addr);
316
317 return s;
318 }
319
320 static void *sparc32_dma_init(hwaddr dma_base,
321 hwaddr esp_base, qemu_irq espdma_irq,
322 hwaddr le_base, qemu_irq ledma_irq)
323 {
324 DeviceState *dma;
325 ESPDMADeviceState *espdma;
326 LEDMADeviceState *ledma;
327 SysBusESPState *esp;
328 SysBusPCNetState *lance;
329
330 dma = qdev_new(TYPE_SPARC32_DMA);
331 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
332 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base);
333
334 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component(
335 OBJECT(dma), "espdma"));
336 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq);
337
338 esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp"));
339 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base);
340 scsi_bus_legacy_handle_cmdline(&esp->esp.bus);
341
342 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component(
343 OBJECT(dma), "ledma"));
344 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq);
345
346 lance = SYSBUS_PCNET(object_resolve_path_component(
347 OBJECT(ledma), "lance"));
348 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base);
349
350 return dma;
351 }
352
353 static DeviceState *slavio_intctl_init(hwaddr addr,
354 hwaddr addrg,
355 qemu_irq **parent_irq)
356 {
357 DeviceState *dev;
358 SysBusDevice *s;
359 unsigned int i, j;
360
361 dev = qdev_new("slavio_intctl");
362
363 s = SYS_BUS_DEVICE(dev);
364 sysbus_realize_and_unref(s, &error_fatal);
365
366 for (i = 0; i < MAX_CPUS; i++) {
367 for (j = 0; j < MAX_PILS; j++) {
368 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
369 }
370 }
371 sysbus_mmio_map(s, 0, addrg);
372 for (i = 0; i < MAX_CPUS; i++) {
373 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
374 }
375
376 return dev;
377 }
378
379 #define SYS_TIMER_OFFSET 0x10000ULL
380 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
381
382 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
383 qemu_irq *cpu_irqs, unsigned int num_cpus)
384 {
385 DeviceState *dev;
386 SysBusDevice *s;
387 unsigned int i;
388
389 dev = qdev_new("slavio_timer");
390 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
391 s = SYS_BUS_DEVICE(dev);
392 sysbus_realize_and_unref(s, &error_fatal);
393 sysbus_connect_irq(s, 0, master_irq);
394 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
395
396 for (i = 0; i < MAX_CPUS; i++) {
397 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
398 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
399 }
400 }
401
402 static qemu_irq slavio_system_powerdown;
403
404 static void slavio_powerdown_req(Notifier *n, void *opaque)
405 {
406 qemu_irq_raise(slavio_system_powerdown);
407 }
408
409 static Notifier slavio_system_powerdown_notifier = {
410 .notify = slavio_powerdown_req
411 };
412
413 #define MISC_LEDS 0x01600000
414 #define MISC_CFG 0x01800000
415 #define MISC_DIAG 0x01a00000
416 #define MISC_MDM 0x01b00000
417 #define MISC_SYS 0x01f00000
418
419 static void slavio_misc_init(hwaddr base,
420 hwaddr aux1_base,
421 hwaddr aux2_base, qemu_irq irq,
422 qemu_irq fdc_tc)
423 {
424 DeviceState *dev;
425 SysBusDevice *s;
426
427 dev = qdev_new("slavio_misc");
428 s = SYS_BUS_DEVICE(dev);
429 sysbus_realize_and_unref(s, &error_fatal);
430 if (base) {
431 /* 8 bit registers */
432 /* Slavio control */
433 sysbus_mmio_map(s, 0, base + MISC_CFG);
434 /* Diagnostics */
435 sysbus_mmio_map(s, 1, base + MISC_DIAG);
436 /* Modem control */
437 sysbus_mmio_map(s, 2, base + MISC_MDM);
438 /* 16 bit registers */
439 /* ss600mp diag LEDs */
440 sysbus_mmio_map(s, 3, base + MISC_LEDS);
441 /* 32 bit registers */
442 /* System control */
443 sysbus_mmio_map(s, 4, base + MISC_SYS);
444 }
445 if (aux1_base) {
446 /* AUX 1 (Misc System Functions) */
447 sysbus_mmio_map(s, 5, aux1_base);
448 }
449 if (aux2_base) {
450 /* AUX 2 (Software Powerdown Control) */
451 sysbus_mmio_map(s, 6, aux2_base);
452 }
453 sysbus_connect_irq(s, 0, irq);
454 sysbus_connect_irq(s, 1, fdc_tc);
455 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
456 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
457 }
458
459 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
460 {
461 DeviceState *dev;
462 SysBusDevice *s;
463
464 dev = qdev_new("eccmemctl");
465 qdev_prop_set_uint32(dev, "version", version);
466 s = SYS_BUS_DEVICE(dev);
467 sysbus_realize_and_unref(s, &error_fatal);
468 sysbus_connect_irq(s, 0, irq);
469 sysbus_mmio_map(s, 0, base);
470 if (version == 0) { // SS-600MP only
471 sysbus_mmio_map(s, 1, base + 0x1000);
472 }
473 }
474
475 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
476 {
477 DeviceState *dev;
478 SysBusDevice *s;
479
480 dev = qdev_new("apc");
481 s = SYS_BUS_DEVICE(dev);
482 sysbus_realize_and_unref(s, &error_fatal);
483 /* Power management (APC) XXX: not a Slavio device */
484 sysbus_mmio_map(s, 0, power_base);
485 sysbus_connect_irq(s, 0, cpu_halt);
486 }
487
488 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
489 int height, int depth)
490 {
491 DeviceState *dev;
492 SysBusDevice *s;
493
494 dev = qdev_new("SUNW,tcx");
495 qdev_prop_set_uint32(dev, "vram_size", vram_size);
496 qdev_prop_set_uint16(dev, "width", width);
497 qdev_prop_set_uint16(dev, "height", height);
498 qdev_prop_set_uint16(dev, "depth", depth);
499 s = SYS_BUS_DEVICE(dev);
500 sysbus_realize_and_unref(s, &error_fatal);
501
502 /* 10/ROM : FCode ROM */
503 sysbus_mmio_map(s, 0, addr);
504 /* 2/STIP : Stipple */
505 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
506 /* 3/BLIT : Blitter */
507 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
508 /* 5/RSTIP : Raw Stipple */
509 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
510 /* 6/RBLIT : Raw Blitter */
511 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
512 /* 7/TEC : Transform Engine */
513 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
514 /* 8/CMAP : DAC */
515 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
516 /* 9/THC : */
517 if (depth == 8) {
518 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
519 } else {
520 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
521 }
522 /* 11/DHC : */
523 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
524 /* 12/ALT : */
525 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
526 /* 0/DFB8 : 8-bit plane */
527 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
528 /* 1/DFB24 : 24bit plane */
529 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
530 /* 4/RDFB32: Raw framebuffer. Control plane */
531 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
532 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */
533 if (depth == 8) {
534 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
535 }
536
537 sysbus_connect_irq(s, 0, irq);
538 }
539
540 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
541 int height, int depth)
542 {
543 DeviceState *dev;
544 SysBusDevice *s;
545
546 dev = qdev_new("cgthree");
547 qdev_prop_set_uint32(dev, "vram-size", vram_size);
548 qdev_prop_set_uint16(dev, "width", width);
549 qdev_prop_set_uint16(dev, "height", height);
550 qdev_prop_set_uint16(dev, "depth", depth);
551 s = SYS_BUS_DEVICE(dev);
552 sysbus_realize_and_unref(s, &error_fatal);
553
554 /* FCode ROM */
555 sysbus_mmio_map(s, 0, addr);
556 /* DAC */
557 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
558 /* 8-bit plane */
559 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
560
561 sysbus_connect_irq(s, 0, irq);
562 }
563
564 /* NCR89C100/MACIO Internal ID register */
565
566 #define TYPE_MACIO_ID_REGISTER "macio_idreg"
567
568 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
569
570 static void idreg_init(hwaddr addr)
571 {
572 DeviceState *dev;
573 SysBusDevice *s;
574
575 dev = qdev_new(TYPE_MACIO_ID_REGISTER);
576 s = SYS_BUS_DEVICE(dev);
577 sysbus_realize_and_unref(s, &error_fatal);
578
579 sysbus_mmio_map(s, 0, addr);
580 address_space_write_rom(&address_space_memory, addr,
581 MEMTXATTRS_UNSPECIFIED,
582 idreg_data, sizeof(idreg_data));
583 }
584
585 typedef struct IDRegState IDRegState;
586 DECLARE_INSTANCE_CHECKER(IDRegState, MACIO_ID_REGISTER,
587 TYPE_MACIO_ID_REGISTER)
588
589 struct IDRegState {
590 SysBusDevice parent_obj;
591
592 MemoryRegion mem;
593 };
594
595 static void idreg_realize(DeviceState *ds, Error **errp)
596 {
597 IDRegState *s = MACIO_ID_REGISTER(ds);
598 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
599 Error *local_err = NULL;
600
601 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg",
602 sizeof(idreg_data), &local_err);
603 if (local_err) {
604 error_propagate(errp, local_err);
605 return;
606 }
607
608 vmstate_register_ram_global(&s->mem);
609 memory_region_set_readonly(&s->mem, true);
610 sysbus_init_mmio(dev, &s->mem);
611 }
612
613 static void idreg_class_init(ObjectClass *oc, void *data)
614 {
615 DeviceClass *dc = DEVICE_CLASS(oc);
616
617 dc->realize = idreg_realize;
618 }
619
620 static const TypeInfo idreg_info = {
621 .name = TYPE_MACIO_ID_REGISTER,
622 .parent = TYPE_SYS_BUS_DEVICE,
623 .instance_size = sizeof(IDRegState),
624 .class_init = idreg_class_init,
625 };
626
627 #define TYPE_TCX_AFX "tcx_afx"
628 typedef struct AFXState AFXState;
629 DECLARE_INSTANCE_CHECKER(AFXState, TCX_AFX,
630 TYPE_TCX_AFX)
631
632 struct AFXState {
633 SysBusDevice parent_obj;
634
635 MemoryRegion mem;
636 };
637
638 /* SS-5 TCX AFX register */
639 static void afx_init(hwaddr addr)
640 {
641 DeviceState *dev;
642 SysBusDevice *s;
643
644 dev = qdev_new(TYPE_TCX_AFX);
645 s = SYS_BUS_DEVICE(dev);
646 sysbus_realize_and_unref(s, &error_fatal);
647
648 sysbus_mmio_map(s, 0, addr);
649 }
650
651 static void afx_realize(DeviceState *ds, Error **errp)
652 {
653 AFXState *s = TCX_AFX(ds);
654 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
655 Error *local_err = NULL;
656
657 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4,
658 &local_err);
659 if (local_err) {
660 error_propagate(errp, local_err);
661 return;
662 }
663
664 vmstate_register_ram_global(&s->mem);
665 sysbus_init_mmio(dev, &s->mem);
666 }
667
668 static void afx_class_init(ObjectClass *oc, void *data)
669 {
670 DeviceClass *dc = DEVICE_CLASS(oc);
671
672 dc->realize = afx_realize;
673 }
674
675 static const TypeInfo afx_info = {
676 .name = TYPE_TCX_AFX,
677 .parent = TYPE_SYS_BUS_DEVICE,
678 .instance_size = sizeof(AFXState),
679 .class_init = afx_class_init,
680 };
681
682 #define TYPE_OPENPROM "openprom"
683 typedef struct PROMState PROMState;
684 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
685 TYPE_OPENPROM)
686
687 struct PROMState {
688 SysBusDevice parent_obj;
689
690 MemoryRegion prom;
691 };
692
693 /* Boot PROM (OpenBIOS) */
694 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
695 {
696 hwaddr *base_addr = (hwaddr *)opaque;
697 return addr + *base_addr - PROM_VADDR;
698 }
699
700 static void prom_init(hwaddr addr, const char *bios_name)
701 {
702 DeviceState *dev;
703 SysBusDevice *s;
704 char *filename;
705 int ret;
706
707 dev = qdev_new(TYPE_OPENPROM);
708 s = SYS_BUS_DEVICE(dev);
709 sysbus_realize_and_unref(s, &error_fatal);
710
711 sysbus_mmio_map(s, 0, addr);
712
713 /* load boot prom */
714 if (bios_name == NULL) {
715 bios_name = PROM_FILENAME;
716 }
717 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
718 if (filename) {
719 ret = load_elf(filename, NULL,
720 translate_prom_address, &addr, NULL,
721 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
722 if (ret < 0 || ret > PROM_SIZE_MAX) {
723 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
724 }
725 g_free(filename);
726 } else {
727 ret = -1;
728 }
729 if (ret < 0 || ret > PROM_SIZE_MAX) {
730 error_report("could not load prom '%s'", bios_name);
731 exit(1);
732 }
733 }
734
735 static void prom_realize(DeviceState *ds, Error **errp)
736 {
737 PROMState *s = OPENPROM(ds);
738 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
739 Error *local_err = NULL;
740
741 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom",
742 PROM_SIZE_MAX, &local_err);
743 if (local_err) {
744 error_propagate(errp, local_err);
745 return;
746 }
747
748 vmstate_register_ram_global(&s->prom);
749 memory_region_set_readonly(&s->prom, true);
750 sysbus_init_mmio(dev, &s->prom);
751 }
752
753 static Property prom_properties[] = {
754 {/* end of property list */},
755 };
756
757 static void prom_class_init(ObjectClass *klass, void *data)
758 {
759 DeviceClass *dc = DEVICE_CLASS(klass);
760
761 device_class_set_props(dc, prom_properties);
762 dc->realize = prom_realize;
763 }
764
765 static const TypeInfo prom_info = {
766 .name = TYPE_OPENPROM,
767 .parent = TYPE_SYS_BUS_DEVICE,
768 .instance_size = sizeof(PROMState),
769 .class_init = prom_class_init,
770 };
771
772 #define TYPE_SUN4M_MEMORY "memory"
773 typedef struct RamDevice RamDevice;
774 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM,
775 TYPE_SUN4M_MEMORY)
776
777 struct RamDevice {
778 SysBusDevice parent_obj;
779 HostMemoryBackend *memdev;
780 };
781
782 /* System RAM */
783 static void ram_realize(DeviceState *dev, Error **errp)
784 {
785 RamDevice *d = SUN4M_RAM(dev);
786 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev);
787
788 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram);
789 }
790
791 static void ram_initfn(Object *obj)
792 {
793 RamDevice *d = SUN4M_RAM(obj);
794 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND,
795 (Object **)&d->memdev,
796 object_property_allow_set_link,
797 OBJ_PROP_LINK_STRONG);
798 object_property_set_description(obj, "memdev", "Set RAM backend"
799 "Valid value is ID of a hostmem backend");
800 }
801
802 static void ram_class_init(ObjectClass *klass, void *data)
803 {
804 DeviceClass *dc = DEVICE_CLASS(klass);
805
806 dc->realize = ram_realize;
807 }
808
809 static const TypeInfo ram_info = {
810 .name = TYPE_SUN4M_MEMORY,
811 .parent = TYPE_SYS_BUS_DEVICE,
812 .instance_size = sizeof(RamDevice),
813 .instance_init = ram_initfn,
814 .class_init = ram_class_init,
815 };
816
817 static void cpu_devinit(const char *cpu_type, unsigned int id,
818 uint64_t prom_addr, qemu_irq **cpu_irqs)
819 {
820 SPARCCPU *cpu;
821 CPUSPARCState *env;
822
823 cpu = SPARC_CPU(object_new(cpu_type));
824 env = &cpu->env;
825
826 cpu_sparc_set_id(env, id);
827 qemu_register_reset(sun4m_cpu_reset, cpu);
828 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0,
829 &error_fatal);
830 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
831 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
832 env->prom_addr = prom_addr;
833 }
834
835 static void dummy_fdc_tc(void *opaque, int irq, int level)
836 {
837 }
838
839 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
840 MachineState *machine)
841 {
842 DeviceState *slavio_intctl;
843 unsigned int i;
844 void *nvram;
845 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS];
846 qemu_irq fdc_tc;
847 unsigned long kernel_size;
848 uint32_t initrd_size;
849 DriveInfo *fd[MAX_FD];
850 FWCfgState *fw_cfg;
851 DeviceState *dev;
852 SysBusDevice *s;
853 unsigned int smp_cpus = machine->smp.cpus;
854 unsigned int max_cpus = machine->smp.max_cpus;
855 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id,
856 TYPE_MEMORY_BACKEND, NULL);
857
858 if (machine->ram_size > hwdef->max_mem) {
859 error_report("Too much memory for this machine: %" PRId64 ","
860 " maximum %" PRId64,
861 machine->ram_size / MiB, hwdef->max_mem / MiB);
862 exit(1);
863 }
864
865 /* init CPUs */
866 for(i = 0; i < smp_cpus; i++) {
867 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]);
868 }
869
870 for (i = smp_cpus; i < MAX_CPUS; i++)
871 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
872
873 /* Create and map RAM frontend */
874 dev = qdev_new("memory");
875 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal);
876 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
877 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0);
878
879 /* models without ECC don't trap when missing ram is accessed */
880 if (!hwdef->ecc_base) {
881 empty_slot_init("ecc", machine->ram_size,
882 hwdef->max_mem - machine->ram_size);
883 }
884
885 prom_init(hwdef->slavio_base, bios_name);
886
887 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
888 hwdef->intctl_base + 0x10000ULL,
889 cpu_irqs);
890
891 for (i = 0; i < 32; i++) {
892 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
893 }
894 for (i = 0; i < MAX_CPUS; i++) {
895 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
896 }
897
898 if (hwdef->idreg_base) {
899 idreg_init(hwdef->idreg_base);
900 }
901
902 if (hwdef->afx_base) {
903 afx_init(hwdef->afx_base);
904 }
905
906 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]);
907
908 if (hwdef->iommu_pad_base) {
909 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
910 Software shouldn't use aliased addresses, neither should it crash
911 when does. Using empty_slot instead of aliasing can help with
912 debugging such accesses */
913 empty_slot_init("iommu.alias",
914 hwdef->iommu_pad_base, hwdef->iommu_pad_len);
915 }
916
917 sparc32_dma_init(hwdef->dma_base,
918 hwdef->esp_base, slavio_irq[18],
919 hwdef->le_base, slavio_irq[16]);
920
921 if (graphic_depth != 8 && graphic_depth != 24) {
922 error_report("Unsupported depth: %d", graphic_depth);
923 exit (1);
924 }
925 if (vga_interface_type != VGA_NONE) {
926 if (vga_interface_type == VGA_CG3) {
927 if (graphic_depth != 8) {
928 error_report("Unsupported depth: %d", graphic_depth);
929 exit(1);
930 }
931
932 if (!(graphic_width == 1024 && graphic_height == 768) &&
933 !(graphic_width == 1152 && graphic_height == 900)) {
934 error_report("Unsupported resolution: %d x %d", graphic_width,
935 graphic_height);
936 exit(1);
937 }
938
939 /* sbus irq 5 */
940 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
941 graphic_width, graphic_height, graphic_depth);
942 } else {
943 /* If no display specified, default to TCX */
944 if (graphic_depth != 8 && graphic_depth != 24) {
945 error_report("Unsupported depth: %d", graphic_depth);
946 exit(1);
947 }
948
949 if (!(graphic_width == 1024 && graphic_height == 768)) {
950 error_report("Unsupported resolution: %d x %d",
951 graphic_width, graphic_height);
952 exit(1);
953 }
954
955 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
956 graphic_width, graphic_height, graphic_depth);
957 }
958 }
959
960 for (i = 0; i < MAX_VSIMMS; i++) {
961 /* vsimm registers probed by OBP */
962 if (hwdef->vsimm[i].reg_base) {
963 char *name = g_strdup_printf("vsimm[%d]", i);
964 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
965 g_free(name);
966 }
967 }
968
969 if (hwdef->sx_base) {
970 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
971 }
972
973 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
974
975 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
976
977 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
978 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
979 dev = qdev_new(TYPE_ESCC);
980 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics);
981 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
982 qdev_prop_set_uint32(dev, "it_shift", 1);
983 qdev_prop_set_chr(dev, "chrB", NULL);
984 qdev_prop_set_chr(dev, "chrA", NULL);
985 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse);
986 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd);
987 s = SYS_BUS_DEVICE(dev);
988 sysbus_realize_and_unref(s, &error_fatal);
989 sysbus_connect_irq(s, 0, slavio_irq[14]);
990 sysbus_connect_irq(s, 1, slavio_irq[14]);
991 sysbus_mmio_map(s, 0, hwdef->ms_kb_base);
992
993 dev = qdev_new(TYPE_ESCC);
994 qdev_prop_set_uint32(dev, "disabled", 0);
995 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK);
996 qdev_prop_set_uint32(dev, "it_shift", 1);
997 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
998 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
999 qdev_prop_set_uint32(dev, "chnBtype", escc_serial);
1000 qdev_prop_set_uint32(dev, "chnAtype", escc_serial);
1001
1002 s = SYS_BUS_DEVICE(dev);
1003 sysbus_realize_and_unref(s, &error_fatal);
1004 sysbus_connect_irq(s, 0, slavio_irq[15]);
1005 sysbus_connect_irq(s, 1, slavio_irq[15]);
1006 sysbus_mmio_map(s, 0, hwdef->serial_base);
1007
1008 if (hwdef->apc_base) {
1009 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1010 }
1011
1012 if (hwdef->fd_base) {
1013 /* there is zero or one floppy drive */
1014 memset(fd, 0, sizeof(fd));
1015 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1016 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1017 &fdc_tc);
1018 } else {
1019 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1020 }
1021
1022 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1023 slavio_irq[30], fdc_tc);
1024
1025 if (hwdef->cs_base) {
1026 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1027 slavio_irq[5]);
1028 }
1029
1030 if (hwdef->dbri_base) {
1031 /* ISDN chip with attached CS4215 audio codec */
1032 /* prom space */
1033 create_unimplemented_device("SUNW,DBRI.prom",
1034 hwdef->dbri_base + 0x1000, 0x30);
1035 /* reg space */
1036 create_unimplemented_device("SUNW,DBRI",
1037 hwdef->dbri_base + 0x10000, 0x100);
1038 }
1039
1040 if (hwdef->bpp_base) {
1041 /* parallel port */
1042 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
1043 }
1044
1045 initrd_size = 0;
1046 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1047 machine->initrd_filename,
1048 machine->ram_size, &initrd_size);
1049
1050 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1051 machine->boot_order, machine->ram_size, kernel_size,
1052 graphic_width, graphic_height, graphic_depth,
1053 hwdef->nvram_machine_id, "Sun4m");
1054
1055 if (hwdef->ecc_base)
1056 ecc_init(hwdef->ecc_base, slavio_irq[28],
1057 hwdef->ecc_version);
1058
1059 dev = qdev_new(TYPE_FW_CFG_MEM);
1060 fw_cfg = FW_CFG(dev);
1061 qdev_prop_set_uint32(dev, "data_width", 1);
1062 qdev_prop_set_bit(dev, "dma_enabled", false);
1063 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1064 OBJECT(fw_cfg));
1065 s = SYS_BUS_DEVICE(dev);
1066 sysbus_realize_and_unref(s, &error_fatal);
1067 sysbus_mmio_map(s, 0, CFG_ADDR);
1068 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
1069
1070 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
1071 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1072 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
1073 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1077 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1078 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1079 if (machine->kernel_cmdline) {
1080 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1081 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1082 machine->kernel_cmdline);
1083 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1084 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1085 strlen(machine->kernel_cmdline) + 1);
1086 } else {
1087 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1088 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1089 }
1090 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1091 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
1092 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1093 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1094 }
1095
1096 enum {
1097 ss5_id = 32,
1098 vger_id,
1099 lx_id,
1100 ss4_id,
1101 scls_id,
1102 sbook_id,
1103 ss10_id = 64,
1104 ss20_id,
1105 ss600mp_id,
1106 };
1107
1108 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1109 /* SS-5 */
1110 {
1111 .iommu_base = 0x10000000,
1112 .iommu_pad_base = 0x10004000,
1113 .iommu_pad_len = 0x0fffb000,
1114 .tcx_base = 0x50000000,
1115 .cs_base = 0x6c000000,
1116 .slavio_base = 0x70000000,
1117 .ms_kb_base = 0x71000000,
1118 .serial_base = 0x71100000,
1119 .nvram_base = 0x71200000,
1120 .fd_base = 0x71400000,
1121 .counter_base = 0x71d00000,
1122 .intctl_base = 0x71e00000,
1123 .idreg_base = 0x78000000,
1124 .dma_base = 0x78400000,
1125 .esp_base = 0x78800000,
1126 .le_base = 0x78c00000,
1127 .apc_base = 0x6a000000,
1128 .afx_base = 0x6e000000,
1129 .aux1_base = 0x71900000,
1130 .aux2_base = 0x71910000,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = ss5_id,
1133 .iommu_version = 0x05000000,
1134 .max_mem = 0x10000000,
1135 },
1136 /* SS-10 */
1137 {
1138 .iommu_base = 0xfe0000000ULL,
1139 .tcx_base = 0xe20000000ULL,
1140 .slavio_base = 0xff0000000ULL,
1141 .ms_kb_base = 0xff1000000ULL,
1142 .serial_base = 0xff1100000ULL,
1143 .nvram_base = 0xff1200000ULL,
1144 .fd_base = 0xff1700000ULL,
1145 .counter_base = 0xff1300000ULL,
1146 .intctl_base = 0xff1400000ULL,
1147 .idreg_base = 0xef0000000ULL,
1148 .dma_base = 0xef0400000ULL,
1149 .esp_base = 0xef0800000ULL,
1150 .le_base = 0xef0c00000ULL,
1151 .apc_base = 0xefa000000ULL, // XXX should not exist
1152 .aux1_base = 0xff1800000ULL,
1153 .aux2_base = 0xff1a01000ULL,
1154 .ecc_base = 0xf00000000ULL,
1155 .ecc_version = 0x10000000, // version 0, implementation 1
1156 .nvram_machine_id = 0x72,
1157 .machine_id = ss10_id,
1158 .iommu_version = 0x03000000,
1159 .max_mem = 0xf00000000ULL,
1160 },
1161 /* SS-600MP */
1162 {
1163 .iommu_base = 0xfe0000000ULL,
1164 .tcx_base = 0xe20000000ULL,
1165 .slavio_base = 0xff0000000ULL,
1166 .ms_kb_base = 0xff1000000ULL,
1167 .serial_base = 0xff1100000ULL,
1168 .nvram_base = 0xff1200000ULL,
1169 .counter_base = 0xff1300000ULL,
1170 .intctl_base = 0xff1400000ULL,
1171 .dma_base = 0xef0081000ULL,
1172 .esp_base = 0xef0080000ULL,
1173 .le_base = 0xef0060000ULL,
1174 .apc_base = 0xefa000000ULL, // XXX should not exist
1175 .aux1_base = 0xff1800000ULL,
1176 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1177 .ecc_base = 0xf00000000ULL,
1178 .ecc_version = 0x00000000, // version 0, implementation 0
1179 .nvram_machine_id = 0x71,
1180 .machine_id = ss600mp_id,
1181 .iommu_version = 0x01000000,
1182 .max_mem = 0xf00000000ULL,
1183 },
1184 /* SS-20 */
1185 {
1186 .iommu_base = 0xfe0000000ULL,
1187 .tcx_base = 0xe20000000ULL,
1188 .slavio_base = 0xff0000000ULL,
1189 .ms_kb_base = 0xff1000000ULL,
1190 .serial_base = 0xff1100000ULL,
1191 .nvram_base = 0xff1200000ULL,
1192 .fd_base = 0xff1700000ULL,
1193 .counter_base = 0xff1300000ULL,
1194 .intctl_base = 0xff1400000ULL,
1195 .idreg_base = 0xef0000000ULL,
1196 .dma_base = 0xef0400000ULL,
1197 .esp_base = 0xef0800000ULL,
1198 .le_base = 0xef0c00000ULL,
1199 .bpp_base = 0xef4800000ULL,
1200 .apc_base = 0xefa000000ULL, // XXX should not exist
1201 .aux1_base = 0xff1800000ULL,
1202 .aux2_base = 0xff1a01000ULL,
1203 .dbri_base = 0xee0000000ULL,
1204 .sx_base = 0xf80000000ULL,
1205 .vsimm = {
1206 {
1207 .reg_base = 0x9c000000ULL,
1208 .vram_base = 0xfc000000ULL
1209 }, {
1210 .reg_base = 0x90000000ULL,
1211 .vram_base = 0xf0000000ULL
1212 }, {
1213 .reg_base = 0x94000000ULL
1214 }, {
1215 .reg_base = 0x98000000ULL
1216 }
1217 },
1218 .ecc_base = 0xf00000000ULL,
1219 .ecc_version = 0x20000000, // version 0, implementation 2
1220 .nvram_machine_id = 0x72,
1221 .machine_id = ss20_id,
1222 .iommu_version = 0x13000000,
1223 .max_mem = 0xf00000000ULL,
1224 },
1225 /* Voyager */
1226 {
1227 .iommu_base = 0x10000000,
1228 .tcx_base = 0x50000000,
1229 .slavio_base = 0x70000000,
1230 .ms_kb_base = 0x71000000,
1231 .serial_base = 0x71100000,
1232 .nvram_base = 0x71200000,
1233 .fd_base = 0x71400000,
1234 .counter_base = 0x71d00000,
1235 .intctl_base = 0x71e00000,
1236 .idreg_base = 0x78000000,
1237 .dma_base = 0x78400000,
1238 .esp_base = 0x78800000,
1239 .le_base = 0x78c00000,
1240 .apc_base = 0x71300000, // pmc
1241 .aux1_base = 0x71900000,
1242 .aux2_base = 0x71910000,
1243 .nvram_machine_id = 0x80,
1244 .machine_id = vger_id,
1245 .iommu_version = 0x05000000,
1246 .max_mem = 0x10000000,
1247 },
1248 /* LX */
1249 {
1250 .iommu_base = 0x10000000,
1251 .iommu_pad_base = 0x10004000,
1252 .iommu_pad_len = 0x0fffb000,
1253 .tcx_base = 0x50000000,
1254 .slavio_base = 0x70000000,
1255 .ms_kb_base = 0x71000000,
1256 .serial_base = 0x71100000,
1257 .nvram_base = 0x71200000,
1258 .fd_base = 0x71400000,
1259 .counter_base = 0x71d00000,
1260 .intctl_base = 0x71e00000,
1261 .idreg_base = 0x78000000,
1262 .dma_base = 0x78400000,
1263 .esp_base = 0x78800000,
1264 .le_base = 0x78c00000,
1265 .aux1_base = 0x71900000,
1266 .aux2_base = 0x71910000,
1267 .nvram_machine_id = 0x80,
1268 .machine_id = lx_id,
1269 .iommu_version = 0x04000000,
1270 .max_mem = 0x10000000,
1271 },
1272 /* SS-4 */
1273 {
1274 .iommu_base = 0x10000000,
1275 .tcx_base = 0x50000000,
1276 .cs_base = 0x6c000000,
1277 .slavio_base = 0x70000000,
1278 .ms_kb_base = 0x71000000,
1279 .serial_base = 0x71100000,
1280 .nvram_base = 0x71200000,
1281 .fd_base = 0x71400000,
1282 .counter_base = 0x71d00000,
1283 .intctl_base = 0x71e00000,
1284 .idreg_base = 0x78000000,
1285 .dma_base = 0x78400000,
1286 .esp_base = 0x78800000,
1287 .le_base = 0x78c00000,
1288 .apc_base = 0x6a000000,
1289 .aux1_base = 0x71900000,
1290 .aux2_base = 0x71910000,
1291 .nvram_machine_id = 0x80,
1292 .machine_id = ss4_id,
1293 .iommu_version = 0x05000000,
1294 .max_mem = 0x10000000,
1295 },
1296 /* SPARCClassic */
1297 {
1298 .iommu_base = 0x10000000,
1299 .tcx_base = 0x50000000,
1300 .slavio_base = 0x70000000,
1301 .ms_kb_base = 0x71000000,
1302 .serial_base = 0x71100000,
1303 .nvram_base = 0x71200000,
1304 .fd_base = 0x71400000,
1305 .counter_base = 0x71d00000,
1306 .intctl_base = 0x71e00000,
1307 .idreg_base = 0x78000000,
1308 .dma_base = 0x78400000,
1309 .esp_base = 0x78800000,
1310 .le_base = 0x78c00000,
1311 .apc_base = 0x6a000000,
1312 .aux1_base = 0x71900000,
1313 .aux2_base = 0x71910000,
1314 .nvram_machine_id = 0x80,
1315 .machine_id = scls_id,
1316 .iommu_version = 0x05000000,
1317 .max_mem = 0x10000000,
1318 },
1319 /* SPARCbook */
1320 {
1321 .iommu_base = 0x10000000,
1322 .tcx_base = 0x50000000, // XXX
1323 .slavio_base = 0x70000000,
1324 .ms_kb_base = 0x71000000,
1325 .serial_base = 0x71100000,
1326 .nvram_base = 0x71200000,
1327 .fd_base = 0x71400000,
1328 .counter_base = 0x71d00000,
1329 .intctl_base = 0x71e00000,
1330 .idreg_base = 0x78000000,
1331 .dma_base = 0x78400000,
1332 .esp_base = 0x78800000,
1333 .le_base = 0x78c00000,
1334 .apc_base = 0x6a000000,
1335 .aux1_base = 0x71900000,
1336 .aux2_base = 0x71910000,
1337 .nvram_machine_id = 0x80,
1338 .machine_id = sbook_id,
1339 .iommu_version = 0x05000000,
1340 .max_mem = 0x10000000,
1341 },
1342 };
1343
1344 /* SPARCstation 5 hardware initialisation */
1345 static void ss5_init(MachineState *machine)
1346 {
1347 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1348 }
1349
1350 /* SPARCstation 10 hardware initialisation */
1351 static void ss10_init(MachineState *machine)
1352 {
1353 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1354 }
1355
1356 /* SPARCserver 600MP hardware initialisation */
1357 static void ss600mp_init(MachineState *machine)
1358 {
1359 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1360 }
1361
1362 /* SPARCstation 20 hardware initialisation */
1363 static void ss20_init(MachineState *machine)
1364 {
1365 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1366 }
1367
1368 /* SPARCstation Voyager hardware initialisation */
1369 static void vger_init(MachineState *machine)
1370 {
1371 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1372 }
1373
1374 /* SPARCstation LX hardware initialisation */
1375 static void ss_lx_init(MachineState *machine)
1376 {
1377 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1378 }
1379
1380 /* SPARCstation 4 hardware initialisation */
1381 static void ss4_init(MachineState *machine)
1382 {
1383 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1384 }
1385
1386 /* SPARCClassic hardware initialisation */
1387 static void scls_init(MachineState *machine)
1388 {
1389 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1390 }
1391
1392 /* SPARCbook hardware initialisation */
1393 static void sbook_init(MachineState *machine)
1394 {
1395 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1396 }
1397
1398 static void ss5_class_init(ObjectClass *oc, void *data)
1399 {
1400 MachineClass *mc = MACHINE_CLASS(oc);
1401
1402 mc->desc = "Sun4m platform, SPARCstation 5";
1403 mc->init = ss5_init;
1404 mc->block_default_type = IF_SCSI;
1405 mc->is_default = true;
1406 mc->default_boot_order = "c";
1407 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1408 mc->default_display = "tcx";
1409 mc->default_ram_id = "sun4m.ram";
1410 }
1411
1412 static const TypeInfo ss5_type = {
1413 .name = MACHINE_TYPE_NAME("SS-5"),
1414 .parent = TYPE_MACHINE,
1415 .class_init = ss5_class_init,
1416 };
1417
1418 static void ss10_class_init(ObjectClass *oc, void *data)
1419 {
1420 MachineClass *mc = MACHINE_CLASS(oc);
1421
1422 mc->desc = "Sun4m platform, SPARCstation 10";
1423 mc->init = ss10_init;
1424 mc->block_default_type = IF_SCSI;
1425 mc->max_cpus = 4;
1426 mc->default_boot_order = "c";
1427 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1428 mc->default_display = "tcx";
1429 mc->default_ram_id = "sun4m.ram";
1430 }
1431
1432 static const TypeInfo ss10_type = {
1433 .name = MACHINE_TYPE_NAME("SS-10"),
1434 .parent = TYPE_MACHINE,
1435 .class_init = ss10_class_init,
1436 };
1437
1438 static void ss600mp_class_init(ObjectClass *oc, void *data)
1439 {
1440 MachineClass *mc = MACHINE_CLASS(oc);
1441
1442 mc->desc = "Sun4m platform, SPARCserver 600MP";
1443 mc->init = ss600mp_init;
1444 mc->block_default_type = IF_SCSI;
1445 mc->max_cpus = 4;
1446 mc->default_boot_order = "c";
1447 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1448 mc->default_display = "tcx";
1449 mc->default_ram_id = "sun4m.ram";
1450 }
1451
1452 static const TypeInfo ss600mp_type = {
1453 .name = MACHINE_TYPE_NAME("SS-600MP"),
1454 .parent = TYPE_MACHINE,
1455 .class_init = ss600mp_class_init,
1456 };
1457
1458 static void ss20_class_init(ObjectClass *oc, void *data)
1459 {
1460 MachineClass *mc = MACHINE_CLASS(oc);
1461
1462 mc->desc = "Sun4m platform, SPARCstation 20";
1463 mc->init = ss20_init;
1464 mc->block_default_type = IF_SCSI;
1465 mc->max_cpus = 4;
1466 mc->default_boot_order = "c";
1467 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II");
1468 mc->default_display = "tcx";
1469 mc->default_ram_id = "sun4m.ram";
1470 }
1471
1472 static const TypeInfo ss20_type = {
1473 .name = MACHINE_TYPE_NAME("SS-20"),
1474 .parent = TYPE_MACHINE,
1475 .class_init = ss20_class_init,
1476 };
1477
1478 static void voyager_class_init(ObjectClass *oc, void *data)
1479 {
1480 MachineClass *mc = MACHINE_CLASS(oc);
1481
1482 mc->desc = "Sun4m platform, SPARCstation Voyager";
1483 mc->init = vger_init;
1484 mc->block_default_type = IF_SCSI;
1485 mc->default_boot_order = "c";
1486 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1487 mc->default_display = "tcx";
1488 mc->default_ram_id = "sun4m.ram";
1489 }
1490
1491 static const TypeInfo voyager_type = {
1492 .name = MACHINE_TYPE_NAME("Voyager"),
1493 .parent = TYPE_MACHINE,
1494 .class_init = voyager_class_init,
1495 };
1496
1497 static void ss_lx_class_init(ObjectClass *oc, void *data)
1498 {
1499 MachineClass *mc = MACHINE_CLASS(oc);
1500
1501 mc->desc = "Sun4m platform, SPARCstation LX";
1502 mc->init = ss_lx_init;
1503 mc->block_default_type = IF_SCSI;
1504 mc->default_boot_order = "c";
1505 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1506 mc->default_display = "tcx";
1507 mc->default_ram_id = "sun4m.ram";
1508 }
1509
1510 static const TypeInfo ss_lx_type = {
1511 .name = MACHINE_TYPE_NAME("LX"),
1512 .parent = TYPE_MACHINE,
1513 .class_init = ss_lx_class_init,
1514 };
1515
1516 static void ss4_class_init(ObjectClass *oc, void *data)
1517 {
1518 MachineClass *mc = MACHINE_CLASS(oc);
1519
1520 mc->desc = "Sun4m platform, SPARCstation 4";
1521 mc->init = ss4_init;
1522 mc->block_default_type = IF_SCSI;
1523 mc->default_boot_order = "c";
1524 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904");
1525 mc->default_display = "tcx";
1526 mc->default_ram_id = "sun4m.ram";
1527 }
1528
1529 static const TypeInfo ss4_type = {
1530 .name = MACHINE_TYPE_NAME("SS-4"),
1531 .parent = TYPE_MACHINE,
1532 .class_init = ss4_class_init,
1533 };
1534
1535 static void scls_class_init(ObjectClass *oc, void *data)
1536 {
1537 MachineClass *mc = MACHINE_CLASS(oc);
1538
1539 mc->desc = "Sun4m platform, SPARCClassic";
1540 mc->init = scls_init;
1541 mc->block_default_type = IF_SCSI;
1542 mc->default_boot_order = "c";
1543 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1544 mc->default_display = "tcx";
1545 mc->default_ram_id = "sun4m.ram";
1546 }
1547
1548 static const TypeInfo scls_type = {
1549 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1550 .parent = TYPE_MACHINE,
1551 .class_init = scls_class_init,
1552 };
1553
1554 static void sbook_class_init(ObjectClass *oc, void *data)
1555 {
1556 MachineClass *mc = MACHINE_CLASS(oc);
1557
1558 mc->desc = "Sun4m platform, SPARCbook";
1559 mc->init = sbook_init;
1560 mc->block_default_type = IF_SCSI;
1561 mc->default_boot_order = "c";
1562 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I");
1563 mc->default_display = "tcx";
1564 mc->default_ram_id = "sun4m.ram";
1565 }
1566
1567 static const TypeInfo sbook_type = {
1568 .name = MACHINE_TYPE_NAME("SPARCbook"),
1569 .parent = TYPE_MACHINE,
1570 .class_init = sbook_class_init,
1571 };
1572
1573 static void sun4m_register_types(void)
1574 {
1575 type_register_static(&idreg_info);
1576 type_register_static(&afx_info);
1577 type_register_static(&prom_info);
1578 type_register_static(&ram_info);
1579
1580 type_register_static(&ss5_type);
1581 type_register_static(&ss10_type);
1582 type_register_static(&ss600mp_type);
1583 type_register_static(&ss20_type);
1584 type_register_static(&voyager_type);
1585 type_register_static(&ss_lx_type);
1586 type_register_static(&ss4_type);
1587 type_register_static(&scls_type);
1588 type_register_static(&sbook_type);
1589 }
1590
1591 type_init(sun4m_register_types)
AR7 emulation for QEMU