2 * OneNAND flash memories emulation.
4 * Copyright (C) 2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
24 #include "hw/block/flash.h"
26 #include "hw/qdev-properties.h"
27 #include "sysemu/block-backend.h"
28 #include "exec/memory.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "qemu/error-report.h"
33 #include "qemu/module.h"
34 #include "qom/object.h"
36 /* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
40 #define BLOCK_SHIFT (PAGE_SHIFT + 6)
42 #define TYPE_ONE_NAND "onenand"
43 OBJECT_DECLARE_SIMPLE_TYPE(OneNANDState
, ONE_NAND
)
46 SysBusDevice parent_obj
;
58 BlockBackend
*blk_cur
;
63 MemoryRegion mapped_ram
;
64 uint8_t current_direction
;
68 MemoryRegion container
;
94 ONEN_BUF_DEST_BLOCK
= 2,
95 ONEN_BUF_DEST_PAGE
= 3,
100 ONEN_ERR_CMD
= 1 << 10,
101 ONEN_ERR_ERASE
= 1 << 11,
102 ONEN_ERR_PROG
= 1 << 12,
103 ONEN_ERR_LOAD
= 1 << 13,
107 ONEN_INT_RESET
= 1 << 4,
108 ONEN_INT_ERASE
= 1 << 5,
109 ONEN_INT_PROG
= 1 << 6,
110 ONEN_INT_LOAD
= 1 << 7,
115 ONEN_LOCK_LOCKTIGHTEN
= 1 << 0,
116 ONEN_LOCK_LOCKED
= 1 << 1,
117 ONEN_LOCK_UNLOCKED
= 1 << 2,
120 static void onenand_mem_setup(OneNANDState
*s
)
122 /* XXX: We should use IO_MEM_ROMD but we broke it earlier...
123 * Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
124 * write boot commands. Also take note of the BWPS bit. */
125 memory_region_init(&s
->container
, OBJECT(s
), "onenand",
126 0x10000 << s
->shift
);
127 memory_region_add_subregion(&s
->container
, 0, &s
->iomem
);
128 memory_region_init_alias(&s
->mapped_ram
, OBJECT(s
), "onenand-mapped-ram",
129 &s
->ram
, 0x0200 << s
->shift
,
131 memory_region_add_subregion_overlap(&s
->container
,
137 static void onenand_intr_update(OneNANDState
*s
)
139 qemu_set_irq(s
->intr
, ((s
->intstatus
>> 15) ^ (~s
->config
[0] >> 6)) & 1);
142 static int onenand_pre_save(void *opaque
)
144 OneNANDState
*s
= opaque
;
145 if (s
->current
== s
->otp
) {
146 s
->current_direction
= 1;
147 } else if (s
->current
== s
->image
) {
148 s
->current_direction
= 2;
150 s
->current_direction
= 0;
156 static int onenand_post_load(void *opaque
, int version_id
)
158 OneNANDState
*s
= opaque
;
159 switch (s
->current_direction
) {
166 s
->current
= s
->image
;
171 onenand_intr_update(s
);
175 static const VMStateDescription vmstate_onenand
= {
178 .minimum_version_id
= 1,
179 .pre_save
= onenand_pre_save
,
180 .post_load
= onenand_post_load
,
181 .fields
= (VMStateField
[]) {
182 VMSTATE_UINT8(current_direction
, OneNANDState
),
183 VMSTATE_INT32(cycle
, OneNANDState
),
184 VMSTATE_INT32(otpmode
, OneNANDState
),
185 VMSTATE_UINT16_ARRAY(addr
, OneNANDState
, 8),
186 VMSTATE_UINT16_ARRAY(unladdr
, OneNANDState
, 8),
187 VMSTATE_INT32(bufaddr
, OneNANDState
),
188 VMSTATE_INT32(count
, OneNANDState
),
189 VMSTATE_UINT16(command
, OneNANDState
),
190 VMSTATE_UINT16_ARRAY(config
, OneNANDState
, 2),
191 VMSTATE_UINT16(status
, OneNANDState
),
192 VMSTATE_UINT16(intstatus
, OneNANDState
),
193 VMSTATE_UINT16(wpstatus
, OneNANDState
),
194 VMSTATE_INT32(secs_cur
, OneNANDState
),
195 VMSTATE_PARTIAL_VBUFFER(blockwp
, OneNANDState
, blocks
),
196 VMSTATE_UINT8(ecc
.cp
, OneNANDState
),
197 VMSTATE_UINT16_ARRAY(ecc
.lp
, OneNANDState
, 2),
198 VMSTATE_UINT16(ecc
.count
, OneNANDState
),
199 VMSTATE_BUFFER_POINTER_UNSAFE(otp
, OneNANDState
, 0,
200 ((64 + 2) << PAGE_SHIFT
)),
201 VMSTATE_END_OF_LIST()
205 /* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
206 static void onenand_reset(OneNANDState
*s
, int cold
)
208 memset(&s
->addr
, 0, sizeof(s
->addr
));
212 s
->config
[0] = 0x40c0;
213 s
->config
[1] = 0x0000;
214 onenand_intr_update(s
);
215 qemu_irq_raise(s
->rdy
);
217 s
->intstatus
= cold
? 0x8080 : 0x8010;
220 s
->wpstatus
= 0x0002;
224 s
->current
= s
->image
;
225 s
->secs_cur
= s
->secs
;
228 /* Lock the whole flash */
229 memset(s
->blockwp
, ONEN_LOCK_LOCKED
, s
->blocks
);
231 if (s
->blk_cur
&& blk_pread(s
->blk_cur
, 0, s
->boot
[0],
232 8 << BDRV_SECTOR_BITS
) < 0) {
233 hw_error("%s: Loading the BootRAM failed.\n", __func__
);
238 static void onenand_system_reset(DeviceState
*dev
)
240 OneNANDState
*s
= ONE_NAND(dev
);
245 static inline int onenand_load_main(OneNANDState
*s
, int sec
, int secn
,
248 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> sec
);
249 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> secn
);
251 return blk_pread(s
->blk_cur
, sec
<< BDRV_SECTOR_BITS
, dest
,
252 secn
<< BDRV_SECTOR_BITS
) < 0;
253 } else if (sec
+ secn
> s
->secs_cur
) {
257 memcpy(dest
, s
->current
+ (sec
<< 9), secn
<< 9);
262 static inline int onenand_prog_main(OneNANDState
*s
, int sec
, int secn
,
268 uint32_t size
= secn
<< BDRV_SECTOR_BITS
;
269 uint32_t offset
= sec
<< BDRV_SECTOR_BITS
;
270 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> sec
);
271 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> secn
);
272 const uint8_t *sp
= (const uint8_t *)src
;
276 if (!dp
|| blk_pread(s
->blk_cur
, offset
, dp
, size
) < 0) {
280 if (sec
+ secn
> s
->secs_cur
) {
283 dp
= (uint8_t *)s
->current
+ offset
;
288 for (i
= 0; i
< size
; i
++) {
292 result
= blk_pwrite(s
->blk_cur
, offset
, dp
, size
, 0) < 0;
295 if (dp
&& s
->blk_cur
) {
303 static inline int onenand_load_spare(OneNANDState
*s
, int sec
, int secn
,
309 uint32_t offset
= (s
->secs_cur
+ (sec
>> 5)) << BDRV_SECTOR_BITS
;
310 if (blk_pread(s
->blk_cur
, offset
, buf
, BDRV_SECTOR_SIZE
) < 0) {
313 memcpy(dest
, buf
+ ((sec
& 31) << 4), secn
<< 4);
314 } else if (sec
+ secn
> s
->secs_cur
) {
317 memcpy(dest
, s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4), secn
<< 4);
323 static inline int onenand_prog_spare(OneNANDState
*s
, int sec
, int secn
,
328 const uint8_t *sp
= (const uint8_t *)src
;
329 uint8_t *dp
= 0, *dpp
= 0;
330 uint32_t offset
= (s
->secs_cur
+ (sec
>> 5)) << BDRV_SECTOR_BITS
;
331 assert(UINT32_MAX
>> BDRV_SECTOR_BITS
> s
->secs_cur
+ (sec
>> 5));
335 || blk_pread(s
->blk_cur
, offset
, dp
, BDRV_SECTOR_SIZE
) < 0) {
338 dpp
= dp
+ ((sec
& 31) << 4);
341 if (sec
+ secn
> s
->secs_cur
) {
344 dpp
= s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4);
349 for (i
= 0; i
< (secn
<< 4); i
++) {
353 result
= blk_pwrite(s
->blk_cur
, offset
, dp
,
354 BDRV_SECTOR_SIZE
, 0) < 0;
362 static inline int onenand_erase(OneNANDState
*s
, int sec
, int num
)
364 uint8_t *blankbuf
, *tmpbuf
;
366 blankbuf
= g_malloc(512);
367 tmpbuf
= g_malloc(512);
368 memset(blankbuf
, 0xff, 512);
369 for (; num
> 0; num
--, sec
++) {
371 int erasesec
= s
->secs_cur
+ (sec
>> 5);
372 if (blk_pwrite(s
->blk_cur
, sec
<< BDRV_SECTOR_BITS
, blankbuf
,
373 BDRV_SECTOR_SIZE
, 0) < 0) {
376 if (blk_pread(s
->blk_cur
, erasesec
<< BDRV_SECTOR_BITS
, tmpbuf
,
377 BDRV_SECTOR_SIZE
) < 0) {
380 memcpy(tmpbuf
+ ((sec
& 31) << 4), blankbuf
, 1 << 4);
381 if (blk_pwrite(s
->blk_cur
, erasesec
<< BDRV_SECTOR_BITS
, tmpbuf
,
382 BDRV_SECTOR_SIZE
, 0) < 0) {
386 if (sec
+ 1 > s
->secs_cur
) {
389 memcpy(s
->current
+ (sec
<< 9), blankbuf
, 512);
390 memcpy(s
->current
+ (s
->secs_cur
<< 9) + (sec
<< 4),
405 static void onenand_command(OneNANDState
*s
)
410 #define SETADDR(block, page) \
411 sec = (s->addr[page] & 3) + \
412 ((((s->addr[page] >> 2) & 0x3f) + \
413 (((s->addr[block] & 0xfff) | \
414 (s->addr[block] >> 15 ? \
415 s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
417 buf = (s->bufaddr & 8) ? \
418 s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
419 buf += (s->bufaddr & 3) << 9;
421 buf = (s->bufaddr & 8) ? \
422 s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
423 buf += (s->bufaddr & 3) << 4;
425 switch (s
->command
) {
426 case 0x00: /* Load single/multiple sector data unit into buffer */
427 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
430 if (onenand_load_main(s
, sec
, s
->count
, buf
))
431 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
435 if (onenand_load_spare(s
, sec
, s
->count
, buf
))
436 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
439 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
440 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
441 * then we need two split the read/write into two chunks.
443 s
->intstatus
|= ONEN_INT
| ONEN_INT_LOAD
;
445 case 0x13: /* Load single/multiple spare sector into buffer */
446 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
449 if (onenand_load_spare(s
, sec
, s
->count
, buf
))
450 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_LOAD
;
452 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
453 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
454 * then we need two split the read/write into two chunks.
456 s
->intstatus
|= ONEN_INT
| ONEN_INT_LOAD
;
458 case 0x80: /* Program single/multiple sector data unit from buffer */
459 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
462 if (onenand_prog_main(s
, sec
, s
->count
, buf
))
463 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
467 if (onenand_prog_spare(s
, sec
, s
->count
, buf
))
468 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
471 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
472 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
473 * then we need two split the read/write into two chunks.
475 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
477 case 0x1a: /* Program single/multiple spare area sector from buffer */
478 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
481 if (onenand_prog_spare(s
, sec
, s
->count
, buf
))
482 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
484 /* TODO: if (s->bufaddr & 3) + s->count was > 4 (2k-pages)
485 * or if (s->bufaddr & 1) + s->count was > 2 (1k-pages)
486 * then we need two split the read/write into two chunks.
488 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
490 case 0x1b: /* Copy-back program */
493 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
494 if (onenand_load_main(s
, sec
, s
->count
, buf
))
495 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
497 SETADDR(ONEN_BUF_DEST_BLOCK
, ONEN_BUF_DEST_PAGE
)
498 if (onenand_prog_main(s
, sec
, s
->count
, buf
))
499 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_PROG
;
501 /* TODO: spare areas */
503 s
->intstatus
|= ONEN_INT
| ONEN_INT_PROG
;
506 case 0x23: /* Unlock NAND array block(s) */
507 s
->intstatus
|= ONEN_INT
;
509 /* XXX the previous (?) area should be locked automatically */
510 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
511 if (b
>= s
->blocks
) {
512 s
->status
|= ONEN_ERR_CMD
;
515 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
518 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_UNLOCKED
;
521 case 0x27: /* Unlock All NAND array blocks */
522 s
->intstatus
|= ONEN_INT
;
524 for (b
= 0; b
< s
->blocks
; b
++) {
525 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
528 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_UNLOCKED
;
532 case 0x2a: /* Lock NAND array block(s) */
533 s
->intstatus
|= ONEN_INT
;
535 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
536 if (b
>= s
->blocks
) {
537 s
->status
|= ONEN_ERR_CMD
;
540 if (s
->blockwp
[b
] == ONEN_LOCK_LOCKTIGHTEN
)
543 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_LOCKED
;
546 case 0x2c: /* Lock-tight NAND array block(s) */
547 s
->intstatus
|= ONEN_INT
;
549 for (b
= s
->unladdr
[0]; b
<= s
->unladdr
[1]; b
++) {
550 if (b
>= s
->blocks
) {
551 s
->status
|= ONEN_ERR_CMD
;
554 if (s
->blockwp
[b
] == ONEN_LOCK_UNLOCKED
)
557 s
->wpstatus
= s
->blockwp
[b
] = ONEN_LOCK_LOCKTIGHTEN
;
561 case 0x71: /* Erase-Verify-Read */
562 s
->intstatus
|= ONEN_INT
;
564 case 0x95: /* Multi-block erase */
565 qemu_irq_pulse(s
->intr
);
567 case 0x94: /* Block erase */
568 sec
= ((s
->addr
[ONEN_BUF_BLOCK
] & 0xfff) |
569 (s
->addr
[ONEN_BUF_BLOCK
] >> 15 ? s
->density_mask
: 0))
570 << (BLOCK_SHIFT
- 9);
571 if (onenand_erase(s
, sec
, 1 << (BLOCK_SHIFT
- 9)))
572 s
->status
|= ONEN_ERR_CMD
| ONEN_ERR_ERASE
;
574 s
->intstatus
|= ONEN_INT
| ONEN_INT_ERASE
;
576 case 0xb0: /* Erase suspend */
578 case 0x30: /* Erase resume */
579 s
->intstatus
|= ONEN_INT
| ONEN_INT_ERASE
;
582 case 0xf0: /* Reset NAND Flash core */
585 case 0xf3: /* Reset OneNAND */
589 case 0x65: /* OTP Access */
590 s
->intstatus
|= ONEN_INT
;
593 s
->secs_cur
= 1 << (BLOCK_SHIFT
- 9);
594 s
->addr
[ONEN_BUF_BLOCK
] = 0;
599 s
->status
|= ONEN_ERR_CMD
;
600 s
->intstatus
|= ONEN_INT
;
601 qemu_log_mask(LOG_GUEST_ERROR
, "unknown OneNAND command %x\n",
605 onenand_intr_update(s
);
608 static uint64_t onenand_read(void *opaque
, hwaddr addr
,
611 OneNANDState
*s
= (OneNANDState
*) opaque
;
612 int offset
= addr
>> s
->shift
;
615 case 0x0000 ... 0xbffe:
616 return lduw_le_p(s
->boot
[0] + addr
);
618 case 0xf000: /* Manufacturer ID */
620 case 0xf001: /* Device ID */
622 case 0xf002: /* Version ID */
624 /* TODO: get the following values from a real chip! */
625 case 0xf003: /* Data Buffer size */
626 return 1 << PAGE_SHIFT
;
627 case 0xf004: /* Boot Buffer size */
629 case 0xf005: /* Amount of buffers */
631 case 0xf006: /* Technology */
634 case 0xf100 ... 0xf107: /* Start addresses */
635 return s
->addr
[offset
- 0xf100];
637 case 0xf200: /* Start buffer */
638 return (s
->bufaddr
<< 8) | ((s
->count
- 1) & (1 << (PAGE_SHIFT
- 10)));
640 case 0xf220: /* Command */
642 case 0xf221: /* System Configuration 1 */
643 return s
->config
[0] & 0xffe0;
644 case 0xf222: /* System Configuration 2 */
647 case 0xf240: /* Controller Status */
649 case 0xf241: /* Interrupt */
651 case 0xf24c: /* Unlock Start Block Address */
652 return s
->unladdr
[0];
653 case 0xf24d: /* Unlock End Block Address */
654 return s
->unladdr
[1];
655 case 0xf24e: /* Write Protection Status */
658 case 0xff00: /* ECC Status */
660 case 0xff01: /* ECC Result of main area data */
661 case 0xff02: /* ECC Result of spare area data */
662 case 0xff03: /* ECC Result of main area data */
663 case 0xff04: /* ECC Result of spare area data */
664 qemu_log_mask(LOG_UNIMP
,
665 "onenand: ECC result registers unimplemented\n");
669 qemu_log_mask(LOG_GUEST_ERROR
, "read of unknown OneNAND register 0x%x\n",
674 static void onenand_write(void *opaque
, hwaddr addr
,
675 uint64_t value
, unsigned size
)
677 OneNANDState
*s
= (OneNANDState
*) opaque
;
678 int offset
= addr
>> s
->shift
;
682 case 0x0000 ... 0x01ff:
683 case 0x8000 ... 0x800f:
687 if (value
== 0x0000) {
688 SETADDR(ONEN_BUF_BLOCK
, ONEN_BUF_PAGE
)
689 onenand_load_main(s
, sec
,
690 1 << (PAGE_SHIFT
- 9), s
->data
[0][0]);
691 s
->addr
[ONEN_BUF_PAGE
] += 4;
692 s
->addr
[ONEN_BUF_PAGE
] &= 0xff;
698 case 0x00f0: /* Reset OneNAND */
702 case 0x00e0: /* Load Data into Buffer */
706 case 0x0090: /* Read Identification Data */
707 memset(s
->boot
[0], 0, 3 << s
->shift
);
708 s
->boot
[0][0 << s
->shift
] = s
->id
.man
& 0xff;
709 s
->boot
[0][1 << s
->shift
] = s
->id
.dev
& 0xff;
710 s
->boot
[0][2 << s
->shift
] = s
->wpstatus
& 0xff;
714 qemu_log_mask(LOG_GUEST_ERROR
,
715 "unknown OneNAND boot command %" PRIx64
"\n",
720 case 0xf100 ... 0xf107: /* Start addresses */
721 s
->addr
[offset
- 0xf100] = value
;
724 case 0xf200: /* Start buffer */
725 s
->bufaddr
= (value
>> 8) & 0xf;
726 if (PAGE_SHIFT
== 11)
727 s
->count
= (value
& 3) ?: 4;
728 else if (PAGE_SHIFT
== 10)
729 s
->count
= (value
& 1) ?: 2;
732 case 0xf220: /* Command */
733 if (s
->intstatus
& (1 << 15))
738 case 0xf221: /* System Configuration 1 */
739 s
->config
[0] = value
;
740 onenand_intr_update(s
);
741 qemu_set_irq(s
->rdy
, (s
->config
[0] >> 7) & 1);
743 case 0xf222: /* System Configuration 2 */
744 s
->config
[1] = value
;
747 case 0xf241: /* Interrupt */
748 s
->intstatus
&= value
;
749 if ((1 << 15) & ~s
->intstatus
)
750 s
->status
&= ~(ONEN_ERR_CMD
| ONEN_ERR_ERASE
|
751 ONEN_ERR_PROG
| ONEN_ERR_LOAD
);
752 onenand_intr_update(s
);
754 case 0xf24c: /* Unlock Start Block Address */
755 s
->unladdr
[0] = value
& (s
->blocks
- 1);
756 /* For some reason we have to set the end address to by default
757 * be same as start because the software forgets to write anything
759 s
->unladdr
[1] = value
& (s
->blocks
- 1);
761 case 0xf24d: /* Unlock End Block Address */
762 s
->unladdr
[1] = value
& (s
->blocks
- 1);
766 qemu_log_mask(LOG_GUEST_ERROR
,
767 "write to unknown OneNAND register 0x%x\n",
772 static const MemoryRegionOps onenand_ops
= {
773 .read
= onenand_read
,
774 .write
= onenand_write
,
775 .endianness
= DEVICE_NATIVE_ENDIAN
,
778 static void onenand_realize(DeviceState
*dev
, Error
**errp
)
780 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
781 OneNANDState
*s
= ONE_NAND(dev
);
782 uint32_t size
= 1 << (24 + ((s
->id
.dev
>> 4) & 7));
784 Error
*local_err
= NULL
;
786 s
->base
= (hwaddr
)-1;
788 s
->blocks
= size
>> BLOCK_SHIFT
;
790 s
->blockwp
= g_malloc(s
->blocks
);
791 s
->density_mask
= (s
->id
.dev
& 0x08)
792 ? (1 << (6 + ((s
->id
.dev
>> 4) & 7))) : 0;
793 memory_region_init_io(&s
->iomem
, OBJECT(s
), &onenand_ops
, s
, "onenand",
794 0x10000 << s
->shift
);
796 s
->image
= memset(g_malloc(size
+ (size
>> 5)),
797 0xff, size
+ (size
>> 5));
799 if (blk_is_read_only(s
->blk
)) {
800 error_setg(errp
, "Can't use a read-only drive");
803 blk_set_perm(s
->blk
, BLK_PERM_CONSISTENT_READ
| BLK_PERM_WRITE
,
804 BLK_PERM_ALL
, &local_err
);
806 error_propagate(errp
, local_err
);
811 s
->otp
= memset(g_malloc((64 + 2) << PAGE_SHIFT
),
812 0xff, (64 + 2) << PAGE_SHIFT
);
813 memory_region_init_ram_nomigrate(&s
->ram
, OBJECT(s
), "onenand.ram",
814 0xc000 << s
->shift
, &error_fatal
);
815 vmstate_register_ram_global(&s
->ram
);
816 ram
= memory_region_get_ram_ptr(&s
->ram
);
817 s
->boot
[0] = ram
+ (0x0000 << s
->shift
);
818 s
->boot
[1] = ram
+ (0x8000 << s
->shift
);
819 s
->data
[0][0] = ram
+ ((0x0200 + (0 << (PAGE_SHIFT
- 1))) << s
->shift
);
820 s
->data
[0][1] = ram
+ ((0x8010 + (0 << (PAGE_SHIFT
- 6))) << s
->shift
);
821 s
->data
[1][0] = ram
+ ((0x0200 + (1 << (PAGE_SHIFT
- 1))) << s
->shift
);
822 s
->data
[1][1] = ram
+ ((0x8010 + (1 << (PAGE_SHIFT
- 6))) << s
->shift
);
823 onenand_mem_setup(s
);
824 sysbus_init_irq(sbd
, &s
->intr
);
825 sysbus_init_mmio(sbd
, &s
->container
);
826 vmstate_register(VMSTATE_IF(dev
),
827 ((s
->shift
& 0x7f) << 24)
828 | ((s
->id
.man
& 0xff) << 16)
829 | ((s
->id
.dev
& 0xff) << 8)
830 | (s
->id
.ver
& 0xff),
831 &vmstate_onenand
, s
);
834 static Property onenand_properties
[] = {
835 DEFINE_PROP_UINT16("manufacturer_id", OneNANDState
, id
.man
, 0),
836 DEFINE_PROP_UINT16("device_id", OneNANDState
, id
.dev
, 0),
837 DEFINE_PROP_UINT16("version_id", OneNANDState
, id
.ver
, 0),
838 DEFINE_PROP_INT32("shift", OneNANDState
, shift
, 0),
839 DEFINE_PROP_DRIVE("drive", OneNANDState
, blk
),
840 DEFINE_PROP_END_OF_LIST(),
843 static void onenand_class_init(ObjectClass
*klass
, void *data
)
845 DeviceClass
*dc
= DEVICE_CLASS(klass
);
847 dc
->realize
= onenand_realize
;
848 dc
->reset
= onenand_system_reset
;
849 device_class_set_props(dc
, onenand_properties
);
852 static const TypeInfo onenand_info
= {
853 .name
= TYPE_ONE_NAND
,
854 .parent
= TYPE_SYS_BUS_DEVICE
,
855 .instance_size
= sizeof(OneNANDState
),
856 .class_init
= onenand_class_init
,
859 static void onenand_register_types(void)
861 type_register_static(&onenand_info
);
864 void *onenand_raw_otp(DeviceState
*onenand_device
)
866 OneNANDState
*s
= ONE_NAND(onenand_device
);
871 type_init(onenand_register_types
)