2 * QEMU PowerPC sPAPR IRQ interface
4 * Copyright (c) 2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
15 #include "hw/ppc/spapr.h"
16 #include "hw/ppc/spapr_cpu_core.h"
17 #include "hw/ppc/spapr_xive.h"
18 #include "hw/ppc/xics.h"
19 #include "hw/ppc/xics_spapr.h"
20 #include "hw/qdev-properties.h"
21 #include "cpu-models.h"
22 #include "sysemu/kvm.h"
26 void spapr_irq_msi_init(SpaprMachineState
*spapr
, uint32_t nr_msis
)
28 spapr
->irq_map_nr
= nr_msis
;
29 spapr
->irq_map
= bitmap_new(spapr
->irq_map_nr
);
32 int spapr_irq_msi_alloc(SpaprMachineState
*spapr
, uint32_t num
, bool align
,
38 * The 'align_mask' parameter of bitmap_find_next_zero_area()
39 * should be one less than a power of 2; 0 means no
40 * alignment. Adapt the 'align' value of the former allocator
41 * to fit the requirements of bitmap_find_next_zero_area()
45 irq
= bitmap_find_next_zero_area(spapr
->irq_map
, spapr
->irq_map_nr
, 0, num
,
47 if (irq
== spapr
->irq_map_nr
) {
48 error_setg(errp
, "can't find a free %d-IRQ block", num
);
52 bitmap_set(spapr
->irq_map
, irq
, num
);
54 return irq
+ SPAPR_IRQ_MSI
;
57 void spapr_irq_msi_free(SpaprMachineState
*spapr
, int irq
, uint32_t num
)
59 bitmap_clear(spapr
->irq_map
, irq
- SPAPR_IRQ_MSI
, num
);
62 static void spapr_irq_init_kvm(SpaprMachineState
*spapr
,
63 SpaprIrq
*irq
, Error
**errp
)
65 MachineState
*machine
= MACHINE(spapr
);
66 Error
*local_err
= NULL
;
68 if (kvm_enabled() && machine_kernel_irqchip_allowed(machine
)) {
69 irq
->init_kvm(spapr
, &local_err
);
70 if (local_err
&& machine_kernel_irqchip_required(machine
)) {
71 error_prepend(&local_err
,
72 "kernel_irqchip requested but unavailable: ");
73 error_propagate(errp
, local_err
);
82 * We failed to initialize the KVM device, fallback to
85 error_prepend(&local_err
, "kernel_irqchip allowed but unavailable: ");
86 error_append_hint(&local_err
, "Falling back to kernel-irqchip=off\n");
87 warn_report_err(local_err
);
95 static void spapr_irq_init_xics(SpaprMachineState
*spapr
, Error
**errp
)
98 Error
*local_err
= NULL
;
100 obj
= object_new(TYPE_ICS_SPAPR
);
101 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
102 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
104 object_property_set_int(obj
, spapr
->irq
->nr_xirqs
,
105 "nr-irqs", &error_fatal
);
106 object_property_set_bool(obj
, true, "realized", &local_err
);
108 error_propagate(errp
, local_err
);
112 spapr
->ics
= ICS_SPAPR(obj
);
115 static int spapr_irq_claim_xics(SpaprMachineState
*spapr
, int irq
, bool lsi
,
118 ICSState
*ics
= spapr
->ics
;
122 if (!ics_valid_irq(ics
, irq
)) {
123 error_setg(errp
, "IRQ %d is invalid", irq
);
127 if (!ics_irq_free(ics
, irq
- ics
->offset
)) {
128 error_setg(errp
, "IRQ %d is not free", irq
);
132 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
136 static void spapr_irq_free_xics(SpaprMachineState
*spapr
, int irq
, int num
)
138 ICSState
*ics
= spapr
->ics
;
139 uint32_t srcno
= irq
- ics
->offset
;
142 if (ics_valid_irq(ics
, irq
)) {
143 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
144 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
149 static void spapr_irq_print_info_xics(SpaprMachineState
*spapr
, Monitor
*mon
)
154 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
156 icp_pic_print_info(spapr_cpu_state(cpu
)->icp
, mon
);
159 ics_pic_print_info(spapr
->ics
, mon
);
162 static void spapr_irq_cpu_intc_create_xics(SpaprMachineState
*spapr
,
163 PowerPCCPU
*cpu
, Error
**errp
)
165 Error
*local_err
= NULL
;
167 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
169 obj
= icp_create(OBJECT(cpu
), TYPE_ICP
, XICS_FABRIC(spapr
),
172 error_propagate(errp
, local_err
);
176 spapr_cpu
->icp
= ICP(obj
);
179 static int spapr_irq_post_load_xics(SpaprMachineState
*spapr
, int version_id
)
181 if (!kvm_irqchip_in_kernel()) {
184 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
185 icp_resend(spapr_cpu_state(cpu
)->icp
);
191 static void spapr_irq_set_irq_xics(void *opaque
, int irq
, int val
)
193 SpaprMachineState
*spapr
= opaque
;
194 uint32_t srcno
= irq
- spapr
->ics
->offset
;
196 ics_set_irq(spapr
->ics
, srcno
, val
);
199 static void spapr_irq_reset_xics(SpaprMachineState
*spapr
, Error
**errp
)
201 Error
*local_err
= NULL
;
203 spapr_irq_init_kvm(spapr
, &spapr_irq_xics
, &local_err
);
205 error_propagate(errp
, local_err
);
210 static void spapr_irq_init_kvm_xics(SpaprMachineState
*spapr
, Error
**errp
)
213 xics_kvm_connect(spapr
, errp
);
217 SpaprIrq spapr_irq_xics
= {
218 .nr_xirqs
= SPAPR_NR_XIRQS
,
219 .nr_msis
= SPAPR_NR_MSIS
,
220 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
222 .init
= spapr_irq_init_xics
,
223 .claim
= spapr_irq_claim_xics
,
224 .free
= spapr_irq_free_xics
,
225 .print_info
= spapr_irq_print_info_xics
,
226 .dt_populate
= spapr_dt_xics
,
227 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
228 .post_load
= spapr_irq_post_load_xics
,
229 .reset
= spapr_irq_reset_xics
,
230 .set_irq
= spapr_irq_set_irq_xics
,
231 .init_kvm
= spapr_irq_init_kvm_xics
,
237 static void spapr_irq_init_xive(SpaprMachineState
*spapr
, Error
**errp
)
239 uint32_t nr_servers
= spapr_max_server_number(spapr
);
243 dev
= qdev_create(NULL
, TYPE_SPAPR_XIVE
);
244 qdev_prop_set_uint32(dev
, "nr-irqs",
245 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
247 * 8 XIVE END structures per CPU. One for each available priority
249 qdev_prop_set_uint32(dev
, "nr-ends", nr_servers
<< 3);
250 qdev_init_nofail(dev
);
252 spapr
->xive
= SPAPR_XIVE(dev
);
254 /* Enable the CPU IPIs */
255 for (i
= 0; i
< nr_servers
; ++i
) {
256 spapr_xive_irq_claim(spapr
->xive
, SPAPR_IRQ_IPI
+ i
, false);
259 spapr_xive_hcall_init(spapr
);
262 static int spapr_irq_claim_xive(SpaprMachineState
*spapr
, int irq
, bool lsi
,
265 if (!spapr_xive_irq_claim(spapr
->xive
, irq
, lsi
)) {
266 error_setg(errp
, "IRQ %d is invalid", irq
);
272 static void spapr_irq_free_xive(SpaprMachineState
*spapr
, int irq
, int num
)
276 for (i
= irq
; i
< irq
+ num
; ++i
) {
277 spapr_xive_irq_free(spapr
->xive
, i
);
281 static void spapr_irq_print_info_xive(SpaprMachineState
*spapr
,
287 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
289 xive_tctx_pic_print_info(spapr_cpu_state(cpu
)->tctx
, mon
);
292 spapr_xive_pic_print_info(spapr
->xive
, mon
);
295 static void spapr_irq_cpu_intc_create_xive(SpaprMachineState
*spapr
,
296 PowerPCCPU
*cpu
, Error
**errp
)
298 Error
*local_err
= NULL
;
300 SpaprCpuState
*spapr_cpu
= spapr_cpu_state(cpu
);
302 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(spapr
->xive
), &local_err
);
304 error_propagate(errp
, local_err
);
308 spapr_cpu
->tctx
= XIVE_TCTX(obj
);
311 * (TCG) Early setting the OS CAM line for hotplugged CPUs as they
312 * don't beneficiate from the reset of the XIVE IRQ backend
314 spapr_xive_set_tctx_os_cam(spapr_cpu
->tctx
);
317 static int spapr_irq_post_load_xive(SpaprMachineState
*spapr
, int version_id
)
319 return spapr_xive_post_load(spapr
->xive
, version_id
);
322 static void spapr_irq_reset_xive(SpaprMachineState
*spapr
, Error
**errp
)
325 Error
*local_err
= NULL
;
328 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
330 /* (TCG) Set the OS CAM line of the thread interrupt context. */
331 spapr_xive_set_tctx_os_cam(spapr_cpu_state(cpu
)->tctx
);
334 spapr_irq_init_kvm(spapr
, &spapr_irq_xive
, &local_err
);
336 error_propagate(errp
, local_err
);
340 /* Activate the XIVE MMIOs */
341 spapr_xive_mmio_set_enabled(spapr
->xive
, true);
344 static void spapr_irq_set_irq_xive(void *opaque
, int irq
, int val
)
346 SpaprMachineState
*spapr
= opaque
;
348 if (kvm_irqchip_in_kernel()) {
349 kvmppc_xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
351 xive_source_set_irq(&spapr
->xive
->source
, irq
, val
);
355 static void spapr_irq_init_kvm_xive(SpaprMachineState
*spapr
, Error
**errp
)
358 kvmppc_xive_connect(spapr
->xive
, errp
);
362 SpaprIrq spapr_irq_xive
= {
363 .nr_xirqs
= SPAPR_NR_XIRQS
,
364 .nr_msis
= SPAPR_NR_MSIS
,
365 .ov5
= SPAPR_OV5_XIVE_EXPLOIT
,
367 .init
= spapr_irq_init_xive
,
368 .claim
= spapr_irq_claim_xive
,
369 .free
= spapr_irq_free_xive
,
370 .print_info
= spapr_irq_print_info_xive
,
371 .dt_populate
= spapr_dt_xive
,
372 .cpu_intc_create
= spapr_irq_cpu_intc_create_xive
,
373 .post_load
= spapr_irq_post_load_xive
,
374 .reset
= spapr_irq_reset_xive
,
375 .set_irq
= spapr_irq_set_irq_xive
,
376 .init_kvm
= spapr_irq_init_kvm_xive
,
380 * Dual XIVE and XICS IRQ backend.
382 * Both interrupt mode, XIVE and XICS, objects are created but the
383 * machine starts in legacy interrupt mode (XICS). It can be changed
384 * by the CAS negotiation process and, in that case, the new mode is
385 * activated after an extra machine reset.
389 * Returns the sPAPR IRQ backend negotiated by CAS. XICS is the
392 static SpaprIrq
*spapr_irq_current(SpaprMachineState
*spapr
)
394 return spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
) ?
395 &spapr_irq_xive
: &spapr_irq_xics
;
398 static void spapr_irq_init_dual(SpaprMachineState
*spapr
, Error
**errp
)
400 Error
*local_err
= NULL
;
402 spapr_irq_xics
.init(spapr
, &local_err
);
404 error_propagate(errp
, local_err
);
408 spapr_irq_xive
.init(spapr
, &local_err
);
410 error_propagate(errp
, local_err
);
415 static int spapr_irq_claim_dual(SpaprMachineState
*spapr
, int irq
, bool lsi
,
418 Error
*local_err
= NULL
;
421 ret
= spapr_irq_xics
.claim(spapr
, irq
, lsi
, &local_err
);
423 error_propagate(errp
, local_err
);
427 ret
= spapr_irq_xive
.claim(spapr
, irq
, lsi
, &local_err
);
429 error_propagate(errp
, local_err
);
436 static void spapr_irq_free_dual(SpaprMachineState
*spapr
, int irq
, int num
)
438 spapr_irq_xics
.free(spapr
, irq
, num
);
439 spapr_irq_xive
.free(spapr
, irq
, num
);
442 static void spapr_irq_print_info_dual(SpaprMachineState
*spapr
, Monitor
*mon
)
444 spapr_irq_current(spapr
)->print_info(spapr
, mon
);
447 static void spapr_irq_dt_populate_dual(SpaprMachineState
*spapr
,
448 uint32_t nr_servers
, void *fdt
,
451 spapr_irq_current(spapr
)->dt_populate(spapr
, nr_servers
, fdt
, phandle
);
454 static void spapr_irq_cpu_intc_create_dual(SpaprMachineState
*spapr
,
455 PowerPCCPU
*cpu
, Error
**errp
)
457 Error
*local_err
= NULL
;
459 spapr_irq_xive
.cpu_intc_create(spapr
, cpu
, &local_err
);
461 error_propagate(errp
, local_err
);
465 spapr_irq_xics
.cpu_intc_create(spapr
, cpu
, errp
);
468 static int spapr_irq_post_load_dual(SpaprMachineState
*spapr
, int version_id
)
471 * Force a reset of the XIVE backend after migration. The machine
472 * defaults to XICS at startup.
474 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
475 if (kvm_irqchip_in_kernel()) {
476 xics_kvm_disconnect(spapr
, &error_fatal
);
478 spapr_irq_xive
.reset(spapr
, &error_fatal
);
481 return spapr_irq_current(spapr
)->post_load(spapr
, version_id
);
484 static void spapr_irq_reset_dual(SpaprMachineState
*spapr
, Error
**errp
)
486 Error
*local_err
= NULL
;
489 * Deactivate the XIVE MMIOs. The XIVE backend will reenable them
492 spapr_xive_mmio_set_enabled(spapr
->xive
, false);
494 /* Destroy all KVM devices */
495 if (kvm_irqchip_in_kernel()) {
496 xics_kvm_disconnect(spapr
, &local_err
);
498 error_propagate(errp
, local_err
);
499 error_prepend(errp
, "KVM XICS disconnect failed: ");
502 kvmppc_xive_disconnect(spapr
->xive
, &local_err
);
504 error_propagate(errp
, local_err
);
505 error_prepend(errp
, "KVM XIVE disconnect failed: ");
510 spapr_irq_current(spapr
)->reset(spapr
, errp
);
513 static void spapr_irq_set_irq_dual(void *opaque
, int irq
, int val
)
515 SpaprMachineState
*spapr
= opaque
;
517 spapr_irq_current(spapr
)->set_irq(spapr
, irq
, val
);
521 * Define values in sync with the XIVE and XICS backend
523 SpaprIrq spapr_irq_dual
= {
524 .nr_xirqs
= SPAPR_NR_XIRQS
,
525 .nr_msis
= SPAPR_NR_MSIS
,
526 .ov5
= SPAPR_OV5_XIVE_BOTH
,
528 .init
= spapr_irq_init_dual
,
529 .claim
= spapr_irq_claim_dual
,
530 .free
= spapr_irq_free_dual
,
531 .print_info
= spapr_irq_print_info_dual
,
532 .dt_populate
= spapr_irq_dt_populate_dual
,
533 .cpu_intc_create
= spapr_irq_cpu_intc_create_dual
,
534 .post_load
= spapr_irq_post_load_dual
,
535 .reset
= spapr_irq_reset_dual
,
536 .set_irq
= spapr_irq_set_irq_dual
,
537 .init_kvm
= NULL
, /* should not be used */
541 static void spapr_irq_check(SpaprMachineState
*spapr
, Error
**errp
)
543 MachineState
*machine
= MACHINE(spapr
);
546 * Sanity checks on non-P9 machines. On these, XIVE is not
547 * advertised, see spapr_dt_ov5_platform_support()
549 if (!ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
550 0, spapr
->max_compat_pvr
)) {
552 * If the 'dual' interrupt mode is selected, force XICS as CAS
553 * negotiation is useless.
555 if (spapr
->irq
== &spapr_irq_dual
) {
556 spapr
->irq
= &spapr_irq_xics
;
561 * Non-P9 machines using only XIVE is a bogus setup. We have two
562 * scenarios to take into account because of the compat mode:
564 * 1. POWER7/8 machines should fail to init later on when creating
565 * the XIVE interrupt presenters because a POWER9 exception
568 * 2. POWER9 machines using the POWER8 compat mode won't fail and
569 * will let the OS boot with a partial XIVE setup : DT
570 * properties but no hcalls.
572 * To cover both and not confuse the OS, add an early failure in
575 if (spapr
->irq
== &spapr_irq_xive
) {
576 error_setg(errp
, "XIVE-only machines require a POWER9 CPU");
582 * On a POWER9 host, some older KVM XICS devices cannot be destroyed and
583 * re-created. Detect that early to avoid QEMU to exit later when the
587 spapr
->irq
== &spapr_irq_dual
&&
588 machine_kernel_irqchip_required(machine
) &&
589 xics_kvm_has_broken_disconnect(spapr
)) {
590 error_setg(errp
, "KVM is too old to support ic-mode=dual,kernel-irqchip=on");
596 * sPAPR IRQ frontend routines for devices
598 void spapr_irq_init(SpaprMachineState
*spapr
, Error
**errp
)
600 MachineState
*machine
= MACHINE(spapr
);
601 Error
*local_err
= NULL
;
603 if (machine_kernel_irqchip_split(machine
)) {
604 error_setg(errp
, "kernel_irqchip split mode not supported on pseries");
608 if (!kvm_enabled() && machine_kernel_irqchip_required(machine
)) {
610 "kernel_irqchip requested but only available with KVM");
614 spapr_irq_check(spapr
, &local_err
);
616 error_propagate(errp
, local_err
);
620 /* Initialize the MSI IRQ allocator. */
621 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
622 spapr_irq_msi_init(spapr
, spapr
->irq
->nr_msis
);
625 spapr
->irq
->init(spapr
, errp
);
627 spapr
->qirqs
= qemu_allocate_irqs(spapr
->irq
->set_irq
, spapr
,
628 spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
);
631 int spapr_irq_claim(SpaprMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
633 return spapr
->irq
->claim(spapr
, irq
, lsi
, errp
);
636 void spapr_irq_free(SpaprMachineState
*spapr
, int irq
, int num
)
638 spapr
->irq
->free(spapr
, irq
, num
);
641 qemu_irq
spapr_qirq(SpaprMachineState
*spapr
, int irq
)
644 * This interface is basically for VIO and PHB devices to find the
645 * right qemu_irq to manipulate, so we only allow access to the
646 * external irqs for now. Currently anything which needs to
647 * access the IPIs most naturally gets there via the guest side
648 * interfaces, we can change this if we need to in future.
650 assert(irq
>= SPAPR_XIRQ_BASE
);
651 assert(irq
< (spapr
->irq
->nr_xirqs
+ SPAPR_XIRQ_BASE
));
654 assert(ics_valid_irq(spapr
->ics
, irq
));
657 assert(irq
< spapr
->xive
->nr_irqs
);
658 assert(xive_eas_is_valid(&spapr
->xive
->eat
[irq
]));
661 return spapr
->qirqs
[irq
];
664 int spapr_irq_post_load(SpaprMachineState
*spapr
, int version_id
)
666 return spapr
->irq
->post_load(spapr
, version_id
);
669 void spapr_irq_reset(SpaprMachineState
*spapr
, Error
**errp
)
671 assert(!spapr
->irq_map
|| bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
));
673 if (spapr
->irq
->reset
) {
674 spapr
->irq
->reset(spapr
, errp
);
678 int spapr_irq_get_phandle(SpaprMachineState
*spapr
, void *fdt
, Error
**errp
)
680 const char *nodename
= "interrupt-controller";
683 offset
= fdt_subnode_offset(fdt
, 0, nodename
);
685 error_setg(errp
, "Can't find node \"%s\": %s",
686 nodename
, fdt_strerror(offset
));
690 phandle
= fdt_get_phandle(fdt
, offset
);
692 error_setg(errp
, "Can't get phandle of node \"%s\"", nodename
);
700 * XICS legacy routines - to deprecate one day
703 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
707 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
708 if (num
> (ics
->nr_irqs
- first
)) {
711 for (i
= first
; i
< first
+ num
; ++i
) {
712 if (!ics_irq_free(ics
, i
)) {
716 if (i
== (first
+ num
)) {
724 int spapr_irq_find(SpaprMachineState
*spapr
, int num
, bool align
, Error
**errp
)
726 ICSState
*ics
= spapr
->ics
;
732 * MSIMesage::data is used for storing VIRQ so
733 * it has to be aligned to num to support multiple
734 * MSI vectors. MSI-X is not affected by this.
735 * The hint is used for the first IRQ, the rest should
736 * be allocated continuously.
739 assert((num
== 1) || (num
== 2) || (num
== 4) ||
740 (num
== 8) || (num
== 16) || (num
== 32));
741 first
= ics_find_free_block(ics
, num
, num
);
743 first
= ics_find_free_block(ics
, num
, 1);
747 error_setg(errp
, "can't find a free %d-IRQ block", num
);
751 return first
+ ics
->offset
;
754 #define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
756 SpaprIrq spapr_irq_xics_legacy
= {
757 .nr_xirqs
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
758 .nr_msis
= SPAPR_IRQ_XICS_LEGACY_NR_XIRQS
,
759 .ov5
= SPAPR_OV5_XIVE_LEGACY
,
761 .init
= spapr_irq_init_xics
,
762 .claim
= spapr_irq_claim_xics
,
763 .free
= spapr_irq_free_xics
,
764 .print_info
= spapr_irq_print_info_xics
,
765 .dt_populate
= spapr_dt_xics
,
766 .cpu_intc_create
= spapr_irq_cpu_intc_create_xics
,
767 .post_load
= spapr_irq_post_load_xics
,
768 .reset
= spapr_irq_reset_xics
,
769 .set_irq
= spapr_irq_set_irq_xics
,
770 .init_kvm
= spapr_irq_init_kvm_xics
,