tests/libqos/pci.c

   1 /*
   2  * libqos PCI bindings
   3  *
   4  * Copyright IBM, Corp. 2012-2013
   5  *
   6  * Authors:
   7  *  Anthony Liguori   <aliguori@us.ibm.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "libqos/pci.h"
  15
  16 #include "hw/pci/pci_regs.h"
  17 #include "qemu/host-utils.h"
  18 #include "libqos/qgraph.h"
  19
  20 void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
  21                          void (*func)(QPCIDevice *dev, int devfn, void *data),
  22                          void *data)
  23 {
  24     int slot;
  25
  26     for (slot = 0; slot < 32; slot++) {
  27         int fn;
  28
  29         for (fn = 0; fn < 8; fn++) {
  30             QPCIDevice *dev;
  31
  32             dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
  33             if (!dev) {
  34                 continue;
  35             }
  36
  37             if (vendor_id != -1 &&
  38                 qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
  39                 g_free(dev);
  40                 continue;
  41             }
  42
  43             if (device_id != -1 &&
  44                 qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
  45                 g_free(dev);
  46                 continue;
  47             }
  48
  49             func(dev, QPCI_DEVFN(slot, fn), data);
  50         }
  51     }
  52 }
  53
  54 static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn)
  55 {
  56     g_assert(dev);
  57
  58     dev->bus = bus;
  59     dev->devfn = devfn;
  60 }
  61
  62 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
  63 {
  64     QPCIDevice *dev;
  65
  66     dev = g_malloc0(sizeof(*dev));
  67     qpci_device_set(dev, bus, devfn);
  68
  69     if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
  70         g_free(dev);
  71         return NULL;
  72     }
  73
  74     return dev;
  75 }
  76
  77 void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr)
  78 {
  79     uint16_t vendor_id, device_id;
  80
  81     qpci_device_set(dev, bus, addr->devfn);
  82     vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
  83     device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
  84     g_assert(!addr->vendor_id || vendor_id == addr->vendor_id);
  85     g_assert(!addr->device_id || device_id == addr->device_id);
  86 }
  87
  88 void qpci_device_enable(QPCIDevice *dev)
  89 {
  90     uint16_t cmd;
  91
  92     /* FIXME -- does this need to be a bus callout? */
  93     cmd = qpci_config_readw(dev, PCI_COMMAND);
  94     cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  95     qpci_config_writew(dev, PCI_COMMAND, cmd);
  96
  97     /* Verify the bits are now set. */
  98     cmd = qpci_config_readw(dev, PCI_COMMAND);
  99     g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
 100     g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
 101     g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
 102 }
 103
 104 uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id)
 105 {
 106     uint8_t cap;
 107     uint8_t addr = qpci_config_readb(dev, PCI_CAPABILITY_LIST);
 108
 109     do {
 110         cap = qpci_config_readb(dev, addr);
 111         if (cap != id) {
 112             addr = qpci_config_readb(dev, addr + PCI_CAP_LIST_NEXT);
 113         }
 114     } while (cap != id && addr != 0);
 115
 116     return addr;
 117 }
 118
 119 void qpci_msix_enable(QPCIDevice *dev)
 120 {
 121     uint8_t addr;
 122     uint16_t val;
 123     uint32_t table;
 124     uint8_t bir_table;
 125     uint8_t bir_pba;
 126
 127     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 128     g_assert_cmphex(addr, !=, 0);
 129
 130     val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 131     qpci_config_writew(dev, addr + PCI_MSIX_FLAGS, val | PCI_MSIX_FLAGS_ENABLE);
 132
 133     table = qpci_config_readl(dev, addr + PCI_MSIX_TABLE);
 134     bir_table = table & PCI_MSIX_FLAGS_BIRMASK;
 135     dev->msix_table_bar = qpci_iomap(dev, bir_table, NULL);
 136     dev->msix_table_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
 137
 138     table = qpci_config_readl(dev, addr + PCI_MSIX_PBA);
 139     bir_pba = table & PCI_MSIX_FLAGS_BIRMASK;
 140     if (bir_pba != bir_table) {
 141         dev->msix_pba_bar = qpci_iomap(dev, bir_pba, NULL);
 142     } else {
 143         dev->msix_pba_bar = dev->msix_table_bar;
 144     }
 145     dev->msix_pba_off = table & ~PCI_MSIX_FLAGS_BIRMASK;
 146
 147     dev->msix_enabled = true;
 148 }
 149
 150 void qpci_msix_disable(QPCIDevice *dev)
 151 {
 152     uint8_t addr;
 153     uint16_t val;
 154
 155     g_assert(dev->msix_enabled);
 156     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 157     g_assert_cmphex(addr, !=, 0);
 158     val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 159     qpci_config_writew(dev, addr + PCI_MSIX_FLAGS,
 160                                                 val & ~PCI_MSIX_FLAGS_ENABLE);
 161
 162     if (dev->msix_pba_bar.addr != dev->msix_table_bar.addr) {
 163         qpci_iounmap(dev, dev->msix_pba_bar);
 164     }
 165     qpci_iounmap(dev, dev->msix_table_bar);
 166
 167     dev->msix_enabled = 0;
 168     dev->msix_table_off = 0;
 169     dev->msix_pba_off = 0;
 170 }
 171
 172 bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
 173 {
 174     uint32_t pba_entry;
 175     uint8_t bit_n = entry % 32;
 176     uint64_t  off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
 177
 178     g_assert(dev->msix_enabled);
 179     pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
 180     qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
 181                    pba_entry & ~(1 << bit_n));
 182     return (pba_entry & (1 << bit_n)) != 0;
 183 }
 184
 185 bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
 186 {
 187     uint8_t addr;
 188     uint16_t val;
 189     uint64_t vector_off = dev->msix_table_off + entry * PCI_MSIX_ENTRY_SIZE;
 190
 191     g_assert(dev->msix_enabled);
 192     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 193     g_assert_cmphex(addr, !=, 0);
 194     val = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 195
 196     if (val & PCI_MSIX_FLAGS_MASKALL) {
 197         return true;
 198     } else {
 199         return (qpci_io_readl(dev, dev->msix_table_bar,
 200                               vector_off + PCI_MSIX_ENTRY_VECTOR_CTRL)
 201                 & PCI_MSIX_ENTRY_CTRL_MASKBIT) != 0;
 202     }
 203 }
 204
 205 uint16_t qpci_msix_table_size(QPCIDevice *dev)
 206 {
 207     uint8_t addr;
 208     uint16_t control;
 209
 210     addr = qpci_find_capability(dev, PCI_CAP_ID_MSIX);
 211     g_assert_cmphex(addr, !=, 0);
 212
 213     control = qpci_config_readw(dev, addr + PCI_MSIX_FLAGS);
 214     return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
 215 }
 216
 217 uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
 218 {
 219     return dev->bus->config_readb(dev->bus, dev->devfn, offset);
 220 }
 221
 222 uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
 223 {
 224     return dev->bus->config_readw(dev->bus, dev->devfn, offset);
 225 }
 226
 227 uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
 228 {
 229     return dev->bus->config_readl(dev->bus, dev->devfn, offset);
 230 }
 231
 232
 233 void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
 234 {
 235     dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
 236 }
 237
 238 void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
 239 {
 240     dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
 241 }
 242
 243 void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
 244 {
 245     dev->bus->config_writel(dev->bus, dev->devfn, offset, value);
 246 }
 247
 248 uint8_t qpci_io_readb(QPCIDevice *dev, QPCIBar token, uint64_t off)
 249 {
 250     if (token.addr < QPCI_PIO_LIMIT) {
 251         return dev->bus->pio_readb(dev->bus, token.addr + off);
 252     } else {
 253         uint8_t val;
 254         dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
 255         return val;
 256     }
 257 }
 258
 259 uint16_t qpci_io_readw(QPCIDevice *dev, QPCIBar token, uint64_t off)
 260 {
 261     if (token.addr < QPCI_PIO_LIMIT) {
 262         return dev->bus->pio_readw(dev->bus, token.addr + off);
 263     } else {
 264         uint16_t val;
 265         dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
 266         return le16_to_cpu(val);
 267     }
 268 }
 269
 270 uint32_t qpci_io_readl(QPCIDevice *dev, QPCIBar token, uint64_t off)
 271 {
 272     if (token.addr < QPCI_PIO_LIMIT) {
 273         return dev->bus->pio_readl(dev->bus, token.addr + off);
 274     } else {
 275         uint32_t val;
 276         dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
 277         return le32_to_cpu(val);
 278     }
 279 }
 280
 281 uint64_t qpci_io_readq(QPCIDevice *dev, QPCIBar token, uint64_t off)
 282 {
 283     if (token.addr < QPCI_PIO_LIMIT) {
 284         return dev->bus->pio_readq(dev->bus, token.addr + off);
 285     } else {
 286         uint64_t val;
 287         dev->bus->memread(dev->bus, token.addr + off, &val, sizeof(val));
 288         return le64_to_cpu(val);
 289     }
 290 }
 291
 292 void qpci_io_writeb(QPCIDevice *dev, QPCIBar token, uint64_t off,
 293                     uint8_t value)
 294 {
 295     if (token.addr < QPCI_PIO_LIMIT) {
 296         dev->bus->pio_writeb(dev->bus, token.addr + off, value);
 297     } else {
 298         dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
 299     }
 300 }
 301
 302 void qpci_io_writew(QPCIDevice *dev, QPCIBar token, uint64_t off,
 303                     uint16_t value)
 304 {
 305     if (token.addr < QPCI_PIO_LIMIT) {
 306         dev->bus->pio_writew(dev->bus, token.addr + off, value);
 307     } else {
 308         value = cpu_to_le16(value);
 309         dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
 310     }
 311 }
 312
 313 void qpci_io_writel(QPCIDevice *dev, QPCIBar token, uint64_t off,
 314                     uint32_t value)
 315 {
 316     if (token.addr < QPCI_PIO_LIMIT) {
 317         dev->bus->pio_writel(dev->bus, token.addr + off, value);
 318     } else {
 319         value = cpu_to_le32(value);
 320         dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
 321     }
 322 }
 323
 324 void qpci_io_writeq(QPCIDevice *dev, QPCIBar token, uint64_t off,
 325                     uint64_t value)
 326 {
 327     if (token.addr < QPCI_PIO_LIMIT) {
 328         dev->bus->pio_writeq(dev->bus, token.addr + off, value);
 329     } else {
 330         value = cpu_to_le64(value);
 331         dev->bus->memwrite(dev->bus, token.addr + off, &value, sizeof(value));
 332     }
 333 }
 334
 335 void qpci_memread(QPCIDevice *dev, QPCIBar token, uint64_t off,
 336                   void *buf, size_t len)
 337 {
 338     g_assert(token.addr >= QPCI_PIO_LIMIT);
 339     dev->bus->memread(dev->bus, token.addr + off, buf, len);
 340 }
 341
 342 void qpci_memwrite(QPCIDevice *dev, QPCIBar token, uint64_t off,
 343                    const void *buf, size_t len)
 344 {
 345     g_assert(token.addr >= QPCI_PIO_LIMIT);
 346     dev->bus->memwrite(dev->bus, token.addr + off, buf, len);
 347 }
 348
 349 QPCIBar qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
 350 {
 351     QPCIBus *bus = dev->bus;
 352     static const int bar_reg_map[] = {
 353         PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
 354         PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
 355     };
 356     QPCIBar bar;
 357     int bar_reg;
 358     uint32_t addr, size;
 359     uint32_t io_type;
 360     uint64_t loc;
 361
 362     g_assert(barno >= 0 && barno <= 5);
 363     bar_reg = bar_reg_map[barno];
 364
 365     qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
 366     addr = qpci_config_readl(dev, bar_reg);
 367
 368     io_type = addr & PCI_BASE_ADDRESS_SPACE;
 369     if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
 370         addr &= PCI_BASE_ADDRESS_IO_MASK;
 371     } else {
 372         addr &= PCI_BASE_ADDRESS_MEM_MASK;
 373     }
 374
 375     g_assert(addr); /* Must have *some* size bits */
 376
 377     size = 1U << ctz32(addr);
 378     if (sizeptr) {
 379         *sizeptr = size;
 380     }
 381
 382     if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
 383         loc = QEMU_ALIGN_UP(bus->pio_alloc_ptr, size);
 384
 385         g_assert(loc >= bus->pio_alloc_ptr);
 386         g_assert(loc + size <= QPCI_PIO_LIMIT); /* Keep PIO below 64kiB */
 387
 388         bus->pio_alloc_ptr = loc + size;
 389
 390         qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
 391     } else {
 392         loc = QEMU_ALIGN_UP(bus->mmio_alloc_ptr, size);
 393
 394         /* Check for space */
 395         g_assert(loc >= bus->mmio_alloc_ptr);
 396         g_assert(loc + size <= bus->mmio_limit);
 397
 398         bus->mmio_alloc_ptr = loc + size;
 399
 400         qpci_config_writel(dev, bar_reg, loc);
 401     }
 402
 403     bar.addr = loc;
 404     return bar;
 405 }
 406
 407 void qpci_iounmap(QPCIDevice *dev, QPCIBar bar)
 408 {
 409     /* FIXME */
 410 }
 411
 412 QPCIBar qpci_legacy_iomap(QPCIDevice *dev, uint16_t addr)
 413 {
 414     QPCIBar bar = { .addr = addr };
 415     return bar;
 416 }
 417
 418 void add_qpci_address(QOSGraphEdgeOptions *opts, QPCIAddress *addr)
 419 {
 420     g_assert(addr);
 421     g_assert(opts);
 422
 423     opts->arg = addr;
 424     opts->size_arg = sizeof(QPCIAddress);
 425 }