2 * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI).
3 * Copyright (c) 2015, Microsoft
4 * Written by Andrew Baumann
5 * Based on pl011.c, copyright terms below:
7 * Arm PrimeCell PL011 UART
9 * Copyright (c) 2006 CodeSourcery.
10 * Written by Paul Brook
12 * This code is licensed under the GPL.
14 * At present only the core UART functions (data path for tx/rx) are
15 * implemented. The following features/registers are unimplemented:
16 * - Line/modem control
23 #include "qemu/osdep.h"
24 #include "hw/char/bcm2835_aux.h"
28 #define AUX_ENABLES 0x4
29 #define AUX_MU_IO_REG 0x40
30 #define AUX_MU_IER_REG 0x44
31 #define AUX_MU_IIR_REG 0x48
32 #define AUX_MU_LCR_REG 0x4c
33 #define AUX_MU_MCR_REG 0x50
34 #define AUX_MU_LSR_REG 0x54
35 #define AUX_MU_MSR_REG 0x58
36 #define AUX_MU_SCRATCH 0x5c
37 #define AUX_MU_CNTL_REG 0x60
38 #define AUX_MU_STAT_REG 0x64
39 #define AUX_MU_BAUD_REG 0x68
41 /* bits in IER/IIR registers */
45 static void bcm2835_aux_update(BCM2835AuxState
*s
)
47 /* signal an interrupt if either:
48 * 1. rx interrupt is enabled and we have a non-empty rx fifo, or
49 * 2. the tx interrupt is enabled (since we instantly drain the tx fifo)
52 if ((s
->ier
& RX_INT
) && s
->read_count
!= 0) {
55 if (s
->ier
& TX_INT
) {
58 qemu_set_irq(s
->irq
, s
->iir
!= 0);
61 static uint64_t bcm2835_aux_read(void *opaque
, hwaddr offset
, unsigned size
)
63 BCM2835AuxState
*s
= opaque
;
71 return 1; /* mini UART permanently enabled */
74 /* "DLAB bit set means access baudrate register" is NYI */
75 c
= s
->read_fifo
[s
->read_pos
];
76 if (s
->read_count
> 0) {
78 if (++s
->read_pos
== BCM2835_AUX_RX_FIFO_LEN
) {
83 qemu_chr_accept_input(s
->chr
);
85 bcm2835_aux_update(s
);
89 /* "DLAB bit set means access baudrate register" is NYI */
90 return 0xc0 | s
->ier
; /* FIFO enables always read 1 */
93 res
= 0xc0; /* FIFO enables */
94 /* The spec is unclear on what happens when both tx and rx
95 * interrupts are active, besides that this cannot occur. At
96 * present, we choose to prioritise the rx interrupt, since
97 * the tx fifo is always empty. */
98 if (s
->read_count
!= 0) {
109 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_LCR_REG unsupported\n", __func__
);
113 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_MCR_REG unsupported\n", __func__
);
117 res
= 0x60; /* tx idle, empty */
118 if (s
->read_count
!= 0) {
124 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_MSR_REG unsupported\n", __func__
);
128 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_SCRATCH unsupported\n", __func__
);
131 case AUX_MU_CNTL_REG
:
132 return 0x3; /* tx, rx enabled */
134 case AUX_MU_STAT_REG
:
135 res
= 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */
136 if (s
->read_count
> 0) {
137 res
|= 0x1; /* data in input buffer */
138 assert(s
->read_count
< BCM2835_AUX_RX_FIFO_LEN
);
139 res
|= ((uint32_t)s
->read_count
) << 16; /* rx fifo fill level */
143 case AUX_MU_BAUD_REG
:
144 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_BAUD_REG unsupported\n", __func__
);
148 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset %"HWADDR_PRIx
"\n",
154 static void bcm2835_aux_write(void *opaque
, hwaddr offset
, uint64_t value
,
157 BCM2835AuxState
*s
= opaque
;
163 qemu_log_mask(LOG_UNIMP
, "%s: unsupported attempt to enable SPI "
164 "or disable UART\n", __func__
);
169 /* "DLAB bit set means access baudrate register" is NYI */
172 /* XXX this blocks entire thread. Rewrite to use
173 * qemu_chr_fe_write and background I/O callbacks */
174 qemu_chr_fe_write_all(s
->chr
, &ch
, 1);
179 /* "DLAB bit set means access baudrate register" is NYI */
180 s
->ier
= value
& (TX_INT
| RX_INT
);
181 bcm2835_aux_update(s
);
191 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_LCR_REG unsupported\n", __func__
);
195 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_MCR_REG unsupported\n", __func__
);
199 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_SCRATCH unsupported\n", __func__
);
202 case AUX_MU_CNTL_REG
:
203 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_CNTL_REG unsupported\n", __func__
);
206 case AUX_MU_BAUD_REG
:
207 qemu_log_mask(LOG_UNIMP
, "%s: AUX_MU_BAUD_REG unsupported\n", __func__
);
211 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset %"HWADDR_PRIx
"\n",
215 bcm2835_aux_update(s
);
218 static int bcm2835_aux_can_receive(void *opaque
)
220 BCM2835AuxState
*s
= opaque
;
222 return s
->read_count
< BCM2835_AUX_RX_FIFO_LEN
;
225 static void bcm2835_aux_put_fifo(void *opaque
, uint8_t value
)
227 BCM2835AuxState
*s
= opaque
;
230 slot
= s
->read_pos
+ s
->read_count
;
231 if (slot
>= BCM2835_AUX_RX_FIFO_LEN
) {
232 slot
-= BCM2835_AUX_RX_FIFO_LEN
;
234 s
->read_fifo
[slot
] = value
;
236 if (s
->read_count
== BCM2835_AUX_RX_FIFO_LEN
) {
239 bcm2835_aux_update(s
);
242 static void bcm2835_aux_receive(void *opaque
, const uint8_t *buf
, int size
)
244 bcm2835_aux_put_fifo(opaque
, *buf
);
247 static const MemoryRegionOps bcm2835_aux_ops
= {
248 .read
= bcm2835_aux_read
,
249 .write
= bcm2835_aux_write
,
250 .endianness
= DEVICE_NATIVE_ENDIAN
,
251 .valid
.min_access_size
= 4,
252 .valid
.max_access_size
= 4,
255 static const VMStateDescription vmstate_bcm2835_aux
= {
256 .name
= TYPE_BCM2835_AUX
,
258 .minimum_version_id
= 1,
259 .fields
= (VMStateField
[]) {
260 VMSTATE_UINT8_ARRAY(read_fifo
, BCM2835AuxState
,
261 BCM2835_AUX_RX_FIFO_LEN
),
262 VMSTATE_UINT8(read_pos
, BCM2835AuxState
),
263 VMSTATE_UINT8(read_count
, BCM2835AuxState
),
264 VMSTATE_UINT8(ier
, BCM2835AuxState
),
265 VMSTATE_UINT8(iir
, BCM2835AuxState
),
266 VMSTATE_END_OF_LIST()
270 static void bcm2835_aux_init(Object
*obj
)
272 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
273 BCM2835AuxState
*s
= BCM2835_AUX(obj
);
275 memory_region_init_io(&s
->iomem
, OBJECT(s
), &bcm2835_aux_ops
, s
,
276 TYPE_BCM2835_AUX
, 0x100);
277 sysbus_init_mmio(sbd
, &s
->iomem
);
278 sysbus_init_irq(sbd
, &s
->irq
);
281 static void bcm2835_aux_realize(DeviceState
*dev
, Error
**errp
)
283 BCM2835AuxState
*s
= BCM2835_AUX(dev
);
286 qemu_chr_add_handlers(s
->chr
, bcm2835_aux_can_receive
,
287 bcm2835_aux_receive
, NULL
, s
);
291 static Property bcm2835_aux_props
[] = {
292 DEFINE_PROP_CHR("chardev", BCM2835AuxState
, chr
),
293 DEFINE_PROP_END_OF_LIST(),
296 static void bcm2835_aux_class_init(ObjectClass
*oc
, void *data
)
298 DeviceClass
*dc
= DEVICE_CLASS(oc
);
300 dc
->realize
= bcm2835_aux_realize
;
301 dc
->vmsd
= &vmstate_bcm2835_aux
;
302 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
303 dc
->props
= bcm2835_aux_props
;
306 static const TypeInfo bcm2835_aux_info
= {
307 .name
= TYPE_BCM2835_AUX
,
308 .parent
= TYPE_SYS_BUS_DEVICE
,
309 .instance_size
= sizeof(BCM2835AuxState
),
310 .instance_init
= bcm2835_aux_init
,
311 .class_init
= bcm2835_aux_class_init
,
314 static void bcm2835_aux_register_types(void)
316 type_register_static(&bcm2835_aux_info
);
319 type_init(bcm2835_aux_register_types
)