2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
28 #include "sparc32_dma.h"
33 #include "firmware_abi.h"
39 #include "qdev-addr.h"
46 * Sun4m architecture was used in the following machines:
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
58 * Sun4d architecture was used in the following machines:
63 * Sun4c architecture was used in the following machines:
64 * SPARCstation 1/1+, SPARCserver 1/1+
70 * See for example: http://www.sunhelp.org/faq/sunref1.html
74 #define DPRINTF(fmt, ...) \
75 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
77 #define DPRINTF(fmt, ...)
80 #define KERNEL_LOAD_ADDR 0x00004000
81 #define CMDLINE_ADDR 0x007ff000
82 #define INITRD_LOAD_ADDR 0x00800000
83 #define PROM_SIZE_MAX (1024 * 1024)
84 #define PROM_VADDR 0xffd00000
85 #define PROM_FILENAME "openbios-sparc32"
86 #define CFG_ADDR 0xd00000510ULL
87 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
92 #define ESCC_CLOCK 4915200
95 target_phys_addr_t iommu_base
, slavio_base
;
96 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
97 target_phys_addr_t serial_base
, fd_base
;
98 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
99 target_phys_addr_t tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
100 target_phys_addr_t ecc_base
;
101 uint32_t ecc_version
;
102 uint8_t nvram_machine_id
;
104 uint32_t iommu_version
;
106 const char * const default_cpu_model
;
109 #define MAX_IOUNITS 5
112 target_phys_addr_t iounit_bases
[MAX_IOUNITS
], slavio_base
;
113 target_phys_addr_t counter_base
, nvram_base
, ms_kb_base
;
114 target_phys_addr_t serial_base
;
115 target_phys_addr_t espdma_base
, esp_base
;
116 target_phys_addr_t ledma_base
, le_base
;
117 target_phys_addr_t tcx_base
;
118 target_phys_addr_t sbi_base
;
119 uint8_t nvram_machine_id
;
121 uint32_t iounit_version
;
123 const char * const default_cpu_model
;
127 target_phys_addr_t iommu_base
, slavio_base
;
128 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
129 target_phys_addr_t serial_base
, fd_base
;
130 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
131 target_phys_addr_t tcx_base
, aux1_base
;
132 uint8_t nvram_machine_id
;
134 uint32_t iommu_version
;
136 const char * const default_cpu_model
;
139 int DMA_get_channel_mode (int nchan
)
143 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
147 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
151 void DMA_hold_DREQ (int nchan
) {}
152 void DMA_release_DREQ (int nchan
) {}
153 void DMA_schedule(int nchan
) {}
154 void DMA_init (int high_page_enable
) {}
155 void DMA_register_channel (int nchan
,
156 DMA_transfer_handler transfer_handler
,
161 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
163 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
167 static void nvram_init(m48t59_t
*nvram
, uint8_t *macaddr
, const char *cmdline
,
168 const char *boot_devices
, ram_addr_t RAM_size
,
169 uint32_t kernel_size
,
170 int width
, int height
, int depth
,
171 int nvram_machine_id
, const char *arch
)
175 uint8_t image
[0x1ff0];
176 struct OpenBIOS_nvpart_v1
*part_header
;
178 memset(image
, '\0', sizeof(image
));
182 // OpenBIOS nvram variables
183 // Variable partition
184 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
185 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
186 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
188 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
189 for (i
= 0; i
< nb_prom_envs
; i
++)
190 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
195 end
= start
+ ((end
- start
+ 15) & ~15);
196 OpenBIOS_finish_partition(part_header
, end
- start
);
200 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
201 part_header
->signature
= OPENBIOS_PART_FREE
;
202 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
205 OpenBIOS_finish_partition(part_header
, end
- start
);
207 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
210 for (i
= 0; i
< sizeof(image
); i
++)
211 m48t59_write(nvram
, i
, image
[i
]);
214 static DeviceState
*slavio_intctl
;
216 void pic_info(Monitor
*mon
)
219 slavio_pic_info(mon
, slavio_intctl
);
222 void irq_info(Monitor
*mon
)
225 slavio_irq_info(mon
, slavio_intctl
);
228 void cpu_check_irqs(CPUState
*env
)
230 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
231 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
234 for (i
= 15; i
> 0; i
--) {
235 if (env
->pil_in
& (1 << i
)) {
236 int old_interrupt
= env
->interrupt_index
;
238 env
->interrupt_index
= TT_EXTINT
| i
;
239 if (old_interrupt
!= env
->interrupt_index
) {
240 DPRINTF("Set CPU IRQ %d\n", i
);
241 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
246 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
247 DPRINTF("Reset CPU IRQ %d\n", env
->interrupt_index
& 15);
248 env
->interrupt_index
= 0;
249 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
253 static void cpu_set_irq(void *opaque
, int irq
, int level
)
255 CPUState
*env
= opaque
;
258 DPRINTF("Raise CPU IRQ %d\n", irq
);
260 env
->pil_in
|= 1 << irq
;
263 DPRINTF("Lower CPU IRQ %d\n", irq
);
264 env
->pil_in
&= ~(1 << irq
);
269 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
273 static void main_cpu_reset(void *opaque
)
275 CPUState
*env
= opaque
;
281 static void secondary_cpu_reset(void *opaque
)
283 CPUState
*env
= opaque
;
289 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
291 if (level
&& cpu_single_env
)
292 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
295 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
296 const char *initrd_filename
,
301 long initrd_size
, kernel_size
;
303 linux_boot
= (kernel_filename
!= NULL
);
314 kernel_size
= load_elf(kernel_filename
, -0xf0000000ULL
, NULL
, NULL
,
315 NULL
, 1, ELF_MACHINE
, 0);
317 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
318 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
321 kernel_size
= load_image_targphys(kernel_filename
,
323 RAM_size
- KERNEL_LOAD_ADDR
);
324 if (kernel_size
< 0) {
325 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
332 if (initrd_filename
) {
333 initrd_size
= load_image_targphys(initrd_filename
,
335 RAM_size
- INITRD_LOAD_ADDR
);
336 if (initrd_size
< 0) {
337 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
342 if (initrd_size
> 0) {
343 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
344 if (ldl_phys(KERNEL_LOAD_ADDR
+ i
) == 0x48647253) { // HdrS
345 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 16, INITRD_LOAD_ADDR
);
346 stl_phys(KERNEL_LOAD_ADDR
+ i
+ 20, initrd_size
);
355 static void *iommu_init(target_phys_addr_t addr
, uint32_t version
, qemu_irq irq
)
360 dev
= qdev_create(NULL
, "iommu");
361 qdev_prop_set_uint32(dev
, "version", version
);
363 s
= sysbus_from_qdev(dev
);
364 sysbus_connect_irq(s
, 0, irq
);
365 sysbus_mmio_map(s
, 0, addr
);
370 static void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
371 void *iommu
, qemu_irq
*dev_irq
)
376 dev
= qdev_create(NULL
, "sparc32_dma");
377 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
379 s
= sysbus_from_qdev(dev
);
380 sysbus_connect_irq(s
, 0, parent_irq
);
381 *dev_irq
= qdev_get_gpio_in(dev
, 0);
382 sysbus_mmio_map(s
, 0, daddr
);
387 static void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
,
388 void *dma_opaque
, qemu_irq irq
)
394 qemu_check_nic_model(&nd_table
[0], "lance");
396 dev
= qdev_create(NULL
, "lance");
398 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
400 s
= sysbus_from_qdev(dev
);
401 sysbus_mmio_map(s
, 0, leaddr
);
402 sysbus_connect_irq(s
, 0, irq
);
403 reset
= qdev_get_gpio_in(dev
, 0);
404 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
407 static DeviceState
*slavio_intctl_init(target_phys_addr_t addr
,
408 target_phys_addr_t addrg
,
409 qemu_irq
**parent_irq
)
415 dev
= qdev_create(NULL
, "slavio_intctl");
418 s
= sysbus_from_qdev(dev
);
420 for (i
= 0; i
< MAX_CPUS
; i
++) {
421 for (j
= 0; j
< MAX_PILS
; j
++) {
422 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
425 sysbus_mmio_map(s
, 0, addrg
);
426 for (i
= 0; i
< MAX_CPUS
; i
++) {
427 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
433 #define SYS_TIMER_OFFSET 0x10000ULL
434 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
436 static void slavio_timer_init_all(target_phys_addr_t addr
, qemu_irq master_irq
,
437 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
443 dev
= qdev_create(NULL
, "slavio_timer");
444 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
446 s
= sysbus_from_qdev(dev
);
447 sysbus_connect_irq(s
, 0, master_irq
);
448 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
450 for (i
= 0; i
< MAX_CPUS
; i
++) {
451 sysbus_mmio_map(s
, i
+ 1, addr
+ (target_phys_addr_t
)CPU_TIMER_OFFSET(i
));
452 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
456 #define MISC_LEDS 0x01600000
457 #define MISC_CFG 0x01800000
458 #define MISC_DIAG 0x01a00000
459 #define MISC_MDM 0x01b00000
460 #define MISC_SYS 0x01f00000
462 static void slavio_misc_init(target_phys_addr_t base
,
463 target_phys_addr_t aux1_base
,
464 target_phys_addr_t aux2_base
, qemu_irq irq
,
470 dev
= qdev_create(NULL
, "slavio_misc");
472 s
= sysbus_from_qdev(dev
);
474 /* 8 bit registers */
476 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
478 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
480 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
481 /* 16 bit registers */
482 /* ss600mp diag LEDs */
483 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
484 /* 32 bit registers */
486 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
489 /* AUX 1 (Misc System Functions) */
490 sysbus_mmio_map(s
, 5, aux1_base
);
493 /* AUX 2 (Software Powerdown Control) */
494 sysbus_mmio_map(s
, 6, aux2_base
);
496 sysbus_connect_irq(s
, 0, irq
);
497 sysbus_connect_irq(s
, 1, fdc_tc
);
498 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 0);
501 static void ecc_init(target_phys_addr_t base
, qemu_irq irq
, uint32_t version
)
506 dev
= qdev_create(NULL
, "eccmemctl");
507 qdev_prop_set_uint32(dev
, "version", version
);
509 s
= sysbus_from_qdev(dev
);
510 sysbus_connect_irq(s
, 0, irq
);
511 sysbus_mmio_map(s
, 0, base
);
512 if (version
== 0) { // SS-600MP only
513 sysbus_mmio_map(s
, 1, base
+ 0x1000);
517 static void apc_init(target_phys_addr_t power_base
, qemu_irq cpu_halt
)
522 dev
= qdev_create(NULL
, "apc");
524 s
= sysbus_from_qdev(dev
);
525 /* Power management (APC) XXX: not a Slavio device */
526 sysbus_mmio_map(s
, 0, power_base
);
527 sysbus_connect_irq(s
, 0, cpu_halt
);
530 static void tcx_init(target_phys_addr_t addr
, int vram_size
, int width
,
531 int height
, int depth
)
536 dev
= qdev_create(NULL
, "SUNW,tcx");
537 qdev_prop_set_taddr(dev
, "addr", addr
);
538 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
539 qdev_prop_set_uint16(dev
, "width", width
);
540 qdev_prop_set_uint16(dev
, "height", height
);
541 qdev_prop_set_uint16(dev
, "depth", depth
);
543 s
= sysbus_from_qdev(dev
);
545 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
547 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
549 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
550 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
551 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
554 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
556 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
558 /* THC 8 bit (dummy) */
559 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
563 /* NCR89C100/MACIO Internal ID register */
564 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
566 static void idreg_init(target_phys_addr_t addr
)
571 dev
= qdev_create(NULL
, "macio_idreg");
573 s
= sysbus_from_qdev(dev
);
575 sysbus_mmio_map(s
, 0, addr
);
576 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
579 static int idreg_init1(SysBusDevice
*dev
)
581 ram_addr_t idreg_offset
;
583 idreg_offset
= qemu_ram_alloc(sizeof(idreg_data
));
584 sysbus_init_mmio(dev
, sizeof(idreg_data
), idreg_offset
| IO_MEM_ROM
);
588 static SysBusDeviceInfo idreg_info
= {
590 .qdev
.name
= "macio_idreg",
591 .qdev
.size
= sizeof(SysBusDevice
),
594 static void idreg_register_devices(void)
596 sysbus_register_withprop(&idreg_info
);
599 device_init(idreg_register_devices
);
601 /* Boot PROM (OpenBIOS) */
602 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
609 dev
= qdev_create(NULL
, "openprom");
611 s
= sysbus_from_qdev(dev
);
613 sysbus_mmio_map(s
, 0, addr
);
616 if (bios_name
== NULL
) {
617 bios_name
= PROM_FILENAME
;
619 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
621 ret
= load_elf(filename
, addr
- PROM_VADDR
, NULL
, NULL
, NULL
,
623 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
624 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
630 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
631 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
636 static int prom_init1(SysBusDevice
*dev
)
638 ram_addr_t prom_offset
;
640 prom_offset
= qemu_ram_alloc(PROM_SIZE_MAX
);
641 sysbus_init_mmio(dev
, PROM_SIZE_MAX
, prom_offset
| IO_MEM_ROM
);
645 static SysBusDeviceInfo prom_info
= {
647 .qdev
.name
= "openprom",
648 .qdev
.size
= sizeof(SysBusDevice
),
649 .qdev
.props
= (Property
[]) {
650 {/* end of property list */}
654 static void prom_register_devices(void)
656 sysbus_register_withprop(&prom_info
);
659 device_init(prom_register_devices
);
661 typedef struct RamDevice
668 static int ram_init1(SysBusDevice
*dev
)
670 ram_addr_t RAM_size
, ram_offset
;
671 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
675 ram_offset
= qemu_ram_alloc(RAM_size
);
676 sysbus_init_mmio(dev
, RAM_size
, ram_offset
);
680 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
,
688 if ((uint64_t)RAM_size
> max_mem
) {
690 "qemu: Too much memory for this machine: %d, maximum %d\n",
691 (unsigned int)(RAM_size
/ (1024 * 1024)),
692 (unsigned int)(max_mem
/ (1024 * 1024)));
695 dev
= qdev_create(NULL
, "memory");
696 s
= sysbus_from_qdev(dev
);
698 d
= FROM_SYSBUS(RamDevice
, s
);
702 sysbus_mmio_map(s
, 0, addr
);
705 static SysBusDeviceInfo ram_info
= {
707 .qdev
.name
= "memory",
708 .qdev
.size
= sizeof(RamDevice
),
709 .qdev
.props
= (Property
[]) {
710 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
711 DEFINE_PROP_END_OF_LIST(),
715 static void ram_register_devices(void)
717 sysbus_register_withprop(&ram_info
);
720 device_init(ram_register_devices
);
722 static CPUState
*cpu_devinit(const char *cpu_model
, unsigned int id
,
723 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
727 env
= cpu_init(cpu_model
);
729 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
733 cpu_sparc_set_id(env
, id
);
735 qemu_register_reset(main_cpu_reset
, env
);
737 qemu_register_reset(secondary_cpu_reset
, env
);
740 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
741 env
->prom_addr
= prom_addr
;
746 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
747 const char *boot_device
,
748 const char *kernel_filename
,
749 const char *kernel_cmdline
,
750 const char *initrd_filename
, const char *cpu_model
)
752 CPUState
*envs
[MAX_CPUS
];
754 void *iommu
, *espdma
, *ledma
, *nvram
;
755 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
756 espdma_irq
, ledma_irq
;
760 unsigned long kernel_size
;
761 DriveInfo
*fd
[MAX_FD
];
766 cpu_model
= hwdef
->default_cpu_model
;
768 for(i
= 0; i
< smp_cpus
; i
++) {
769 envs
[i
] = cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
772 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
773 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
777 ram_init(0, RAM_size
, hwdef
->max_mem
);
779 prom_init(hwdef
->slavio_base
, bios_name
);
781 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
782 hwdef
->intctl_base
+ 0x10000ULL
,
785 for (i
= 0; i
< 32; i
++) {
786 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
788 for (i
= 0; i
< MAX_CPUS
; i
++) {
789 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
792 if (hwdef
->idreg_base
) {
793 idreg_init(hwdef
->idreg_base
);
796 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
799 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
802 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
803 slavio_irq
[16], iommu
, &ledma_irq
);
805 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
806 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
809 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
812 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
814 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
816 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
818 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
819 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
820 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
821 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
822 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
823 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
825 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
826 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
827 slavio_irq
[30], fdc_tc
);
829 if (hwdef
->apc_base
) {
830 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
833 if (hwdef
->fd_base
) {
834 /* there is zero or one floppy drive */
835 memset(fd
, 0, sizeof(fd
));
836 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
837 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
841 if (drive_get_max_bus(IF_SCSI
) > 0) {
842 fprintf(stderr
, "qemu: too many SCSI bus\n");
846 esp_reset
= qdev_get_gpio_in(espdma
, 0);
847 esp_init(hwdef
->esp_base
, 2,
848 espdma_memory_read
, espdma_memory_write
,
849 espdma
, espdma_irq
, &esp_reset
);
852 if (hwdef
->cs_base
) {
853 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
857 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
860 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
861 boot_device
, RAM_size
, kernel_size
, graphic_width
,
862 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
866 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
869 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
870 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
871 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
872 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
873 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
874 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
875 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
876 if (kernel_cmdline
) {
877 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
878 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
880 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
882 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
883 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
884 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
885 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
903 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
906 .iommu_base
= 0x10000000,
907 .tcx_base
= 0x50000000,
908 .cs_base
= 0x6c000000,
909 .slavio_base
= 0x70000000,
910 .ms_kb_base
= 0x71000000,
911 .serial_base
= 0x71100000,
912 .nvram_base
= 0x71200000,
913 .fd_base
= 0x71400000,
914 .counter_base
= 0x71d00000,
915 .intctl_base
= 0x71e00000,
916 .idreg_base
= 0x78000000,
917 .dma_base
= 0x78400000,
918 .esp_base
= 0x78800000,
919 .le_base
= 0x78c00000,
920 .apc_base
= 0x6a000000,
921 .aux1_base
= 0x71900000,
922 .aux2_base
= 0x71910000,
923 .nvram_machine_id
= 0x80,
924 .machine_id
= ss5_id
,
925 .iommu_version
= 0x05000000,
926 .max_mem
= 0x10000000,
927 .default_cpu_model
= "Fujitsu MB86904",
931 .iommu_base
= 0xfe0000000ULL
,
932 .tcx_base
= 0xe20000000ULL
,
933 .slavio_base
= 0xff0000000ULL
,
934 .ms_kb_base
= 0xff1000000ULL
,
935 .serial_base
= 0xff1100000ULL
,
936 .nvram_base
= 0xff1200000ULL
,
937 .fd_base
= 0xff1700000ULL
,
938 .counter_base
= 0xff1300000ULL
,
939 .intctl_base
= 0xff1400000ULL
,
940 .idreg_base
= 0xef0000000ULL
,
941 .dma_base
= 0xef0400000ULL
,
942 .esp_base
= 0xef0800000ULL
,
943 .le_base
= 0xef0c00000ULL
,
944 .apc_base
= 0xefa000000ULL
, // XXX should not exist
945 .aux1_base
= 0xff1800000ULL
,
946 .aux2_base
= 0xff1a01000ULL
,
947 .ecc_base
= 0xf00000000ULL
,
948 .ecc_version
= 0x10000000, // version 0, implementation 1
949 .nvram_machine_id
= 0x72,
950 .machine_id
= ss10_id
,
951 .iommu_version
= 0x03000000,
952 .max_mem
= 0xf00000000ULL
,
953 .default_cpu_model
= "TI SuperSparc II",
957 .iommu_base
= 0xfe0000000ULL
,
958 .tcx_base
= 0xe20000000ULL
,
959 .slavio_base
= 0xff0000000ULL
,
960 .ms_kb_base
= 0xff1000000ULL
,
961 .serial_base
= 0xff1100000ULL
,
962 .nvram_base
= 0xff1200000ULL
,
963 .counter_base
= 0xff1300000ULL
,
964 .intctl_base
= 0xff1400000ULL
,
965 .dma_base
= 0xef0081000ULL
,
966 .esp_base
= 0xef0080000ULL
,
967 .le_base
= 0xef0060000ULL
,
968 .apc_base
= 0xefa000000ULL
, // XXX should not exist
969 .aux1_base
= 0xff1800000ULL
,
970 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
971 .ecc_base
= 0xf00000000ULL
,
972 .ecc_version
= 0x00000000, // version 0, implementation 0
973 .nvram_machine_id
= 0x71,
974 .machine_id
= ss600mp_id
,
975 .iommu_version
= 0x01000000,
976 .max_mem
= 0xf00000000ULL
,
977 .default_cpu_model
= "TI SuperSparc II",
981 .iommu_base
= 0xfe0000000ULL
,
982 .tcx_base
= 0xe20000000ULL
,
983 .slavio_base
= 0xff0000000ULL
,
984 .ms_kb_base
= 0xff1000000ULL
,
985 .serial_base
= 0xff1100000ULL
,
986 .nvram_base
= 0xff1200000ULL
,
987 .fd_base
= 0xff1700000ULL
,
988 .counter_base
= 0xff1300000ULL
,
989 .intctl_base
= 0xff1400000ULL
,
990 .idreg_base
= 0xef0000000ULL
,
991 .dma_base
= 0xef0400000ULL
,
992 .esp_base
= 0xef0800000ULL
,
993 .le_base
= 0xef0c00000ULL
,
994 .apc_base
= 0xefa000000ULL
, // XXX should not exist
995 .aux1_base
= 0xff1800000ULL
,
996 .aux2_base
= 0xff1a01000ULL
,
997 .ecc_base
= 0xf00000000ULL
,
998 .ecc_version
= 0x20000000, // version 0, implementation 2
999 .nvram_machine_id
= 0x72,
1000 .machine_id
= ss20_id
,
1001 .iommu_version
= 0x13000000,
1002 .max_mem
= 0xf00000000ULL
,
1003 .default_cpu_model
= "TI SuperSparc II",
1007 .iommu_base
= 0x10000000,
1008 .tcx_base
= 0x50000000,
1009 .slavio_base
= 0x70000000,
1010 .ms_kb_base
= 0x71000000,
1011 .serial_base
= 0x71100000,
1012 .nvram_base
= 0x71200000,
1013 .fd_base
= 0x71400000,
1014 .counter_base
= 0x71d00000,
1015 .intctl_base
= 0x71e00000,
1016 .idreg_base
= 0x78000000,
1017 .dma_base
= 0x78400000,
1018 .esp_base
= 0x78800000,
1019 .le_base
= 0x78c00000,
1020 .apc_base
= 0x71300000, // pmc
1021 .aux1_base
= 0x71900000,
1022 .aux2_base
= 0x71910000,
1023 .nvram_machine_id
= 0x80,
1024 .machine_id
= vger_id
,
1025 .iommu_version
= 0x05000000,
1026 .max_mem
= 0x10000000,
1027 .default_cpu_model
= "Fujitsu MB86904",
1031 .iommu_base
= 0x10000000,
1032 .tcx_base
= 0x50000000,
1033 .slavio_base
= 0x70000000,
1034 .ms_kb_base
= 0x71000000,
1035 .serial_base
= 0x71100000,
1036 .nvram_base
= 0x71200000,
1037 .fd_base
= 0x71400000,
1038 .counter_base
= 0x71d00000,
1039 .intctl_base
= 0x71e00000,
1040 .idreg_base
= 0x78000000,
1041 .dma_base
= 0x78400000,
1042 .esp_base
= 0x78800000,
1043 .le_base
= 0x78c00000,
1044 .aux1_base
= 0x71900000,
1045 .aux2_base
= 0x71910000,
1046 .nvram_machine_id
= 0x80,
1047 .machine_id
= lx_id
,
1048 .iommu_version
= 0x04000000,
1049 .max_mem
= 0x10000000,
1050 .default_cpu_model
= "TI MicroSparc I",
1054 .iommu_base
= 0x10000000,
1055 .tcx_base
= 0x50000000,
1056 .cs_base
= 0x6c000000,
1057 .slavio_base
= 0x70000000,
1058 .ms_kb_base
= 0x71000000,
1059 .serial_base
= 0x71100000,
1060 .nvram_base
= 0x71200000,
1061 .fd_base
= 0x71400000,
1062 .counter_base
= 0x71d00000,
1063 .intctl_base
= 0x71e00000,
1064 .idreg_base
= 0x78000000,
1065 .dma_base
= 0x78400000,
1066 .esp_base
= 0x78800000,
1067 .le_base
= 0x78c00000,
1068 .apc_base
= 0x6a000000,
1069 .aux1_base
= 0x71900000,
1070 .aux2_base
= 0x71910000,
1071 .nvram_machine_id
= 0x80,
1072 .machine_id
= ss4_id
,
1073 .iommu_version
= 0x05000000,
1074 .max_mem
= 0x10000000,
1075 .default_cpu_model
= "Fujitsu MB86904",
1079 .iommu_base
= 0x10000000,
1080 .tcx_base
= 0x50000000,
1081 .slavio_base
= 0x70000000,
1082 .ms_kb_base
= 0x71000000,
1083 .serial_base
= 0x71100000,
1084 .nvram_base
= 0x71200000,
1085 .fd_base
= 0x71400000,
1086 .counter_base
= 0x71d00000,
1087 .intctl_base
= 0x71e00000,
1088 .idreg_base
= 0x78000000,
1089 .dma_base
= 0x78400000,
1090 .esp_base
= 0x78800000,
1091 .le_base
= 0x78c00000,
1092 .apc_base
= 0x6a000000,
1093 .aux1_base
= 0x71900000,
1094 .aux2_base
= 0x71910000,
1095 .nvram_machine_id
= 0x80,
1096 .machine_id
= scls_id
,
1097 .iommu_version
= 0x05000000,
1098 .max_mem
= 0x10000000,
1099 .default_cpu_model
= "TI MicroSparc I",
1103 .iommu_base
= 0x10000000,
1104 .tcx_base
= 0x50000000, // XXX
1105 .slavio_base
= 0x70000000,
1106 .ms_kb_base
= 0x71000000,
1107 .serial_base
= 0x71100000,
1108 .nvram_base
= 0x71200000,
1109 .fd_base
= 0x71400000,
1110 .counter_base
= 0x71d00000,
1111 .intctl_base
= 0x71e00000,
1112 .idreg_base
= 0x78000000,
1113 .dma_base
= 0x78400000,
1114 .esp_base
= 0x78800000,
1115 .le_base
= 0x78c00000,
1116 .apc_base
= 0x6a000000,
1117 .aux1_base
= 0x71900000,
1118 .aux2_base
= 0x71910000,
1119 .nvram_machine_id
= 0x80,
1120 .machine_id
= sbook_id
,
1121 .iommu_version
= 0x05000000,
1122 .max_mem
= 0x10000000,
1123 .default_cpu_model
= "TI MicroSparc I",
1127 /* SPARCstation 5 hardware initialisation */
1128 static void ss5_init(ram_addr_t RAM_size
,
1129 const char *boot_device
,
1130 const char *kernel_filename
, const char *kernel_cmdline
,
1131 const char *initrd_filename
, const char *cpu_model
)
1133 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1134 kernel_cmdline
, initrd_filename
, cpu_model
);
1137 /* SPARCstation 10 hardware initialisation */
1138 static void ss10_init(ram_addr_t RAM_size
,
1139 const char *boot_device
,
1140 const char *kernel_filename
, const char *kernel_cmdline
,
1141 const char *initrd_filename
, const char *cpu_model
)
1143 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1144 kernel_cmdline
, initrd_filename
, cpu_model
);
1147 /* SPARCserver 600MP hardware initialisation */
1148 static void ss600mp_init(ram_addr_t RAM_size
,
1149 const char *boot_device
,
1150 const char *kernel_filename
,
1151 const char *kernel_cmdline
,
1152 const char *initrd_filename
, const char *cpu_model
)
1154 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1155 kernel_cmdline
, initrd_filename
, cpu_model
);
1158 /* SPARCstation 20 hardware initialisation */
1159 static void ss20_init(ram_addr_t RAM_size
,
1160 const char *boot_device
,
1161 const char *kernel_filename
, const char *kernel_cmdline
,
1162 const char *initrd_filename
, const char *cpu_model
)
1164 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1165 kernel_cmdline
, initrd_filename
, cpu_model
);
1168 /* SPARCstation Voyager hardware initialisation */
1169 static void vger_init(ram_addr_t RAM_size
,
1170 const char *boot_device
,
1171 const char *kernel_filename
, const char *kernel_cmdline
,
1172 const char *initrd_filename
, const char *cpu_model
)
1174 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1175 kernel_cmdline
, initrd_filename
, cpu_model
);
1178 /* SPARCstation LX hardware initialisation */
1179 static void ss_lx_init(ram_addr_t RAM_size
,
1180 const char *boot_device
,
1181 const char *kernel_filename
, const char *kernel_cmdline
,
1182 const char *initrd_filename
, const char *cpu_model
)
1184 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1185 kernel_cmdline
, initrd_filename
, cpu_model
);
1188 /* SPARCstation 4 hardware initialisation */
1189 static void ss4_init(ram_addr_t RAM_size
,
1190 const char *boot_device
,
1191 const char *kernel_filename
, const char *kernel_cmdline
,
1192 const char *initrd_filename
, const char *cpu_model
)
1194 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1195 kernel_cmdline
, initrd_filename
, cpu_model
);
1198 /* SPARCClassic hardware initialisation */
1199 static void scls_init(ram_addr_t RAM_size
,
1200 const char *boot_device
,
1201 const char *kernel_filename
, const char *kernel_cmdline
,
1202 const char *initrd_filename
, const char *cpu_model
)
1204 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1205 kernel_cmdline
, initrd_filename
, cpu_model
);
1208 /* SPARCbook hardware initialisation */
1209 static void sbook_init(ram_addr_t RAM_size
,
1210 const char *boot_device
,
1211 const char *kernel_filename
, const char *kernel_cmdline
,
1212 const char *initrd_filename
, const char *cpu_model
)
1214 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1215 kernel_cmdline
, initrd_filename
, cpu_model
);
1218 static QEMUMachine ss5_machine
= {
1220 .desc
= "Sun4m platform, SPARCstation 5",
1226 static QEMUMachine ss10_machine
= {
1228 .desc
= "Sun4m platform, SPARCstation 10",
1234 static QEMUMachine ss600mp_machine
= {
1236 .desc
= "Sun4m platform, SPARCserver 600MP",
1237 .init
= ss600mp_init
,
1242 static QEMUMachine ss20_machine
= {
1244 .desc
= "Sun4m platform, SPARCstation 20",
1250 static QEMUMachine voyager_machine
= {
1252 .desc
= "Sun4m platform, SPARCstation Voyager",
1257 static QEMUMachine ss_lx_machine
= {
1259 .desc
= "Sun4m platform, SPARCstation LX",
1264 static QEMUMachine ss4_machine
= {
1266 .desc
= "Sun4m platform, SPARCstation 4",
1271 static QEMUMachine scls_machine
= {
1272 .name
= "SPARCClassic",
1273 .desc
= "Sun4m platform, SPARCClassic",
1278 static QEMUMachine sbook_machine
= {
1279 .name
= "SPARCbook",
1280 .desc
= "Sun4m platform, SPARCbook",
1285 static const struct sun4d_hwdef sun4d_hwdefs
[] = {
1295 .tcx_base
= 0x820000000ULL
,
1296 .slavio_base
= 0xf00000000ULL
,
1297 .ms_kb_base
= 0xf00240000ULL
,
1298 .serial_base
= 0xf00200000ULL
,
1299 .nvram_base
= 0xf00280000ULL
,
1300 .counter_base
= 0xf00300000ULL
,
1301 .espdma_base
= 0x800081000ULL
,
1302 .esp_base
= 0x800080000ULL
,
1303 .ledma_base
= 0x800040000ULL
,
1304 .le_base
= 0x800060000ULL
,
1305 .sbi_base
= 0xf02800000ULL
,
1306 .nvram_machine_id
= 0x80,
1307 .machine_id
= ss1000_id
,
1308 .iounit_version
= 0x03000000,
1309 .max_mem
= 0xf00000000ULL
,
1310 .default_cpu_model
= "TI SuperSparc II",
1321 .tcx_base
= 0x820000000ULL
,
1322 .slavio_base
= 0xf00000000ULL
,
1323 .ms_kb_base
= 0xf00240000ULL
,
1324 .serial_base
= 0xf00200000ULL
,
1325 .nvram_base
= 0xf00280000ULL
,
1326 .counter_base
= 0xf00300000ULL
,
1327 .espdma_base
= 0x800081000ULL
,
1328 .esp_base
= 0x800080000ULL
,
1329 .ledma_base
= 0x800040000ULL
,
1330 .le_base
= 0x800060000ULL
,
1331 .sbi_base
= 0xf02800000ULL
,
1332 .nvram_machine_id
= 0x80,
1333 .machine_id
= ss2000_id
,
1334 .iounit_version
= 0x03000000,
1335 .max_mem
= 0xf00000000ULL
,
1336 .default_cpu_model
= "TI SuperSparc II",
1340 static DeviceState
*sbi_init(target_phys_addr_t addr
, qemu_irq
**parent_irq
)
1346 dev
= qdev_create(NULL
, "sbi");
1349 s
= sysbus_from_qdev(dev
);
1351 for (i
= 0; i
< MAX_CPUS
; i
++) {
1352 sysbus_connect_irq(s
, i
, *parent_irq
[i
]);
1355 sysbus_mmio_map(s
, 0, addr
);
1360 static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef
, ram_addr_t RAM_size
,
1361 const char *boot_device
,
1362 const char *kernel_filename
,
1363 const char *kernel_cmdline
,
1364 const char *initrd_filename
, const char *cpu_model
)
1366 CPUState
*envs
[MAX_CPUS
];
1368 void *iounits
[MAX_IOUNITS
], *espdma
, *ledma
, *nvram
;
1369 qemu_irq
*cpu_irqs
[MAX_CPUS
], sbi_irq
[32], sbi_cpu_irq
[MAX_CPUS
],
1370 espdma_irq
, ledma_irq
;
1372 unsigned long kernel_size
;
1378 cpu_model
= hwdef
->default_cpu_model
;
1380 for(i
= 0; i
< smp_cpus
; i
++) {
1381 envs
[i
] = cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
1384 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
1385 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
1387 /* set up devices */
1388 ram_init(0, RAM_size
, hwdef
->max_mem
);
1390 prom_init(hwdef
->slavio_base
, bios_name
);
1392 dev
= sbi_init(hwdef
->sbi_base
, cpu_irqs
);
1394 for (i
= 0; i
< 32; i
++) {
1395 sbi_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1397 for (i
= 0; i
< MAX_CPUS
; i
++) {
1398 sbi_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
1401 for (i
= 0; i
< MAX_IOUNITS
; i
++)
1402 if (hwdef
->iounit_bases
[i
] != (target_phys_addr_t
)-1)
1403 iounits
[i
] = iommu_init(hwdef
->iounit_bases
[i
],
1404 hwdef
->iounit_version
,
1407 espdma
= sparc32_dma_init(hwdef
->espdma_base
, sbi_irq
[3],
1408 iounits
[0], &espdma_irq
);
1410 ledma
= sparc32_dma_init(hwdef
->ledma_base
, sbi_irq
[4],
1411 iounits
[0], &ledma_irq
);
1413 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1414 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1417 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1420 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1422 nvram
= m48t59_init(sbi_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
1424 slavio_timer_init_all(hwdef
->counter_base
, sbi_irq
[10], sbi_cpu_irq
, smp_cpus
);
1426 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, sbi_irq
[12],
1427 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1428 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1429 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1430 escc_init(hwdef
->serial_base
, sbi_irq
[12], sbi_irq
[12],
1431 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1433 if (drive_get_max_bus(IF_SCSI
) > 0) {
1434 fprintf(stderr
, "qemu: too many SCSI bus\n");
1438 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1439 esp_init(hwdef
->esp_base
, 2,
1440 espdma_memory_read
, espdma_memory_write
,
1441 espdma
, espdma_irq
, &esp_reset
);
1443 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1446 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1447 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1448 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1451 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1452 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1453 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1454 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1455 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1456 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1457 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1458 if (kernel_cmdline
) {
1459 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1460 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1462 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1464 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1465 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1466 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1467 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1470 /* SPARCserver 1000 hardware initialisation */
1471 static void ss1000_init(ram_addr_t RAM_size
,
1472 const char *boot_device
,
1473 const char *kernel_filename
, const char *kernel_cmdline
,
1474 const char *initrd_filename
, const char *cpu_model
)
1476 sun4d_hw_init(&sun4d_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1477 kernel_cmdline
, initrd_filename
, cpu_model
);
1480 /* SPARCcenter 2000 hardware initialisation */
1481 static void ss2000_init(ram_addr_t RAM_size
,
1482 const char *boot_device
,
1483 const char *kernel_filename
, const char *kernel_cmdline
,
1484 const char *initrd_filename
, const char *cpu_model
)
1486 sun4d_hw_init(&sun4d_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1487 kernel_cmdline
, initrd_filename
, cpu_model
);
1490 static QEMUMachine ss1000_machine
= {
1492 .desc
= "Sun4d platform, SPARCserver 1000",
1493 .init
= ss1000_init
,
1498 static QEMUMachine ss2000_machine
= {
1500 .desc
= "Sun4d platform, SPARCcenter 2000",
1501 .init
= ss2000_init
,
1506 static const struct sun4c_hwdef sun4c_hwdefs
[] = {
1509 .iommu_base
= 0xf8000000,
1510 .tcx_base
= 0xfe000000,
1511 .slavio_base
= 0xf6000000,
1512 .intctl_base
= 0xf5000000,
1513 .counter_base
= 0xf3000000,
1514 .ms_kb_base
= 0xf0000000,
1515 .serial_base
= 0xf1000000,
1516 .nvram_base
= 0xf2000000,
1517 .fd_base
= 0xf7200000,
1518 .dma_base
= 0xf8400000,
1519 .esp_base
= 0xf8800000,
1520 .le_base
= 0xf8c00000,
1521 .aux1_base
= 0xf7400003,
1522 .nvram_machine_id
= 0x55,
1523 .machine_id
= ss2_id
,
1524 .max_mem
= 0x10000000,
1525 .default_cpu_model
= "Cypress CY7C601",
1529 static DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
,
1530 qemu_irq
*parent_irq
)
1536 dev
= qdev_create(NULL
, "sun4c_intctl");
1539 s
= sysbus_from_qdev(dev
);
1541 for (i
= 0; i
< MAX_PILS
; i
++) {
1542 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
1544 sysbus_mmio_map(s
, 0, addr
);
1549 static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef
, ram_addr_t RAM_size
,
1550 const char *boot_device
,
1551 const char *kernel_filename
,
1552 const char *kernel_cmdline
,
1553 const char *initrd_filename
, const char *cpu_model
)
1556 void *iommu
, *espdma
, *ledma
, *nvram
;
1557 qemu_irq
*cpu_irqs
, slavio_irq
[8], espdma_irq
, ledma_irq
;
1560 unsigned long kernel_size
;
1561 DriveInfo
*fd
[MAX_FD
];
1568 cpu_model
= hwdef
->default_cpu_model
;
1570 env
= cpu_devinit(cpu_model
, 0, hwdef
->slavio_base
, &cpu_irqs
);
1572 /* set up devices */
1573 ram_init(0, RAM_size
, hwdef
->max_mem
);
1575 prom_init(hwdef
->slavio_base
, bios_name
);
1577 dev
= sun4c_intctl_init(hwdef
->intctl_base
, cpu_irqs
);
1579 for (i
= 0; i
< 8; i
++) {
1580 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1583 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
1586 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[2],
1587 iommu
, &espdma_irq
);
1589 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
1590 slavio_irq
[3], iommu
, &ledma_irq
);
1592 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1593 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1596 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1599 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1601 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x800, 2);
1603 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[1],
1604 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1605 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1606 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1607 escc_init(hwdef
->serial_base
, slavio_irq
[1],
1608 slavio_irq
[1], serial_hds
[0], serial_hds
[1],
1611 slavio_misc_init(0, hwdef
->aux1_base
, 0, slavio_irq
[1], fdc_tc
);
1613 if (hwdef
->fd_base
!= (target_phys_addr_t
)-1) {
1614 /* there is zero or one floppy drive */
1615 memset(fd
, 0, sizeof(fd
));
1616 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1617 sun4m_fdctrl_init(slavio_irq
[1], hwdef
->fd_base
, fd
,
1621 if (drive_get_max_bus(IF_SCSI
) > 0) {
1622 fprintf(stderr
, "qemu: too many SCSI bus\n");
1626 esp_reset
= qdev_get_gpio_in(espdma
, 0);
1627 esp_init(hwdef
->esp_base
, 2,
1628 espdma_memory_read
, espdma_memory_write
,
1629 espdma
, espdma_irq
, &esp_reset
);
1631 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1634 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1635 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1636 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1639 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1640 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1641 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1642 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1643 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1644 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1645 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1646 if (kernel_cmdline
) {
1647 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1648 pstrcpy_targphys(CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1650 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1652 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1653 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1654 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1655 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1658 /* SPARCstation 2 hardware initialisation */
1659 static void ss2_init(ram_addr_t RAM_size
,
1660 const char *boot_device
,
1661 const char *kernel_filename
, const char *kernel_cmdline
,
1662 const char *initrd_filename
, const char *cpu_model
)
1664 sun4c_hw_init(&sun4c_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1665 kernel_cmdline
, initrd_filename
, cpu_model
);
1668 static QEMUMachine ss2_machine
= {
1670 .desc
= "Sun4c platform, SPARCstation 2",
1675 static void ss2_machine_init(void)
1677 qemu_register_machine(&ss5_machine
);
1678 qemu_register_machine(&ss10_machine
);
1679 qemu_register_machine(&ss600mp_machine
);
1680 qemu_register_machine(&ss20_machine
);
1681 qemu_register_machine(&voyager_machine
);
1682 qemu_register_machine(&ss_lx_machine
);
1683 qemu_register_machine(&ss4_machine
);
1684 qemu_register_machine(&scls_machine
);
1685 qemu_register_machine(&sbook_machine
);
1686 qemu_register_machine(&ss1000_machine
);
1687 qemu_register_machine(&ss2000_machine
);
1688 qemu_register_machine(&ss2_machine
);
1691 machine_init(ss2_machine_init
);