hmp: fix info cpus for sparc targets
[qemu/ar7.git] / target-arm / op_helper.c
blobaef592ab8d4632aa67bf292c69ca0353984dbefa
1 /*
2 * ARM helper routines
4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "cpu.h"
20 #include "helper.h"
22 #define SIGNBIT (uint32_t)0x80000000
23 #define SIGNBIT64 ((uint64_t)1 << 63)
25 static void raise_exception(CPUARMState *env, int tt)
27 env->exception_index = tt;
28 cpu_loop_exit(env);
31 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
32 uint32_t rn, uint32_t maxindex)
34 uint32_t val;
35 uint32_t tmp;
36 int index;
37 int shift;
38 uint64_t *table;
39 table = (uint64_t *)&env->vfp.regs[rn];
40 val = 0;
41 for (shift = 0; shift < 32; shift += 8) {
42 index = (ireg >> shift) & 0xff;
43 if (index < maxindex) {
44 tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
45 val |= tmp << shift;
46 } else {
47 val |= def & (0xff << shift);
50 return val;
53 #if !defined(CONFIG_USER_ONLY)
55 #include "softmmu_exec.h"
57 #define MMUSUFFIX _mmu
59 #define SHIFT 0
60 #include "softmmu_template.h"
62 #define SHIFT 1
63 #include "softmmu_template.h"
65 #define SHIFT 2
66 #include "softmmu_template.h"
68 #define SHIFT 3
69 #include "softmmu_template.h"
71 /* try to fill the TLB and return an exception if error. If retaddr is
72 NULL, it means that the function was called in C code (i.e. not
73 from generated code or from helper.c) */
74 void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
75 uintptr_t retaddr)
77 TranslationBlock *tb;
78 int ret;
80 ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
81 if (unlikely(ret)) {
82 if (retaddr) {
83 /* now we have a real cpu fault */
84 tb = tb_find_pc(retaddr);
85 if (tb) {
86 /* the PC is inside the translated code. It means that we have
87 a virtual CPU fault */
88 cpu_restore_state(tb, env, retaddr);
91 raise_exception(env, env->exception_index);
94 #endif
96 /* FIXME: Pass an explicit pointer to QF to CPUARMState, and move saturating
97 instructions into helper.c */
98 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
100 uint32_t res = a + b;
101 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
102 env->QF = 1;
103 return res;
106 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
108 uint32_t res = a + b;
109 if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
110 env->QF = 1;
111 res = ~(((int32_t)a >> 31) ^ SIGNBIT);
113 return res;
116 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
118 uint32_t res = a - b;
119 if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
120 env->QF = 1;
121 res = ~(((int32_t)a >> 31) ^ SIGNBIT);
123 return res;
126 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
128 uint32_t res;
129 if (val >= 0x40000000) {
130 res = ~SIGNBIT;
131 env->QF = 1;
132 } else if (val <= (int32_t)0xc0000000) {
133 res = SIGNBIT;
134 env->QF = 1;
135 } else {
136 res = val << 1;
138 return res;
141 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
143 uint32_t res = a + b;
144 if (res < a) {
145 env->QF = 1;
146 res = ~0;
148 return res;
151 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
153 uint32_t res = a - b;
154 if (res > a) {
155 env->QF = 1;
156 res = 0;
158 return res;
161 /* Signed saturation. */
162 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
164 int32_t top;
165 uint32_t mask;
167 top = val >> shift;
168 mask = (1u << shift) - 1;
169 if (top > 0) {
170 env->QF = 1;
171 return mask;
172 } else if (top < -1) {
173 env->QF = 1;
174 return ~mask;
176 return val;
179 /* Unsigned saturation. */
180 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
182 uint32_t max;
184 max = (1u << shift) - 1;
185 if (val < 0) {
186 env->QF = 1;
187 return 0;
188 } else if (val > max) {
189 env->QF = 1;
190 return max;
192 return val;
195 /* Signed saturate. */
196 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
198 return do_ssat(env, x, shift);
201 /* Dual halfword signed saturate. */
202 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
204 uint32_t res;
206 res = (uint16_t)do_ssat(env, (int16_t)x, shift);
207 res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
208 return res;
211 /* Unsigned saturate. */
212 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
214 return do_usat(env, x, shift);
217 /* Dual halfword unsigned saturate. */
218 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
220 uint32_t res;
222 res = (uint16_t)do_usat(env, (int16_t)x, shift);
223 res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
224 return res;
227 void HELPER(wfi)(CPUARMState *env)
229 env->exception_index = EXCP_HLT;
230 env->halted = 1;
231 cpu_loop_exit(env);
234 void HELPER(exception)(CPUARMState *env, uint32_t excp)
236 env->exception_index = excp;
237 cpu_loop_exit(env);
240 uint32_t HELPER(cpsr_read)(CPUARMState *env)
242 return cpsr_read(env) & ~CPSR_EXEC;
245 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
247 cpsr_write(env, val, mask);
250 /* Access to user mode registers from privileged modes. */
251 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
253 uint32_t val;
255 if (regno == 13) {
256 val = env->banked_r13[0];
257 } else if (regno == 14) {
258 val = env->banked_r14[0];
259 } else if (regno >= 8
260 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
261 val = env->usr_regs[regno - 8];
262 } else {
263 val = env->regs[regno];
265 return val;
268 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
270 if (regno == 13) {
271 env->banked_r13[0] = val;
272 } else if (regno == 14) {
273 env->banked_r14[0] = val;
274 } else if (regno >= 8
275 && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
276 env->usr_regs[regno - 8] = val;
277 } else {
278 env->regs[regno] = val;
282 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
284 const ARMCPRegInfo *ri = rip;
285 int excp = ri->writefn(env, ri, value);
286 if (excp) {
287 raise_exception(env, excp);
291 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
293 const ARMCPRegInfo *ri = rip;
294 uint64_t value;
295 int excp = ri->readfn(env, ri, &value);
296 if (excp) {
297 raise_exception(env, excp);
299 return value;
302 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
304 const ARMCPRegInfo *ri = rip;
305 int excp = ri->writefn(env, ri, value);
306 if (excp) {
307 raise_exception(env, excp);
311 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
313 const ARMCPRegInfo *ri = rip;
314 uint64_t value;
315 int excp = ri->readfn(env, ri, &value);
316 if (excp) {
317 raise_exception(env, excp);
319 return value;
322 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
323 The only way to do that in TCG is a conditional branch, which clobbers
324 all our temporaries. For now implement these as helper functions. */
326 uint32_t HELPER(adc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
328 uint32_t result;
329 if (!env->CF) {
330 result = a + b;
331 env->CF = result < a;
332 } else {
333 result = a + b + 1;
334 env->CF = result <= a;
336 env->VF = (a ^ b ^ -1) & (a ^ result);
337 env->NF = env->ZF = result;
338 return result;
341 uint32_t HELPER(sbc_cc)(CPUARMState *env, uint32_t a, uint32_t b)
343 uint32_t result;
344 if (!env->CF) {
345 result = a - b - 1;
346 env->CF = a > b;
347 } else {
348 result = a - b;
349 env->CF = a >= b;
351 env->VF = (a ^ b) & (a ^ result);
352 env->NF = env->ZF = result;
353 return result;
356 /* Similarly for variable shift instructions. */
358 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
360 int shift = i & 0xff;
361 if (shift >= 32) {
362 if (shift == 32)
363 env->CF = x & 1;
364 else
365 env->CF = 0;
366 return 0;
367 } else if (shift != 0) {
368 env->CF = (x >> (32 - shift)) & 1;
369 return x << shift;
371 return x;
374 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
376 int shift = i & 0xff;
377 if (shift >= 32) {
378 if (shift == 32)
379 env->CF = (x >> 31) & 1;
380 else
381 env->CF = 0;
382 return 0;
383 } else if (shift != 0) {
384 env->CF = (x >> (shift - 1)) & 1;
385 return x >> shift;
387 return x;
390 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
392 int shift = i & 0xff;
393 if (shift >= 32) {
394 env->CF = (x >> 31) & 1;
395 return (int32_t)x >> 31;
396 } else if (shift != 0) {
397 env->CF = (x >> (shift - 1)) & 1;
398 return (int32_t)x >> shift;
400 return x;
403 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
405 int shift1, shift;
406 shift1 = i & 0xff;
407 shift = shift1 & 0x1f;
408 if (shift == 0) {
409 if (shift1 != 0)
410 env->CF = (x >> 31) & 1;
411 return x;
412 } else {
413 env->CF = (x >> (shift - 1)) & 1;
414 return ((uint32_t)x >> shift) | (x << (32 - shift));