hw/mips/cps.c

   1 /*
   2  * Coherent Processing System emulation.
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/module.h"
  23 #include "hw/mips/cps.h"
  24 #include "hw/mips/mips.h"
  25 #include "hw/qdev-properties.h"
  26 #include "hw/mips/cpudevs.h"
  27 #include "sysemu/kvm.h"
  28 #include "sysemu/reset.h"
  29
  30 qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number)
  31 {
  32     assert(pin_number < s->num_irq);
  33     return s->gic.irq_state[pin_number].irq;
  34 }
  35
  36 static void mips_cps_init(Object *obj)
  37 {
  38     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
  39     MIPSCPSState *s = MIPS_CPS(obj);
  40
  41     /*
  42      * Cover entire address space as there do not seem to be any
  43      * constraints for the base address of CPC and GIC.
  44      */
  45     memory_region_init(&s->container, obj, "mips-cps-container", UINT64_MAX);
  46     sysbus_init_mmio(sbd, &s->container);
  47 }
  48
  49 static void main_cpu_reset(void *opaque)
  50 {
  51     MIPSCPU *cpu = opaque;
  52     CPUState *cs = CPU(cpu);
  53
  54     cpu_reset(cs);
  55
  56     /* All VPs are halted on reset. Leave powering up to CPC. */
  57     cs->halted = 1;
  58 }
  59
  60 static bool cpu_mips_itu_supported(CPUMIPSState *env)
  61 {
  62     bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) ||
  63                  (env->CP0_Config3 & (1 << CP0C3_MT));
  64
  65     return is_mt && !kvm_enabled();
  66 }
  67
  68 static void mips_cps_realize(DeviceState *dev, Error **errp)
  69 {
  70     MIPSCPSState *s = MIPS_CPS(dev);
  71     CPUMIPSState *env;
  72     MIPSCPU *cpu;
  73     int i;
  74     target_ulong gcr_base;
  75     bool itu_present = false;
  76     bool saar_present = false;
  77
  78     for (i = 0; i < s->num_vp; i++) {
  79         cpu = MIPS_CPU(cpu_create(s->cpu_type));
  80
  81         /* Init internal devices */
  82         cpu_mips_irq_init_cpu(cpu);
  83         cpu_mips_clock_init(cpu);
  84
  85         env = &cpu->env;
  86         if (cpu_mips_itu_supported(env)) {
  87             itu_present = true;
  88             /* Attach ITC Tag to the VP */
  89             env->itc_tag = mips_itu_get_tag_region(&s->itu);
  90             env->itu = &s->itu;
  91         }
  92         qemu_register_reset(main_cpu_reset, cpu);
  93     }
  94
  95     cpu = MIPS_CPU(first_cpu);
  96     env = &cpu->env;
  97     saar_present = (bool)env->saarp;
  98
  99     /* Inter-Thread Communication Unit */
 100     if (itu_present) {
 101         object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU);
 102         object_property_set_int(OBJECT(&s->itu), "num-fifo", 16,
 103                                 &error_abort);
 104         object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16,
 105                                 &error_abort);
 106         object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_present,
 107                                  &error_abort);
 108         if (saar_present) {
 109             s->itu.saar = &env->CP0_SAAR;
 110         }
 111         if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) {
 112             return;
 113         }
 114
 115         memory_region_add_subregion(&s->container, 0,
 116                            sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
 117     }
 118
 119     /* Cluster Power Controller */
 120     object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC);
 121     object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp,
 122                             &error_abort);
 123     object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1,
 124                             &error_abort);
 125     if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpc), errp)) {
 126         return;
 127     }
 128
 129     memory_region_add_subregion(&s->container, 0,
 130                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
 131
 132     /* Global Interrupt Controller */
 133     object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC);
 134     object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp,
 135                             &error_abort);
 136     object_property_set_int(OBJECT(&s->gic), "num-irq", 128,
 137                             &error_abort);
 138     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) {
 139         return;
 140     }
 141
 142     memory_region_add_subregion(&s->container, 0,
 143                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
 144
 145     /* Global Configuration Registers */
 146     gcr_base = env->CP0_CMGCRBase << 4;
 147
 148     object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
 149     object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp,
 150                             &error_abort);
 151     object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800,
 152                             &error_abort);
 153     object_property_set_int(OBJECT(&s->gcr), "gcr-base", gcr_base,
 154                             &error_abort);
 155     object_property_set_link(OBJECT(&s->gcr), "gic", OBJECT(&s->gic.mr),
 156                              &error_abort);
 157     object_property_set_link(OBJECT(&s->gcr), "cpc", OBJECT(&s->cpc.mr),
 158                              &error_abort);
 159     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
 160         return;
 161     }
 162
 163     memory_region_add_subregion(&s->container, gcr_base,
 164                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
 165 }
 166
 167 static Property mips_cps_properties[] = {
 168     DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, 1),
 169     DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256),
 170     DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type),
 171     DEFINE_PROP_END_OF_LIST()
 172 };
 173
 174 static void mips_cps_class_init(ObjectClass *klass, void *data)
 175 {
 176     DeviceClass *dc = DEVICE_CLASS(klass);
 177
 178     dc->realize = mips_cps_realize;
 179     device_class_set_props(dc, mips_cps_properties);
 180 }
 181
 182 static const TypeInfo mips_cps_info = {
 183     .name = TYPE_MIPS_CPS,
 184     .parent = TYPE_SYS_BUS_DEVICE,
 185     .instance_size = sizeof(MIPSCPSState),
 186     .instance_init = mips_cps_init,
 187     .class_init = mips_cps_class_init,
 188 };
 189
 190 static void mips_cps_register_types(void)
 191 {
 192     type_register_static(&mips_cps_info);
 193 }
 194
 195 type_init(mips_cps_register_types)