hw/xio3130_upstream.c

   1 /*
   2  * xio3130_upstream.c
   3  * TI X3130 pci express upstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "pci/pci_ids.h"
  23 #include "pci/msi.h"
  24 #include "pci/pcie.h"
  25 #include "xio3130_upstream.h"
  26
  27 #define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
  28 #define XIO3130_REVISION                0x2
  29 #define XIO3130_MSI_OFFSET              0x70
  30 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  31 #define XIO3130_MSI_NR_VECTOR           1
  32 #define XIO3130_SSVID_OFFSET            0x80
  33 #define XIO3130_SSVID_SVID              0
  34 #define XIO3130_SSVID_SSID              0
  35 #define XIO3130_EXP_OFFSET              0x90
  36 #define XIO3130_AER_OFFSET              0x100
  37
  38 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
  39                                           uint32_t val, int len)
  40 {
  41     pci_bridge_write_config(d, address, val, len);
  42     pcie_cap_flr_write_config(d, address, val, len);
  43     pcie_aer_write_config(d, address, val, len);
  44 }
  45
  46 static void xio3130_upstream_reset(DeviceState *qdev)
  47 {
  48     PCIDevice *d = PCI_DEVICE(qdev);
  49
  50     pci_bridge_reset(qdev);
  51     pcie_cap_deverr_reset(d);
  52 }
  53
  54 static int xio3130_upstream_initfn(PCIDevice *d)
  55 {
  56     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  57     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  58     int rc;
  59
  60     rc = pci_bridge_initfn(d);
  61     if (rc < 0) {
  62         return rc;
  63     }
  64
  65     pcie_port_init_reg(d);
  66
  67     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  68                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  69                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  70     if (rc < 0) {
  71         goto err_bridge;
  72     }
  73     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  74                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  75     if (rc < 0) {
  76         goto err_bridge;
  77     }
  78     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
  79                        p->port);
  80     if (rc < 0) {
  81         goto err_msi;
  82     }
  83     pcie_cap_flr_init(d);
  84     pcie_cap_deverr_init(d);
  85     rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
  86     if (rc < 0) {
  87         goto err;
  88     }
  89
  90     return 0;
  91
  92 err:
  93     pcie_cap_exit(d);
  94 err_msi:
  95     msi_uninit(d);
  96 err_bridge:
  97     pci_bridge_exitfn(d);
  98     return rc;
  99 }
 100
 101 static void xio3130_upstream_exitfn(PCIDevice *d)
 102 {
 103     pcie_aer_exit(d);
 104     pcie_cap_exit(d);
 105     msi_uninit(d);
 106     pci_bridge_exitfn(d);
 107 }
 108
 109 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
 110                              const char *bus_name, pci_map_irq_fn map_irq,
 111                              uint8_t port)
 112 {
 113     PCIDevice *d;
 114     PCIBridge *br;
 115     DeviceState *qdev;
 116
 117     d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
 118     if (!d) {
 119         return NULL;
 120     }
 121     br = DO_UPCAST(PCIBridge, dev, d);
 122
 123     qdev = &br->dev.qdev;
 124     pci_bridge_map_irq(br, bus_name, map_irq);
 125     qdev_prop_set_uint8(qdev, "port", port);
 126     qdev_init_nofail(qdev);
 127
 128     return DO_UPCAST(PCIEPort, br, br);
 129 }
 130
 131 static const VMStateDescription vmstate_xio3130_upstream = {
 132     .name = "xio3130-express-upstream-port",
 133     .version_id = 1,
 134     .minimum_version_id = 1,
 135     .minimum_version_id_old = 1,
 136     .fields = (VMStateField[]) {
 137         VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
 138         VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
 139                        PCIEAERLog),
 140         VMSTATE_END_OF_LIST()
 141     }
 142 };
 143
 144 static Property xio3130_upstream_properties[] = {
 145     DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
 146     DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
 147     PCIE_AER_LOG_MAX_DEFAULT),
 148     DEFINE_PROP_END_OF_LIST(),
 149 };
 150
 151 static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
 152 {
 153     DeviceClass *dc = DEVICE_CLASS(klass);
 154     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 155
 156     k->is_express = 1;
 157     k->is_bridge = 1;
 158     k->config_write = xio3130_upstream_write_config;
 159     k->init = xio3130_upstream_initfn;
 160     k->exit = xio3130_upstream_exitfn;
 161     k->vendor_id = PCI_VENDOR_ID_TI;
 162     k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
 163     k->revision = XIO3130_REVISION;
 164     dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
 165     dc->reset = xio3130_upstream_reset;
 166     dc->vmsd = &vmstate_xio3130_upstream;
 167     dc->props = xio3130_upstream_properties;
 168 }
 169
 170 static const TypeInfo xio3130_upstream_info = {
 171     .name          = "x3130-upstream",
 172     .parent        = TYPE_PCI_DEVICE,
 173     .instance_size = sizeof(PCIEPort),
 174     .class_init    = xio3130_upstream_class_init,
 175 };
 176
 177 static void xio3130_upstream_register_types(void)
 178 {
 179     type_register_static(&xio3130_upstream_info);
 180 }
 181
 182 type_init(xio3130_upstream_register_types)
 183
 184
 185 /*
 186  * Local variables:
 187  *  c-indent-level: 4
 188  *  c-basic-offset: 4
 189  *  tab-width: 8
 190  *  indent-tab-mode: nil
 191  * End:
 192  */