4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qapi/error.h"
22 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "exec/target_page.h"
27 #include "hw/qdev-core.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/boards.h"
31 #include "hw/xen/xen.h"
33 #include "sysemu/kvm.h"
34 #include "sysemu/sysemu.h"
35 #include "qemu/timer.h"
36 #include "qemu/config-file.h"
37 #include "qemu/error-report.h"
38 #if defined(CONFIG_USER_ONLY)
40 #else /* !CONFIG_USER_ONLY */
42 #include "exec/memory.h"
43 #include "exec/ioport.h"
44 #include "sysemu/dma.h"
45 #include "sysemu/numa.h"
46 #include "sysemu/hw_accel.h"
47 #include "exec/address-spaces.h"
48 #include "sysemu/xen-mapcache.h"
49 #include "trace-root.h"
51 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
52 #include <linux/falloc.h>
56 #include "qemu/rcu_queue.h"
57 #include "qemu/main-loop.h"
58 #include "translate-all.h"
59 #include "sysemu/replay.h"
61 #include "exec/memory-internal.h"
62 #include "exec/ram_addr.h"
65 #include "migration/vmstate.h"
67 #include "qemu/range.h"
69 #include "qemu/mmap-alloc.h"
72 #include "monitor/monitor.h"
74 //#define DEBUG_SUBPAGE
76 #if !defined(CONFIG_USER_ONLY)
77 /* ram_list is read under rcu_read_lock()/rcu_read_unlock(). Writes
78 * are protected by the ramlist lock.
80 RAMList ram_list
= { .blocks
= QLIST_HEAD_INITIALIZER(ram_list
.blocks
) };
82 static MemoryRegion
*system_memory
;
83 static MemoryRegion
*system_io
;
85 AddressSpace address_space_io
;
86 AddressSpace address_space_memory
;
88 MemoryRegion io_mem_rom
, io_mem_notdirty
;
89 static MemoryRegion io_mem_unassigned
;
92 #ifdef TARGET_PAGE_BITS_VARY
94 bool target_page_bits_decided
;
97 struct CPUTailQ cpus
= QTAILQ_HEAD_INITIALIZER(cpus
);
98 /* current CPU in the current thread. It is only valid inside
100 __thread CPUState
*current_cpu
;
101 /* 0 = Do not count executed instructions.
102 1 = Precise instruction counting.
103 2 = Adaptive rate instruction counting. */
106 uintptr_t qemu_host_page_size
;
107 intptr_t qemu_host_page_mask
;
109 bool set_preferred_target_page_bits(int bits
)
111 /* The target page size is the lowest common denominator for all
112 * the CPUs in the system, so we can only make it smaller, never
113 * larger. And we can't make it smaller once we've committed to
116 #ifdef TARGET_PAGE_BITS_VARY
117 assert(bits
>= TARGET_PAGE_BITS_MIN
);
118 if (target_page_bits
== 0 || target_page_bits
> bits
) {
119 if (target_page_bits_decided
) {
122 target_page_bits
= bits
;
128 #if !defined(CONFIG_USER_ONLY)
130 static void finalize_target_page_bits(void)
132 #ifdef TARGET_PAGE_BITS_VARY
133 if (target_page_bits
== 0) {
134 target_page_bits
= TARGET_PAGE_BITS_MIN
;
136 target_page_bits_decided
= true;
140 typedef struct PhysPageEntry PhysPageEntry
;
142 struct PhysPageEntry
{
143 /* How many bits skip to next level (in units of L2_SIZE). 0 for a leaf. */
145 /* index into phys_sections (!skip) or phys_map_nodes (skip) */
149 #define PHYS_MAP_NODE_NIL (((uint32_t)~0) >> 6)
151 /* Size of the L2 (and L3, etc) page tables. */
152 #define ADDR_SPACE_BITS 64
155 #define P_L2_SIZE (1 << P_L2_BITS)
157 #define P_L2_LEVELS (((ADDR_SPACE_BITS - TARGET_PAGE_BITS - 1) / P_L2_BITS) + 1)
159 typedef PhysPageEntry Node
[P_L2_SIZE
];
161 typedef struct PhysPageMap
{
164 unsigned sections_nb
;
165 unsigned sections_nb_alloc
;
167 unsigned nodes_nb_alloc
;
169 MemoryRegionSection
*sections
;
172 struct AddressSpaceDispatch
{
173 MemoryRegionSection
*mru_section
;
174 /* This is a multi-level map on the physical address space.
175 * The bottom level has pointers to MemoryRegionSections.
177 PhysPageEntry phys_map
;
181 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
182 typedef struct subpage_t
{
186 uint16_t sub_section
[];
189 #define PHYS_SECTION_UNASSIGNED 0
190 #define PHYS_SECTION_NOTDIRTY 1
191 #define PHYS_SECTION_ROM 2
192 #define PHYS_SECTION_WATCH 3
194 static void io_mem_init(void);
195 static void memory_map_init(void);
196 static void tcg_commit(MemoryListener
*listener
);
198 static MemoryRegion io_mem_watch
;
201 * CPUAddressSpace: all the information a CPU needs about an AddressSpace
202 * @cpu: the CPU whose AddressSpace this is
203 * @as: the AddressSpace itself
204 * @memory_dispatch: its dispatch pointer (cached, RCU protected)
205 * @tcg_as_listener: listener for tracking changes to the AddressSpace
207 struct CPUAddressSpace
{
210 struct AddressSpaceDispatch
*memory_dispatch
;
211 MemoryListener tcg_as_listener
;
214 struct DirtyBitmapSnapshot
{
217 unsigned long dirty
[];
222 #if !defined(CONFIG_USER_ONLY)
224 static void phys_map_node_reserve(PhysPageMap
*map
, unsigned nodes
)
226 static unsigned alloc_hint
= 16;
227 if (map
->nodes_nb
+ nodes
> map
->nodes_nb_alloc
) {
228 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, alloc_hint
);
229 map
->nodes_nb_alloc
= MAX(map
->nodes_nb_alloc
, map
->nodes_nb
+ nodes
);
230 map
->nodes
= g_renew(Node
, map
->nodes
, map
->nodes_nb_alloc
);
231 alloc_hint
= map
->nodes_nb_alloc
;
235 static uint32_t phys_map_node_alloc(PhysPageMap
*map
, bool leaf
)
242 ret
= map
->nodes_nb
++;
244 assert(ret
!= PHYS_MAP_NODE_NIL
);
245 assert(ret
!= map
->nodes_nb_alloc
);
247 e
.skip
= leaf
? 0 : 1;
248 e
.ptr
= leaf
? PHYS_SECTION_UNASSIGNED
: PHYS_MAP_NODE_NIL
;
249 for (i
= 0; i
< P_L2_SIZE
; ++i
) {
250 memcpy(&p
[i
], &e
, sizeof(e
));
255 static void phys_page_set_level(PhysPageMap
*map
, PhysPageEntry
*lp
,
256 hwaddr
*index
, hwaddr
*nb
, uint16_t leaf
,
260 hwaddr step
= (hwaddr
)1 << (level
* P_L2_BITS
);
262 if (lp
->skip
&& lp
->ptr
== PHYS_MAP_NODE_NIL
) {
263 lp
->ptr
= phys_map_node_alloc(map
, level
== 0);
265 p
= map
->nodes
[lp
->ptr
];
266 lp
= &p
[(*index
>> (level
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
268 while (*nb
&& lp
< &p
[P_L2_SIZE
]) {
269 if ((*index
& (step
- 1)) == 0 && *nb
>= step
) {
275 phys_page_set_level(map
, lp
, index
, nb
, leaf
, level
- 1);
281 static void phys_page_set(AddressSpaceDispatch
*d
,
282 hwaddr index
, hwaddr nb
,
285 /* Wildly overreserve - it doesn't matter much. */
286 phys_map_node_reserve(&d
->map
, 3 * P_L2_LEVELS
);
288 phys_page_set_level(&d
->map
, &d
->phys_map
, &index
, &nb
, leaf
, P_L2_LEVELS
- 1);
291 /* Compact a non leaf page entry. Simply detect that the entry has a single child,
292 * and update our entry so we can skip it and go directly to the destination.
294 static void phys_page_compact(PhysPageEntry
*lp
, Node
*nodes
)
296 unsigned valid_ptr
= P_L2_SIZE
;
301 if (lp
->ptr
== PHYS_MAP_NODE_NIL
) {
306 for (i
= 0; i
< P_L2_SIZE
; i
++) {
307 if (p
[i
].ptr
== PHYS_MAP_NODE_NIL
) {
314 phys_page_compact(&p
[i
], nodes
);
318 /* We can only compress if there's only one child. */
323 assert(valid_ptr
< P_L2_SIZE
);
325 /* Don't compress if it won't fit in the # of bits we have. */
326 if (lp
->skip
+ p
[valid_ptr
].skip
>= (1 << 3)) {
330 lp
->ptr
= p
[valid_ptr
].ptr
;
331 if (!p
[valid_ptr
].skip
) {
332 /* If our only child is a leaf, make this a leaf. */
333 /* By design, we should have made this node a leaf to begin with so we
334 * should never reach here.
335 * But since it's so simple to handle this, let's do it just in case we
340 lp
->skip
+= p
[valid_ptr
].skip
;
344 void address_space_dispatch_compact(AddressSpaceDispatch
*d
)
346 if (d
->phys_map
.skip
) {
347 phys_page_compact(&d
->phys_map
, d
->map
.nodes
);
351 static inline bool section_covers_addr(const MemoryRegionSection
*section
,
354 /* Memory topology clips a memory region to [0, 2^64); size.hi > 0 means
355 * the section must cover the entire address space.
357 return int128_gethi(section
->size
) ||
358 range_covers_byte(section
->offset_within_address_space
,
359 int128_getlo(section
->size
), addr
);
362 static MemoryRegionSection
*phys_page_find(AddressSpaceDispatch
*d
, hwaddr addr
)
364 PhysPageEntry lp
= d
->phys_map
, *p
;
365 Node
*nodes
= d
->map
.nodes
;
366 MemoryRegionSection
*sections
= d
->map
.sections
;
367 hwaddr index
= addr
>> TARGET_PAGE_BITS
;
370 for (i
= P_L2_LEVELS
; lp
.skip
&& (i
-= lp
.skip
) >= 0;) {
371 if (lp
.ptr
== PHYS_MAP_NODE_NIL
) {
372 return §ions
[PHYS_SECTION_UNASSIGNED
];
375 lp
= p
[(index
>> (i
* P_L2_BITS
)) & (P_L2_SIZE
- 1)];
378 if (section_covers_addr(§ions
[lp
.ptr
], addr
)) {
379 return §ions
[lp
.ptr
];
381 return §ions
[PHYS_SECTION_UNASSIGNED
];
385 /* Called from RCU critical section */
386 static MemoryRegionSection
*address_space_lookup_region(AddressSpaceDispatch
*d
,
388 bool resolve_subpage
)
390 MemoryRegionSection
*section
= atomic_read(&d
->mru_section
);
393 if (!section
|| section
== &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
] ||
394 !section_covers_addr(section
, addr
)) {
395 section
= phys_page_find(d
, addr
);
396 atomic_set(&d
->mru_section
, section
);
398 if (resolve_subpage
&& section
->mr
->subpage
) {
399 subpage
= container_of(section
->mr
, subpage_t
, iomem
);
400 section
= &d
->map
.sections
[subpage
->sub_section
[SUBPAGE_IDX(addr
)]];
405 /* Called from RCU critical section */
406 static MemoryRegionSection
*
407 address_space_translate_internal(AddressSpaceDispatch
*d
, hwaddr addr
, hwaddr
*xlat
,
408 hwaddr
*plen
, bool resolve_subpage
)
410 MemoryRegionSection
*section
;
414 section
= address_space_lookup_region(d
, addr
, resolve_subpage
);
415 /* Compute offset within MemoryRegionSection */
416 addr
-= section
->offset_within_address_space
;
418 /* Compute offset within MemoryRegion */
419 *xlat
= addr
+ section
->offset_within_region
;
423 /* MMIO registers can be expected to perform full-width accesses based only
424 * on their address, without considering adjacent registers that could
425 * decode to completely different MemoryRegions. When such registers
426 * exist (e.g. I/O ports 0xcf8 and 0xcf9 on most PC chipsets), MMIO
427 * regions overlap wildly. For this reason we cannot clamp the accesses
430 * If the length is small (as is the case for address_space_ldl/stl),
431 * everything works fine. If the incoming length is large, however,
432 * the caller really has to do the clamping through memory_access_size.
434 if (memory_region_is_ram(mr
)) {
435 diff
= int128_sub(section
->size
, int128_make64(addr
));
436 *plen
= int128_get64(int128_min(diff
, int128_make64(*plen
)));
442 * address_space_translate_iommu - translate an address through an IOMMU
443 * memory region and then through the target address space.
445 * @iommu_mr: the IOMMU memory region that we start the translation from
446 * @addr: the address to be translated through the MMU
447 * @xlat: the translated address offset within the destination memory region.
448 * It cannot be %NULL.
449 * @plen_out: valid read/write length of the translated address. It
451 * @page_mask_out: page mask for the translated address. This
452 * should only be meaningful for IOMMU translated
453 * addresses, since there may be huge pages that this bit
454 * would tell. It can be %NULL if we don't care about it.
455 * @is_write: whether the translation operation is for write
456 * @is_mmio: whether this can be MMIO, set true if it can
457 * @target_as: the address space targeted by the IOMMU
458 * @attrs: transaction attributes
460 * This function is called from RCU critical section. It is the common
461 * part of flatview_do_translate and address_space_translate_cached.
463 static MemoryRegionSection
address_space_translate_iommu(IOMMUMemoryRegion
*iommu_mr
,
466 hwaddr
*page_mask_out
,
469 AddressSpace
**target_as
,
472 MemoryRegionSection
*section
;
473 hwaddr page_mask
= (hwaddr
)-1;
477 IOMMUMemoryRegionClass
*imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
481 if (imrc
->attrs_to_index
) {
482 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
485 iotlb
= imrc
->translate(iommu_mr
, addr
, is_write
?
486 IOMMU_WO
: IOMMU_RO
, iommu_idx
);
488 if (!(iotlb
.perm
& (1 << is_write
))) {
492 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
493 | (addr
& iotlb
.addr_mask
));
494 page_mask
&= iotlb
.addr_mask
;
495 *plen_out
= MIN(*plen_out
, (addr
| iotlb
.addr_mask
) - addr
+ 1);
496 *target_as
= iotlb
.target_as
;
498 section
= address_space_translate_internal(
499 address_space_to_dispatch(iotlb
.target_as
), addr
, xlat
,
502 iommu_mr
= memory_region_get_iommu(section
->mr
);
503 } while (unlikely(iommu_mr
));
506 *page_mask_out
= page_mask
;
511 return (MemoryRegionSection
) { .mr
= &io_mem_unassigned
};
515 * flatview_do_translate - translate an address in FlatView
517 * @fv: the flat view that we want to translate on
518 * @addr: the address to be translated in above address space
519 * @xlat: the translated address offset within memory region. It
521 * @plen_out: valid read/write length of the translated address. It
522 * can be @NULL when we don't care about it.
523 * @page_mask_out: page mask for the translated address. This
524 * should only be meaningful for IOMMU translated
525 * addresses, since there may be huge pages that this bit
526 * would tell. It can be @NULL if we don't care about it.
527 * @is_write: whether the translation operation is for write
528 * @is_mmio: whether this can be MMIO, set true if it can
529 * @target_as: the address space targeted by the IOMMU
530 * @attrs: memory transaction attributes
532 * This function is called from RCU critical section
534 static MemoryRegionSection
flatview_do_translate(FlatView
*fv
,
538 hwaddr
*page_mask_out
,
541 AddressSpace
**target_as
,
544 MemoryRegionSection
*section
;
545 IOMMUMemoryRegion
*iommu_mr
;
546 hwaddr plen
= (hwaddr
)(-1);
552 section
= address_space_translate_internal(
553 flatview_to_dispatch(fv
), addr
, xlat
,
556 iommu_mr
= memory_region_get_iommu(section
->mr
);
557 if (unlikely(iommu_mr
)) {
558 return address_space_translate_iommu(iommu_mr
, xlat
,
559 plen_out
, page_mask_out
,
564 /* Not behind an IOMMU, use default page size. */
565 *page_mask_out
= ~TARGET_PAGE_MASK
;
571 /* Called from RCU critical section */
572 IOMMUTLBEntry
address_space_get_iotlb_entry(AddressSpace
*as
, hwaddr addr
,
573 bool is_write
, MemTxAttrs attrs
)
575 MemoryRegionSection section
;
576 hwaddr xlat
, page_mask
;
579 * This can never be MMIO, and we don't really care about plen,
582 section
= flatview_do_translate(address_space_to_flatview(as
), addr
, &xlat
,
583 NULL
, &page_mask
, is_write
, false, &as
,
586 /* Illegal translation */
587 if (section
.mr
== &io_mem_unassigned
) {
591 /* Convert memory region offset into address space offset */
592 xlat
+= section
.offset_within_address_space
-
593 section
.offset_within_region
;
595 return (IOMMUTLBEntry
) {
597 .iova
= addr
& ~page_mask
,
598 .translated_addr
= xlat
& ~page_mask
,
599 .addr_mask
= page_mask
,
600 /* IOTLBs are for DMAs, and DMA only allows on RAMs. */
605 return (IOMMUTLBEntry
) {0};
608 /* Called from RCU critical section */
609 MemoryRegion
*flatview_translate(FlatView
*fv
, hwaddr addr
, hwaddr
*xlat
,
610 hwaddr
*plen
, bool is_write
,
614 MemoryRegionSection section
;
615 AddressSpace
*as
= NULL
;
617 /* This can be MMIO, so setup MMIO bit. */
618 section
= flatview_do_translate(fv
, addr
, xlat
, plen
, NULL
,
619 is_write
, true, &as
, attrs
);
622 if (xen_enabled() && memory_access_is_direct(mr
, is_write
)) {
623 hwaddr page
= ((addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
) - addr
;
624 *plen
= MIN(page
, *plen
);
630 typedef struct TCGIOMMUNotifier
{
638 static void tcg_iommu_unmap_notify(IOMMUNotifier
*n
, IOMMUTLBEntry
*iotlb
)
640 TCGIOMMUNotifier
*notifier
= container_of(n
, TCGIOMMUNotifier
, n
);
642 if (!notifier
->active
) {
645 tlb_flush(notifier
->cpu
);
646 notifier
->active
= false;
647 /* We leave the notifier struct on the list to avoid reallocating it later.
648 * Generally the number of IOMMUs a CPU deals with will be small.
649 * In any case we can't unregister the iommu notifier from a notify
654 static void tcg_register_iommu_notifier(CPUState
*cpu
,
655 IOMMUMemoryRegion
*iommu_mr
,
658 /* Make sure this CPU has an IOMMU notifier registered for this
659 * IOMMU/IOMMU index combination, so that we can flush its TLB
660 * when the IOMMU tells us the mappings we've cached have changed.
662 MemoryRegion
*mr
= MEMORY_REGION(iommu_mr
);
663 TCGIOMMUNotifier
*notifier
;
666 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
667 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
668 if (notifier
->mr
== mr
&& notifier
->iommu_idx
== iommu_idx
) {
672 if (i
== cpu
->iommu_notifiers
->len
) {
673 /* Not found, add a new entry at the end of the array */
674 cpu
->iommu_notifiers
= g_array_set_size(cpu
->iommu_notifiers
, i
+ 1);
675 notifier
= g_new0(TCGIOMMUNotifier
, 1);
676 g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
) = notifier
;
679 notifier
->iommu_idx
= iommu_idx
;
681 /* Rather than trying to register interest in the specific part
682 * of the iommu's address space that we've accessed and then
683 * expand it later as subsequent accesses touch more of it, we
684 * just register interest in the whole thing, on the assumption
685 * that iommu reconfiguration will be rare.
687 iommu_notifier_init(¬ifier
->n
,
688 tcg_iommu_unmap_notify
,
689 IOMMU_NOTIFIER_UNMAP
,
693 memory_region_register_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
696 if (!notifier
->active
) {
697 notifier
->active
= true;
701 static void tcg_iommu_free_notifier_list(CPUState
*cpu
)
703 /* Destroy the CPU's notifier list */
705 TCGIOMMUNotifier
*notifier
;
707 for (i
= 0; i
< cpu
->iommu_notifiers
->len
; i
++) {
708 notifier
= g_array_index(cpu
->iommu_notifiers
, TCGIOMMUNotifier
*, i
);
709 memory_region_unregister_iommu_notifier(notifier
->mr
, ¬ifier
->n
);
712 g_array_free(cpu
->iommu_notifiers
, true);
715 /* Called from RCU critical section */
716 MemoryRegionSection
*
717 address_space_translate_for_iotlb(CPUState
*cpu
, int asidx
, hwaddr addr
,
718 hwaddr
*xlat
, hwaddr
*plen
,
719 MemTxAttrs attrs
, int *prot
)
721 MemoryRegionSection
*section
;
722 IOMMUMemoryRegion
*iommu_mr
;
723 IOMMUMemoryRegionClass
*imrc
;
726 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpu
->cpu_ases
[asidx
].memory_dispatch
);
729 section
= address_space_translate_internal(d
, addr
, &addr
, plen
, false);
731 iommu_mr
= memory_region_get_iommu(section
->mr
);
736 imrc
= memory_region_get_iommu_class_nocheck(iommu_mr
);
738 iommu_idx
= imrc
->attrs_to_index(iommu_mr
, attrs
);
739 tcg_register_iommu_notifier(cpu
, iommu_mr
, iommu_idx
);
740 /* We need all the permissions, so pass IOMMU_NONE so the IOMMU
741 * doesn't short-cut its translation table walk.
743 iotlb
= imrc
->translate(iommu_mr
, addr
, IOMMU_NONE
, iommu_idx
);
744 addr
= ((iotlb
.translated_addr
& ~iotlb
.addr_mask
)
745 | (addr
& iotlb
.addr_mask
));
746 /* Update the caller's prot bits to remove permissions the IOMMU
747 * is giving us a failure response for. If we get down to no
748 * permissions left at all we can give up now.
750 if (!(iotlb
.perm
& IOMMU_RO
)) {
751 *prot
&= ~(PAGE_READ
| PAGE_EXEC
);
753 if (!(iotlb
.perm
& IOMMU_WO
)) {
754 *prot
&= ~PAGE_WRITE
;
761 d
= flatview_to_dispatch(address_space_to_flatview(iotlb
.target_as
));
764 assert(!memory_region_is_iommu(section
->mr
));
769 return &d
->map
.sections
[PHYS_SECTION_UNASSIGNED
];
773 #if !defined(CONFIG_USER_ONLY)
775 static int cpu_common_post_load(void *opaque
, int version_id
)
777 CPUState
*cpu
= opaque
;
779 /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
780 version_id is increased. */
781 cpu
->interrupt_request
&= ~0x01;
784 /* loadvm has just updated the content of RAM, bypassing the
785 * usual mechanisms that ensure we flush TBs for writes to
786 * memory we've translated code from. So we must flush all TBs,
787 * which will now be stale.
794 static int cpu_common_pre_load(void *opaque
)
796 CPUState
*cpu
= opaque
;
798 cpu
->exception_index
= -1;
803 static bool cpu_common_exception_index_needed(void *opaque
)
805 CPUState
*cpu
= opaque
;
807 return tcg_enabled() && cpu
->exception_index
!= -1;
810 static const VMStateDescription vmstate_cpu_common_exception_index
= {
811 .name
= "cpu_common/exception_index",
813 .minimum_version_id
= 1,
814 .needed
= cpu_common_exception_index_needed
,
815 .fields
= (VMStateField
[]) {
816 VMSTATE_INT32(exception_index
, CPUState
),
817 VMSTATE_END_OF_LIST()
821 static bool cpu_common_crash_occurred_needed(void *opaque
)
823 CPUState
*cpu
= opaque
;
825 return cpu
->crash_occurred
;
828 static const VMStateDescription vmstate_cpu_common_crash_occurred
= {
829 .name
= "cpu_common/crash_occurred",
831 .minimum_version_id
= 1,
832 .needed
= cpu_common_crash_occurred_needed
,
833 .fields
= (VMStateField
[]) {
834 VMSTATE_BOOL(crash_occurred
, CPUState
),
835 VMSTATE_END_OF_LIST()
839 const VMStateDescription vmstate_cpu_common
= {
840 .name
= "cpu_common",
842 .minimum_version_id
= 1,
843 .pre_load
= cpu_common_pre_load
,
844 .post_load
= cpu_common_post_load
,
845 .fields
= (VMStateField
[]) {
846 VMSTATE_UINT32(halted
, CPUState
),
847 VMSTATE_UINT32(interrupt_request
, CPUState
),
848 VMSTATE_END_OF_LIST()
850 .subsections
= (const VMStateDescription
*[]) {
851 &vmstate_cpu_common_exception_index
,
852 &vmstate_cpu_common_crash_occurred
,
859 CPUState
*qemu_get_cpu(int index
)
864 if (cpu
->cpu_index
== index
) {
872 #if !defined(CONFIG_USER_ONLY)
873 void cpu_address_space_init(CPUState
*cpu
, int asidx
,
874 const char *prefix
, MemoryRegion
*mr
)
876 CPUAddressSpace
*newas
;
877 AddressSpace
*as
= g_new0(AddressSpace
, 1);
881 as_name
= g_strdup_printf("%s-%d", prefix
, cpu
->cpu_index
);
882 address_space_init(as
, mr
, as_name
);
885 /* Target code should have set num_ases before calling us */
886 assert(asidx
< cpu
->num_ases
);
889 /* address space 0 gets the convenience alias */
893 /* KVM cannot currently support multiple address spaces. */
894 assert(asidx
== 0 || !kvm_enabled());
896 if (!cpu
->cpu_ases
) {
897 cpu
->cpu_ases
= g_new0(CPUAddressSpace
, cpu
->num_ases
);
900 newas
= &cpu
->cpu_ases
[asidx
];
904 newas
->tcg_as_listener
.commit
= tcg_commit
;
905 memory_listener_register(&newas
->tcg_as_listener
, as
);
909 AddressSpace
*cpu_get_address_space(CPUState
*cpu
, int asidx
)
911 /* Return the AddressSpace corresponding to the specified index */
912 return cpu
->cpu_ases
[asidx
].as
;
916 void cpu_exec_unrealizefn(CPUState
*cpu
)
918 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
920 cpu_list_remove(cpu
);
922 if (cc
->vmsd
!= NULL
) {
923 vmstate_unregister(NULL
, cc
->vmsd
, cpu
);
925 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
926 vmstate_unregister(NULL
, &vmstate_cpu_common
, cpu
);
928 #ifndef CONFIG_USER_ONLY
929 tcg_iommu_free_notifier_list(cpu
);
933 Property cpu_common_props
[] = {
934 #ifndef CONFIG_USER_ONLY
935 /* Create a memory property for softmmu CPU object,
936 * so users can wire up its memory. (This can't go in qom/cpu.c
937 * because that file is compiled only once for both user-mode
938 * and system builds.) The default if no link is set up is to use
939 * the system address space.
941 DEFINE_PROP_LINK("memory", CPUState
, memory
, TYPE_MEMORY_REGION
,
944 DEFINE_PROP_END_OF_LIST(),
947 void cpu_exec_initfn(CPUState
*cpu
)
952 #ifndef CONFIG_USER_ONLY
953 cpu
->thread_id
= qemu_get_thread_id();
954 cpu
->memory
= system_memory
;
955 object_ref(OBJECT(cpu
->memory
));
959 void cpu_exec_realizefn(CPUState
*cpu
, Error
**errp
)
961 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
962 static bool tcg_target_initialized
;
966 if (tcg_enabled() && !tcg_target_initialized
) {
967 tcg_target_initialized
= true;
968 cc
->tcg_initialize();
972 #ifndef CONFIG_USER_ONLY
973 if (qdev_get_vmsd(DEVICE(cpu
)) == NULL
) {
974 vmstate_register(NULL
, cpu
->cpu_index
, &vmstate_cpu_common
, cpu
);
976 if (cc
->vmsd
!= NULL
) {
977 vmstate_register(NULL
, cpu
->cpu_index
, cc
->vmsd
, cpu
);
980 cpu
->iommu_notifiers
= g_array_new(false, true, sizeof(TCGIOMMUNotifier
*));
984 const char *parse_cpu_model(const char *cpu_model
)
988 gchar
**model_pieces
;
989 const char *cpu_type
;
991 model_pieces
= g_strsplit(cpu_model
, ",", 2);
993 oc
= cpu_class_by_name(CPU_RESOLVING_TYPE
, model_pieces
[0]);
995 error_report("unable to find CPU model '%s'", model_pieces
[0]);
996 g_strfreev(model_pieces
);
1000 cpu_type
= object_class_get_name(oc
);
1002 cc
->parse_features(cpu_type
, model_pieces
[1], &error_fatal
);
1003 g_strfreev(model_pieces
);
1007 #if defined(CONFIG_USER_ONLY)
1008 void tb_invalidate_phys_addr(target_ulong addr
)
1011 tb_invalidate_phys_page_range(addr
, addr
+ 1, 0);
1015 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1017 tb_invalidate_phys_addr(pc
);
1020 void tb_invalidate_phys_addr(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
)
1022 ram_addr_t ram_addr
;
1026 if (!tcg_enabled()) {
1031 mr
= address_space_translate(as
, addr
, &addr
, &l
, false, attrs
);
1032 if (!(memory_region_is_ram(mr
)
1033 || memory_region_is_romd(mr
))) {
1037 ram_addr
= memory_region_get_ram_addr(mr
) + addr
;
1038 tb_invalidate_phys_page_range(ram_addr
, ram_addr
+ 1, 0);
1042 static void breakpoint_invalidate(CPUState
*cpu
, target_ulong pc
)
1045 hwaddr phys
= cpu_get_phys_page_attrs_debug(cpu
, pc
, &attrs
);
1046 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
1048 /* Locks grabbed by tb_invalidate_phys_addr */
1049 tb_invalidate_phys_addr(cpu
->cpu_ases
[asidx
].as
,
1050 phys
| (pc
& ~TARGET_PAGE_MASK
), attrs
);
1055 #if defined(CONFIG_USER_ONLY)
1056 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1061 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1067 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1071 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1072 int flags
, CPUWatchpoint
**watchpoint
)
1077 /* Add a watchpoint. */
1078 int cpu_watchpoint_insert(CPUState
*cpu
, vaddr addr
, vaddr len
,
1079 int flags
, CPUWatchpoint
**watchpoint
)
1083 /* forbid ranges which are empty or run off the end of the address space */
1084 if (len
== 0 || (addr
+ len
- 1) < addr
) {
1085 error_report("tried to set invalid watchpoint at %"
1086 VADDR_PRIx
", len=%" VADDR_PRIu
, addr
, len
);
1089 wp
= g_malloc(sizeof(*wp
));
1095 /* keep all GDB-injected watchpoints in front */
1096 if (flags
& BP_GDB
) {
1097 QTAILQ_INSERT_HEAD(&cpu
->watchpoints
, wp
, entry
);
1099 QTAILQ_INSERT_TAIL(&cpu
->watchpoints
, wp
, entry
);
1102 tlb_flush_page(cpu
, addr
);
1109 /* Remove a specific watchpoint. */
1110 int cpu_watchpoint_remove(CPUState
*cpu
, vaddr addr
, vaddr len
,
1115 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1116 if (addr
== wp
->vaddr
&& len
== wp
->len
1117 && flags
== (wp
->flags
& ~BP_WATCHPOINT_HIT
)) {
1118 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1125 /* Remove a specific watchpoint by reference. */
1126 void cpu_watchpoint_remove_by_ref(CPUState
*cpu
, CPUWatchpoint
*watchpoint
)
1128 QTAILQ_REMOVE(&cpu
->watchpoints
, watchpoint
, entry
);
1130 tlb_flush_page(cpu
, watchpoint
->vaddr
);
1135 /* Remove all matching watchpoints. */
1136 void cpu_watchpoint_remove_all(CPUState
*cpu
, int mask
)
1138 CPUWatchpoint
*wp
, *next
;
1140 QTAILQ_FOREACH_SAFE(wp
, &cpu
->watchpoints
, entry
, next
) {
1141 if (wp
->flags
& mask
) {
1142 cpu_watchpoint_remove_by_ref(cpu
, wp
);
1147 /* Return true if this watchpoint address matches the specified
1148 * access (ie the address range covered by the watchpoint overlaps
1149 * partially or completely with the address range covered by the
1152 static inline bool cpu_watchpoint_address_matches(CPUWatchpoint
*wp
,
1156 /* We know the lengths are non-zero, but a little caution is
1157 * required to avoid errors in the case where the range ends
1158 * exactly at the top of the address space and so addr + len
1159 * wraps round to zero.
1161 vaddr wpend
= wp
->vaddr
+ wp
->len
- 1;
1162 vaddr addrend
= addr
+ len
- 1;
1164 return !(addr
> wpend
|| wp
->vaddr
> addrend
);
1169 /* Add a breakpoint. */
1170 int cpu_breakpoint_insert(CPUState
*cpu
, vaddr pc
, int flags
,
1171 CPUBreakpoint
**breakpoint
)
1175 bp
= g_malloc(sizeof(*bp
));
1180 /* keep all GDB-injected breakpoints in front */
1181 if (flags
& BP_GDB
) {
1182 QTAILQ_INSERT_HEAD(&cpu
->breakpoints
, bp
, entry
);
1184 QTAILQ_INSERT_TAIL(&cpu
->breakpoints
, bp
, entry
);
1187 breakpoint_invalidate(cpu
, pc
);
1195 /* Remove a specific breakpoint. */
1196 int cpu_breakpoint_remove(CPUState
*cpu
, vaddr pc
, int flags
)
1200 QTAILQ_FOREACH(bp
, &cpu
->breakpoints
, entry
) {
1201 if (bp
->pc
== pc
&& bp
->flags
== flags
) {
1202 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1209 /* Remove a specific breakpoint by reference. */
1210 void cpu_breakpoint_remove_by_ref(CPUState
*cpu
, CPUBreakpoint
*breakpoint
)
1212 QTAILQ_REMOVE(&cpu
->breakpoints
, breakpoint
, entry
);
1214 breakpoint_invalidate(cpu
, breakpoint
->pc
);
1219 /* Remove all matching breakpoints. */
1220 void cpu_breakpoint_remove_all(CPUState
*cpu
, int mask
)
1222 CPUBreakpoint
*bp
, *next
;
1224 QTAILQ_FOREACH_SAFE(bp
, &cpu
->breakpoints
, entry
, next
) {
1225 if (bp
->flags
& mask
) {
1226 cpu_breakpoint_remove_by_ref(cpu
, bp
);
1231 /* enable or disable single step mode. EXCP_DEBUG is returned by the
1232 CPU loop after each instruction */
1233 void cpu_single_step(CPUState
*cpu
, int enabled
)
1235 if (cpu
->singlestep_enabled
!= enabled
) {
1236 cpu
->singlestep_enabled
= enabled
;
1237 if (kvm_enabled()) {
1238 kvm_update_guest_debug(cpu
, 0);
1240 /* must flush all the translated code to avoid inconsistencies */
1241 /* XXX: only flush what is necessary */
1247 void cpu_abort(CPUState
*cpu
, const char *fmt
, ...)
1254 fprintf(stderr
, "qemu: fatal: ");
1255 vfprintf(stderr
, fmt
, ap
);
1256 fprintf(stderr
, "\n");
1257 cpu_dump_state(cpu
, stderr
, fprintf
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1258 if (qemu_log_separate()) {
1260 qemu_log("qemu: fatal: ");
1261 qemu_log_vprintf(fmt
, ap2
);
1263 log_cpu_state(cpu
, CPU_DUMP_FPU
| CPU_DUMP_CCOP
);
1271 #if defined(CONFIG_USER_ONLY)
1273 struct sigaction act
;
1274 sigfillset(&act
.sa_mask
);
1275 act
.sa_handler
= SIG_DFL
;
1277 sigaction(SIGABRT
, &act
, NULL
);
1283 #if !defined(CONFIG_USER_ONLY)
1284 /* Called from RCU critical section */
1285 static RAMBlock
*qemu_get_ram_block(ram_addr_t addr
)
1289 block
= atomic_rcu_read(&ram_list
.mru_block
);
1290 if (block
&& addr
- block
->offset
< block
->max_length
) {
1293 RAMBLOCK_FOREACH(block
) {
1294 if (addr
- block
->offset
< block
->max_length
) {
1299 fprintf(stderr
, "Bad ram offset %" PRIx64
"\n", (uint64_t)addr
);
1303 /* It is safe to write mru_block outside the iothread lock. This
1308 * xxx removed from list
1312 * call_rcu(reclaim_ramblock, xxx);
1315 * atomic_rcu_set is not needed here. The block was already published
1316 * when it was placed into the list. Here we're just making an extra
1317 * copy of the pointer.
1319 ram_list
.mru_block
= block
;
1323 static void tlb_reset_dirty_range_all(ram_addr_t start
, ram_addr_t length
)
1330 assert(tcg_enabled());
1331 end
= TARGET_PAGE_ALIGN(start
+ length
);
1332 start
&= TARGET_PAGE_MASK
;
1335 block
= qemu_get_ram_block(start
);
1336 assert(block
== qemu_get_ram_block(end
- 1));
1337 start1
= (uintptr_t)ramblock_ptr(block
, start
- block
->offset
);
1339 tlb_reset_dirty(cpu
, start1
, length
);
1344 /* Note: start and end must be within the same ram block. */
1345 bool cpu_physical_memory_test_and_clear_dirty(ram_addr_t start
,
1349 DirtyMemoryBlocks
*blocks
;
1350 unsigned long end
, page
;
1357 end
= TARGET_PAGE_ALIGN(start
+ length
) >> TARGET_PAGE_BITS
;
1358 page
= start
>> TARGET_PAGE_BITS
;
1362 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1364 while (page
< end
) {
1365 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1366 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1367 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1369 dirty
|= bitmap_test_and_clear_atomic(blocks
->blocks
[idx
],
1376 if (dirty
&& tcg_enabled()) {
1377 tlb_reset_dirty_range_all(start
, length
);
1383 DirtyBitmapSnapshot
*cpu_physical_memory_snapshot_and_clear_dirty
1384 (ram_addr_t start
, ram_addr_t length
, unsigned client
)
1386 DirtyMemoryBlocks
*blocks
;
1387 unsigned long align
= 1UL << (TARGET_PAGE_BITS
+ BITS_PER_LEVEL
);
1388 ram_addr_t first
= QEMU_ALIGN_DOWN(start
, align
);
1389 ram_addr_t last
= QEMU_ALIGN_UP(start
+ length
, align
);
1390 DirtyBitmapSnapshot
*snap
;
1391 unsigned long page
, end
, dest
;
1393 snap
= g_malloc0(sizeof(*snap
) +
1394 ((last
- first
) >> (TARGET_PAGE_BITS
+ 3)));
1395 snap
->start
= first
;
1398 page
= first
>> TARGET_PAGE_BITS
;
1399 end
= last
>> TARGET_PAGE_BITS
;
1404 blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[client
]);
1406 while (page
< end
) {
1407 unsigned long idx
= page
/ DIRTY_MEMORY_BLOCK_SIZE
;
1408 unsigned long offset
= page
% DIRTY_MEMORY_BLOCK_SIZE
;
1409 unsigned long num
= MIN(end
- page
, DIRTY_MEMORY_BLOCK_SIZE
- offset
);
1411 assert(QEMU_IS_ALIGNED(offset
, (1 << BITS_PER_LEVEL
)));
1412 assert(QEMU_IS_ALIGNED(num
, (1 << BITS_PER_LEVEL
)));
1413 offset
>>= BITS_PER_LEVEL
;
1415 bitmap_copy_and_clear_atomic(snap
->dirty
+ dest
,
1416 blocks
->blocks
[idx
] + offset
,
1419 dest
+= num
>> BITS_PER_LEVEL
;
1424 if (tcg_enabled()) {
1425 tlb_reset_dirty_range_all(start
, length
);
1431 bool cpu_physical_memory_snapshot_get_dirty(DirtyBitmapSnapshot
*snap
,
1435 unsigned long page
, end
;
1437 assert(start
>= snap
->start
);
1438 assert(start
+ length
<= snap
->end
);
1440 end
= TARGET_PAGE_ALIGN(start
+ length
- snap
->start
) >> TARGET_PAGE_BITS
;
1441 page
= (start
- snap
->start
) >> TARGET_PAGE_BITS
;
1443 while (page
< end
) {
1444 if (test_bit(page
, snap
->dirty
)) {
1452 /* Called from RCU critical section */
1453 hwaddr
memory_region_section_get_iotlb(CPUState
*cpu
,
1454 MemoryRegionSection
*section
,
1456 hwaddr paddr
, hwaddr xlat
,
1458 target_ulong
*address
)
1463 if (memory_region_is_ram(section
->mr
)) {
1465 iotlb
= memory_region_get_ram_addr(section
->mr
) + xlat
;
1466 if (!section
->readonly
) {
1467 iotlb
|= PHYS_SECTION_NOTDIRTY
;
1469 iotlb
|= PHYS_SECTION_ROM
;
1472 AddressSpaceDispatch
*d
;
1474 d
= flatview_to_dispatch(section
->fv
);
1475 iotlb
= section
- d
->map
.sections
;
1479 /* Make accesses to pages with watchpoints go via the
1480 watchpoint trap routines. */
1481 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
1482 if (cpu_watchpoint_address_matches(wp
, vaddr
, TARGET_PAGE_SIZE
)) {
1483 /* Avoid trapping reads of pages with a write breakpoint. */
1484 if ((prot
& PAGE_WRITE
) || (wp
->flags
& BP_MEM_READ
)) {
1485 iotlb
= PHYS_SECTION_WATCH
+ paddr
;
1486 *address
|= TLB_MMIO
;
1494 #endif /* defined(CONFIG_USER_ONLY) */
1496 #if !defined(CONFIG_USER_ONLY)
1498 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
1500 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
);
1502 static void *(*phys_mem_alloc
)(size_t size
, uint64_t *align
, bool shared
) =
1503 qemu_anon_ram_alloc
;
1506 * Set a custom physical guest memory alloator.
1507 * Accelerators with unusual needs may need this. Hopefully, we can
1508 * get rid of it eventually.
1510 void phys_mem_set_alloc(void *(*alloc
)(size_t, uint64_t *align
, bool shared
))
1512 phys_mem_alloc
= alloc
;
1515 static uint16_t phys_section_add(PhysPageMap
*map
,
1516 MemoryRegionSection
*section
)
1518 /* The physical section number is ORed with a page-aligned
1519 * pointer to produce the iotlb entries. Thus it should
1520 * never overflow into the page-aligned value.
1522 assert(map
->sections_nb
< TARGET_PAGE_SIZE
);
1524 if (map
->sections_nb
== map
->sections_nb_alloc
) {
1525 map
->sections_nb_alloc
= MAX(map
->sections_nb_alloc
* 2, 16);
1526 map
->sections
= g_renew(MemoryRegionSection
, map
->sections
,
1527 map
->sections_nb_alloc
);
1529 map
->sections
[map
->sections_nb
] = *section
;
1530 memory_region_ref(section
->mr
);
1531 return map
->sections_nb
++;
1534 static void phys_section_destroy(MemoryRegion
*mr
)
1536 bool have_sub_page
= mr
->subpage
;
1538 memory_region_unref(mr
);
1540 if (have_sub_page
) {
1541 subpage_t
*subpage
= container_of(mr
, subpage_t
, iomem
);
1542 object_unref(OBJECT(&subpage
->iomem
));
1547 static void phys_sections_free(PhysPageMap
*map
)
1549 while (map
->sections_nb
> 0) {
1550 MemoryRegionSection
*section
= &map
->sections
[--map
->sections_nb
];
1551 phys_section_destroy(section
->mr
);
1553 g_free(map
->sections
);
1557 static void register_subpage(FlatView
*fv
, MemoryRegionSection
*section
)
1559 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1561 hwaddr base
= section
->offset_within_address_space
1563 MemoryRegionSection
*existing
= phys_page_find(d
, base
);
1564 MemoryRegionSection subsection
= {
1565 .offset_within_address_space
= base
,
1566 .size
= int128_make64(TARGET_PAGE_SIZE
),
1570 assert(existing
->mr
->subpage
|| existing
->mr
== &io_mem_unassigned
);
1572 if (!(existing
->mr
->subpage
)) {
1573 subpage
= subpage_init(fv
, base
);
1575 subsection
.mr
= &subpage
->iomem
;
1576 phys_page_set(d
, base
>> TARGET_PAGE_BITS
, 1,
1577 phys_section_add(&d
->map
, &subsection
));
1579 subpage
= container_of(existing
->mr
, subpage_t
, iomem
);
1581 start
= section
->offset_within_address_space
& ~TARGET_PAGE_MASK
;
1582 end
= start
+ int128_get64(section
->size
) - 1;
1583 subpage_register(subpage
, start
, end
,
1584 phys_section_add(&d
->map
, section
));
1588 static void register_multipage(FlatView
*fv
,
1589 MemoryRegionSection
*section
)
1591 AddressSpaceDispatch
*d
= flatview_to_dispatch(fv
);
1592 hwaddr start_addr
= section
->offset_within_address_space
;
1593 uint16_t section_index
= phys_section_add(&d
->map
, section
);
1594 uint64_t num_pages
= int128_get64(int128_rshift(section
->size
,
1598 phys_page_set(d
, start_addr
>> TARGET_PAGE_BITS
, num_pages
, section_index
);
1601 void flatview_add_to_dispatch(FlatView
*fv
, MemoryRegionSection
*section
)
1603 MemoryRegionSection now
= *section
, remain
= *section
;
1604 Int128 page_size
= int128_make64(TARGET_PAGE_SIZE
);
1606 if (now
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1607 uint64_t left
= TARGET_PAGE_ALIGN(now
.offset_within_address_space
)
1608 - now
.offset_within_address_space
;
1610 now
.size
= int128_min(int128_make64(left
), now
.size
);
1611 register_subpage(fv
, &now
);
1613 now
.size
= int128_zero();
1615 while (int128_ne(remain
.size
, now
.size
)) {
1616 remain
.size
= int128_sub(remain
.size
, now
.size
);
1617 remain
.offset_within_address_space
+= int128_get64(now
.size
);
1618 remain
.offset_within_region
+= int128_get64(now
.size
);
1620 if (int128_lt(remain
.size
, page_size
)) {
1621 register_subpage(fv
, &now
);
1622 } else if (remain
.offset_within_address_space
& ~TARGET_PAGE_MASK
) {
1623 now
.size
= page_size
;
1624 register_subpage(fv
, &now
);
1626 now
.size
= int128_and(now
.size
, int128_neg(page_size
));
1627 register_multipage(fv
, &now
);
1632 void qemu_flush_coalesced_mmio_buffer(void)
1635 kvm_flush_coalesced_mmio_buffer();
1638 void qemu_mutex_lock_ramlist(void)
1640 qemu_mutex_lock(&ram_list
.mutex
);
1643 void qemu_mutex_unlock_ramlist(void)
1645 qemu_mutex_unlock(&ram_list
.mutex
);
1648 void ram_block_dump(Monitor
*mon
)
1654 monitor_printf(mon
, "%24s %8s %18s %18s %18s\n",
1655 "Block Name", "PSize", "Offset", "Used", "Total");
1656 RAMBLOCK_FOREACH(block
) {
1657 psize
= size_to_str(block
->page_size
);
1658 monitor_printf(mon
, "%24s %8s 0x%016" PRIx64
" 0x%016" PRIx64
1659 " 0x%016" PRIx64
"\n", block
->idstr
, psize
,
1660 (uint64_t)block
->offset
,
1661 (uint64_t)block
->used_length
,
1662 (uint64_t)block
->max_length
);
1670 * FIXME TOCTTOU: this iterates over memory backends' mem-path, which
1671 * may or may not name the same files / on the same filesystem now as
1672 * when we actually open and map them. Iterate over the file
1673 * descriptors instead, and use qemu_fd_getpagesize().
1675 static int find_max_supported_pagesize(Object
*obj
, void *opaque
)
1677 long *hpsize_min
= opaque
;
1679 if (object_dynamic_cast(obj
, TYPE_MEMORY_BACKEND
)) {
1680 long hpsize
= host_memory_backend_pagesize(MEMORY_BACKEND(obj
));
1682 if (hpsize
< *hpsize_min
) {
1683 *hpsize_min
= hpsize
;
1690 long qemu_getrampagesize(void)
1692 long hpsize
= LONG_MAX
;
1693 long mainrampagesize
;
1694 Object
*memdev_root
;
1696 mainrampagesize
= qemu_mempath_getpagesize(mem_path
);
1698 /* it's possible we have memory-backend objects with
1699 * hugepage-backed RAM. these may get mapped into system
1700 * address space via -numa parameters or memory hotplug
1701 * hooks. we want to take these into account, but we
1702 * also want to make sure these supported hugepage
1703 * sizes are applicable across the entire range of memory
1704 * we may boot from, so we take the min across all
1705 * backends, and assume normal pages in cases where a
1706 * backend isn't backed by hugepages.
1708 memdev_root
= object_resolve_path("/objects", NULL
);
1710 object_child_foreach(memdev_root
, find_max_supported_pagesize
, &hpsize
);
1712 if (hpsize
== LONG_MAX
) {
1713 /* No additional memory regions found ==> Report main RAM page size */
1714 return mainrampagesize
;
1717 /* If NUMA is disabled or the NUMA nodes are not backed with a
1718 * memory-backend, then there is at least one node using "normal" RAM,
1719 * so if its page size is smaller we have got to report that size instead.
1721 if (hpsize
> mainrampagesize
&&
1722 (nb_numa_nodes
== 0 || numa_info
[0].node_memdev
== NULL
)) {
1725 error_report("Huge page support disabled (n/a for main memory).");
1728 return mainrampagesize
;
1734 long qemu_getrampagesize(void)
1736 return getpagesize();
1741 static int64_t get_file_size(int fd
)
1743 int64_t size
= lseek(fd
, 0, SEEK_END
);
1750 static int file_ram_open(const char *path
,
1751 const char *region_name
,
1756 char *sanitized_name
;
1762 fd
= open(path
, O_RDWR
);
1764 /* @path names an existing file, use it */
1767 if (errno
== ENOENT
) {
1768 /* @path names a file that doesn't exist, create it */
1769 fd
= open(path
, O_RDWR
| O_CREAT
| O_EXCL
, 0644);
1774 } else if (errno
== EISDIR
) {
1775 /* @path names a directory, create a file there */
1776 /* Make name safe to use with mkstemp by replacing '/' with '_'. */
1777 sanitized_name
= g_strdup(region_name
);
1778 for (c
= sanitized_name
; *c
!= '\0'; c
++) {
1784 filename
= g_strdup_printf("%s/qemu_back_mem.%s.XXXXXX", path
,
1786 g_free(sanitized_name
);
1788 fd
= mkstemp(filename
);
1796 if (errno
!= EEXIST
&& errno
!= EINTR
) {
1797 error_setg_errno(errp
, errno
,
1798 "can't open backing store %s for guest RAM",
1803 * Try again on EINTR and EEXIST. The latter happens when
1804 * something else creates the file between our two open().
1811 static void *file_ram_alloc(RAMBlock
*block
,
1819 block
->page_size
= qemu_fd_getpagesize(fd
);
1820 if (block
->mr
->align
% block
->page_size
) {
1821 error_setg(errp
, "alignment 0x%" PRIx64
1822 " must be multiples of page size 0x%zx",
1823 block
->mr
->align
, block
->page_size
);
1825 } else if (block
->mr
->align
&& !is_power_of_2(block
->mr
->align
)) {
1826 error_setg(errp
, "alignment 0x%" PRIx64
1827 " must be a power of two", block
->mr
->align
);
1830 block
->mr
->align
= MAX(block
->page_size
, block
->mr
->align
);
1831 #if defined(__s390x__)
1832 if (kvm_enabled()) {
1833 block
->mr
->align
= MAX(block
->mr
->align
, QEMU_VMALLOC_ALIGN
);
1837 if (memory
< block
->page_size
) {
1838 error_setg(errp
, "memory size 0x" RAM_ADDR_FMT
" must be equal to "
1839 "or larger than page size 0x%zx",
1840 memory
, block
->page_size
);
1844 memory
= ROUND_UP(memory
, block
->page_size
);
1847 * ftruncate is not supported by hugetlbfs in older
1848 * hosts, so don't bother bailing out on errors.
1849 * If anything goes wrong with it under other filesystems,
1852 * Do not truncate the non-empty backend file to avoid corrupting
1853 * the existing data in the file. Disabling shrinking is not
1854 * enough. For example, the current vNVDIMM implementation stores
1855 * the guest NVDIMM labels at the end of the backend file. If the
1856 * backend file is later extended, QEMU will not be able to find
1857 * those labels. Therefore, extending the non-empty backend file
1858 * is disabled as well.
1860 if (truncate
&& ftruncate(fd
, memory
)) {
1861 perror("ftruncate");
1864 area
= qemu_ram_mmap(fd
, memory
, block
->mr
->align
,
1865 block
->flags
& RAM_SHARED
);
1866 if (area
== MAP_FAILED
) {
1867 error_setg_errno(errp
, errno
,
1868 "unable to map backing store for guest RAM");
1873 os_mem_prealloc(fd
, area
, memory
, smp_cpus
, errp
);
1874 if (errp
&& *errp
) {
1875 qemu_ram_munmap(area
, memory
);
1885 /* Allocate space within the ram_addr_t space that governs the
1887 * Called with the ramlist lock held.
1889 static ram_addr_t
find_ram_offset(ram_addr_t size
)
1891 RAMBlock
*block
, *next_block
;
1892 ram_addr_t offset
= RAM_ADDR_MAX
, mingap
= RAM_ADDR_MAX
;
1894 assert(size
!= 0); /* it would hand out same offset multiple times */
1896 if (QLIST_EMPTY_RCU(&ram_list
.blocks
)) {
1900 RAMBLOCK_FOREACH(block
) {
1901 ram_addr_t candidate
, next
= RAM_ADDR_MAX
;
1903 /* Align blocks to start on a 'long' in the bitmap
1904 * which makes the bitmap sync'ing take the fast path.
1906 candidate
= block
->offset
+ block
->max_length
;
1907 candidate
= ROUND_UP(candidate
, BITS_PER_LONG
<< TARGET_PAGE_BITS
);
1909 /* Search for the closest following block
1912 RAMBLOCK_FOREACH(next_block
) {
1913 if (next_block
->offset
>= candidate
) {
1914 next
= MIN(next
, next_block
->offset
);
1918 /* If it fits remember our place and remember the size
1919 * of gap, but keep going so that we might find a smaller
1920 * gap to fill so avoiding fragmentation.
1922 if (next
- candidate
>= size
&& next
- candidate
< mingap
) {
1924 mingap
= next
- candidate
;
1927 trace_find_ram_offset_loop(size
, candidate
, offset
, next
, mingap
);
1930 if (offset
== RAM_ADDR_MAX
) {
1931 fprintf(stderr
, "Failed to find gap of requested size: %" PRIu64
"\n",
1936 trace_find_ram_offset(size
, offset
);
1941 static unsigned long last_ram_page(void)
1944 ram_addr_t last
= 0;
1947 RAMBLOCK_FOREACH(block
) {
1948 last
= MAX(last
, block
->offset
+ block
->max_length
);
1951 return last
>> TARGET_PAGE_BITS
;
1954 static void qemu_ram_setup_dump(void *addr
, ram_addr_t size
)
1958 /* Use MADV_DONTDUMP, if user doesn't want the guest memory in the core */
1959 if (!machine_dump_guest_core(current_machine
)) {
1960 ret
= qemu_madvise(addr
, size
, QEMU_MADV_DONTDUMP
);
1962 perror("qemu_madvise");
1963 fprintf(stderr
, "madvise doesn't support MADV_DONTDUMP, "
1964 "but dump_guest_core=off specified\n");
1969 const char *qemu_ram_get_idstr(RAMBlock
*rb
)
1974 bool qemu_ram_is_shared(RAMBlock
*rb
)
1976 return rb
->flags
& RAM_SHARED
;
1979 /* Note: Only set at the start of postcopy */
1980 bool qemu_ram_is_uf_zeroable(RAMBlock
*rb
)
1982 return rb
->flags
& RAM_UF_ZEROPAGE
;
1985 void qemu_ram_set_uf_zeroable(RAMBlock
*rb
)
1987 rb
->flags
|= RAM_UF_ZEROPAGE
;
1990 bool qemu_ram_is_migratable(RAMBlock
*rb
)
1992 return rb
->flags
& RAM_MIGRATABLE
;
1995 void qemu_ram_set_migratable(RAMBlock
*rb
)
1997 rb
->flags
|= RAM_MIGRATABLE
;
2000 void qemu_ram_unset_migratable(RAMBlock
*rb
)
2002 rb
->flags
&= ~RAM_MIGRATABLE
;
2005 /* Called with iothread lock held. */
2006 void qemu_ram_set_idstr(RAMBlock
*new_block
, const char *name
, DeviceState
*dev
)
2011 assert(!new_block
->idstr
[0]);
2014 char *id
= qdev_get_dev_path(dev
);
2016 snprintf(new_block
->idstr
, sizeof(new_block
->idstr
), "%s/", id
);
2020 pstrcat(new_block
->idstr
, sizeof(new_block
->idstr
), name
);
2023 RAMBLOCK_FOREACH(block
) {
2024 if (block
!= new_block
&&
2025 !strcmp(block
->idstr
, new_block
->idstr
)) {
2026 fprintf(stderr
, "RAMBlock \"%s\" already registered, abort!\n",
2034 /* Called with iothread lock held. */
2035 void qemu_ram_unset_idstr(RAMBlock
*block
)
2037 /* FIXME: arch_init.c assumes that this is not called throughout
2038 * migration. Ignore the problem since hot-unplug during migration
2039 * does not work anyway.
2042 memset(block
->idstr
, 0, sizeof(block
->idstr
));
2046 size_t qemu_ram_pagesize(RAMBlock
*rb
)
2048 return rb
->page_size
;
2051 /* Returns the largest size of page in use */
2052 size_t qemu_ram_pagesize_largest(void)
2057 RAMBLOCK_FOREACH(block
) {
2058 largest
= MAX(largest
, qemu_ram_pagesize(block
));
2064 static int memory_try_enable_merging(void *addr
, size_t len
)
2066 if (!machine_mem_merge(current_machine
)) {
2067 /* disabled by the user */
2071 return qemu_madvise(addr
, len
, QEMU_MADV_MERGEABLE
);
2074 /* Only legal before guest might have detected the memory size: e.g. on
2075 * incoming migration, or right after reset.
2077 * As memory core doesn't know how is memory accessed, it is up to
2078 * resize callback to update device state and/or add assertions to detect
2079 * misuse, if necessary.
2081 int qemu_ram_resize(RAMBlock
*block
, ram_addr_t newsize
, Error
**errp
)
2085 newsize
= HOST_PAGE_ALIGN(newsize
);
2087 if (block
->used_length
== newsize
) {
2091 if (!(block
->flags
& RAM_RESIZEABLE
)) {
2092 error_setg_errno(errp
, EINVAL
,
2093 "Length mismatch: %s: 0x" RAM_ADDR_FMT
2094 " in != 0x" RAM_ADDR_FMT
, block
->idstr
,
2095 newsize
, block
->used_length
);
2099 if (block
->max_length
< newsize
) {
2100 error_setg_errno(errp
, EINVAL
,
2101 "Length too large: %s: 0x" RAM_ADDR_FMT
2102 " > 0x" RAM_ADDR_FMT
, block
->idstr
,
2103 newsize
, block
->max_length
);
2107 cpu_physical_memory_clear_dirty_range(block
->offset
, block
->used_length
);
2108 block
->used_length
= newsize
;
2109 cpu_physical_memory_set_dirty_range(block
->offset
, block
->used_length
,
2111 memory_region_set_size(block
->mr
, newsize
);
2112 if (block
->resized
) {
2113 block
->resized(block
->idstr
, newsize
, block
->host
);
2118 /* Called with ram_list.mutex held */
2119 static void dirty_memory_extend(ram_addr_t old_ram_size
,
2120 ram_addr_t new_ram_size
)
2122 ram_addr_t old_num_blocks
= DIV_ROUND_UP(old_ram_size
,
2123 DIRTY_MEMORY_BLOCK_SIZE
);
2124 ram_addr_t new_num_blocks
= DIV_ROUND_UP(new_ram_size
,
2125 DIRTY_MEMORY_BLOCK_SIZE
);
2128 /* Only need to extend if block count increased */
2129 if (new_num_blocks
<= old_num_blocks
) {
2133 for (i
= 0; i
< DIRTY_MEMORY_NUM
; i
++) {
2134 DirtyMemoryBlocks
*old_blocks
;
2135 DirtyMemoryBlocks
*new_blocks
;
2138 old_blocks
= atomic_rcu_read(&ram_list
.dirty_memory
[i
]);
2139 new_blocks
= g_malloc(sizeof(*new_blocks
) +
2140 sizeof(new_blocks
->blocks
[0]) * new_num_blocks
);
2142 if (old_num_blocks
) {
2143 memcpy(new_blocks
->blocks
, old_blocks
->blocks
,
2144 old_num_blocks
* sizeof(old_blocks
->blocks
[0]));
2147 for (j
= old_num_blocks
; j
< new_num_blocks
; j
++) {
2148 new_blocks
->blocks
[j
] = bitmap_new(DIRTY_MEMORY_BLOCK_SIZE
);
2151 atomic_rcu_set(&ram_list
.dirty_memory
[i
], new_blocks
);
2154 g_free_rcu(old_blocks
, rcu
);
2159 static void ram_block_add(RAMBlock
*new_block
, Error
**errp
, bool shared
)
2162 RAMBlock
*last_block
= NULL
;
2163 ram_addr_t old_ram_size
, new_ram_size
;
2166 old_ram_size
= last_ram_page();
2168 qemu_mutex_lock_ramlist();
2169 new_block
->offset
= find_ram_offset(new_block
->max_length
);
2171 if (!new_block
->host
) {
2172 if (xen_enabled()) {
2173 xen_ram_alloc(new_block
->offset
, new_block
->max_length
,
2174 new_block
->mr
, &err
);
2176 error_propagate(errp
, err
);
2177 qemu_mutex_unlock_ramlist();
2181 new_block
->host
= phys_mem_alloc(new_block
->max_length
,
2182 &new_block
->mr
->align
, shared
);
2183 if (!new_block
->host
) {
2184 error_setg_errno(errp
, errno
,
2185 "cannot set up guest memory '%s'",
2186 memory_region_name(new_block
->mr
));
2187 qemu_mutex_unlock_ramlist();
2190 memory_try_enable_merging(new_block
->host
, new_block
->max_length
);
2194 new_ram_size
= MAX(old_ram_size
,
2195 (new_block
->offset
+ new_block
->max_length
) >> TARGET_PAGE_BITS
);
2196 if (new_ram_size
> old_ram_size
) {
2197 dirty_memory_extend(old_ram_size
, new_ram_size
);
2199 /* Keep the list sorted from biggest to smallest block. Unlike QTAILQ,
2200 * QLIST (which has an RCU-friendly variant) does not have insertion at
2201 * tail, so save the last element in last_block.
2203 RAMBLOCK_FOREACH(block
) {
2205 if (block
->max_length
< new_block
->max_length
) {
2210 QLIST_INSERT_BEFORE_RCU(block
, new_block
, next
);
2211 } else if (last_block
) {
2212 QLIST_INSERT_AFTER_RCU(last_block
, new_block
, next
);
2213 } else { /* list is empty */
2214 QLIST_INSERT_HEAD_RCU(&ram_list
.blocks
, new_block
, next
);
2216 ram_list
.mru_block
= NULL
;
2218 /* Write list before version */
2221 qemu_mutex_unlock_ramlist();
2223 cpu_physical_memory_set_dirty_range(new_block
->offset
,
2224 new_block
->used_length
,
2227 if (new_block
->host
) {
2228 qemu_ram_setup_dump(new_block
->host
, new_block
->max_length
);
2229 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_HUGEPAGE
);
2230 /* MADV_DONTFORK is also needed by KVM in absence of synchronous MMU */
2231 qemu_madvise(new_block
->host
, new_block
->max_length
, QEMU_MADV_DONTFORK
);
2232 ram_block_notify_add(new_block
->host
, new_block
->max_length
);
2237 RAMBlock
*qemu_ram_alloc_from_fd(ram_addr_t size
, MemoryRegion
*mr
,
2238 uint32_t ram_flags
, int fd
,
2241 RAMBlock
*new_block
;
2242 Error
*local_err
= NULL
;
2245 /* Just support these ram flags by now. */
2246 assert((ram_flags
& ~(RAM_SHARED
| RAM_PMEM
)) == 0);
2248 if (xen_enabled()) {
2249 error_setg(errp
, "-mem-path not supported with Xen");
2253 if (kvm_enabled() && !kvm_has_sync_mmu()) {
2255 "host lacks kvm mmu notifiers, -mem-path unsupported");
2259 if (phys_mem_alloc
!= qemu_anon_ram_alloc
) {
2261 * file_ram_alloc() needs to allocate just like
2262 * phys_mem_alloc, but we haven't bothered to provide
2266 "-mem-path not supported with this accelerator");
2270 size
= HOST_PAGE_ALIGN(size
);
2271 file_size
= get_file_size(fd
);
2272 if (file_size
> 0 && file_size
< size
) {
2273 error_setg(errp
, "backing store %s size 0x%" PRIx64
2274 " does not match 'size' option 0x" RAM_ADDR_FMT
,
2275 mem_path
, file_size
, size
);
2279 new_block
= g_malloc0(sizeof(*new_block
));
2281 new_block
->used_length
= size
;
2282 new_block
->max_length
= size
;
2283 new_block
->flags
= ram_flags
;
2284 new_block
->host
= file_ram_alloc(new_block
, size
, fd
, !file_size
, errp
);
2285 if (!new_block
->host
) {
2290 ram_block_add(new_block
, &local_err
, ram_flags
& RAM_SHARED
);
2293 error_propagate(errp
, local_err
);
2301 RAMBlock
*qemu_ram_alloc_from_file(ram_addr_t size
, MemoryRegion
*mr
,
2302 uint32_t ram_flags
, const char *mem_path
,
2309 fd
= file_ram_open(mem_path
, memory_region_name(mr
), &created
, errp
);
2314 block
= qemu_ram_alloc_from_fd(size
, mr
, ram_flags
, fd
, errp
);
2328 RAMBlock
*qemu_ram_alloc_internal(ram_addr_t size
, ram_addr_t max_size
,
2329 void (*resized
)(const char*,
2332 void *host
, bool resizeable
, bool share
,
2333 MemoryRegion
*mr
, Error
**errp
)
2335 RAMBlock
*new_block
;
2336 Error
*local_err
= NULL
;
2338 size
= HOST_PAGE_ALIGN(size
);
2339 max_size
= HOST_PAGE_ALIGN(max_size
);
2340 new_block
= g_malloc0(sizeof(*new_block
));
2342 new_block
->resized
= resized
;
2343 new_block
->used_length
= size
;
2344 new_block
->max_length
= max_size
;
2345 assert(max_size
>= size
);
2347 new_block
->page_size
= getpagesize();
2348 new_block
->host
= host
;
2350 new_block
->flags
|= RAM_PREALLOC
;
2353 new_block
->flags
|= RAM_RESIZEABLE
;
2355 ram_block_add(new_block
, &local_err
, share
);
2358 error_propagate(errp
, local_err
);
2364 RAMBlock
*qemu_ram_alloc_from_ptr(ram_addr_t size
, void *host
,
2365 MemoryRegion
*mr
, Error
**errp
)
2367 return qemu_ram_alloc_internal(size
, size
, NULL
, host
, false,
2371 RAMBlock
*qemu_ram_alloc(ram_addr_t size
, bool share
,
2372 MemoryRegion
*mr
, Error
**errp
)
2374 return qemu_ram_alloc_internal(size
, size
, NULL
, NULL
, false,
2378 RAMBlock
*qemu_ram_alloc_resizeable(ram_addr_t size
, ram_addr_t maxsz
,
2379 void (*resized
)(const char*,
2382 MemoryRegion
*mr
, Error
**errp
)
2384 return qemu_ram_alloc_internal(size
, maxsz
, resized
, NULL
, true,
2388 static void reclaim_ramblock(RAMBlock
*block
)
2390 if (block
->flags
& RAM_PREALLOC
) {
2392 } else if (xen_enabled()) {
2393 xen_invalidate_map_cache_entry(block
->host
);
2395 } else if (block
->fd
>= 0) {
2396 qemu_ram_munmap(block
->host
, block
->max_length
);
2400 qemu_anon_ram_free(block
->host
, block
->max_length
);
2405 void qemu_ram_free(RAMBlock
*block
)
2412 ram_block_notify_remove(block
->host
, block
->max_length
);
2415 qemu_mutex_lock_ramlist();
2416 QLIST_REMOVE_RCU(block
, next
);
2417 ram_list
.mru_block
= NULL
;
2418 /* Write list before version */
2421 call_rcu(block
, reclaim_ramblock
, rcu
);
2422 qemu_mutex_unlock_ramlist();
2426 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
)
2433 RAMBLOCK_FOREACH(block
) {
2434 offset
= addr
- block
->offset
;
2435 if (offset
< block
->max_length
) {
2436 vaddr
= ramblock_ptr(block
, offset
);
2437 if (block
->flags
& RAM_PREALLOC
) {
2439 } else if (xen_enabled()) {
2443 if (block
->fd
>= 0) {
2444 flags
|= (block
->flags
& RAM_SHARED
?
2445 MAP_SHARED
: MAP_PRIVATE
);
2446 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2447 flags
, block
->fd
, offset
);
2450 * Remap needs to match alloc. Accelerators that
2451 * set phys_mem_alloc never remap. If they did,
2452 * we'd need a remap hook here.
2454 assert(phys_mem_alloc
== qemu_anon_ram_alloc
);
2456 flags
|= MAP_PRIVATE
| MAP_ANONYMOUS
;
2457 area
= mmap(vaddr
, length
, PROT_READ
| PROT_WRITE
,
2460 if (area
!= vaddr
) {
2461 error_report("Could not remap addr: "
2462 RAM_ADDR_FMT
"@" RAM_ADDR_FMT
"",
2466 memory_try_enable_merging(vaddr
, length
);
2467 qemu_ram_setup_dump(vaddr
, length
);
2472 #endif /* !_WIN32 */
2474 /* Return a host pointer to ram allocated with qemu_ram_alloc.
2475 * This should not be used for general purpose DMA. Use address_space_map
2476 * or address_space_rw instead. For local memory (e.g. video ram) that the
2477 * device owns, use memory_region_get_ram_ptr.
2479 * Called within RCU critical section.
2481 void *qemu_map_ram_ptr(RAMBlock
*ram_block
, ram_addr_t addr
)
2483 RAMBlock
*block
= ram_block
;
2485 if (block
== NULL
) {
2486 block
= qemu_get_ram_block(addr
);
2487 addr
-= block
->offset
;
2490 if (xen_enabled() && block
->host
== NULL
) {
2491 /* We need to check if the requested address is in the RAM
2492 * because we don't want to map the entire memory in QEMU.
2493 * In that case just map until the end of the page.
2495 if (block
->offset
== 0) {
2496 return xen_map_cache(addr
, 0, 0, false);
2499 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, false);
2501 return ramblock_ptr(block
, addr
);
2504 /* Return a host pointer to guest's ram. Similar to qemu_map_ram_ptr
2505 * but takes a size argument.
2507 * Called within RCU critical section.
2509 static void *qemu_ram_ptr_length(RAMBlock
*ram_block
, ram_addr_t addr
,
2510 hwaddr
*size
, bool lock
)
2512 RAMBlock
*block
= ram_block
;
2517 if (block
== NULL
) {
2518 block
= qemu_get_ram_block(addr
);
2519 addr
-= block
->offset
;
2521 *size
= MIN(*size
, block
->max_length
- addr
);
2523 if (xen_enabled() && block
->host
== NULL
) {
2524 /* We need to check if the requested address is in the RAM
2525 * because we don't want to map the entire memory in QEMU.
2526 * In that case just map the requested area.
2528 if (block
->offset
== 0) {
2529 return xen_map_cache(addr
, *size
, lock
, lock
);
2532 block
->host
= xen_map_cache(block
->offset
, block
->max_length
, 1, lock
);
2535 return ramblock_ptr(block
, addr
);
2538 /* Return the offset of a hostpointer within a ramblock */
2539 ram_addr_t
qemu_ram_block_host_offset(RAMBlock
*rb
, void *host
)
2541 ram_addr_t res
= (uint8_t *)host
- (uint8_t *)rb
->host
;
2542 assert((uintptr_t)host
>= (uintptr_t)rb
->host
);
2543 assert(res
< rb
->max_length
);
2549 * Translates a host ptr back to a RAMBlock, a ram_addr and an offset
2552 * ptr: Host pointer to look up
2553 * round_offset: If true round the result offset down to a page boundary
2554 * *ram_addr: set to result ram_addr
2555 * *offset: set to result offset within the RAMBlock
2557 * Returns: RAMBlock (or NULL if not found)
2559 * By the time this function returns, the returned pointer is not protected
2560 * by RCU anymore. If the caller is not within an RCU critical section and
2561 * does not hold the iothread lock, it must have other means of protecting the
2562 * pointer, such as a reference to the region that includes the incoming
2565 RAMBlock
*qemu_ram_block_from_host(void *ptr
, bool round_offset
,
2569 uint8_t *host
= ptr
;
2571 if (xen_enabled()) {
2572 ram_addr_t ram_addr
;
2574 ram_addr
= xen_ram_addr_from_mapcache(ptr
);
2575 block
= qemu_get_ram_block(ram_addr
);
2577 *offset
= ram_addr
- block
->offset
;
2584 block
= atomic_rcu_read(&ram_list
.mru_block
);
2585 if (block
&& block
->host
&& host
- block
->host
< block
->max_length
) {
2589 RAMBLOCK_FOREACH(block
) {
2590 /* This case append when the block is not mapped. */
2591 if (block
->host
== NULL
) {
2594 if (host
- block
->host
< block
->max_length
) {
2603 *offset
= (host
- block
->host
);
2605 *offset
&= TARGET_PAGE_MASK
;
2612 * Finds the named RAMBlock
2614 * name: The name of RAMBlock to find
2616 * Returns: RAMBlock (or NULL if not found)
2618 RAMBlock
*qemu_ram_block_by_name(const char *name
)
2622 RAMBLOCK_FOREACH(block
) {
2623 if (!strcmp(name
, block
->idstr
)) {
2631 /* Some of the softmmu routines need to translate from a host pointer
2632 (typically a TLB entry) back to a ram offset. */
2633 ram_addr_t
qemu_ram_addr_from_host(void *ptr
)
2638 block
= qemu_ram_block_from_host(ptr
, false, &offset
);
2640 return RAM_ADDR_INVALID
;
2643 return block
->offset
+ offset
;
2646 /* Called within RCU critical section. */
2647 void memory_notdirty_write_prepare(NotDirtyInfo
*ndi
,
2650 ram_addr_t ram_addr
,
2654 ndi
->ram_addr
= ram_addr
;
2655 ndi
->mem_vaddr
= mem_vaddr
;
2659 assert(tcg_enabled());
2660 if (!cpu_physical_memory_get_dirty_flag(ram_addr
, DIRTY_MEMORY_CODE
)) {
2661 ndi
->pages
= page_collection_lock(ram_addr
, ram_addr
+ size
);
2662 tb_invalidate_phys_page_fast(ndi
->pages
, ram_addr
, size
);
2666 /* Called within RCU critical section. */
2667 void memory_notdirty_write_complete(NotDirtyInfo
*ndi
)
2670 assert(tcg_enabled());
2671 page_collection_unlock(ndi
->pages
);
2675 /* Set both VGA and migration bits for simplicity and to remove
2676 * the notdirty callback faster.
2678 cpu_physical_memory_set_dirty_range(ndi
->ram_addr
, ndi
->size
,
2679 DIRTY_CLIENTS_NOCODE
);
2680 /* we remove the notdirty callback only if the code has been
2682 if (!cpu_physical_memory_is_clean(ndi
->ram_addr
)) {
2683 tlb_set_dirty(ndi
->cpu
, ndi
->mem_vaddr
);
2687 /* Called within RCU critical section. */
2688 static void notdirty_mem_write(void *opaque
, hwaddr ram_addr
,
2689 uint64_t val
, unsigned size
)
2693 memory_notdirty_write_prepare(&ndi
, current_cpu
, current_cpu
->mem_io_vaddr
,
2696 stn_p(qemu_map_ram_ptr(NULL
, ram_addr
), size
, val
);
2697 memory_notdirty_write_complete(&ndi
);
2700 static bool notdirty_mem_accepts(void *opaque
, hwaddr addr
,
2701 unsigned size
, bool is_write
,
2707 static const MemoryRegionOps notdirty_mem_ops
= {
2708 .write
= notdirty_mem_write
,
2709 .valid
.accepts
= notdirty_mem_accepts
,
2710 .endianness
= DEVICE_NATIVE_ENDIAN
,
2712 .min_access_size
= 1,
2713 .max_access_size
= 8,
2717 .min_access_size
= 1,
2718 .max_access_size
= 8,
2723 /* Generate a debug exception if a watchpoint has been hit. */
2724 static void check_watchpoint(int offset
, int len
, MemTxAttrs attrs
, int flags
)
2726 CPUState
*cpu
= current_cpu
;
2727 CPUClass
*cc
= CPU_GET_CLASS(cpu
);
2731 assert(tcg_enabled());
2732 if (cpu
->watchpoint_hit
) {
2733 /* We re-entered the check after replacing the TB. Now raise
2734 * the debug interrupt so that is will trigger after the
2735 * current instruction. */
2736 cpu_interrupt(cpu
, CPU_INTERRUPT_DEBUG
);
2739 vaddr
= (cpu
->mem_io_vaddr
& TARGET_PAGE_MASK
) + offset
;
2740 vaddr
= cc
->adjust_watchpoint_address(cpu
, vaddr
, len
);
2741 QTAILQ_FOREACH(wp
, &cpu
->watchpoints
, entry
) {
2742 if (cpu_watchpoint_address_matches(wp
, vaddr
, len
)
2743 && (wp
->flags
& flags
)) {
2744 if (flags
== BP_MEM_READ
) {
2745 wp
->flags
|= BP_WATCHPOINT_HIT_READ
;
2747 wp
->flags
|= BP_WATCHPOINT_HIT_WRITE
;
2749 wp
->hitaddr
= vaddr
;
2750 wp
->hitattrs
= attrs
;
2751 if (!cpu
->watchpoint_hit
) {
2752 if (wp
->flags
& BP_CPU
&&
2753 !cc
->debug_check_watchpoint(cpu
, wp
)) {
2754 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2757 cpu
->watchpoint_hit
= wp
;
2760 tb_check_watchpoint(cpu
);
2761 if (wp
->flags
& BP_STOP_BEFORE_ACCESS
) {
2762 cpu
->exception_index
= EXCP_DEBUG
;
2766 /* Force execution of one insn next time. */
2767 cpu
->cflags_next_tb
= 1 | curr_cflags();
2769 cpu_loop_exit_noexc(cpu
);
2773 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
2778 /* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
2779 so these check for a hit then pass through to the normal out-of-line
2781 static MemTxResult
watch_mem_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
2782 unsigned size
, MemTxAttrs attrs
)
2786 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2787 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2789 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_READ
);
2792 data
= address_space_ldub(as
, addr
, attrs
, &res
);
2795 data
= address_space_lduw(as
, addr
, attrs
, &res
);
2798 data
= address_space_ldl(as
, addr
, attrs
, &res
);
2801 data
= address_space_ldq(as
, addr
, attrs
, &res
);
2809 static MemTxResult
watch_mem_write(void *opaque
, hwaddr addr
,
2810 uint64_t val
, unsigned size
,
2814 int asidx
= cpu_asidx_from_attrs(current_cpu
, attrs
);
2815 AddressSpace
*as
= current_cpu
->cpu_ases
[asidx
].as
;
2817 check_watchpoint(addr
& ~TARGET_PAGE_MASK
, size
, attrs
, BP_MEM_WRITE
);
2820 address_space_stb(as
, addr
, val
, attrs
, &res
);
2823 address_space_stw(as
, addr
, val
, attrs
, &res
);
2826 address_space_stl(as
, addr
, val
, attrs
, &res
);
2829 address_space_stq(as
, addr
, val
, attrs
, &res
);
2836 static const MemoryRegionOps watch_mem_ops
= {
2837 .read_with_attrs
= watch_mem_read
,
2838 .write_with_attrs
= watch_mem_write
,
2839 .endianness
= DEVICE_NATIVE_ENDIAN
,
2841 .min_access_size
= 1,
2842 .max_access_size
= 8,
2846 .min_access_size
= 1,
2847 .max_access_size
= 8,
2852 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
2853 MemTxAttrs attrs
, uint8_t *buf
, int len
);
2854 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
2855 const uint8_t *buf
, int len
);
2856 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
2857 bool is_write
, MemTxAttrs attrs
);
2859 static MemTxResult
subpage_read(void *opaque
, hwaddr addr
, uint64_t *data
,
2860 unsigned len
, MemTxAttrs attrs
)
2862 subpage_t
*subpage
= opaque
;
2866 #if defined(DEBUG_SUBPAGE)
2867 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
"\n", __func__
,
2868 subpage
, len
, addr
);
2870 res
= flatview_read(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2874 *data
= ldn_p(buf
, len
);
2878 static MemTxResult
subpage_write(void *opaque
, hwaddr addr
,
2879 uint64_t value
, unsigned len
, MemTxAttrs attrs
)
2881 subpage_t
*subpage
= opaque
;
2884 #if defined(DEBUG_SUBPAGE)
2885 printf("%s: subpage %p len %u addr " TARGET_FMT_plx
2886 " value %"PRIx64
"\n",
2887 __func__
, subpage
, len
, addr
, value
);
2889 stn_p(buf
, len
, value
);
2890 return flatview_write(subpage
->fv
, addr
+ subpage
->base
, attrs
, buf
, len
);
2893 static bool subpage_accepts(void *opaque
, hwaddr addr
,
2894 unsigned len
, bool is_write
,
2897 subpage_t
*subpage
= opaque
;
2898 #if defined(DEBUG_SUBPAGE)
2899 printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx
"\n",
2900 __func__
, subpage
, is_write
? 'w' : 'r', len
, addr
);
2903 return flatview_access_valid(subpage
->fv
, addr
+ subpage
->base
,
2904 len
, is_write
, attrs
);
2907 static const MemoryRegionOps subpage_ops
= {
2908 .read_with_attrs
= subpage_read
,
2909 .write_with_attrs
= subpage_write
,
2910 .impl
.min_access_size
= 1,
2911 .impl
.max_access_size
= 8,
2912 .valid
.min_access_size
= 1,
2913 .valid
.max_access_size
= 8,
2914 .valid
.accepts
= subpage_accepts
,
2915 .endianness
= DEVICE_NATIVE_ENDIAN
,
2918 static int subpage_register (subpage_t
*mmio
, uint32_t start
, uint32_t end
,
2923 if (start
>= TARGET_PAGE_SIZE
|| end
>= TARGET_PAGE_SIZE
)
2925 idx
= SUBPAGE_IDX(start
);
2926 eidx
= SUBPAGE_IDX(end
);
2927 #if defined(DEBUG_SUBPAGE)
2928 printf("%s: %p start %08x end %08x idx %08x eidx %08x section %d\n",
2929 __func__
, mmio
, start
, end
, idx
, eidx
, section
);
2931 for (; idx
<= eidx
; idx
++) {
2932 mmio
->sub_section
[idx
] = section
;
2938 static subpage_t
*subpage_init(FlatView
*fv
, hwaddr base
)
2942 mmio
= g_malloc0(sizeof(subpage_t
) + TARGET_PAGE_SIZE
* sizeof(uint16_t));
2945 memory_region_init_io(&mmio
->iomem
, NULL
, &subpage_ops
, mmio
,
2946 NULL
, TARGET_PAGE_SIZE
);
2947 mmio
->iomem
.subpage
= true;
2948 #if defined(DEBUG_SUBPAGE)
2949 printf("%s: %p base " TARGET_FMT_plx
" len %08x\n", __func__
,
2950 mmio
, base
, TARGET_PAGE_SIZE
);
2952 subpage_register(mmio
, 0, TARGET_PAGE_SIZE
-1, PHYS_SECTION_UNASSIGNED
);
2957 static uint16_t dummy_section(PhysPageMap
*map
, FlatView
*fv
, MemoryRegion
*mr
)
2960 MemoryRegionSection section
= {
2963 .offset_within_address_space
= 0,
2964 .offset_within_region
= 0,
2965 .size
= int128_2_64(),
2968 return phys_section_add(map
, §ion
);
2971 static void readonly_mem_write(void *opaque
, hwaddr addr
,
2972 uint64_t val
, unsigned size
)
2974 /* Ignore any write to ROM. */
2977 static bool readonly_mem_accepts(void *opaque
, hwaddr addr
,
2978 unsigned size
, bool is_write
,
2984 /* This will only be used for writes, because reads are special cased
2985 * to directly access the underlying host ram.
2987 static const MemoryRegionOps readonly_mem_ops
= {
2988 .write
= readonly_mem_write
,
2989 .valid
.accepts
= readonly_mem_accepts
,
2990 .endianness
= DEVICE_NATIVE_ENDIAN
,
2992 .min_access_size
= 1,
2993 .max_access_size
= 8,
2997 .min_access_size
= 1,
2998 .max_access_size
= 8,
3003 MemoryRegionSection
*iotlb_to_section(CPUState
*cpu
,
3004 hwaddr index
, MemTxAttrs attrs
)
3006 int asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3007 CPUAddressSpace
*cpuas
= &cpu
->cpu_ases
[asidx
];
3008 AddressSpaceDispatch
*d
= atomic_rcu_read(&cpuas
->memory_dispatch
);
3009 MemoryRegionSection
*sections
= d
->map
.sections
;
3011 return §ions
[index
& ~TARGET_PAGE_MASK
];
3014 static void io_mem_init(void)
3016 memory_region_init_io(&io_mem_rom
, NULL
, &readonly_mem_ops
,
3017 NULL
, NULL
, UINT64_MAX
);
3018 memory_region_init_io(&io_mem_unassigned
, NULL
, &unassigned_mem_ops
, NULL
,
3021 /* io_mem_notdirty calls tb_invalidate_phys_page_fast,
3022 * which can be called without the iothread mutex.
3024 memory_region_init_io(&io_mem_notdirty
, NULL
, ¬dirty_mem_ops
, NULL
,
3026 memory_region_clear_global_locking(&io_mem_notdirty
);
3028 memory_region_init_io(&io_mem_watch
, NULL
, &watch_mem_ops
, NULL
,
3032 AddressSpaceDispatch
*address_space_dispatch_new(FlatView
*fv
)
3034 AddressSpaceDispatch
*d
= g_new0(AddressSpaceDispatch
, 1);
3037 n
= dummy_section(&d
->map
, fv
, &io_mem_unassigned
);
3038 assert(n
== PHYS_SECTION_UNASSIGNED
);
3039 n
= dummy_section(&d
->map
, fv
, &io_mem_notdirty
);
3040 assert(n
== PHYS_SECTION_NOTDIRTY
);
3041 n
= dummy_section(&d
->map
, fv
, &io_mem_rom
);
3042 assert(n
== PHYS_SECTION_ROM
);
3043 n
= dummy_section(&d
->map
, fv
, &io_mem_watch
);
3044 assert(n
== PHYS_SECTION_WATCH
);
3046 d
->phys_map
= (PhysPageEntry
) { .ptr
= PHYS_MAP_NODE_NIL
, .skip
= 1 };
3051 void address_space_dispatch_free(AddressSpaceDispatch
*d
)
3053 phys_sections_free(&d
->map
);
3057 static void tcg_commit(MemoryListener
*listener
)
3059 CPUAddressSpace
*cpuas
;
3060 AddressSpaceDispatch
*d
;
3062 assert(tcg_enabled());
3063 /* since each CPU stores ram addresses in its TLB cache, we must
3064 reset the modified entries */
3065 cpuas
= container_of(listener
, CPUAddressSpace
, tcg_as_listener
);
3066 cpu_reloading_memory_map();
3067 /* The CPU and TLB are protected by the iothread lock.
3068 * We reload the dispatch pointer now because cpu_reloading_memory_map()
3069 * may have split the RCU critical section.
3071 d
= address_space_to_dispatch(cpuas
->as
);
3072 atomic_rcu_set(&cpuas
->memory_dispatch
, d
);
3073 tlb_flush(cpuas
->cpu
);
3076 static void memory_map_init(void)
3078 system_memory
= g_malloc(sizeof(*system_memory
));
3080 memory_region_init(system_memory
, NULL
, "system", UINT64_MAX
);
3081 address_space_init(&address_space_memory
, system_memory
, "memory");
3083 system_io
= g_malloc(sizeof(*system_io
));
3084 memory_region_init_io(system_io
, NULL
, &unassigned_io_ops
, NULL
, "io",
3086 address_space_init(&address_space_io
, system_io
, "I/O");
3089 MemoryRegion
*get_system_memory(void)
3091 return system_memory
;
3094 MemoryRegion
*get_system_io(void)
3099 #endif /* !defined(CONFIG_USER_ONLY) */
3101 /* physical memory access (slow version, mainly for debug) */
3102 #if defined(CONFIG_USER_ONLY)
3103 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3104 uint8_t *buf
, int len
, int is_write
)
3111 page
= addr
& TARGET_PAGE_MASK
;
3112 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3115 flags
= page_get_flags(page
);
3116 if (!(flags
& PAGE_VALID
))
3119 if (!(flags
& PAGE_WRITE
))
3121 /* XXX: this code should not depend on lock_user */
3122 if (!(p
= lock_user(VERIFY_WRITE
, addr
, l
, 0)))
3125 unlock_user(p
, addr
, l
);
3127 if (!(flags
& PAGE_READ
))
3129 /* XXX: this code should not depend on lock_user */
3130 if (!(p
= lock_user(VERIFY_READ
, addr
, l
, 1)))
3133 unlock_user(p
, addr
, 0);
3144 static void invalidate_and_set_dirty(MemoryRegion
*mr
, hwaddr addr
,
3147 uint8_t dirty_log_mask
= memory_region_get_dirty_log_mask(mr
);
3148 addr
+= memory_region_get_ram_addr(mr
);
3150 /* No early return if dirty_log_mask is or becomes 0, because
3151 * cpu_physical_memory_set_dirty_range will still call
3152 * xen_modified_memory.
3154 if (dirty_log_mask
) {
3156 cpu_physical_memory_range_includes_clean(addr
, length
, dirty_log_mask
);
3158 if (dirty_log_mask
& (1 << DIRTY_MEMORY_CODE
)) {
3159 assert(tcg_enabled());
3160 tb_invalidate_phys_range(addr
, addr
+ length
);
3161 dirty_log_mask
&= ~(1 << DIRTY_MEMORY_CODE
);
3163 cpu_physical_memory_set_dirty_range(addr
, length
, dirty_log_mask
);
3166 static int memory_access_size(MemoryRegion
*mr
, unsigned l
, hwaddr addr
)
3168 unsigned access_size_max
= mr
->ops
->valid
.max_access_size
;
3170 /* Regions are assumed to support 1-4 byte accesses unless
3171 otherwise specified. */
3172 if (access_size_max
== 0) {
3173 access_size_max
= 4;
3176 /* Bound the maximum access by the alignment of the address. */
3177 if (!mr
->ops
->impl
.unaligned
) {
3178 unsigned align_size_max
= addr
& -addr
;
3179 if (align_size_max
!= 0 && align_size_max
< access_size_max
) {
3180 access_size_max
= align_size_max
;
3184 /* Don't attempt accesses larger than the maximum. */
3185 if (l
> access_size_max
) {
3186 l
= access_size_max
;
3193 static bool prepare_mmio_access(MemoryRegion
*mr
)
3195 bool unlocked
= !qemu_mutex_iothread_locked();
3196 bool release_lock
= false;
3198 if (unlocked
&& mr
->global_locking
) {
3199 qemu_mutex_lock_iothread();
3201 release_lock
= true;
3203 if (mr
->flush_coalesced_mmio
) {
3205 qemu_mutex_lock_iothread();
3207 qemu_flush_coalesced_mmio_buffer();
3209 qemu_mutex_unlock_iothread();
3213 return release_lock
;
3216 /* Called within RCU critical section. */
3217 static MemTxResult
flatview_write_continue(FlatView
*fv
, hwaddr addr
,
3220 int len
, hwaddr addr1
,
3221 hwaddr l
, MemoryRegion
*mr
)
3225 MemTxResult result
= MEMTX_OK
;
3226 bool release_lock
= false;
3229 if (!memory_access_is_direct(mr
, true)) {
3230 release_lock
|= prepare_mmio_access(mr
);
3231 l
= memory_access_size(mr
, l
, addr1
);
3232 /* XXX: could force current_cpu to NULL to avoid
3234 val
= ldn_p(buf
, l
);
3235 result
|= memory_region_dispatch_write(mr
, addr1
, val
, l
, attrs
);
3238 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3239 memcpy(ptr
, buf
, l
);
3240 invalidate_and_set_dirty(mr
, addr1
, l
);
3244 qemu_mutex_unlock_iothread();
3245 release_lock
= false;
3257 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3263 /* Called from RCU critical section. */
3264 static MemTxResult
flatview_write(FlatView
*fv
, hwaddr addr
, MemTxAttrs attrs
,
3265 const uint8_t *buf
, int len
)
3270 MemTxResult result
= MEMTX_OK
;
3273 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, true, attrs
);
3274 result
= flatview_write_continue(fv
, addr
, attrs
, buf
, len
,
3280 /* Called within RCU critical section. */
3281 MemTxResult
flatview_read_continue(FlatView
*fv
, hwaddr addr
,
3282 MemTxAttrs attrs
, uint8_t *buf
,
3283 int len
, hwaddr addr1
, hwaddr l
,
3288 MemTxResult result
= MEMTX_OK
;
3289 bool release_lock
= false;
3292 if (!memory_access_is_direct(mr
, false)) {
3294 release_lock
|= prepare_mmio_access(mr
);
3295 l
= memory_access_size(mr
, l
, addr1
);
3296 result
|= memory_region_dispatch_read(mr
, addr1
, &val
, l
, attrs
);
3300 ptr
= qemu_ram_ptr_length(mr
->ram_block
, addr1
, &l
, false);
3301 memcpy(buf
, ptr
, l
);
3305 qemu_mutex_unlock_iothread();
3306 release_lock
= false;
3318 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3324 /* Called from RCU critical section. */
3325 static MemTxResult
flatview_read(FlatView
*fv
, hwaddr addr
,
3326 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3333 mr
= flatview_translate(fv
, addr
, &addr1
, &l
, false, attrs
);
3334 return flatview_read_continue(fv
, addr
, attrs
, buf
, len
,
3338 MemTxResult
address_space_read_full(AddressSpace
*as
, hwaddr addr
,
3339 MemTxAttrs attrs
, uint8_t *buf
, int len
)
3341 MemTxResult result
= MEMTX_OK
;
3346 fv
= address_space_to_flatview(as
);
3347 result
= flatview_read(fv
, addr
, attrs
, buf
, len
);
3354 MemTxResult
address_space_write(AddressSpace
*as
, hwaddr addr
,
3356 const uint8_t *buf
, int len
)
3358 MemTxResult result
= MEMTX_OK
;
3363 fv
= address_space_to_flatview(as
);
3364 result
= flatview_write(fv
, addr
, attrs
, buf
, len
);
3371 MemTxResult
address_space_rw(AddressSpace
*as
, hwaddr addr
, MemTxAttrs attrs
,
3372 uint8_t *buf
, int len
, bool is_write
)
3375 return address_space_write(as
, addr
, attrs
, buf
, len
);
3377 return address_space_read_full(as
, addr
, attrs
, buf
, len
);
3381 void cpu_physical_memory_rw(hwaddr addr
, uint8_t *buf
,
3382 int len
, int is_write
)
3384 address_space_rw(&address_space_memory
, addr
, MEMTXATTRS_UNSPECIFIED
,
3385 buf
, len
, is_write
);
3388 enum write_rom_type
{
3393 static inline void cpu_physical_memory_write_rom_internal(AddressSpace
*as
,
3394 hwaddr addr
, const uint8_t *buf
, int len
, enum write_rom_type type
)
3404 mr
= address_space_translate(as
, addr
, &addr1
, &l
, true,
3405 MEMTXATTRS_UNSPECIFIED
);
3407 if (!(memory_region_is_ram(mr
) ||
3408 memory_region_is_romd(mr
))) {
3409 l
= memory_access_size(mr
, l
, addr1
);
3412 ptr
= qemu_map_ram_ptr(mr
->ram_block
, addr1
);
3415 memcpy(ptr
, buf
, l
);
3416 invalidate_and_set_dirty(mr
, addr1
, l
);
3419 flush_icache_range((uintptr_t)ptr
, (uintptr_t)ptr
+ l
);
3430 /* used for ROM loading : can write in RAM and ROM */
3431 void cpu_physical_memory_write_rom(AddressSpace
*as
, hwaddr addr
,
3432 const uint8_t *buf
, int len
)
3434 cpu_physical_memory_write_rom_internal(as
, addr
, buf
, len
, WRITE_DATA
);
3437 void cpu_flush_icache_range(hwaddr start
, int len
)
3440 * This function should do the same thing as an icache flush that was
3441 * triggered from within the guest. For TCG we are always cache coherent,
3442 * so there is no need to flush anything. For KVM / Xen we need to flush
3443 * the host's instruction cache at least.
3445 if (tcg_enabled()) {
3449 cpu_physical_memory_write_rom_internal(&address_space_memory
,
3450 start
, NULL
, len
, FLUSH_CACHE
);
3461 static BounceBuffer bounce
;
3463 typedef struct MapClient
{
3465 QLIST_ENTRY(MapClient
) link
;
3468 QemuMutex map_client_list_lock
;
3469 static QLIST_HEAD(map_client_list
, MapClient
) map_client_list
3470 = QLIST_HEAD_INITIALIZER(map_client_list
);
3472 static void cpu_unregister_map_client_do(MapClient
*client
)
3474 QLIST_REMOVE(client
, link
);
3478 static void cpu_notify_map_clients_locked(void)
3482 while (!QLIST_EMPTY(&map_client_list
)) {
3483 client
= QLIST_FIRST(&map_client_list
);
3484 qemu_bh_schedule(client
->bh
);
3485 cpu_unregister_map_client_do(client
);
3489 void cpu_register_map_client(QEMUBH
*bh
)
3491 MapClient
*client
= g_malloc(sizeof(*client
));
3493 qemu_mutex_lock(&map_client_list_lock
);
3495 QLIST_INSERT_HEAD(&map_client_list
, client
, link
);
3496 if (!atomic_read(&bounce
.in_use
)) {
3497 cpu_notify_map_clients_locked();
3499 qemu_mutex_unlock(&map_client_list_lock
);
3502 void cpu_exec_init_all(void)
3504 qemu_mutex_init(&ram_list
.mutex
);
3505 /* The data structures we set up here depend on knowing the page size,
3506 * so no more changes can be made after this point.
3507 * In an ideal world, nothing we did before we had finished the
3508 * machine setup would care about the target page size, and we could
3509 * do this much later, rather than requiring board models to state
3510 * up front what their requirements are.
3512 finalize_target_page_bits();
3515 qemu_mutex_init(&map_client_list_lock
);
3518 void cpu_unregister_map_client(QEMUBH
*bh
)
3522 qemu_mutex_lock(&map_client_list_lock
);
3523 QLIST_FOREACH(client
, &map_client_list
, link
) {
3524 if (client
->bh
== bh
) {
3525 cpu_unregister_map_client_do(client
);
3529 qemu_mutex_unlock(&map_client_list_lock
);
3532 static void cpu_notify_map_clients(void)
3534 qemu_mutex_lock(&map_client_list_lock
);
3535 cpu_notify_map_clients_locked();
3536 qemu_mutex_unlock(&map_client_list_lock
);
3539 static bool flatview_access_valid(FlatView
*fv
, hwaddr addr
, int len
,
3540 bool is_write
, MemTxAttrs attrs
)
3547 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3548 if (!memory_access_is_direct(mr
, is_write
)) {
3549 l
= memory_access_size(mr
, l
, addr
);
3550 if (!memory_region_access_valid(mr
, xlat
, l
, is_write
, attrs
)) {
3561 bool address_space_access_valid(AddressSpace
*as
, hwaddr addr
,
3562 int len
, bool is_write
,
3569 fv
= address_space_to_flatview(as
);
3570 result
= flatview_access_valid(fv
, addr
, len
, is_write
, attrs
);
3576 flatview_extend_translation(FlatView
*fv
, hwaddr addr
,
3578 MemoryRegion
*mr
, hwaddr base
, hwaddr len
,
3579 bool is_write
, MemTxAttrs attrs
)
3583 MemoryRegion
*this_mr
;
3589 if (target_len
== 0) {
3594 this_mr
= flatview_translate(fv
, addr
, &xlat
,
3595 &len
, is_write
, attrs
);
3596 if (this_mr
!= mr
|| xlat
!= base
+ done
) {
3602 /* Map a physical memory region into a host virtual address.
3603 * May map a subset of the requested range, given by and returned in *plen.
3604 * May return NULL if resources needed to perform the mapping are exhausted.
3605 * Use only for reads OR writes - not for read-modify-write operations.
3606 * Use cpu_register_map_client() to know when retrying the map operation is
3607 * likely to succeed.
3609 void *address_space_map(AddressSpace
*as
,
3627 fv
= address_space_to_flatview(as
);
3628 mr
= flatview_translate(fv
, addr
, &xlat
, &l
, is_write
, attrs
);
3630 if (!memory_access_is_direct(mr
, is_write
)) {
3631 if (atomic_xchg(&bounce
.in_use
, true)) {
3635 /* Avoid unbounded allocations */
3636 l
= MIN(l
, TARGET_PAGE_SIZE
);
3637 bounce
.buffer
= qemu_memalign(TARGET_PAGE_SIZE
, l
);
3641 memory_region_ref(mr
);
3644 flatview_read(fv
, addr
, MEMTXATTRS_UNSPECIFIED
,
3650 return bounce
.buffer
;
3654 memory_region_ref(mr
);
3655 *plen
= flatview_extend_translation(fv
, addr
, len
, mr
, xlat
,
3656 l
, is_write
, attrs
);
3657 ptr
= qemu_ram_ptr_length(mr
->ram_block
, xlat
, plen
, true);
3663 /* Unmaps a memory region previously mapped by address_space_map().
3664 * Will also mark the memory as dirty if is_write == 1. access_len gives
3665 * the amount of memory that was actually read or written by the caller.
3667 void address_space_unmap(AddressSpace
*as
, void *buffer
, hwaddr len
,
3668 int is_write
, hwaddr access_len
)
3670 if (buffer
!= bounce
.buffer
) {
3674 mr
= memory_region_from_host(buffer
, &addr1
);
3677 invalidate_and_set_dirty(mr
, addr1
, access_len
);
3679 if (xen_enabled()) {
3680 xen_invalidate_map_cache_entry(buffer
);
3682 memory_region_unref(mr
);
3686 address_space_write(as
, bounce
.addr
, MEMTXATTRS_UNSPECIFIED
,
3687 bounce
.buffer
, access_len
);
3689 qemu_vfree(bounce
.buffer
);
3690 bounce
.buffer
= NULL
;
3691 memory_region_unref(bounce
.mr
);
3692 atomic_mb_set(&bounce
.in_use
, false);
3693 cpu_notify_map_clients();
3696 void *cpu_physical_memory_map(hwaddr addr
,
3700 return address_space_map(&address_space_memory
, addr
, plen
, is_write
,
3701 MEMTXATTRS_UNSPECIFIED
);
3704 void cpu_physical_memory_unmap(void *buffer
, hwaddr len
,
3705 int is_write
, hwaddr access_len
)
3707 return address_space_unmap(&address_space_memory
, buffer
, len
, is_write
, access_len
);
3710 #define ARG1_DECL AddressSpace *as
3713 #define TRANSLATE(...) address_space_translate(as, __VA_ARGS__)
3714 #define RCU_READ_LOCK(...) rcu_read_lock()
3715 #define RCU_READ_UNLOCK(...) rcu_read_unlock()
3716 #include "memory_ldst.inc.c"
3718 int64_t address_space_cache_init(MemoryRegionCache
*cache
,
3724 AddressSpaceDispatch
*d
;
3731 cache
->fv
= address_space_get_flatview(as
);
3732 d
= flatview_to_dispatch(cache
->fv
);
3733 cache
->mrs
= *address_space_translate_internal(d
, addr
, &cache
->xlat
, &l
, true);
3736 memory_region_ref(mr
);
3737 if (memory_access_is_direct(mr
, is_write
)) {
3738 /* We don't care about the memory attributes here as we're only
3739 * doing this if we found actual RAM, which behaves the same
3740 * regardless of attributes; so UNSPECIFIED is fine.
3742 l
= flatview_extend_translation(cache
->fv
, addr
, len
, mr
,
3743 cache
->xlat
, l
, is_write
,
3744 MEMTXATTRS_UNSPECIFIED
);
3745 cache
->ptr
= qemu_ram_ptr_length(mr
->ram_block
, cache
->xlat
, &l
, true);
3751 cache
->is_write
= is_write
;
3755 void address_space_cache_invalidate(MemoryRegionCache
*cache
,
3759 assert(cache
->is_write
);
3760 if (likely(cache
->ptr
)) {
3761 invalidate_and_set_dirty(cache
->mrs
.mr
, addr
+ cache
->xlat
, access_len
);
3765 void address_space_cache_destroy(MemoryRegionCache
*cache
)
3767 if (!cache
->mrs
.mr
) {
3771 if (xen_enabled()) {
3772 xen_invalidate_map_cache_entry(cache
->ptr
);
3774 memory_region_unref(cache
->mrs
.mr
);
3775 flatview_unref(cache
->fv
);
3776 cache
->mrs
.mr
= NULL
;
3780 /* Called from RCU critical section. This function has the same
3781 * semantics as address_space_translate, but it only works on a
3782 * predefined range of a MemoryRegion that was mapped with
3783 * address_space_cache_init.
3785 static inline MemoryRegion
*address_space_translate_cached(
3786 MemoryRegionCache
*cache
, hwaddr addr
, hwaddr
*xlat
,
3787 hwaddr
*plen
, bool is_write
, MemTxAttrs attrs
)
3789 MemoryRegionSection section
;
3791 IOMMUMemoryRegion
*iommu_mr
;
3792 AddressSpace
*target_as
;
3794 assert(!cache
->ptr
);
3795 *xlat
= addr
+ cache
->xlat
;
3798 iommu_mr
= memory_region_get_iommu(mr
);
3804 section
= address_space_translate_iommu(iommu_mr
, xlat
, plen
,
3805 NULL
, is_write
, true,
3810 /* Called from RCU critical section. address_space_read_cached uses this
3811 * out of line function when the target is an MMIO or IOMMU region.
3814 address_space_read_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3821 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, false,
3822 MEMTXATTRS_UNSPECIFIED
);
3823 flatview_read_continue(cache
->fv
,
3824 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3828 /* Called from RCU critical section. address_space_write_cached uses this
3829 * out of line function when the target is an MMIO or IOMMU region.
3832 address_space_write_cached_slow(MemoryRegionCache
*cache
, hwaddr addr
,
3833 const void *buf
, int len
)
3839 mr
= address_space_translate_cached(cache
, addr
, &addr1
, &l
, true,
3840 MEMTXATTRS_UNSPECIFIED
);
3841 flatview_write_continue(cache
->fv
,
3842 addr
, MEMTXATTRS_UNSPECIFIED
, buf
, len
,
3846 #define ARG1_DECL MemoryRegionCache *cache
3848 #define SUFFIX _cached_slow
3849 #define TRANSLATE(...) address_space_translate_cached(cache, __VA_ARGS__)
3850 #define RCU_READ_LOCK() ((void)0)
3851 #define RCU_READ_UNLOCK() ((void)0)
3852 #include "memory_ldst.inc.c"
3854 /* virtual memory access for debug (includes writing to ROM) */
3855 int cpu_memory_rw_debug(CPUState
*cpu
, target_ulong addr
,
3856 uint8_t *buf
, int len
, int is_write
)
3862 cpu_synchronize_state(cpu
);
3867 page
= addr
& TARGET_PAGE_MASK
;
3868 phys_addr
= cpu_get_phys_page_attrs_debug(cpu
, page
, &attrs
);
3869 asidx
= cpu_asidx_from_attrs(cpu
, attrs
);
3870 /* if no physical page mapped, return an error */
3871 if (phys_addr
== -1)
3873 l
= (page
+ TARGET_PAGE_SIZE
) - addr
;
3876 phys_addr
+= (addr
& ~TARGET_PAGE_MASK
);
3878 cpu_physical_memory_write_rom(cpu
->cpu_ases
[asidx
].as
,
3881 address_space_rw(cpu
->cpu_ases
[asidx
].as
, phys_addr
,
3882 MEMTXATTRS_UNSPECIFIED
,
3893 * Allows code that needs to deal with migration bitmaps etc to still be built
3894 * target independent.
3896 size_t qemu_target_page_size(void)
3898 return TARGET_PAGE_SIZE
;
3901 int qemu_target_page_bits(void)
3903 return TARGET_PAGE_BITS
;
3906 int qemu_target_page_bits_min(void)
3908 return TARGET_PAGE_BITS_MIN
;
3912 bool target_words_bigendian(void)
3914 #if defined(TARGET_WORDS_BIGENDIAN)
3921 #ifndef CONFIG_USER_ONLY
3922 bool cpu_physical_memory_is_io(hwaddr phys_addr
)
3929 mr
= address_space_translate(&address_space_memory
,
3930 phys_addr
, &phys_addr
, &l
, false,
3931 MEMTXATTRS_UNSPECIFIED
);
3933 res
= !(memory_region_is_ram(mr
) || memory_region_is_romd(mr
));
3938 int qemu_ram_foreach_block(RAMBlockIterFunc func
, void *opaque
)
3944 RAMBLOCK_FOREACH(block
) {
3945 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3946 block
->used_length
, opaque
);
3955 int qemu_ram_foreach_migratable_block(RAMBlockIterFunc func
, void *opaque
)
3961 RAMBLOCK_FOREACH(block
) {
3962 if (!qemu_ram_is_migratable(block
)) {
3965 ret
= func(block
->idstr
, block
->host
, block
->offset
,
3966 block
->used_length
, opaque
);
3976 * Unmap pages of memory from start to start+length such that
3977 * they a) read as 0, b) Trigger whatever fault mechanism
3978 * the OS provides for postcopy.
3979 * The pages must be unmapped by the end of the function.
3980 * Returns: 0 on success, none-0 on failure
3983 int ram_block_discard_range(RAMBlock
*rb
, uint64_t start
, size_t length
)
3987 uint8_t *host_startaddr
= rb
->host
+ start
;
3989 if ((uintptr_t)host_startaddr
& (rb
->page_size
- 1)) {
3990 error_report("ram_block_discard_range: Unaligned start address: %p",
3995 if ((start
+ length
) <= rb
->used_length
) {
3996 bool need_madvise
, need_fallocate
;
3997 uint8_t *host_endaddr
= host_startaddr
+ length
;
3998 if ((uintptr_t)host_endaddr
& (rb
->page_size
- 1)) {
3999 error_report("ram_block_discard_range: Unaligned end address: %p",
4004 errno
= ENOTSUP
; /* If we are missing MADVISE etc */
4006 /* The logic here is messy;
4007 * madvise DONTNEED fails for hugepages
4008 * fallocate works on hugepages and shmem
4010 need_madvise
= (rb
->page_size
== qemu_host_page_size
);
4011 need_fallocate
= rb
->fd
!= -1;
4012 if (need_fallocate
) {
4013 /* For a file, this causes the area of the file to be zero'd
4014 * if read, and for hugetlbfs also causes it to be unmapped
4015 * so a userfault will trigger.
4017 #ifdef CONFIG_FALLOCATE_PUNCH_HOLE
4018 ret
= fallocate(rb
->fd
, FALLOC_FL_PUNCH_HOLE
| FALLOC_FL_KEEP_SIZE
,
4022 error_report("ram_block_discard_range: Failed to fallocate "
4023 "%s:%" PRIx64
" +%zx (%d)",
4024 rb
->idstr
, start
, length
, ret
);
4029 error_report("ram_block_discard_range: fallocate not available/file"
4030 "%s:%" PRIx64
" +%zx (%d)",
4031 rb
->idstr
, start
, length
, ret
);
4036 /* For normal RAM this causes it to be unmapped,
4037 * for shared memory it causes the local mapping to disappear
4038 * and to fall back on the file contents (which we just
4039 * fallocate'd away).
4041 #if defined(CONFIG_MADVISE)
4042 ret
= madvise(host_startaddr
, length
, MADV_DONTNEED
);
4045 error_report("ram_block_discard_range: Failed to discard range "
4046 "%s:%" PRIx64
" +%zx (%d)",
4047 rb
->idstr
, start
, length
, ret
);
4052 error_report("ram_block_discard_range: MADVISE not available"
4053 "%s:%" PRIx64
" +%zx (%d)",
4054 rb
->idstr
, start
, length
, ret
);
4058 trace_ram_block_discard_range(rb
->idstr
, host_startaddr
, length
,
4059 need_madvise
, need_fallocate
, ret
);
4061 error_report("ram_block_discard_range: Overrun block '%s' (%" PRIu64
4062 "/%zx/" RAM_ADDR_FMT
")",
4063 rb
->idstr
, start
, length
, rb
->used_length
);
4070 bool ramblock_is_pmem(RAMBlock
*rb
)
4072 return rb
->flags
& RAM_PMEM
;
4077 void page_size_init(void)
4079 /* NOTE: we can always suppose that qemu_host_page_size >=
4081 if (qemu_host_page_size
== 0) {
4082 qemu_host_page_size
= qemu_real_host_page_size
;
4084 if (qemu_host_page_size
< TARGET_PAGE_SIZE
) {
4085 qemu_host_page_size
= TARGET_PAGE_SIZE
;
4087 qemu_host_page_mask
= -(intptr_t)qemu_host_page_size
;
4090 #if !defined(CONFIG_USER_ONLY)
4092 static void mtree_print_phys_entries(fprintf_function mon
, void *f
,
4093 int start
, int end
, int skip
, int ptr
)
4095 if (start
== end
- 1) {
4096 mon(f
, "\t%3d ", start
);
4098 mon(f
, "\t%3d..%-3d ", start
, end
- 1);
4100 mon(f
, " skip=%d ", skip
);
4101 if (ptr
== PHYS_MAP_NODE_NIL
) {
4104 mon(f
, " ptr=#%d", ptr
);
4106 mon(f
, " ptr=[%d]", ptr
);
4111 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
4112 int128_sub((size), int128_one())) : 0)
4114 void mtree_print_dispatch(fprintf_function mon
, void *f
,
4115 AddressSpaceDispatch
*d
, MemoryRegion
*root
)
4119 mon(f
, " Dispatch\n");
4120 mon(f
, " Physical sections\n");
4122 for (i
= 0; i
< d
->map
.sections_nb
; ++i
) {
4123 MemoryRegionSection
*s
= d
->map
.sections
+ i
;
4124 const char *names
[] = { " [unassigned]", " [not dirty]",
4125 " [ROM]", " [watch]" };
4127 mon(f
, " #%d @" TARGET_FMT_plx
".." TARGET_FMT_plx
" %s%s%s%s%s",
4129 s
->offset_within_address_space
,
4130 s
->offset_within_address_space
+ MR_SIZE(s
->mr
->size
),
4131 s
->mr
->name
? s
->mr
->name
: "(noname)",
4132 i
< ARRAY_SIZE(names
) ? names
[i
] : "",
4133 s
->mr
== root
? " [ROOT]" : "",
4134 s
== d
->mru_section
? " [MRU]" : "",
4135 s
->mr
->is_iommu
? " [iommu]" : "");
4138 mon(f
, " alias=%s", s
->mr
->alias
->name
?
4139 s
->mr
->alias
->name
: "noname");
4144 mon(f
, " Nodes (%d bits per level, %d levels) ptr=[%d] skip=%d\n",
4145 P_L2_BITS
, P_L2_LEVELS
, d
->phys_map
.ptr
, d
->phys_map
.skip
);
4146 for (i
= 0; i
< d
->map
.nodes_nb
; ++i
) {
4149 Node
*n
= d
->map
.nodes
+ i
;
4151 mon(f
, " [%d]\n", i
);
4153 for (j
= 0, jprev
= 0, prev
= *n
[0]; j
< ARRAY_SIZE(*n
); ++j
) {
4154 PhysPageEntry
*pe
= *n
+ j
;
4156 if (pe
->ptr
== prev
.ptr
&& pe
->skip
== prev
.skip
) {
4160 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);
4166 if (jprev
!= ARRAY_SIZE(*n
)) {
4167 mtree_print_phys_entries(mon
, f
, jprev
, j
, prev
.skip
, prev
.ptr
);