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iov: add const annotation
[qemu/ar7.git] / hw / sun4m.c
blobc98cd5ec3f5fedd91c85f9bb3c7405862b7c7825
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUSPARCState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(CPUSPARCState *env)
257 {
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261 }
262
263 static void cpu_set_irq(void *opaque, int irq, int level)
264 {
265 CPUSPARCState *env = opaque;
266
267 if (level) {
268 trace_sun4m_cpu_set_irq_raise(irq);
269 env->pil_in |= 1 << irq;
270 cpu_kick_irq(env);
271 } else {
272 trace_sun4m_cpu_set_irq_lower(irq);
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
275 }
276 }
277
278 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279 {
280 }
281
282 static void main_cpu_reset(void *opaque)
283 {
284 SPARCCPU *cpu = opaque;
285 CPUSPARCState *env = &cpu->env;
286
287 cpu_reset(CPU(cpu));
288 env->halted = 0;
289 }
290
291 static void secondary_cpu_reset(void *opaque)
292 {
293 SPARCCPU *cpu = opaque;
294 CPUSPARCState *env = &cpu->env;
295
296 cpu_reset(CPU(cpu));
297 env->halted = 1;
298 }
299
300 static void cpu_halt_signal(void *opaque, int irq, int level)
301 {
302 if (level && cpu_single_env)
303 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
304 }
305
306 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
307 {
308 return addr - 0xf0000000ULL;
309 }
310
311 static unsigned long sun4m_load_kernel(const char *kernel_filename,
312 const char *initrd_filename,
313 ram_addr_t RAM_size)
314 {
315 int linux_boot;
316 unsigned int i;
317 long initrd_size, kernel_size;
318 uint8_t *ptr;
319
320 linux_boot = (kernel_filename != NULL);
321
322 kernel_size = 0;
323 if (linux_boot) {
324 int bswap_needed;
325
326 #ifdef BSWAP_NEEDED
327 bswap_needed = 1;
328 #else
329 bswap_needed = 0;
330 #endif
331 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
332 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
333 if (kernel_size < 0)
334 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
336 TARGET_PAGE_SIZE);
337 if (kernel_size < 0)
338 kernel_size = load_image_targphys(kernel_filename,
339 KERNEL_LOAD_ADDR,
340 RAM_size - KERNEL_LOAD_ADDR);
341 if (kernel_size < 0) {
342 fprintf(stderr, "qemu: could not load kernel '%s'\n",
343 kernel_filename);
344 exit(1);
345 }
346
347 /* load initrd */
348 initrd_size = 0;
349 if (initrd_filename) {
350 initrd_size = load_image_targphys(initrd_filename,
351 INITRD_LOAD_ADDR,
352 RAM_size - INITRD_LOAD_ADDR);
353 if (initrd_size < 0) {
354 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
355 initrd_filename);
356 exit(1);
357 }
358 }
359 if (initrd_size > 0) {
360 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
361 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
362 if (ldl_p(ptr) == 0x48647253) { // HdrS
363 stl_p(ptr + 16, INITRD_LOAD_ADDR);
364 stl_p(ptr + 20, initrd_size);
365 break;
366 }
367 }
368 }
369 }
370 return kernel_size;
371 }
372
373 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
374 {
375 DeviceState *dev;
376 SysBusDevice *s;
377
378 dev = qdev_create(NULL, "iommu");
379 qdev_prop_set_uint32(dev, "version", version);
380 qdev_init_nofail(dev);
381 s = sysbus_from_qdev(dev);
382 sysbus_connect_irq(s, 0, irq);
383 sysbus_mmio_map(s, 0, addr);
384
385 return s;
386 }
387
388 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
389 void *iommu, qemu_irq *dev_irq, int is_ledma)
390 {
391 DeviceState *dev;
392 SysBusDevice *s;
393
394 dev = qdev_create(NULL, "sparc32_dma");
395 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
396 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
397 qdev_init_nofail(dev);
398 s = sysbus_from_qdev(dev);
399 sysbus_connect_irq(s, 0, parent_irq);
400 *dev_irq = qdev_get_gpio_in(dev, 0);
401 sysbus_mmio_map(s, 0, daddr);
402
403 return s;
404 }
405
406 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
407 void *dma_opaque, qemu_irq irq)
408 {
409 DeviceState *dev;
410 SysBusDevice *s;
411 qemu_irq reset;
412
413 qemu_check_nic_model(&nd_table[0], "lance");
414
415 dev = qdev_create(NULL, "lance");
416 qdev_set_nic_properties(dev, nd);
417 qdev_prop_set_ptr(dev, "dma", dma_opaque);
418 qdev_init_nofail(dev);
419 s = sysbus_from_qdev(dev);
420 sysbus_mmio_map(s, 0, leaddr);
421 sysbus_connect_irq(s, 0, irq);
422 reset = qdev_get_gpio_in(dev, 0);
423 qdev_connect_gpio_out(dma_opaque, 0, reset);
424 }
425
426 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
427 target_phys_addr_t addrg,
428 qemu_irq **parent_irq)
429 {
430 DeviceState *dev;
431 SysBusDevice *s;
432 unsigned int i, j;
433
434 dev = qdev_create(NULL, "slavio_intctl");
435 qdev_init_nofail(dev);
436
437 s = sysbus_from_qdev(dev);
438
439 for (i = 0; i < MAX_CPUS; i++) {
440 for (j = 0; j < MAX_PILS; j++) {
441 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
442 }
443 }
444 sysbus_mmio_map(s, 0, addrg);
445 for (i = 0; i < MAX_CPUS; i++) {
446 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
447 }
448
449 return dev;
450 }
451
452 #define SYS_TIMER_OFFSET 0x10000ULL
453 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
454
455 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
456 qemu_irq *cpu_irqs, unsigned int num_cpus)
457 {
458 DeviceState *dev;
459 SysBusDevice *s;
460 unsigned int i;
461
462 dev = qdev_create(NULL, "slavio_timer");
463 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
464 qdev_init_nofail(dev);
465 s = sysbus_from_qdev(dev);
466 sysbus_connect_irq(s, 0, master_irq);
467 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
468
469 for (i = 0; i < MAX_CPUS; i++) {
470 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
471 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
472 }
473 }
474
475 static qemu_irq slavio_system_powerdown;
476
477 static void slavio_powerdown_req(Notifier *n, void *opaque)
478 {
479 qemu_irq_raise(slavio_system_powerdown);
480 }
481
482 static Notifier slavio_system_powerdown_notifier = {
483 .notify = slavio_powerdown_req
484 };
485
486 #define MISC_LEDS 0x01600000
487 #define MISC_CFG 0x01800000
488 #define MISC_DIAG 0x01a00000
489 #define MISC_MDM 0x01b00000
490 #define MISC_SYS 0x01f00000
491
492 static void slavio_misc_init(target_phys_addr_t base,
493 target_phys_addr_t aux1_base,
494 target_phys_addr_t aux2_base, qemu_irq irq,
495 qemu_irq fdc_tc)
496 {
497 DeviceState *dev;
498 SysBusDevice *s;
499
500 dev = qdev_create(NULL, "slavio_misc");
501 qdev_init_nofail(dev);
502 s = sysbus_from_qdev(dev);
503 if (base) {
504 /* 8 bit registers */
505 /* Slavio control */
506 sysbus_mmio_map(s, 0, base + MISC_CFG);
507 /* Diagnostics */
508 sysbus_mmio_map(s, 1, base + MISC_DIAG);
509 /* Modem control */
510 sysbus_mmio_map(s, 2, base + MISC_MDM);
511 /* 16 bit registers */
512 /* ss600mp diag LEDs */
513 sysbus_mmio_map(s, 3, base + MISC_LEDS);
514 /* 32 bit registers */
515 /* System control */
516 sysbus_mmio_map(s, 4, base + MISC_SYS);
517 }
518 if (aux1_base) {
519 /* AUX 1 (Misc System Functions) */
520 sysbus_mmio_map(s, 5, aux1_base);
521 }
522 if (aux2_base) {
523 /* AUX 2 (Software Powerdown Control) */
524 sysbus_mmio_map(s, 6, aux2_base);
525 }
526 sysbus_connect_irq(s, 0, irq);
527 sysbus_connect_irq(s, 1, fdc_tc);
528 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
529 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
530 }
531
532 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
533 {
534 DeviceState *dev;
535 SysBusDevice *s;
536
537 dev = qdev_create(NULL, "eccmemctl");
538 qdev_prop_set_uint32(dev, "version", version);
539 qdev_init_nofail(dev);
540 s = sysbus_from_qdev(dev);
541 sysbus_connect_irq(s, 0, irq);
542 sysbus_mmio_map(s, 0, base);
543 if (version == 0) { // SS-600MP only
544 sysbus_mmio_map(s, 1, base + 0x1000);
545 }
546 }
547
548 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
549 {
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "apc");
554 qdev_init_nofail(dev);
555 s = sysbus_from_qdev(dev);
556 /* Power management (APC) XXX: not a Slavio device */
557 sysbus_mmio_map(s, 0, power_base);
558 sysbus_connect_irq(s, 0, cpu_halt);
559 }
560
561 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
562 int height, int depth)
563 {
564 DeviceState *dev;
565 SysBusDevice *s;
566
567 dev = qdev_create(NULL, "SUNW,tcx");
568 qdev_prop_set_taddr(dev, "addr", addr);
569 qdev_prop_set_uint32(dev, "vram_size", vram_size);
570 qdev_prop_set_uint16(dev, "width", width);
571 qdev_prop_set_uint16(dev, "height", height);
572 qdev_prop_set_uint16(dev, "depth", depth);
573 qdev_init_nofail(dev);
574 s = sysbus_from_qdev(dev);
575 /* 8-bit plane */
576 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
577 /* DAC */
578 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
579 /* TEC (dummy) */
580 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
581 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
582 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
583 if (depth == 24) {
584 /* 24-bit plane */
585 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
586 /* Control plane */
587 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
588 } else {
589 /* THC 8 bit (dummy) */
590 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
591 }
592 }
593
594 /* NCR89C100/MACIO Internal ID register */
595 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
596
597 static void idreg_init(target_phys_addr_t addr)
598 {
599 DeviceState *dev;
600 SysBusDevice *s;
601
602 dev = qdev_create(NULL, "macio_idreg");
603 qdev_init_nofail(dev);
604 s = sysbus_from_qdev(dev);
605
606 sysbus_mmio_map(s, 0, addr);
607 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
608 }
609
610 typedef struct IDRegState {
611 SysBusDevice busdev;
612 MemoryRegion mem;
613 } IDRegState;
614
615 static int idreg_init1(SysBusDevice *dev)
616 {
617 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
618
619 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
620 vmstate_register_ram_global(&s->mem);
621 memory_region_set_readonly(&s->mem, true);
622 sysbus_init_mmio(dev, &s->mem);
623 return 0;
624 }
625
626 static void idreg_class_init(ObjectClass *klass, void *data)
627 {
628 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
629
630 k->init = idreg_init1;
631 }
632
633 static TypeInfo idreg_info = {
634 .name = "macio_idreg",
635 .parent = TYPE_SYS_BUS_DEVICE,
636 .instance_size = sizeof(IDRegState),
637 .class_init = idreg_class_init,
638 };
639
640 typedef struct AFXState {
641 SysBusDevice busdev;
642 MemoryRegion mem;
643 } AFXState;
644
645 /* SS-5 TCX AFX register */
646 static void afx_init(target_phys_addr_t addr)
647 {
648 DeviceState *dev;
649 SysBusDevice *s;
650
651 dev = qdev_create(NULL, "tcx_afx");
652 qdev_init_nofail(dev);
653 s = sysbus_from_qdev(dev);
654
655 sysbus_mmio_map(s, 0, addr);
656 }
657
658 static int afx_init1(SysBusDevice *dev)
659 {
660 AFXState *s = FROM_SYSBUS(AFXState, dev);
661
662 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
663 vmstate_register_ram_global(&s->mem);
664 sysbus_init_mmio(dev, &s->mem);
665 return 0;
666 }
667
668 static void afx_class_init(ObjectClass *klass, void *data)
669 {
670 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
671
672 k->init = afx_init1;
673 }
674
675 static TypeInfo afx_info = {
676 .name = "tcx_afx",
677 .parent = TYPE_SYS_BUS_DEVICE,
678 .instance_size = sizeof(AFXState),
679 .class_init = afx_class_init,
680 };
681
682 typedef struct PROMState {
683 SysBusDevice busdev;
684 MemoryRegion prom;
685 } PROMState;
686
687 /* Boot PROM (OpenBIOS) */
688 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
689 {
690 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
691 return addr + *base_addr - PROM_VADDR;
692 }
693
694 static void prom_init(target_phys_addr_t addr, const char *bios_name)
695 {
696 DeviceState *dev;
697 SysBusDevice *s;
698 char *filename;
699 int ret;
700
701 dev = qdev_create(NULL, "openprom");
702 qdev_init_nofail(dev);
703 s = sysbus_from_qdev(dev);
704
705 sysbus_mmio_map(s, 0, addr);
706
707 /* load boot prom */
708 if (bios_name == NULL) {
709 bios_name = PROM_FILENAME;
710 }
711 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
712 if (filename) {
713 ret = load_elf(filename, translate_prom_address, &addr, NULL,
714 NULL, NULL, 1, ELF_MACHINE, 0);
715 if (ret < 0 || ret > PROM_SIZE_MAX) {
716 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
717 }
718 g_free(filename);
719 } else {
720 ret = -1;
721 }
722 if (ret < 0 || ret > PROM_SIZE_MAX) {
723 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
724 exit(1);
725 }
726 }
727
728 static int prom_init1(SysBusDevice *dev)
729 {
730 PROMState *s = FROM_SYSBUS(PROMState, dev);
731
732 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
733 vmstate_register_ram_global(&s->prom);
734 memory_region_set_readonly(&s->prom, true);
735 sysbus_init_mmio(dev, &s->prom);
736 return 0;
737 }
738
739 static Property prom_properties[] = {
740 {/* end of property list */},
741 };
742
743 static void prom_class_init(ObjectClass *klass, void *data)
744 {
745 DeviceClass *dc = DEVICE_CLASS(klass);
746 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
747
748 k->init = prom_init1;
749 dc->props = prom_properties;
750 }
751
752 static TypeInfo prom_info = {
753 .name = "openprom",
754 .parent = TYPE_SYS_BUS_DEVICE,
755 .instance_size = sizeof(PROMState),
756 .class_init = prom_class_init,
757 };
758
759 typedef struct RamDevice
760 {
761 SysBusDevice busdev;
762 MemoryRegion ram;
763 uint64_t size;
764 } RamDevice;
765
766 /* System RAM */
767 static int ram_init1(SysBusDevice *dev)
768 {
769 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
770
771 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
772 vmstate_register_ram_global(&d->ram);
773 sysbus_init_mmio(dev, &d->ram);
774 return 0;
775 }
776
777 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
778 uint64_t max_mem)
779 {
780 DeviceState *dev;
781 SysBusDevice *s;
782 RamDevice *d;
783
784 /* allocate RAM */
785 if ((uint64_t)RAM_size > max_mem) {
786 fprintf(stderr,
787 "qemu: Too much memory for this machine: %d, maximum %d\n",
788 (unsigned int)(RAM_size / (1024 * 1024)),
789 (unsigned int)(max_mem / (1024 * 1024)));
790 exit(1);
791 }
792 dev = qdev_create(NULL, "memory");
793 s = sysbus_from_qdev(dev);
794
795 d = FROM_SYSBUS(RamDevice, s);
796 d->size = RAM_size;
797 qdev_init_nofail(dev);
798
799 sysbus_mmio_map(s, 0, addr);
800 }
801
802 static Property ram_properties[] = {
803 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
804 DEFINE_PROP_END_OF_LIST(),
805 };
806
807 static void ram_class_init(ObjectClass *klass, void *data)
808 {
809 DeviceClass *dc = DEVICE_CLASS(klass);
810 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
811
812 k->init = ram_init1;
813 dc->props = ram_properties;
814 }
815
816 static TypeInfo ram_info = {
817 .name = "memory",
818 .parent = TYPE_SYS_BUS_DEVICE,
819 .instance_size = sizeof(RamDevice),
820 .class_init = ram_class_init,
821 };
822
823 static void cpu_devinit(const char *cpu_model, unsigned int id,
824 uint64_t prom_addr, qemu_irq **cpu_irqs)
825 {
826 SPARCCPU *cpu;
827 CPUSPARCState *env;
828
829 cpu = cpu_sparc_init(cpu_model);
830 if (cpu == NULL) {
831 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
832 exit(1);
833 }
834 env = &cpu->env;
835
836 cpu_sparc_set_id(env, id);
837 if (id == 0) {
838 qemu_register_reset(main_cpu_reset, cpu);
839 } else {
840 qemu_register_reset(secondary_cpu_reset, cpu);
841 env->halted = 1;
842 }
843 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
844 env->prom_addr = prom_addr;
845 }
846
847 static void dummy_fdc_tc(void *opaque, int irq, int level)
848 {
849 }
850
851 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
852 const char *boot_device,
853 const char *kernel_filename,
854 const char *kernel_cmdline,
855 const char *initrd_filename, const char *cpu_model)
856 {
857 unsigned int i;
858 void *iommu, *espdma, *ledma, *nvram;
859 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
860 espdma_irq, ledma_irq;
861 qemu_irq esp_reset, dma_enable;
862 qemu_irq fdc_tc;
863 qemu_irq *cpu_halt;
864 unsigned long kernel_size;
865 DriveInfo *fd[MAX_FD];
866 void *fw_cfg;
867 unsigned int num_vsimms;
868
869 /* init CPUs */
870 if (!cpu_model)
871 cpu_model = hwdef->default_cpu_model;
872
873 for(i = 0; i < smp_cpus; i++) {
874 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
875 }
876
877 for (i = smp_cpus; i < MAX_CPUS; i++)
878 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
879
880
881 /* set up devices */
882 ram_init(0, RAM_size, hwdef->max_mem);
883 /* models without ECC don't trap when missing ram is accessed */
884 if (!hwdef->ecc_base) {
885 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
886 }
887
888 prom_init(hwdef->slavio_base, bios_name);
889
890 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
891 hwdef->intctl_base + 0x10000ULL,
892 cpu_irqs);
893
894 for (i = 0; i < 32; i++) {
895 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
896 }
897 for (i = 0; i < MAX_CPUS; i++) {
898 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
899 }
900
901 if (hwdef->idreg_base) {
902 idreg_init(hwdef->idreg_base);
903 }
904
905 if (hwdef->afx_base) {
906 afx_init(hwdef->afx_base);
907 }
908
909 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
910 slavio_irq[30]);
911
912 if (hwdef->iommu_pad_base) {
913 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
914 Software shouldn't use aliased addresses, neither should it crash
915 when does. Using empty_slot instead of aliasing can help with
916 debugging such accesses */
917 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
918 }
919
920 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
921 iommu, &espdma_irq, 0);
922
923 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
924 slavio_irq[16], iommu, &ledma_irq, 1);
925
926 if (graphic_depth != 8 && graphic_depth != 24) {
927 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
928 exit (1);
929 }
930 num_vsimms = 0;
931 if (num_vsimms == 0) {
932 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
933 graphic_depth);
934 }
935
936 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
937 /* vsimm registers probed by OBP */
938 if (hwdef->vsimm[i].reg_base) {
939 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
940 }
941 }
942
943 if (hwdef->sx_base) {
944 empty_slot_init(hwdef->sx_base, 0x2000);
945 }
946
947 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
948
949 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
950
951 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
952
953 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
954 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
955 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
956 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
957 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
958 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
959
960 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
961 if (hwdef->apc_base) {
962 apc_init(hwdef->apc_base, cpu_halt[0]);
963 }
964
965 if (hwdef->fd_base) {
966 /* there is zero or one floppy drive */
967 memset(fd, 0, sizeof(fd));
968 fd[0] = drive_get(IF_FLOPPY, 0, 0);
969 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
970 &fdc_tc);
971 } else {
972 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
973 }
974
975 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
976 slavio_irq[30], fdc_tc);
977
978 if (drive_get_max_bus(IF_SCSI) > 0) {
979 fprintf(stderr, "qemu: too many SCSI bus\n");
980 exit(1);
981 }
982
983 esp_init(hwdef->esp_base, 2,
984 espdma_memory_read, espdma_memory_write,
985 espdma, espdma_irq, &esp_reset, &dma_enable);
986
987 qdev_connect_gpio_out(espdma, 0, esp_reset);
988 qdev_connect_gpio_out(espdma, 1, dma_enable);
989
990 if (hwdef->cs_base) {
991 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
992 slavio_irq[5]);
993 }
994
995 if (hwdef->dbri_base) {
996 /* ISDN chip with attached CS4215 audio codec */
997 /* prom space */
998 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
999 /* reg space */
1000 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1001 }
1002
1003 if (hwdef->bpp_base) {
1004 /* parallel port */
1005 empty_slot_init(hwdef->bpp_base, 0x20);
1006 }
1007
1008 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1009 RAM_size);
1010
1011 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1012 boot_device, RAM_size, kernel_size, graphic_width,
1013 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1014 "Sun4m");
1015
1016 if (hwdef->ecc_base)
1017 ecc_init(hwdef->ecc_base, slavio_irq[28],
1018 hwdef->ecc_version);
1019
1020 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1021 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1022 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1023 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1024 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1025 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1026 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1027 if (kernel_cmdline) {
1028 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1029 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1030 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1031 (uint8_t*)strdup(kernel_cmdline),
1032 strlen(kernel_cmdline) + 1);
1033 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1034 strlen(kernel_cmdline) + 1);
1035 } else {
1036 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1037 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1038 }
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1040 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1041 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1042 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1043 }
1044
1045 enum {
1046 ss2_id = 0,
1047 ss5_id = 32,
1048 vger_id,
1049 lx_id,
1050 ss4_id,
1051 scls_id,
1052 sbook_id,
1053 ss10_id = 64,
1054 ss20_id,
1055 ss600mp_id,
1056 ss1000_id = 96,
1057 ss2000_id,
1058 };
1059
1060 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1061 /* SS-5 */
1062 {
1063 .iommu_base = 0x10000000,
1064 .iommu_pad_base = 0x10004000,
1065 .iommu_pad_len = 0x0fffb000,
1066 .tcx_base = 0x50000000,
1067 .cs_base = 0x6c000000,
1068 .slavio_base = 0x70000000,
1069 .ms_kb_base = 0x71000000,
1070 .serial_base = 0x71100000,
1071 .nvram_base = 0x71200000,
1072 .fd_base = 0x71400000,
1073 .counter_base = 0x71d00000,
1074 .intctl_base = 0x71e00000,
1075 .idreg_base = 0x78000000,
1076 .dma_base = 0x78400000,
1077 .esp_base = 0x78800000,
1078 .le_base = 0x78c00000,
1079 .apc_base = 0x6a000000,
1080 .afx_base = 0x6e000000,
1081 .aux1_base = 0x71900000,
1082 .aux2_base = 0x71910000,
1083 .nvram_machine_id = 0x80,
1084 .machine_id = ss5_id,
1085 .iommu_version = 0x05000000,
1086 .max_mem = 0x10000000,
1087 .default_cpu_model = "Fujitsu MB86904",
1088 },
1089 /* SS-10 */
1090 {
1091 .iommu_base = 0xfe0000000ULL,
1092 .tcx_base = 0xe20000000ULL,
1093 .slavio_base = 0xff0000000ULL,
1094 .ms_kb_base = 0xff1000000ULL,
1095 .serial_base = 0xff1100000ULL,
1096 .nvram_base = 0xff1200000ULL,
1097 .fd_base = 0xff1700000ULL,
1098 .counter_base = 0xff1300000ULL,
1099 .intctl_base = 0xff1400000ULL,
1100 .idreg_base = 0xef0000000ULL,
1101 .dma_base = 0xef0400000ULL,
1102 .esp_base = 0xef0800000ULL,
1103 .le_base = 0xef0c00000ULL,
1104 .apc_base = 0xefa000000ULL, // XXX should not exist
1105 .aux1_base = 0xff1800000ULL,
1106 .aux2_base = 0xff1a01000ULL,
1107 .ecc_base = 0xf00000000ULL,
1108 .ecc_version = 0x10000000, // version 0, implementation 1
1109 .nvram_machine_id = 0x72,
1110 .machine_id = ss10_id,
1111 .iommu_version = 0x03000000,
1112 .max_mem = 0xf00000000ULL,
1113 .default_cpu_model = "TI SuperSparc II",
1114 },
1115 /* SS-600MP */
1116 {
1117 .iommu_base = 0xfe0000000ULL,
1118 .tcx_base = 0xe20000000ULL,
1119 .slavio_base = 0xff0000000ULL,
1120 .ms_kb_base = 0xff1000000ULL,
1121 .serial_base = 0xff1100000ULL,
1122 .nvram_base = 0xff1200000ULL,
1123 .counter_base = 0xff1300000ULL,
1124 .intctl_base = 0xff1400000ULL,
1125 .dma_base = 0xef0081000ULL,
1126 .esp_base = 0xef0080000ULL,
1127 .le_base = 0xef0060000ULL,
1128 .apc_base = 0xefa000000ULL, // XXX should not exist
1129 .aux1_base = 0xff1800000ULL,
1130 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1131 .ecc_base = 0xf00000000ULL,
1132 .ecc_version = 0x00000000, // version 0, implementation 0
1133 .nvram_machine_id = 0x71,
1134 .machine_id = ss600mp_id,
1135 .iommu_version = 0x01000000,
1136 .max_mem = 0xf00000000ULL,
1137 .default_cpu_model = "TI SuperSparc II",
1138 },
1139 /* SS-20 */
1140 {
1141 .iommu_base = 0xfe0000000ULL,
1142 .tcx_base = 0xe20000000ULL,
1143 .slavio_base = 0xff0000000ULL,
1144 .ms_kb_base = 0xff1000000ULL,
1145 .serial_base = 0xff1100000ULL,
1146 .nvram_base = 0xff1200000ULL,
1147 .fd_base = 0xff1700000ULL,
1148 .counter_base = 0xff1300000ULL,
1149 .intctl_base = 0xff1400000ULL,
1150 .idreg_base = 0xef0000000ULL,
1151 .dma_base = 0xef0400000ULL,
1152 .esp_base = 0xef0800000ULL,
1153 .le_base = 0xef0c00000ULL,
1154 .bpp_base = 0xef4800000ULL,
1155 .apc_base = 0xefa000000ULL, // XXX should not exist
1156 .aux1_base = 0xff1800000ULL,
1157 .aux2_base = 0xff1a01000ULL,
1158 .dbri_base = 0xee0000000ULL,
1159 .sx_base = 0xf80000000ULL,
1160 .vsimm = {
1161 {
1162 .reg_base = 0x9c000000ULL,
1163 .vram_base = 0xfc000000ULL
1164 }, {
1165 .reg_base = 0x90000000ULL,
1166 .vram_base = 0xf0000000ULL
1167 }, {
1168 .reg_base = 0x94000000ULL
1169 }, {
1170 .reg_base = 0x98000000ULL
1171 }
1172 },
1173 .ecc_base = 0xf00000000ULL,
1174 .ecc_version = 0x20000000, // version 0, implementation 2
1175 .nvram_machine_id = 0x72,
1176 .machine_id = ss20_id,
1177 .iommu_version = 0x13000000,
1178 .max_mem = 0xf00000000ULL,
1179 .default_cpu_model = "TI SuperSparc II",
1180 },
1181 /* Voyager */
1182 {
1183 .iommu_base = 0x10000000,
1184 .tcx_base = 0x50000000,
1185 .slavio_base = 0x70000000,
1186 .ms_kb_base = 0x71000000,
1187 .serial_base = 0x71100000,
1188 .nvram_base = 0x71200000,
1189 .fd_base = 0x71400000,
1190 .counter_base = 0x71d00000,
1191 .intctl_base = 0x71e00000,
1192 .idreg_base = 0x78000000,
1193 .dma_base = 0x78400000,
1194 .esp_base = 0x78800000,
1195 .le_base = 0x78c00000,
1196 .apc_base = 0x71300000, // pmc
1197 .aux1_base = 0x71900000,
1198 .aux2_base = 0x71910000,
1199 .nvram_machine_id = 0x80,
1200 .machine_id = vger_id,
1201 .iommu_version = 0x05000000,
1202 .max_mem = 0x10000000,
1203 .default_cpu_model = "Fujitsu MB86904",
1204 },
1205 /* LX */
1206 {
1207 .iommu_base = 0x10000000,
1208 .iommu_pad_base = 0x10004000,
1209 .iommu_pad_len = 0x0fffb000,
1210 .tcx_base = 0x50000000,
1211 .slavio_base = 0x70000000,
1212 .ms_kb_base = 0x71000000,
1213 .serial_base = 0x71100000,
1214 .nvram_base = 0x71200000,
1215 .fd_base = 0x71400000,
1216 .counter_base = 0x71d00000,
1217 .intctl_base = 0x71e00000,
1218 .idreg_base = 0x78000000,
1219 .dma_base = 0x78400000,
1220 .esp_base = 0x78800000,
1221 .le_base = 0x78c00000,
1222 .aux1_base = 0x71900000,
1223 .aux2_base = 0x71910000,
1224 .nvram_machine_id = 0x80,
1225 .machine_id = lx_id,
1226 .iommu_version = 0x04000000,
1227 .max_mem = 0x10000000,
1228 .default_cpu_model = "TI MicroSparc I",
1229 },
1230 /* SS-4 */
1231 {
1232 .iommu_base = 0x10000000,
1233 .tcx_base = 0x50000000,
1234 .cs_base = 0x6c000000,
1235 .slavio_base = 0x70000000,
1236 .ms_kb_base = 0x71000000,
1237 .serial_base = 0x71100000,
1238 .nvram_base = 0x71200000,
1239 .fd_base = 0x71400000,
1240 .counter_base = 0x71d00000,
1241 .intctl_base = 0x71e00000,
1242 .idreg_base = 0x78000000,
1243 .dma_base = 0x78400000,
1244 .esp_base = 0x78800000,
1245 .le_base = 0x78c00000,
1246 .apc_base = 0x6a000000,
1247 .aux1_base = 0x71900000,
1248 .aux2_base = 0x71910000,
1249 .nvram_machine_id = 0x80,
1250 .machine_id = ss4_id,
1251 .iommu_version = 0x05000000,
1252 .max_mem = 0x10000000,
1253 .default_cpu_model = "Fujitsu MB86904",
1254 },
1255 /* SPARCClassic */
1256 {
1257 .iommu_base = 0x10000000,
1258 .tcx_base = 0x50000000,
1259 .slavio_base = 0x70000000,
1260 .ms_kb_base = 0x71000000,
1261 .serial_base = 0x71100000,
1262 .nvram_base = 0x71200000,
1263 .fd_base = 0x71400000,
1264 .counter_base = 0x71d00000,
1265 .intctl_base = 0x71e00000,
1266 .idreg_base = 0x78000000,
1267 .dma_base = 0x78400000,
1268 .esp_base = 0x78800000,
1269 .le_base = 0x78c00000,
1270 .apc_base = 0x6a000000,
1271 .aux1_base = 0x71900000,
1272 .aux2_base = 0x71910000,
1273 .nvram_machine_id = 0x80,
1274 .machine_id = scls_id,
1275 .iommu_version = 0x05000000,
1276 .max_mem = 0x10000000,
1277 .default_cpu_model = "TI MicroSparc I",
1278 },
1279 /* SPARCbook */
1280 {
1281 .iommu_base = 0x10000000,
1282 .tcx_base = 0x50000000, // XXX
1283 .slavio_base = 0x70000000,
1284 .ms_kb_base = 0x71000000,
1285 .serial_base = 0x71100000,
1286 .nvram_base = 0x71200000,
1287 .fd_base = 0x71400000,
1288 .counter_base = 0x71d00000,
1289 .intctl_base = 0x71e00000,
1290 .idreg_base = 0x78000000,
1291 .dma_base = 0x78400000,
1292 .esp_base = 0x78800000,
1293 .le_base = 0x78c00000,
1294 .apc_base = 0x6a000000,
1295 .aux1_base = 0x71900000,
1296 .aux2_base = 0x71910000,
1297 .nvram_machine_id = 0x80,
1298 .machine_id = sbook_id,
1299 .iommu_version = 0x05000000,
1300 .max_mem = 0x10000000,
1301 .default_cpu_model = "TI MicroSparc I",
1302 },
1303 };
1304
1305 /* SPARCstation 5 hardware initialisation */
1306 static void ss5_init(ram_addr_t RAM_size,
1307 const char *boot_device,
1308 const char *kernel_filename, const char *kernel_cmdline,
1309 const char *initrd_filename, const char *cpu_model)
1310 {
1311 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1312 kernel_cmdline, initrd_filename, cpu_model);
1313 }
1314
1315 /* SPARCstation 10 hardware initialisation */
1316 static void ss10_init(ram_addr_t RAM_size,
1317 const char *boot_device,
1318 const char *kernel_filename, const char *kernel_cmdline,
1319 const char *initrd_filename, const char *cpu_model)
1320 {
1321 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1322 kernel_cmdline, initrd_filename, cpu_model);
1323 }
1324
1325 /* SPARCserver 600MP hardware initialisation */
1326 static void ss600mp_init(ram_addr_t RAM_size,
1327 const char *boot_device,
1328 const char *kernel_filename,
1329 const char *kernel_cmdline,
1330 const char *initrd_filename, const char *cpu_model)
1331 {
1332 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1333 kernel_cmdline, initrd_filename, cpu_model);
1334 }
1335
1336 /* SPARCstation 20 hardware initialisation */
1337 static void ss20_init(ram_addr_t RAM_size,
1338 const char *boot_device,
1339 const char *kernel_filename, const char *kernel_cmdline,
1340 const char *initrd_filename, const char *cpu_model)
1341 {
1342 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1343 kernel_cmdline, initrd_filename, cpu_model);
1344 }
1345
1346 /* SPARCstation Voyager hardware initialisation */
1347 static void vger_init(ram_addr_t RAM_size,
1348 const char *boot_device,
1349 const char *kernel_filename, const char *kernel_cmdline,
1350 const char *initrd_filename, const char *cpu_model)
1351 {
1352 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1353 kernel_cmdline, initrd_filename, cpu_model);
1354 }
1355
1356 /* SPARCstation LX hardware initialisation */
1357 static void ss_lx_init(ram_addr_t RAM_size,
1358 const char *boot_device,
1359 const char *kernel_filename, const char *kernel_cmdline,
1360 const char *initrd_filename, const char *cpu_model)
1361 {
1362 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1363 kernel_cmdline, initrd_filename, cpu_model);
1364 }
1365
1366 /* SPARCstation 4 hardware initialisation */
1367 static void ss4_init(ram_addr_t RAM_size,
1368 const char *boot_device,
1369 const char *kernel_filename, const char *kernel_cmdline,
1370 const char *initrd_filename, const char *cpu_model)
1371 {
1372 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1373 kernel_cmdline, initrd_filename, cpu_model);
1374 }
1375
1376 /* SPARCClassic hardware initialisation */
1377 static void scls_init(ram_addr_t RAM_size,
1378 const char *boot_device,
1379 const char *kernel_filename, const char *kernel_cmdline,
1380 const char *initrd_filename, const char *cpu_model)
1381 {
1382 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1383 kernel_cmdline, initrd_filename, cpu_model);
1384 }
1385
1386 /* SPARCbook hardware initialisation */
1387 static void sbook_init(ram_addr_t RAM_size,
1388 const char *boot_device,
1389 const char *kernel_filename, const char *kernel_cmdline,
1390 const char *initrd_filename, const char *cpu_model)
1391 {
1392 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1393 kernel_cmdline, initrd_filename, cpu_model);
1394 }
1395
1396 static QEMUMachine ss5_machine = {
1397 .name = "SS-5",
1398 .desc = "Sun4m platform, SPARCstation 5",
1399 .init = ss5_init,
1400 .use_scsi = 1,
1401 .is_default = 1,
1402 };
1403
1404 static QEMUMachine ss10_machine = {
1405 .name = "SS-10",
1406 .desc = "Sun4m platform, SPARCstation 10",
1407 .init = ss10_init,
1408 .use_scsi = 1,
1409 .max_cpus = 4,
1410 };
1411
1412 static QEMUMachine ss600mp_machine = {
1413 .name = "SS-600MP",
1414 .desc = "Sun4m platform, SPARCserver 600MP",
1415 .init = ss600mp_init,
1416 .use_scsi = 1,
1417 .max_cpus = 4,
1418 };
1419
1420 static QEMUMachine ss20_machine = {
1421 .name = "SS-20",
1422 .desc = "Sun4m platform, SPARCstation 20",
1423 .init = ss20_init,
1424 .use_scsi = 1,
1425 .max_cpus = 4,
1426 };
1427
1428 static QEMUMachine voyager_machine = {
1429 .name = "Voyager",
1430 .desc = "Sun4m platform, SPARCstation Voyager",
1431 .init = vger_init,
1432 .use_scsi = 1,
1433 };
1434
1435 static QEMUMachine ss_lx_machine = {
1436 .name = "LX",
1437 .desc = "Sun4m platform, SPARCstation LX",
1438 .init = ss_lx_init,
1439 .use_scsi = 1,
1440 };
1441
1442 static QEMUMachine ss4_machine = {
1443 .name = "SS-4",
1444 .desc = "Sun4m platform, SPARCstation 4",
1445 .init = ss4_init,
1446 .use_scsi = 1,
1447 };
1448
1449 static QEMUMachine scls_machine = {
1450 .name = "SPARCClassic",
1451 .desc = "Sun4m platform, SPARCClassic",
1452 .init = scls_init,
1453 .use_scsi = 1,
1454 };
1455
1456 static QEMUMachine sbook_machine = {
1457 .name = "SPARCbook",
1458 .desc = "Sun4m platform, SPARCbook",
1459 .init = sbook_init,
1460 .use_scsi = 1,
1461 };
1462
1463 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1464 /* SS-1000 */
1465 {
1466 .iounit_bases = {
1467 0xfe0200000ULL,
1468 0xfe1200000ULL,
1469 0xfe2200000ULL,
1470 0xfe3200000ULL,
1471 -1,
1472 },
1473 .tcx_base = 0x820000000ULL,
1474 .slavio_base = 0xf00000000ULL,
1475 .ms_kb_base = 0xf00240000ULL,
1476 .serial_base = 0xf00200000ULL,
1477 .nvram_base = 0xf00280000ULL,
1478 .counter_base = 0xf00300000ULL,
1479 .espdma_base = 0x800081000ULL,
1480 .esp_base = 0x800080000ULL,
1481 .ledma_base = 0x800040000ULL,
1482 .le_base = 0x800060000ULL,
1483 .sbi_base = 0xf02800000ULL,
1484 .nvram_machine_id = 0x80,
1485 .machine_id = ss1000_id,
1486 .iounit_version = 0x03000000,
1487 .max_mem = 0xf00000000ULL,
1488 .default_cpu_model = "TI SuperSparc II",
1489 },
1490 /* SS-2000 */
1491 {
1492 .iounit_bases = {
1493 0xfe0200000ULL,
1494 0xfe1200000ULL,
1495 0xfe2200000ULL,
1496 0xfe3200000ULL,
1497 0xfe4200000ULL,
1498 },
1499 .tcx_base = 0x820000000ULL,
1500 .slavio_base = 0xf00000000ULL,
1501 .ms_kb_base = 0xf00240000ULL,
1502 .serial_base = 0xf00200000ULL,
1503 .nvram_base = 0xf00280000ULL,
1504 .counter_base = 0xf00300000ULL,
1505 .espdma_base = 0x800081000ULL,
1506 .esp_base = 0x800080000ULL,
1507 .ledma_base = 0x800040000ULL,
1508 .le_base = 0x800060000ULL,
1509 .sbi_base = 0xf02800000ULL,
1510 .nvram_machine_id = 0x80,
1511 .machine_id = ss2000_id,
1512 .iounit_version = 0x03000000,
1513 .max_mem = 0xf00000000ULL,
1514 .default_cpu_model = "TI SuperSparc II",
1515 },
1516 };
1517
1518 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1519 {
1520 DeviceState *dev;
1521 SysBusDevice *s;
1522 unsigned int i;
1523
1524 dev = qdev_create(NULL, "sbi");
1525 qdev_init_nofail(dev);
1526
1527 s = sysbus_from_qdev(dev);
1528
1529 for (i = 0; i < MAX_CPUS; i++) {
1530 sysbus_connect_irq(s, i, *parent_irq[i]);
1531 }
1532
1533 sysbus_mmio_map(s, 0, addr);
1534
1535 return dev;
1536 }
1537
1538 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1539 const char *boot_device,
1540 const char *kernel_filename,
1541 const char *kernel_cmdline,
1542 const char *initrd_filename, const char *cpu_model)
1543 {
1544 unsigned int i;
1545 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1546 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1547 espdma_irq, ledma_irq;
1548 qemu_irq esp_reset, dma_enable;
1549 unsigned long kernel_size;
1550 void *fw_cfg;
1551 DeviceState *dev;
1552
1553 /* init CPUs */
1554 if (!cpu_model)
1555 cpu_model = hwdef->default_cpu_model;
1556
1557 for(i = 0; i < smp_cpus; i++) {
1558 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1559 }
1560
1561 for (i = smp_cpus; i < MAX_CPUS; i++)
1562 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1563
1564 /* set up devices */
1565 ram_init(0, RAM_size, hwdef->max_mem);
1566
1567 prom_init(hwdef->slavio_base, bios_name);
1568
1569 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1570
1571 for (i = 0; i < 32; i++) {
1572 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1573 }
1574 for (i = 0; i < MAX_CPUS; i++) {
1575 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1576 }
1577
1578 for (i = 0; i < MAX_IOUNITS; i++)
1579 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1580 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1581 hwdef->iounit_version,
1582 sbi_irq[0]);
1583
1584 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1585 iounits[0], &espdma_irq, 0);
1586
1587 /* should be lebuffer instead */
1588 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1589 iounits[0], &ledma_irq, 0);
1590
1591 if (graphic_depth != 8 && graphic_depth != 24) {
1592 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1593 exit (1);
1594 }
1595 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1596 graphic_depth);
1597
1598 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1599
1600 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1601
1602 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1603
1604 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1605 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1606 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1607 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1608 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1609 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1610
1611 if (drive_get_max_bus(IF_SCSI) > 0) {
1612 fprintf(stderr, "qemu: too many SCSI bus\n");
1613 exit(1);
1614 }
1615
1616 esp_init(hwdef->esp_base, 2,
1617 espdma_memory_read, espdma_memory_write,
1618 espdma, espdma_irq, &esp_reset, &dma_enable);
1619
1620 qdev_connect_gpio_out(espdma, 0, esp_reset);
1621 qdev_connect_gpio_out(espdma, 1, dma_enable);
1622
1623 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1624 RAM_size);
1625
1626 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1627 boot_device, RAM_size, kernel_size, graphic_width,
1628 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1629 "Sun4d");
1630
1631 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1632 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1633 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1634 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1635 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1636 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1637 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1638 if (kernel_cmdline) {
1639 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1640 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1641 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1642 (uint8_t*)strdup(kernel_cmdline),
1643 strlen(kernel_cmdline) + 1);
1644 } else {
1645 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1646 }
1647 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1648 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1649 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1650 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1651 }
1652
1653 /* SPARCserver 1000 hardware initialisation */
1654 static void ss1000_init(ram_addr_t RAM_size,
1655 const char *boot_device,
1656 const char *kernel_filename, const char *kernel_cmdline,
1657 const char *initrd_filename, const char *cpu_model)
1658 {
1659 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1660 kernel_cmdline, initrd_filename, cpu_model);
1661 }
1662
1663 /* SPARCcenter 2000 hardware initialisation */
1664 static void ss2000_init(ram_addr_t RAM_size,
1665 const char *boot_device,
1666 const char *kernel_filename, const char *kernel_cmdline,
1667 const char *initrd_filename, const char *cpu_model)
1668 {
1669 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1670 kernel_cmdline, initrd_filename, cpu_model);
1671 }
1672
1673 static QEMUMachine ss1000_machine = {
1674 .name = "SS-1000",
1675 .desc = "Sun4d platform, SPARCserver 1000",
1676 .init = ss1000_init,
1677 .use_scsi = 1,
1678 .max_cpus = 8,
1679 };
1680
1681 static QEMUMachine ss2000_machine = {
1682 .name = "SS-2000",
1683 .desc = "Sun4d platform, SPARCcenter 2000",
1684 .init = ss2000_init,
1685 .use_scsi = 1,
1686 .max_cpus = 20,
1687 };
1688
1689 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1690 /* SS-2 */
1691 {
1692 .iommu_base = 0xf8000000,
1693 .tcx_base = 0xfe000000,
1694 .slavio_base = 0xf6000000,
1695 .intctl_base = 0xf5000000,
1696 .counter_base = 0xf3000000,
1697 .ms_kb_base = 0xf0000000,
1698 .serial_base = 0xf1000000,
1699 .nvram_base = 0xf2000000,
1700 .fd_base = 0xf7200000,
1701 .dma_base = 0xf8400000,
1702 .esp_base = 0xf8800000,
1703 .le_base = 0xf8c00000,
1704 .aux1_base = 0xf7400003,
1705 .nvram_machine_id = 0x55,
1706 .machine_id = ss2_id,
1707 .max_mem = 0x10000000,
1708 .default_cpu_model = "Cypress CY7C601",
1709 },
1710 };
1711
1712 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1713 qemu_irq *parent_irq)
1714 {
1715 DeviceState *dev;
1716 SysBusDevice *s;
1717 unsigned int i;
1718
1719 dev = qdev_create(NULL, "sun4c_intctl");
1720 qdev_init_nofail(dev);
1721
1722 s = sysbus_from_qdev(dev);
1723
1724 for (i = 0; i < MAX_PILS; i++) {
1725 sysbus_connect_irq(s, i, parent_irq[i]);
1726 }
1727 sysbus_mmio_map(s, 0, addr);
1728
1729 return dev;
1730 }
1731
1732 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1733 const char *boot_device,
1734 const char *kernel_filename,
1735 const char *kernel_cmdline,
1736 const char *initrd_filename, const char *cpu_model)
1737 {
1738 void *iommu, *espdma, *ledma, *nvram;
1739 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1740 qemu_irq esp_reset, dma_enable;
1741 qemu_irq fdc_tc;
1742 unsigned long kernel_size;
1743 DriveInfo *fd[MAX_FD];
1744 void *fw_cfg;
1745 DeviceState *dev;
1746 unsigned int i;
1747
1748 /* init CPU */
1749 if (!cpu_model)
1750 cpu_model = hwdef->default_cpu_model;
1751
1752 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1753
1754 /* set up devices */
1755 ram_init(0, RAM_size, hwdef->max_mem);
1756
1757 prom_init(hwdef->slavio_base, bios_name);
1758
1759 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1760
1761 for (i = 0; i < 8; i++) {
1762 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1763 }
1764
1765 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1766 slavio_irq[1]);
1767
1768 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1769 iommu, &espdma_irq, 0);
1770
1771 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1772 slavio_irq[3], iommu, &ledma_irq, 1);
1773
1774 if (graphic_depth != 8 && graphic_depth != 24) {
1775 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1776 exit (1);
1777 }
1778 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1779 graphic_depth);
1780
1781 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1782
1783 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1784
1785 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1786 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1787 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1788 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1789 escc_init(hwdef->serial_base, slavio_irq[1],
1790 slavio_irq[1], serial_hds[0], serial_hds[1],
1791 ESCC_CLOCK, 1);
1792
1793 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1794 /* there is zero or one floppy drive */
1795 memset(fd, 0, sizeof(fd));
1796 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1797 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1798 &fdc_tc);
1799 } else {
1800 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1801 }
1802
1803 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1804
1805 if (drive_get_max_bus(IF_SCSI) > 0) {
1806 fprintf(stderr, "qemu: too many SCSI bus\n");
1807 exit(1);
1808 }
1809
1810 esp_init(hwdef->esp_base, 2,
1811 espdma_memory_read, espdma_memory_write,
1812 espdma, espdma_irq, &esp_reset, &dma_enable);
1813
1814 qdev_connect_gpio_out(espdma, 0, esp_reset);
1815 qdev_connect_gpio_out(espdma, 1, dma_enable);
1816
1817 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1818 RAM_size);
1819
1820 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1821 boot_device, RAM_size, kernel_size, graphic_width,
1822 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1823 "Sun4c");
1824
1825 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1826 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1827 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1828 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1829 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1830 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1831 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1832 if (kernel_cmdline) {
1833 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1834 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1835 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1836 (uint8_t*)strdup(kernel_cmdline),
1837 strlen(kernel_cmdline) + 1);
1838 } else {
1839 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1840 }
1841 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1842 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1843 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1844 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1845 }
1846
1847 /* SPARCstation 2 hardware initialisation */
1848 static void ss2_init(ram_addr_t RAM_size,
1849 const char *boot_device,
1850 const char *kernel_filename, const char *kernel_cmdline,
1851 const char *initrd_filename, const char *cpu_model)
1852 {
1853 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1854 kernel_cmdline, initrd_filename, cpu_model);
1855 }
1856
1857 static QEMUMachine ss2_machine = {
1858 .name = "SS-2",
1859 .desc = "Sun4c platform, SPARCstation 2",
1860 .init = ss2_init,
1861 .use_scsi = 1,
1862 };
1863
1864 static void sun4m_register_types(void)
1865 {
1866 type_register_static(&idreg_info);
1867 type_register_static(&afx_info);
1868 type_register_static(&prom_info);
1869 type_register_static(&ram_info);
1870 }
1871
1872 static void ss2_machine_init(void)
1873 {
1874 qemu_register_machine(&ss5_machine);
1875 qemu_register_machine(&ss10_machine);
1876 qemu_register_machine(&ss600mp_machine);
1877 qemu_register_machine(&ss20_machine);
1878 qemu_register_machine(&voyager_machine);
1879 qemu_register_machine(&ss_lx_machine);
1880 qemu_register_machine(&ss4_machine);
1881 qemu_register_machine(&scls_machine);
1882 qemu_register_machine(&sbook_machine);
1883 qemu_register_machine(&ss1000_machine);
1884 qemu_register_machine(&ss2000_machine);
1885 qemu_register_machine(&ss2_machine);
1886 }
1887
1888 type_init(sun4m_register_types)
1889 machine_init(ss2_machine_init);
AR7 emulation for QEMU