hw/intc/arm_gicv3: Add accessors for ICH_ system registers
[qemu/ar7.git] / include / hw / sparc / grlib.h
blobafbb9bc07c1feab38cc00ad31dee806bf1f6e77c
1 /*
2 * QEMU GRLIB Components
4 * Copyright (c) 2010-2011 AdaCore
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #ifndef GRLIB_H
26 #define GRLIB_H
28 #include "hw/qdev.h"
29 #include "hw/sysbus.h"
31 /* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
32 * http://www.gaisler.com/products/grlib/grip.pdf
35 /* IRQMP */
37 typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
39 void grlib_irqmp_set_irq(void *opaque, int irq, int level);
41 void grlib_irqmp_ack(DeviceState *dev, int intno);
43 static inline
44 DeviceState *grlib_irqmp_create(hwaddr base,
45 CPUSPARCState *env,
46 qemu_irq **cpu_irqs,
47 uint32_t nr_irqs,
48 set_pil_in_fn set_pil_in)
50 DeviceState *dev;
52 assert(cpu_irqs != NULL);
54 dev = qdev_create(NULL, "grlib,irqmp");
55 qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
56 qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
58 qdev_init_nofail(dev);
60 env->irq_manager = dev;
62 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
64 *cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
65 dev,
66 nr_irqs);
68 return dev;
71 /* GPTimer */
73 static inline
74 DeviceState *grlib_gptimer_create(hwaddr base,
75 uint32_t nr_timers,
76 uint32_t freq,
77 qemu_irq *cpu_irqs,
78 int base_irq)
80 DeviceState *dev;
81 int i;
83 dev = qdev_create(NULL, "grlib,gptimer");
84 qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
85 qdev_prop_set_uint32(dev, "frequency", freq);
86 qdev_prop_set_uint32(dev, "irq-line", base_irq);
88 qdev_init_nofail(dev);
90 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
92 for (i = 0; i < nr_timers; i++) {
93 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, cpu_irqs[base_irq + i]);
96 return dev;
99 /* APB UART */
101 static inline
102 DeviceState *grlib_apbuart_create(hwaddr base,
103 CharDriverState *serial,
104 qemu_irq irq)
106 DeviceState *dev;
108 dev = qdev_create(NULL, "grlib,apbuart");
109 qdev_prop_set_chr(dev, "chrdev", serial);
111 qdev_init_nofail(dev);
113 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
115 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq);
117 return dev;
120 #endif /* GRLIB_H */