include/hw/ppc/pnv.h

   1 /*
   2  * QEMU PowerPC PowerNV various definitions
   3  *
   4  * Copyright (c) 2014-2016 BenH, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef _PPC_PNV_H
  20 #define _PPC_PNV_H
  21
  22 #include "hw/boards.h"
  23 #include "hw/sysbus.h"
  24 #include "hw/ppc/pnv_lpc.h"
  25
  26 #define TYPE_PNV_CHIP "powernv-chip"
  27 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
  28 #define PNV_CHIP_CLASS(klass) \
  29      OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
  30 #define PNV_CHIP_GET_CLASS(obj) \
  31      OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
  32
  33 typedef enum PnvChipType {
  34     PNV_CHIP_POWER8E,     /* AKA Murano (default) */
  35     PNV_CHIP_POWER8,      /* AKA Venice */
  36     PNV_CHIP_POWER8NVL,   /* AKA Naples */
  37     PNV_CHIP_POWER9,      /* AKA Nimbus */
  38 } PnvChipType;
  39
  40 typedef struct PnvChip {
  41     /*< private >*/
  42     SysBusDevice parent_obj;
  43
  44     /*< public >*/
  45     uint32_t     chip_id;
  46     uint64_t     ram_start;
  47     uint64_t     ram_size;
  48
  49     uint32_t     nr_cores;
  50     uint64_t     cores_mask;
  51     void         *cores;
  52
  53     hwaddr       xscom_base;
  54     MemoryRegion xscom_mmio;
  55     MemoryRegion xscom;
  56     AddressSpace xscom_as;
  57
  58     PnvLpcController lpc;
  59 } PnvChip;
  60
  61 typedef struct PnvChipClass {
  62     /*< private >*/
  63     SysBusDeviceClass parent_class;
  64
  65     /*< public >*/
  66     const char *cpu_model;
  67     PnvChipType  chip_type;
  68     uint64_t     chip_cfam_id;
  69     uint64_t     cores_mask;
  70
  71     hwaddr       xscom_base;
  72     hwaddr       xscom_core_base;
  73
  74     uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
  75 } PnvChipClass;
  76
  77 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
  78 #define PNV_CHIP_POWER8E(obj) \
  79     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
  80
  81 #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8"
  82 #define PNV_CHIP_POWER8(obj) \
  83     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
  84
  85 #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL"
  86 #define PNV_CHIP_POWER8NVL(obj) \
  87     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
  88
  89 #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9"
  90 #define PNV_CHIP_POWER9(obj) \
  91     OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
  92
  93 /*
  94  * This generates a HW chip id depending on an index:
  95  *
  96  *    0x0, 0x1, 0x10, 0x11
  97  *
  98  * 4 chips should be the maximum
  99  */
 100 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
 101
 102 #define TYPE_POWERNV_MACHINE       MACHINE_TYPE_NAME("powernv")
 103 #define POWERNV_MACHINE(obj) \
 104     OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
 105
 106 typedef struct PnvMachineState {
 107     /*< private >*/
 108     MachineState parent_obj;
 109
 110     uint32_t     initrd_base;
 111     long         initrd_size;
 112
 113     uint32_t     num_chips;
 114     PnvChip      **chips;
 115
 116     ISABus       *isa_bus;
 117 } PnvMachineState;
 118
 119 #define PNV_FDT_ADDR          0x01000000
 120 #define PNV_TIMEBASE_FREQ     512000000ULL
 121
 122 /*
 123  * POWER8 MMIO base addresses
 124  */
 125 #define PNV_XSCOM_SIZE        0x800000000ull
 126 #define PNV_XSCOM_BASE(chip)                                            \
 127     (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
 128
 129 #endif /* _PPC_PNV_H */