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target-tricore: Add instructions of BRN opcode format
[qemu/ar7.git] / target-tricore / tricore-opcodes.h
blob3622d388e21f7a5a49ffe703ee792201d66f5271
1 /*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /*
19 * Opcode Masks for Tricore
20 * Format MASK_OP_InstrFormatName_Field
21 */
22
23 /* This creates a mask with bits start .. end set to 1 and applies it to op */
24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
25 (end) - (start) + 1))
26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
27 (end) - (start) + 1))
28
29 /* new opcode masks */
30
31 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
32
33 /* 16-Bit Formats */
34 #define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
36
37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
39 #define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
40
41 #define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
42 #define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
43
44 #define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
46
47 #define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
48
49 #define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
50 #define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
51
52 #define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
53 #define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
54
55 #define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
56 #define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
57
58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
60 #define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
61
62 #define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
63 #define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
64
65 #define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
66 #define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
67
68 #define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
69 #define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
70 #define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
71
72 #define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
73 #define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
74
75 #define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
76 #define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
77
78 /* 32-Bit Formats */
79
80 /* ABS Format */
81 #define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
84 (MASK_BITS_SHIFT(op, 12, 15) << 14))
85 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
86 #define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
87
88 /* ABSB Format */
89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
90 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
91 #define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
92 #define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 8, 10)
93
94 /* B Format */
95 #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
96 (MASK_BITS_SHIFT(op, 8, 15) << 16))
97 /* BIT Format */
98 #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
99 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
100 #define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
101 #define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
102 #define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
103 #define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
104
105 /* BO Format */
106 #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
107 (MASK_BITS_SHIFT(op, 28, 31) << 6))
108 #define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
109 (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
110 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
111 #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
112 #define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
113
114 /* BOL Format */
115 #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
116 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
117 (MASK_BITS_SHIFT(op, 22, 27) >> 10))
118 #define MASK_OP_BOL_OFF16_SEXT(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
119 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
120 (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
121 #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
122 #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
123
124 /* BRC Format */
125 #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
126 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
127 #define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
128 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
129 #define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
130 #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
131
132 /* BRN Format */
133 #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
134 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
135 #define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
136 #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
137 (MASK_BITS_SHIFT(op, 7, 7) << 4))
138 #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
139 /* BRR Format */
140 #define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
141 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
142 #define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
143 #define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
144
145 /* META MASK for similar instr Formats */
146 #define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
147 #define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
148
149 /* RC Format */
150 #define MASK_OP_RC_D(op) MASK_OP_META_D(op)
151 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
152 #define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
153 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
154
155 /* RCPW Format */
156
157 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
158 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
159 #define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
160 #define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
161 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
162 #define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
163
164 /* RCR Format */
165
166 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
167 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
168 #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
169 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
170 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
171
172 /* RCRR Format */
173
174 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
175 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
176 #define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
177 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
178 #define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
179
180 /* RCRW Format */
181
182 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
183 #define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
184 #define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
185 #define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
186 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
187 #define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
188
189 /* RLC Format */
190
191 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
192 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
193 #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
194
195 /* RR Format */
196 #define MASK_OP_RR_D(op) MASK_OP_META_D(op)
197 #define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
198 #define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
199 #define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
200 #define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
201
202 /* RR1 Format */
203 #define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
204 #define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
205 #define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
206 #define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
207 #define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
208
209 /* RR2 Format */
210 #define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
211 #define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
212 #define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
213 #define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
214
215 /* RRPW Format */
216 #define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
217 #define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
218 #define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
219 #define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
220 #define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
221 #define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
222
223 /* RRR Format */
224 #define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
225 #define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
226 #define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
227 #define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
228 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
229 #define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
230
231 /* RRR1 Format */
232 #define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
233 #define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
234 #define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
235 #define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
236 #define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
237 #define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
238
239 /* RRR2 Format */
240 #define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
241 #define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
242 #define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
243 #define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
244 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
245
246 /* RRRR Format */
247 #define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
248 #define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
249 #define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
250 #define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
251 #define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
252
253 /* RRRW Format */
254 #define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
255 #define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
256 #define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
257 #define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
258 #define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
259 #define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
260
261 /* SYS Format */
262 #define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
263 #define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
264
265
266
267 /*
268 * Tricore Opcodes Enums
269 *
270 * Format: OPC(1|2|M)_InstrLen_Name
271 * OPC1 = only op1 field is used
272 * OPC2 = op1 and op2 field used part of OPCM
273 * OPCM = op1 field used to group Instr
274 * InstrLen = 16|32
275 * Name = Name of Instr
276 */
277
278 /* 16-Bit */
279 enum {
280
281 OPCM_16_SR_SYSTEM = 0x00,
282 OPCM_16_SR_ACCU = 0x32,
283
284 OPC1_16_SRC_ADD = 0xc2,
285 OPC1_16_SRC_ADD_A15 = 0x92,
286 OPC1_16_SRC_ADD_15A = 0x9a,
287 OPC1_16_SRR_ADD = 0x42,
288 OPC1_16_SRR_ADD_A15 = 0x12,
289 OPC1_16_SRR_ADD_15A = 0x1a,
290 OPC1_16_SRC_ADD_A = 0xb0,
291 OPC1_16_SRR_ADD_A = 0x30,
292 OPC1_16_SRR_ADDS = 0x22,
293 OPC1_16_SRRS_ADDSC_A = 0x10,
294 OPC1_16_SC_AND = 0x16,
295 OPC1_16_SRR_AND = 0x26,
296 OPC1_16_SC_BISR = 0xe0,
297 OPC1_16_SRC_CADD = 0x8a,
298 OPC1_16_SRC_CADDN = 0xca,
299 OPC1_16_SB_CALL = 0x5c,
300 OPC1_16_SRC_CMOV = 0xaa,
301 OPC1_16_SRR_CMOV = 0x2a,
302 OPC1_16_SRC_CMOVN = 0xea,
303 OPC1_16_SRR_CMOVN = 0x6a,
304 OPC1_16_SRC_EQ = 0xba,
305 OPC1_16_SRR_EQ = 0x3a,
306 OPC1_16_SB_J = 0x3c,
307 OPC1_16_SBC_JEQ = 0x1e,
308 OPC1_16_SBR_JEQ = 0x3e,
309 OPC1_16_SBR_JGEZ = 0xce,
310 OPC1_16_SBR_JGTZ = 0x4e,
311 OPC1_16_SR_JI = 0xdc,
312 OPC1_16_SBR_JLEZ = 0x8e,
313 OPC1_16_SBR_JLTZ = 0x0e,
314 OPC1_16_SBC_JNE = 0x5e,
315 OPC1_16_SBR_JNE = 0x7e,
316 OPC1_16_SB_JNZ = 0xee,
317 OPC1_16_SBR_JNZ = 0xf6,
318 OPC1_16_SBR_JNZ_A = 0x7c,
319 OPC1_16_SBRN_JNZ_T = 0xae,
320 OPC1_16_SB_JZ = 0x6e,
321 OPC1_16_SBR_JZ = 0x76,
322 OPC1_16_SBR_JZ_A = 0xbc,
323 OPC1_16_SBRN_JZ_T = 0x2e,
324 OPC1_16_SC_LD_A = 0xd8,
325 OPC1_16_SLR_LD_A = 0xd4,
326 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
327 OPC1_16_SLRO_LD_A = 0xc8,
328 OPC1_16_SRO_LD_A = 0xcc,
329 OPC1_16_SLR_LD_BU = 0x14,
330 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
331 OPC1_16_SLRO_LD_BU = 0x08,
332 OPC1_16_SRO_LD_BU = 0x0c,
333 OPC1_16_SLR_LD_H = 0x94,
334 OPC1_16_SLR_LD_H_POSTINC = 0x84,
335 OPC1_16_SLRO_LD_H = 0x88,
336 OPC1_16_SRO_LD_H = 0x8c,
337 OPC1_16_SC_LD_W = 0x58,
338 OPC1_16_SLR_LD_W = 0x54,
339 OPC1_16_SLR_LD_W_POSTINC = 0x44,
340 OPC1_16_SLRO_LD_W = 0x48,
341 OPC1_16_SRO_LD_W = 0x4c,
342 OPC1_16_SBR_LOOP = 0xfc,
343 OPC1_16_SRC_LT = 0xfa,
344 OPC1_16_SRR_LT = 0x7a,
345 OPC1_16_SC_MOV = 0xda,
346 OPC1_16_SRC_MOV = 0x82,
347 OPC1_16_SRR_MOV = 0x02,
348 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
349 OPC1_16_SRC_MOV_A = 0xa0,
350 OPC1_16_SRR_MOV_A = 0x60,
351 OPC1_16_SRR_MOV_AA = 0x40,
352 OPC1_16_SRR_MOV_D = 0x80,
353 OPC1_16_SRR_MUL = 0xe2,
354 OPC1_16_SR_NOT = 0x46,
355 OPC1_16_SC_OR = 0x96,
356 OPC1_16_SRR_OR = 0xa6,
357 OPC1_16_SRC_SH = 0x06,
358 OPC1_16_SRC_SHA = 0x86,
359 OPC1_16_SC_ST_A = 0xf8,
360 OPC1_16_SRO_ST_A = 0xec,
361 OPC1_16_SSR_ST_A = 0xf4,
362 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
363 OPC1_16_SSRO_ST_A = 0xe8,
364 OPC1_16_SRO_ST_B = 0x2c,
365 OPC1_16_SSR_ST_B = 0x34,
366 OPC1_16_SSR_ST_B_POSTINC = 0x24,
367 OPC1_16_SSRO_ST_B = 0x28,
368 OPC1_16_SRO_ST_H = 0xac,
369 OPC1_16_SSR_ST_H = 0xb4,
370 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
371 OPC1_16_SSRO_ST_H = 0xa8,
372 OPC1_16_SC_ST_W = 0x78,
373 OPC1_16_SRO_ST_W = 0x6c,
374 OPC1_16_SSR_ST_W = 0x74,
375 OPC1_16_SSR_ST_W_POSTINC = 0x64,
376 OPC1_16_SSRO_ST_W = 0x68,
377 OPC1_16_SRR_SUB = 0xa2,
378 OPC1_16_SRR_SUB_A15B = 0x52,
379 OPC1_16_SRR_SUB_15AB = 0x5a,
380 OPC1_16_SC_SUB_A = 0x20,
381 OPC1_16_SRR_SUBS = 0x62,
382 OPC1_16_SRR_XOR = 0xc6,
383
384 };
385
386 /*
387 * SR Format
388 */
389 /* OPCM_16_SR_SYSTEM */
390 enum {
391
392 OPC2_16_SR_NOP = 0x00,
393 OPC2_16_SR_RET = 0x09,
394 OPC2_16_SR_RFE = 0x08,
395 OPC2_16_SR_DEBUG = 0x0a,
396 };
397 /* OPCM_16_SR_ACCU */
398 enum {
399 OPC2_16_SR_RSUB = 0x05,
400 OPC2_16_SR_SAT_B = 0x00,
401 OPC2_16_SR_SAT_BU = 0x01,
402 OPC2_16_SR_SAT_H = 0x02,
403 OPC2_16_SR_SAT_HU = 0x03,
404
405 };
406
407 /* 32-Bit */
408
409 enum {
410 /* ABS Format 1, M */
411 OPCM_32_ABS_LDW = 0x85,
412 OPCM_32_ABS_LDB = 0x05,
413 OPCM_32_ABS_LDMST_SWAP = 0xe5,
414 OPCM_32_ABS_LDST_CONTEXT = 0x15,
415 OPCM_32_ABS_STORE = 0xa5,
416 OPCM_32_ABS_STOREB_H = 0x25,
417 OPC1_32_ABS_STOREQ = 0x65,
418 OPC1_32_ABS_LD_Q = 0x45,
419 OPC1_32_ABS_LEA = 0xc5,
420 /* ABSB Format */
421 OPC1_32_ABSB_ST_T = 0xd5,
422 /* B Format */
423 OPC1_32_B_CALL = 0x6d,
424 OPC1_32_B_CALLA = 0xed,
425 OPC1_32_B_J = 0x1d,
426 OPC1_32_B_JA = 0x9d,
427 OPC1_32_B_JL = 0x5d,
428 OPC1_32_B_JLA = 0xdd,
429 /* Bit Format */
430 OPCM_32_BIT_ANDACC = 0x47,
431 OPCM_32_BIT_LOGICAL_T1 = 0x87,
432 OPCM_32_BIT_INSERT = 0x67,
433 OPCM_32_BIT_LOGICAL_T2 = 0x07,
434 OPCM_32_BIT_ORAND = 0xc7,
435 OPCM_32_BIT_SH_LOGIC1 = 0x27,
436 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
437 /* BO Format */
438 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
439 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
440 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
441 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
442 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
443 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
444 /* BOL Format */
445 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
446 OPC1_32_BOL_LD_W_LONFOFF = 0x19,
447 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
448 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
449 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
450 /* BRC Format */
451 OPCM_32_BRC_EQ_NEQ = 0xdf,
452 OPCM_32_BRC_GE = 0xff,
453 OPCM_32_BRC_JLT = 0xbf,
454 OPCM_32_BRC_JNE = 0x9f,
455 /* BRN Format */
456 OPCM_32_BRN_JTT = 0x6f,
457 /* BRR Format */
458 OPCM_32_BRR_EQ_NEQ = 0x5f,
459 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
460 OPCM_32_BRR_GE = 0x7f,
461 OPCM_32_BRR_JLT = 0x3f,
462 OPCM_32_BRR_JNE = 0x1f,
463 OPCM_32_BRR_JNZ = 0xbd,
464 OPCM_32_BRR_LOOP = 0xfd,
465 /* RC Format */
466 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
467 OPCM_32_RC_ACCUMULATOR = 0x8b,
468 OPCM_32_RC_SERVICEROUTINE = 0xad,
469 OPCM_32_RC_MUL = 0x53,
470 /* RCPW Format */
471 OPCM_32_RCPW_MASK_INSERT = 0xb7,
472 /* RCR Format */
473 OPCM_32_RCR_COND_SELECT = 0xab,
474 OPCM_32_RCR_MADD = 0x13,
475 OPCM_32_RCR_MSUB = 0x33,
476 /* RCRR Format */
477 OPC1_32_RCRR_INSERT = 0x97,
478 /* RCRW Format */
479 OPCM_32_RCRW_MASK_INSERT = 0xd7,
480 /* RLC Format */
481 OPC1_32_RLC_ADDI = 0x1b,
482 OPC1_32_RLC_ADDIH = 0x9b,
483 OPC1_32_RLC_ADDIH_A = 0x11,
484 OPC1_32_RLC_MFCR = 0x4d,
485 OPC1_32_RLC_MOV = 0x3b,
486 OPC1_32_RLC_MOV_U = 0xbb,
487 OPC1_32_RLC_MOV_H = 0x7b,
488 OPC1_32_RLC_MOVH_A = 0x91,
489 OPC1_32_RLC_MTCR = 0xcd,
490 /* RR Format */
491 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
492 OPCM_32_RR_ACCUMULATOR = 0x0b,
493 OPCM_32_RR_ADRESS = 0x01,
494 OPCM_32_RR_FLOAT = 0x4b,
495 OPCM_32_RR_IDIRECT = 0x2d,
496 /* RR1 Format */
497 OPCM_32_RR1_MUL = 0xb3,
498 OPCM_32_RR1_MULQ = 0x93,
499 /* RR2 Format */
500 OPCM_32_RR2_MUL = 0x73,
501 /* RRPW Format */
502 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
503 OPC1_32_RRPW_DEXTR = 0x77,
504 /* RRR Format */
505 OPCM_32_RRR_COND_SELECT = 0x2b,
506 OPCM_32_RRR_FLOAT = 0x6b,
507 /* RRR1 Format */
508 OPCM_32_RRR1_MADD = 0x83,
509 OPCM_32_RRR1_MADDQ_H = 0x43,
510 OPCM_32_RRR1_MADDSU_H = 0xc3,
511 OPCM_32_RRR1_MSUB_H = 0xa3,
512 OPCM_32_RRR1_MSUB_Q = 0x63,
513 OPCM_32_RRR1_MSUBADS_H = 0xe3,
514 /* RRR2 Format */
515 OPCM_32_RRR2_MADD = 0x03,
516 OPCM_32_RRR2_MSUB = 0x23,
517 /* RRRR Format */
518 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
519 /* RRRW Format */
520 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
521 /* SYS Format */
522 OPCM_32_SYS_INTERRUPTS = 0x0d,
523 OPC1_32_SYS_RSTV = 0x2f,
524 };
525
526
527
528 /*
529 * ABS Format
530 */
531
532 /* OPCM_32_ABS_LDW */
533 enum {
534
535 OPC2_32_ABS_LD_A = 0x02,
536 OPC2_32_ABS_LD_D = 0x01,
537 OPC2_32_ABS_LD_DA = 0x03,
538 OPC2_32_ABS_LD_W = 0x00,
539 };
540
541 /* OPCM_32_ABS_LDB */
542 enum {
543 OPC2_32_ABS_LD_B = 0x00,
544 OPC2_32_ABS_LD_BU = 0x01,
545 OPC2_32_ABS_LD_H = 0x02,
546 OPC2_32_ABS_LD_HU = 0x03,
547 };
548 /* OPCM_32_ABS_LDMST_SWAP */
549 enum {
550 OPC2_32_ABS_LDMST = 0x01,
551 OPC2_32_ABS_SWAP_W = 0x00,
552 };
553 /* OPCM_32_ABS_LDST_CONTEXT */
554 enum {
555 OPC2_32_ABS_LDLCX = 0x02,
556 OPC2_32_ABS_LDUCX = 0x03,
557 OPC2_32_ABS_STLCX = 0x00,
558 OPC2_32_ABS_STUCX = 0x01,
559 };
560 /* OPCM_32_ABS_STORE */
561 enum {
562 OPC2_32_ABS_ST_A = 0x02,
563 OPC2_32_ABS_ST_D = 0x01,
564 OPC2_32_ABS_ST_DA = 0x03,
565 OPC2_32_ABS_ST_W = 0x00,
566 };
567 /* OPCM_32_ABS_STOREB_H */
568 enum {
569 OPC2_32_ABS_ST_B = 0x00,
570 OPC2_32_ABS_ST_H = 0x02,
571 };
572 /*
573 * Bit Format
574 */
575 /* OPCM_32_BIT_ANDACC */
576 enum {
577 OPC2_32_BIT_AND_AND_T = 0x00,
578 OPC2_32_BIT_AND_ANDN_T = 0x03,
579 OPC2_32_BIT_AND_NOR_T = 0x02,
580 OPC2_32_BIT_AND_OR_T = 0x01,
581 };
582 /* OPCM_32_BIT_LOGICAL_T */
583 enum {
584 OPC2_32_BIT_AND_T = 0x00,
585 OPC2_32_BIT_ANDN_T = 0x03,
586 OPC2_32_BIT_NOR_T = 0x02,
587 OPC2_32_BIT_OR_T = 0x01,
588 };
589 /* OPCM_32_BIT_INSERT */
590 enum {
591 OPC2_32_BIT_INS_T = 0x00,
592 OPC2_32_BIT_INSN_T = 0x01,
593 };
594 /* OPCM_32_BIT_LOGICAL_T2 */
595 enum {
596 OPC2_32_BIT_NAND_T = 0x00,
597 OPC2_32_BIT_ORN_T = 0x01,
598 OPC2_32_BIT_XNOR_T = 0x02,
599 OPC2_32_BIT_XOR_T = 0x03,
600 };
601 /* OPCM_32_BIT_ORAND */
602 enum {
603 OPC2_32_BIT_OR_AND_T = 0x00,
604 OPC2_32_BIT_OR_ANDN_T = 0x03,
605 OPC2_32_BIT_OR_NOR_T = 0x02,
606 OPC2_32_BIT_OR_OR_T = 0x01,
607 };
608 /*OPCM_32_BIT_SH_LOGIC1 */
609 enum {
610 OPC2_32_BIT_SH_AND_T = 0x00,
611 OPC2_32_BIT_SH_ANDN_T = 0x03,
612 OPC2_32_BIT_SH_NOR_T = 0x02,
613 OPC2_32_BIT_SH_OR_T = 0x01,
614 };
615 /* OPCM_32_BIT_SH_LOGIC2 */
616 enum {
617 OPC2_32_BIT_SH_NAND_T = 0x00,
618 OPC2_32_BIT_SH_ORN_T = 0x01,
619 OPC2_32_BIT_SH_XNOR_T = 0x02,
620 OPC2_32_BIT_SH_XOR_T = 0x03,
621 };
622 /*
623 * BO Format
624 */
625 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
626 enum {
627 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
628 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
629 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
630 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
631 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
632 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
633 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
634 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
635 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
636 /* 1.3.1 only */
637 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
638 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
639 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
640 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
641 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
642 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
643 /* end 1.3.1 only */
644 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
645 OPC2_32_BO_ST_A_POSTINC = 0x06,
646 OPC2_32_BO_ST_A_PREINC = 0x16,
647 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
648 OPC2_32_BO_ST_B_POSTINC = 0x00,
649 OPC2_32_BO_ST_B_PREINC = 0x10,
650 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
651 OPC2_32_BO_ST_D_POSTINC = 0x05,
652 OPC2_32_BO_ST_D_PREINC = 0x15,
653 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
654 OPC2_32_BO_ST_DA_POSTINC = 0x07,
655 OPC2_32_BO_ST_DA_PREINC = 0x17,
656 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
657 OPC2_32_BO_ST_H_POSTINC = 0x02,
658 OPC2_32_BO_ST_H_PREINC = 0x12,
659 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
660 OPC2_32_BO_ST_Q_POSTINC = 0x08,
661 OPC2_32_BO_ST_Q_PREINC = 0x18,
662 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
663 OPC2_32_BO_ST_W_POSTINC = 0x04,
664 OPC2_32_BO_ST_W_PREINC = 0x14,
665 };
666 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
667 enum {
668 OPC2_32_BO_CACHEA_I_BR = 0x0e,
669 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
670 OPC2_32_BO_CACHEA_W_BR = 0x0c,
671 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
672 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
673 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
674 OPC2_32_BO_ST_A_BR = 0x06,
675 OPC2_32_BO_ST_A_CIRC = 0x16,
676 OPC2_32_BO_ST_B_BR = 0x00,
677 OPC2_32_BO_ST_B_CIRC = 0x10,
678 OPC2_32_BO_ST_D_BR = 0x05,
679 OPC2_32_BO_ST_D_CIRC = 0x15,
680 OPC2_32_BO_ST_DA_BR = 0x07,
681 OPC2_32_BO_ST_DA_CIRC = 0x17,
682 OPC2_32_BO_ST_H_BR = 0x02,
683 OPC2_32_BO_ST_H_CIRC = 0x12,
684 OPC2_32_BO_ST_Q_BR = 0x08,
685 OPC2_32_BO_ST_Q_CIRC = 0x18,
686 OPC2_32_BO_ST_W_BR = 0x04,
687 OPC2_32_BO_ST_W_CIRC = 0x14,
688 };
689 /* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
690 enum {
691 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
692 OPC2_32_BO_LD_A_POSTINC = 0x06,
693 OPC2_32_BO_LD_A_PREINC = 0x16,
694 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
695 OPC2_32_BO_LD_B_POSTINC = 0x00,
696 OPC2_32_BO_LD_B_PREINC = 0x10,
697 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
698 OPC2_32_BO_LD_BU_POSTINC = 0x01,
699 OPC2_32_BO_LD_BU_PREINC = 0x11,
700 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
701 OPC2_32_BO_LD_D_POSTINC = 0x05,
702 OPC2_32_BO_LD_D_PREINC = 0x15,
703 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
704 OPC2_32_BO_LD_DA_POSTINC = 0x07,
705 OPC2_32_BO_LD_DA_PREINC = 0x17,
706 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
707 OPC2_32_BO_LD_H_POSTINC = 0x02,
708 OPC2_32_BO_LD_H_PREINC = 0x12,
709 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
710 OPC2_32_BO_LD_HU_POSTINC = 0x03,
711 OPC2_32_BO_LD_HU_PREINC = 0x13,
712 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
713 OPC2_32_BO_LD_Q_POSTINC = 0x08,
714 OPC2_32_BO_LD_Q_PREINC = 0x18,
715 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
716 OPC2_32_BO_LD_W_POSTINC = 0x04,
717 OPC2_32_BO_LD_W_PREINC = 0x14,
718 };
719 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
720 enum {
721 OPC2_32_BO_LD_A_BR = 0x06,
722 OPC2_32_BO_LD_A_CIRC = 0x16,
723 OPC2_32_BO_LD_B_BR = 0x00,
724 OPC2_32_BO_LD_B_CIRC = 0x10,
725 OPC2_32_BO_LD_BU_BR = 0x01,
726 OPC2_32_BO_LD_BU_CIRC = 0x11,
727 OPC2_32_BO_LD_D_BR = 0x05,
728 OPC2_32_BO_LD_D_CIRC = 0x15,
729 OPC2_32_BO_LD_DA_BR = 0x07,
730 OPC2_32_BO_LD_DA_CIRC = 0x17,
731 OPC2_32_BO_LD_H_BR = 0x02,
732 OPC2_32_BO_LD_H_CIRC = 0x12,
733 OPC2_32_BO_LD_HU_BR = 0x03,
734 OPC2_32_BO_LD_HU_CIRC = 0x13,
735 OPC2_32_BO_LD_Q_BR = 0x08,
736 OPC2_32_BO_LD_Q_CIRC = 0x18,
737 OPC2_32_BO_LD_W_BR = 0x04,
738 OPC2_32_BO_LD_W_CIRC = 0x14,
739 };
740 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
741 enum {
742 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
743 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
744 OPC2_32_BO_LDMST_POSTINC = 0x01,
745 OPC2_32_BO_LDMST_PREINC = 0x11,
746 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
747 OPC2_32_BO_LEA_SHORTOFF = 0x28,
748 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
749 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
750 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
751 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
752 OPC2_32_BO_SWAP_W_PREINC = 0x10,
753 };
754 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
755 enum {
756 OPC2_32_BO_LDMST_BR = 0x01,
757 OPC2_32_BO_LDMST_CIRC = 0x11,
758 OPC2_32_BO_SWAP_W_BR = 0x00,
759 OPC2_32_BO_SWAP_W_CIRC = 0x10,
760 };
761 /*
762 * BRC Format
763 */
764 /*OPCM_32_BRC_EQ_NEQ */
765 enum {
766 OPC2_32_BRC_JEQ = 0x00,
767 OPC2_32_BRC_JNE = 0x01,
768 };
769 /* OPCM_32_BRC_GE */
770 enum {
771 OP2_32_BRC_JGE = 0x00,
772 OPC_32_BRC_JGE_U = 0x01,
773 };
774 /* OPCM_32_BRC_JLT */
775 enum {
776 OPC2_32_BRC_JLT = 0x00,
777 OPC2_32_BRC_JLT_U = 0x01,
778 };
779 /* OPCM_32_BRC_JNE */
780 enum {
781 OPC2_32_BRC_JNED = 0x01,
782 OPC2_32_BRC_JNEI = 0x00,
783 };
784 /*
785 * BRN Format
786 */
787 /* OPCM_32_BRN_JTT */
788 enum {
789 OPC2_32_BRN_JNZ_T = 0x01,
790 OPC2_32_BRN_JZ_T = 0x00,
791 };
792 /*
793 * BRR Format
794 */
795 /* OPCM_32_BRR_EQ_NEQ */
796 enum {
797 OPC2_32_BRR_JEQ = 0x00,
798 OPC2_32_BRR_JNE = 0x01,
799 };
800 /* OPCM_32_BRR_ADDR_EQ_NEQ */
801 enum {
802 OPC2_32_BRR_JEQ_A = 0x00,
803 OPC2_32_BRR_JNE_A = 0x01,
804 };
805 /*OPCM_32_BRR_GE */
806 enum {
807 OPC2_32_BRR_JGE = 0x00,
808 OPC2_32_BRR_JGE_U = 0x01,
809 };
810 /* OPCM_32_BRR_JLT */
811 enum {
812 OPC2_32_BRR_JLT = 0x00,
813 OPC2_32_BRR_JLT_U = 0x01,
814 };
815 /* OPCM_32_BRR_JNE */
816 enum {
817 OPC2_32_BRR_JNED = 0x01,
818 OPC2_32_BRR_JNEI = 0x00,
819 };
820 /* OPCM_32_BRR_JNZ */
821 enum {
822 OPC2_32_BRR_JNZ_A = 0x01,
823 OPC2_32_BRR_JZ_A = 0x00,
824 };
825 /* OPCM_32_BRR_LOOP */
826 enum {
827 OPC2_32_BRR_LOOP = 0x00,
828 OPC2_32_BRR_LOOPU = 0x01,
829 };
830 /*
831 * RC Format
832 */
833 /* OPCM_32_RC_LOGICAL_SHIFT */
834 enum {
835 OPC2_32_RC_AND = 0x08,
836 OPC2_32_RC_ANDN = 0x0e,
837 OPC2_32_RC_NAND = 0x09,
838 OPC2_32_RC_NOR = 0x0b,
839 OPC2_32_RC_OR = 0x0a,
840 OPC2_32_RC_ORN = 0x0f,
841 OPC2_32_RC_SH = 0x00,
842 OPC2_32_RC_SH_H = 0x40,
843 OPC2_32_RC_SHA = 0x01,
844 OPC2_32_RC_SHA_H = 0x41,
845 OPC2_32_RC_SHAS = 0x02,
846 OPC2_32_RC_XNOR = 0x0d,
847 OPC2_32_RC_XOR = 0x0c,
848 };
849 /* OPCM_32_RC_ACCUMULATOR */
850 enum {
851 OPC2_32_RC_ABSDIF = 0x0e,
852 OPC2_32_RC_ABSDIFS = 0x0f,
853 OPC2_32_RC_ADD = 0x00,
854 OPC2_32_RC_ADDC = 0x05,
855 OPC2_32_RC_ADDS = 0x02,
856 OPC2_32_RC_ADDS_U = 0x03,
857 OPC2_32_RC_ADDX = 0x04,
858 OPC2_32_RC_AND_EQ = 0x20,
859 OPC2_32_RC_AND_GE = 0x24,
860 OPC2_32_RC_AND_GE_U = 0x25,
861 OPC2_32_RC_AND_LT = 0x22,
862 OPC2_32_RC_AND_LT_U = 0x23,
863 OPC2_32_RC_AND_NE = 0x21,
864 OPC2_32_RC_EQ = 0x10,
865 OPC2_32_RC_EQANY_B = 0x56,
866 OPC2_32_RC_EQANY_H = 0x76,
867 OPC2_32_RC_GE = 0x14,
868 OPC2_32_RC_GE_U = 0x15,
869 OPC2_32_RC_LT = 0x12,
870 OPC2_32_RC_LT_U = 0x13,
871 OPC2_32_RC_MAX = 0x1a,
872 OPC2_32_RC_MAX_U = 0x1b,
873 OPC2_32_RC_MIN = 0x18,
874 OPC2_32_RC_MIN_U = 0x19,
875 OPC2_32_RC_NE = 0x11,
876 OPC2_32_RC_OR_EQ = 0x27,
877 OPC2_32_RC_OR_GE = 0x2b,
878 OPC2_32_RC_OR_GE_U = 0x2c,
879 OPC2_32_RC_OR_LT = 0x29,
880 OPC2_32_RC_OR_LT_U = 0x2a,
881 OPC2_32_RC_OR_NE = 0x28,
882 OPC2_32_RC_RSUB = 0x08,
883 OPC2_32_RC_RSUBS = 0x0a,
884 OPC2_32_RC_RSUBS_U = 0x0b,
885 OPC2_32_RC_SH_EQ = 0x37,
886 OPC2_32_RC_SH_GE = 0x3b,
887 OPC2_32_RC_SH_GE_U = 0x3c,
888 OPC2_32_RC_SH_LT = 0x39,
889 OPC2_32_RC_SH_LT_U = 0x3a,
890 OPC2_32_RC_SH_NE = 0x38,
891 OPC2_32_RC_XOR_EQ = 0x2f,
892 OPC2_32_RC_XOR_GE = 0x33,
893 OPC2_32_RC_XOR_GE_U = 0x34,
894 OPC2_32_RC_XOR_LT = 0x31,
895 OPC2_32_RC_XOR_LT_U = 0x32,
896 OPC2_32_RC_XOR_NE = 0x30,
897 };
898 /* OPCM_32_RC_SERVICEROUTINE */
899 enum {
900 OPC2_32_RC_BISR = 0x00,
901 OPC2_32_RC_SYSCALL = 0x04,
902 };
903 /* OPCM_32_RC_MUL */
904 enum {
905 OPC2_32_RC_MUL_32 = 0x01,
906 OPC2_32_RC_MUL_64 = 0x03,
907 OPC2_32_RC_MULS_32 = 0x05,
908 OPC2_32_RC_MUL_U_64 = 0x02,
909 OPC2_32_RC_MULS_U_32 = 0x04,
910 };
911 /*
912 * RCPW Format
913 */
914 /* OPCM_32_RCPW_MASK_INSERT */
915 enum {
916 OPC2_32_RCPW_IMASK = 0x01,
917 OPC2_32_RCPW_INSERT = 0x00,
918 };
919 /*
920 * RCR Format
921 */
922 /* OPCM_32_RCR_COND_SELECT */
923 enum {
924 OPC2_32_RCR_CADD = 0x00,
925 OPC2_32_RCR_CADDN = 0x01,
926 OPC2_32_RCR_SEL = 0x04,
927 OPC2_32_RCR_SELN = 0x05,
928 };
929 /* OPCM_32_RCR_MADD */
930 enum {
931 OPC2_32_RCR_MADD_32 = 0x01,
932 OPC2_32_RCR_MADD_64 = 0x03,
933 OPC2_32_RCR_MADDS_32 = 0x05,
934 OPC2_32_RCR_MADDS_64 = 0x07,
935 OPC2_32_RCR_MADD_U_64 = 0x02,
936 OPC2_32_RCR_MADDS_U_32 = 0x04,
937 OPC2_32_RCR_MADDS_U_64 = 0x06,
938 };
939 /* OPCM_32_RCR_MSUB */
940 enum {
941 OPC2_32_RCR_MSUB_32 = 0x01,
942 OPC2_32_RCR_MSUB_64 = 0x03,
943 OPC2_32_RCR_MSUBS_32 = 0x05,
944 OPC2_32_RCR_MSUBS_64 = 0x07,
945 OPC2_32_RCR_MSUB_U_32 = 0x02,
946 OPC2_32_RCR_MSUBS_U_32 = 0x04,
947 OPC2_32_RCR_MSUBS_U_64 = 0x06,
948 };
949 /*
950 * RCRW Format
951 */
952 /* OPCM_32_RCRW_MASK_INSERT */
953 enum {
954 OPC2_32_RCRW_IMASK = 0x01,
955 OPC2_32_RCRW_INSERT = 0x00,
956 };
957
958 /*
959 * RR Format
960 */
961 /* OPCM_32_RR_LOGICAL_SHIFT */
962 enum {
963 OPC2_32_RR_AND = 0x08,
964 OPC2_32_RR_ANDN = 0x0e,
965 OPC2_32_RR_CLO = 0x1c,
966 OPC2_32_RR_CLO_H = 0x7d,
967 OPC2_32_RR_CLS = 0x1d,
968 OPC2_32_RR_CLS_H = 0x7e,
969 OPC2_32_RR_CLZ = 0x1b,
970 OPC2_32_RR_CLZ_H = 0x7c,
971 OPC2_32_RR_NAND = 0x09,
972 OPC2_32_RR_NOR = 0x0b,
973 OPC2_32_RR_OR = 0x0a,
974 OPC2_32_RR_ORN = 0x0f,
975 OPC2_32_RR_SH = 0x00,
976 OPC2_32_RR_SH_H = 0x40,
977 OPC2_32_RR_SHA = 0x01,
978 OPC2_32_RR_SHA_H = 0x41,
979 OPC2_32_RR_SHAS = 0x02,
980 OPC2_32_RR_XNOR = 0x0d,
981 OPC2_32_RR_XOR = 0x0c,
982 };
983 /* OPCM_32_RR_ACCUMULATOR */
984 enum {
985 OPC2_32_RR_ABS = 0x1c,
986 OPC2_32_RR_ABS_B = 0x5c,
987 OPC2_32_RR_ABS_H = 0x7c,
988 OPC2_32_RR_ABSDIF = 0x0e,
989 OPC2_32_RR_ABSDIF_B = 0x4e,
990 OPC2_32_RR_ABSDIF_H = 0x6e,
991 OPC2_32_RR_ABSDIFS = 0x0f,
992 OPC2_32_RR_ABSDIFS_H = 0x6f,
993 OPC2_32_RR_ABSS = 0x1d,
994 OPC2_32_RR_ABSS_H = 0x7d,
995 OPC2_32_RR_ADD = 0x00,
996 OPC2_32_RR_ADD_B = 0x40,
997 OPC2_32_RR_ADD_H = 0x60,
998 OPC2_32_RR_ADDC = 0x05,
999 OPC2_32_RR_ADDS = 0x02,
1000 OPC2_32_RR_ADDS_H = 0x62,
1001 OPC2_32_RR_ADDS_HU = 0x63,
1002 OPC2_32_RR_ADDS_U = 0x03,
1003 OPC2_32_RR_ADDX = 0x04,
1004 OPC2_32_RR_AND_EQ = 0x20,
1005 OPC2_32_RR_AND_GE = 0x24,
1006 OPC2_32_RR_AND_GE_U = 0x25,
1007 OPC2_32_RR_AND_LT = 0x22,
1008 OPC2_32_RR_AND_LT_U = 0x23,
1009 OPC2_32_RR_AND_NE = 0x21,
1010 OPC2_32_RR_EQ = 0x10,
1011 OPC2_32_RR_EQ_B = 0x50,
1012 OPC2_32_RR_EQ_H = 0x70,
1013 OPC2_32_RR_EQ_W = 0x90,
1014 OPC2_32_RR_EQANY_B = 0x56,
1015 OPC2_32_RR_EQANY_H = 0x76,
1016 OPC2_32_RR_GE = 0x14,
1017 OPC2_32_RR_GE_U = 0x15,
1018 OPC2_32_RR_LT = 0x12,
1019 OPC2_32_RR_LT_U = 0x13,
1020 OPC2_32_RR_LT_B = 0x52,
1021 OPC2_32_RR_LT_BU = 0x53,
1022 OPC2_32_RR_LT_H = 0x72,
1023 OPC2_32_RR_LT_HU = 0x73,
1024 OPC2_32_RR_LT_W = 0x92,
1025 OPC2_32_RR_LT_WU = 0x93,
1026 OPC2_32_RR_MAX = 0x1a,
1027 OPC2_32_RR_MAX_U = 0x1b,
1028 OPC2_32_RR_MAX_B = 0x5a,
1029 OPC2_32_RR_MAX_BU = 0x5b,
1030 OPC2_32_RR_MAX_H = 0x7a,
1031 OPC2_32_RR_MAX_HU = 0x7b,
1032 OPC2_32_RR_MIN = 0x19,
1033 OPC2_32_RR_MIN_U = 0x18,
1034 OPC2_32_RR_MIN_B = 0x58,
1035 OPC2_32_RR_MIN_BU = 0x59,
1036 OPC2_32_RR_MIN_H = 0x78,
1037 OPC2_32_RR_MIN_HU = 0x79,
1038 OPC2_32_RR_MOV = 0x1f,
1039 OPC2_32_RR_NE = 0x11,
1040 OPC2_32_RR_OR_EQ = 0x27,
1041 OPC2_32_RR_OR_GE = 0x2b,
1042 OPC2_32_RR_OR_GE_U = 0x2c,
1043 OPC2_32_RR_OR_LT = 0x29,
1044 OPC2_32_RR_OR_LT_U = 0x2a,
1045 OPC2_32_RR_OR_NE = 0x28,
1046 OPC2_32_RR_SAT_B = 0x5e,
1047 OPC2_32_RR_SAT_BU = 0x5f,
1048 OPC2_32_RR_SAT_H = 0x7e,
1049 OPC2_32_RR_SAT_HU = 0x7f,
1050 OPC2_32_RR_SH_EQ = 0x37,
1051 OPC2_32_RR_SH_GE = 0x3b,
1052 OPC2_32_RR_SH_GE_U = 0x3c,
1053 OPC2_32_RR_SH_LT = 0x39,
1054 OPC2_32_RR_SH_LT_U = 0x3a,
1055 OPC2_32_RR_SH_NE = 0x38,
1056 OPC2_32_RR_SUB = 0x08,
1057 OPC2_32_RR_SUB_B = 0x48,
1058 OPC2_32_RR_SUB_H = 0x68,
1059 OPC2_32_RR_SUBC = 0x0d,
1060 OPC2_32_RR_SUBS = 0x0a,
1061 OPC2_32_RR_SUBS_U = 0x0b,
1062 OPC2_32_RR_SUBS_H = 0x6a,
1063 OPC2_32_RR_SUBS_HU = 0x6b,
1064 OPC2_32_RR_SUBX = 0x0c,
1065 OPC2_32_RR_XOR_EQ = 0x2f,
1066 OPC2_32_RR_XOR_GE = 0x33,
1067 OPC2_32_RR_XOR_GE_U = 0x34,
1068 OPC2_32_RR_XOR_LT = 0x31,
1069 OPC2_32_RR_XOR_LT_U = 0x32,
1070 OPC2_32_RR_XOR_NE = 0x30,
1071 };
1072 /* OPCM_32_RR_ADRESS */
1073 enum {
1074 OPC2_32_RR_ADD_A = 0x01,
1075 OPC2_32_RR_ADDSC_A = 0x60,
1076 OPC2_32_RR_ADDSC_AT = 0x62,
1077 OPC2_32_RR_EQ_A = 0x40,
1078 OPC2_32_RR_EQZ = 0x48,
1079 OPC2_32_RR_GE_A = 0x43,
1080 OPC2_32_RR_LT_A = 0x42,
1081 OPC2_32_RR_MOV_A = 0x63,
1082 OPC2_32_RR_MOV_AA = 0x00,
1083 OPC2_32_RR_MOV_D = 0x4c,
1084 OPC2_32_RR_NE_A = 0x41,
1085 OPC2_32_RR_NEZ_A = 0x49,
1086 OPC2_32_RR_SUB_A = 0x02,
1087 };
1088 /* OPCM_32_RR_FLOAT */
1089 enum {
1090 OPC2_32_RR_BMERGE = 0x01,
1091 OPC2_32_RR_BSPLIT = 0x09,
1092 OPC2_32_RR_DVINIT_B = 0x5a,
1093 OPC2_32_RR_DVINIT_BU = 0x4a,
1094 OPC2_32_RR_DVINIT_H = 0x3a,
1095 OPC2_32_RR_DVINIT_HU = 0x2a,
1096 OPC2_32_RR_DVINIT = 0x1a,
1097 OPC2_32_RR_DVINIT_U = 0x0a,
1098 OPC2_32_RR_PARITY = 0x02,
1099 OPC2_32_RR_UNPACK = 0x08,
1100 };
1101 /* OPCM_32_RR_IDIRECT */
1102 enum {
1103 OPC2_32_RR_JI = 0x03,
1104 OPC2_32_RR_JLI = 0x02,
1105 OPC2_32_RR_CALLI = 0x00,
1106 };
1107 /*
1108 * RR1 Format
1109 */
1110 /* OPCM_32_RR1_MUL */
1111 enum {
1112 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1113 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1114 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1115 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1116 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1117 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1118 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1119 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1120 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1121 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1122 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1123 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1124 };
1125 /* OPCM_32_RR1_MULQ */
1126 enum {
1127 OPC2_32_RR1_MUL_Q_32 = 0x02,
1128 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1129 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1130 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1131 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1132 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1133 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1134 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1135 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1136 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1137 };
1138 /*
1139 * RR2 Format
1140 */
1141 /* OPCM_32_RR2_MUL */
1142 enum {
1143 OPC2_32_RR2_MUL_32 = 0x0a,
1144 OPC2_32_RR2_MUL_64 = 0x6a,
1145 OPC2_32_RR2_MULS_32 = 0x8a,
1146 OPC2_32_RR2_MUL_U_64 = 0x68,
1147 OPC2_32_RR2_MULS_U_32 = 0x88,
1148 };
1149 /*
1150 * RRPW Format
1151 */
1152 /* OPCM_32_RRPW_EXTRACT_INSERT */
1153 enum {
1154
1155 OPC2_32_RRPW_EXTR = 0x02,
1156 OPC2_32_RRPW_EXTR_U = 0x03,
1157 OPC2_32_RRPW_IMASK = 0x01,
1158 OPC2_32_RRPW_INSERT = 0x00,
1159 };
1160 /*
1161 * RRR Format
1162 */
1163 /* OPCM_32_RRR_COND_SELECT */
1164 enum {
1165 OPC2_32_RRR_CADD = 0x00,
1166 OPC2_32_RRR_CADDN = 0x01,
1167 OPC2_32_RRR_CSUB = 0x02,
1168 OPC2_32_RRR_CSUBN = 0x03,
1169 OPC2_32_RRR_SEL = 0x04,
1170 OPC2_32_RRR_SELN = 0x05,
1171 };
1172 /* OPCM_32_RRR_FLOAT */
1173 enum {
1174 OPC2_32_RRR_DVADJ = 0x0d,
1175 OPC2_32_RRR_DVSTEP = 0x0f,
1176 OPC2_32_RRR_DVSTEP_U = 0x0e,
1177 OPC2_32_RRR_IXMAX = 0x0a,
1178 OPC2_32_RRR_IXMAX_U = 0x0b,
1179 OPC2_32_RRR_IXMIN = 0x08,
1180 OPC2_32_RRR_IXMIN_U = 0x09,
1181 OPC2_32_RRR_PACK = 0x00,
1182 };
1183 /*
1184 * RRR1 Format
1185 */
1186 /* OPCM_32_RRR1_MADD */
1187 enum {
1188 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1189 OPC2_32_RRR1_MADD_H_LU = 0x19,
1190 OPC2_32_RRR1_MADD_H_UL = 0x18,
1191 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1192 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1193 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1194 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1195 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1196 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1197 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1198 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1199 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1200 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1201 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1202 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1203 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1204 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1205 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1206 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1207 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1208 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1209 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1210 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1211 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1212 };
1213 /* OPCM_32_RRR1_MADDQ_H */
1214 enum {
1215 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1216 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1217 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1218 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1219 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1220 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1221 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1222 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1223 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1224 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1225 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1226 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1227 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1228 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1229 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1230 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1231 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1232 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1233 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1234 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1235 OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
1236 OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
1237 OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
1238 OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
1239 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1240 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1241 };
1242 /* OPCM_32_RRR1_MADDSU_H */
1243 enum {
1244 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1245 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1246 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1247 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1248 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1249 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1250 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1251 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1252 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1253 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1254 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1255 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1256 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1257 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1258 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1259 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1260 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1261 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1262 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1263 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1264 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1265 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1266 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1267 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1268 };
1269 /* OPCM_32_RRR1_MSUB_H */
1270 enum {
1271 OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
1272 OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
1273 OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
1274 OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
1275 OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
1276 OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
1277 OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
1278 OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
1279 OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
1280 OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
1281 OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
1282 OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
1283 OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
1284 OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
1285 OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
1286 OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
1287 OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
1288 OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
1289 OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
1290 OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
1291 OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
1292 OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
1293 OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
1294 OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
1295 };
1296 /* OPCM_32_RRR1_MSUB_Q */
1297 enum {
1298 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1299 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1300 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1301 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1302 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1303 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1304 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1305 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1306 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1307 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1308 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1309 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1310 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1311 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1312 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1313 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1314 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1315 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1316 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1317 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1318 OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
1319 OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
1320 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1321 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1322 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1323 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1324 };
1325 /* OPCM_32_RRR1_MSUBADS_H */
1326 enum {
1327 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1328 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1329 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1330 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1331 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1332 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1333 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1334 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1335 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1336 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1337 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1338 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1339 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1340 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1341 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1342 OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
1343 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1344 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1345 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1346 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1347 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1348 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1349 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1350 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1351 };
1352 /*
1353 * RRR2 Format
1354 */
1355 /* OPCM_32_RRR2_MADD */
1356 enum {
1357 OPC2_32_RRR2_MADD_32 = 0x0a,
1358 OPC2_32_RRR2_MADD_64 = 0x6a,
1359 OPC2_32_RRR2_MADDS_32 = 0x8a,
1360 OPC2_32_RRR2_MADDS_64 = 0xea,
1361 OPC2_32_RRR2_MADD_U_32 = 0x68,
1362 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1363 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1364 };
1365 /* OPCM_32_RRR2_MSUB */
1366 enum {
1367 OPC2_32_RRR2_MSUB_32 = 0x0a,
1368 OPC2_32_RRR2_MSUB_64 = 0x6a,
1369 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1370 OPC2_32_RRR2_MSUBS_64 = 0xea,
1371 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1372 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1373 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1374 };
1375 /*
1376 * RRRR Format
1377 */
1378 /* OPCM_32_RRRR_EXTRACT_INSERT */
1379 enum {
1380 OPC2_32_RRRR_DEXTR = 0x04,
1381 OPC2_32_RRRR_EXTR = 0x02,
1382 OPC2_32_RRRR_EXTR_U = 0x03,
1383 OPC2_32_RRRR_INSERT = 0x00,
1384 };
1385 /*
1386 * RRRW Format
1387 */
1388 /* OPCM_32_RRRW_EXTRACT_INSERT */
1389 enum {
1390 OPC2_32_RRRW_EXTR = 0x02,
1391 OPC2_32_RRRW_EXTR_U = 0x03,
1392 OPC2_32_RRRW_IMASK = 0x01,
1393 OPC2_32_RRRW_INSERT = 0x00,
1394 };
1395 /*
1396 * SYS Format
1397 */
1398 /* OPCM_32_SYS_INTERRUPTS */
1399 enum {
1400 OPC2_32_SYS_DEBUG = 0x04,
1401 OPC2_32_SYS_DISABLE = 0x0d,
1402 OPC2_32_SYS_DSYNC = 0x12,
1403 OPC2_32_SYS_ENABLE = 0x0c,
1404 OPC2_32_SYS_ISYNC = 0x13,
1405 OPC2_32_SYS_NOP = 0x00,
1406 OPC2_32_SYS_RET = 0x06,
1407 OPC2_32_SYS_RFE = 0x07,
1408 OPC2_32_SYS_RFM = 0x05,
1409 OPC2_32_SYS_RSLCX = 0x09,
1410 OPC2_32_SYS_SVLCX = 0x08,
1411 OPC2_32_SYS_TRAPSV = 0x15,
1412 OPC2_32_SYS_TRAPV = 0x14,
1413 };
AR7 emulation for QEMU