hw/riscv: Update comment for qtest check in riscv_find_firmware()
[qemu/ar7.git] / bsd-user / arm / target_arch_elf.h
blob935bce347fc244b7cfe27c902e2a1b5b8b6a0534
1 /*
2 * arm ELF definitions
4 * Copyright (c) 2013 Stacey D. Son
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
20 #ifndef TARGET_ARCH_ELF_H
21 #define TARGET_ARCH_ELF_H
23 #define ELF_START_MMAP 0x80000000
24 #define ELF_ET_DYN_LOAD_ADDR 0x500000
26 #define elf_check_arch(x) ((x) == EM_ARM)
28 #define ELF_CLASS ELFCLASS32
29 #define ELF_DATA ELFDATA2LSB
30 #define ELF_ARCH EM_ARM
32 #define USE_ELF_CORE_DUMP
33 #define ELF_EXEC_PAGESIZE 4096
35 #define ELF_HWCAP get_elf_hwcap()
36 #define ELF_HWCAP2 get_elf_hwcap2()
38 #define GET_FEATURE(feat, hwcap) \
39 do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
41 #define GET_FEATURE_ID(feat, hwcap) \
42 do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0)
44 enum {
45 ARM_HWCAP_ARM_SWP = 1 << 0,
46 ARM_HWCAP_ARM_HALF = 1 << 1,
47 ARM_HWCAP_ARM_THUMB = 1 << 2,
48 ARM_HWCAP_ARM_26BIT = 1 << 3,
49 ARM_HWCAP_ARM_FAST_MULT = 1 << 4,
50 ARM_HWCAP_ARM_FPA = 1 << 5,
51 ARM_HWCAP_ARM_VFP = 1 << 6,
52 ARM_HWCAP_ARM_EDSP = 1 << 7,
53 ARM_HWCAP_ARM_JAVA = 1 << 8,
54 ARM_HWCAP_ARM_IWMMXT = 1 << 9,
55 ARM_HWCAP_ARM_CRUNCH = 1 << 10,
56 ARM_HWCAP_ARM_THUMBEE = 1 << 11,
57 ARM_HWCAP_ARM_NEON = 1 << 12,
58 ARM_HWCAP_ARM_VFPv3 = 1 << 13,
59 ARM_HWCAP_ARM_VFPv3D16 = 1 << 14,
60 ARM_HWCAP_ARM_TLS = 1 << 15,
61 ARM_HWCAP_ARM_VFPv4 = 1 << 16,
62 ARM_HWCAP_ARM_IDIVA = 1 << 17,
63 ARM_HWCAP_ARM_IDIVT = 1 << 18,
64 ARM_HWCAP_ARM_VFPD32 = 1 << 19,
65 ARM_HWCAP_ARM_LPAE = 1 << 20,
66 ARM_HWCAP_ARM_EVTSTRM = 1 << 21,
69 enum {
70 ARM_HWCAP2_ARM_AES = 1 << 0,
71 ARM_HWCAP2_ARM_PMULL = 1 << 1,
72 ARM_HWCAP2_ARM_SHA1 = 1 << 2,
73 ARM_HWCAP2_ARM_SHA2 = 1 << 3,
74 ARM_HWCAP2_ARM_CRC32 = 1 << 4,
77 static uint32_t get_elf_hwcap(void)
79 ARMCPU *cpu = ARM_CPU(thread_cpu);
80 uint32_t hwcaps = 0;
82 hwcaps |= ARM_HWCAP_ARM_SWP;
83 hwcaps |= ARM_HWCAP_ARM_HALF;
84 hwcaps |= ARM_HWCAP_ARM_THUMB;
85 hwcaps |= ARM_HWCAP_ARM_FAST_MULT;
87 /* probe for the extra features */
88 /* EDSP is in v5TE and above */
89 GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP);
90 GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT);
91 GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE);
92 GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON);
93 GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS);
94 GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE);
95 GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA);
96 GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT);
97 GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP);
99 if (cpu_isar_feature(aa32_fpsp_v3, cpu) ||
100 cpu_isar_feature(aa32_fpdp_v3, cpu)) {
101 hwcaps |= ARM_HWCAP_ARM_VFPv3;
102 if (cpu_isar_feature(aa32_simd_r32, cpu)) {
103 hwcaps |= ARM_HWCAP_ARM_VFPD32;
104 } else {
105 hwcaps |= ARM_HWCAP_ARM_VFPv3D16;
108 GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4);
110 return hwcaps;
113 static uint32_t get_elf_hwcap2(void)
115 ARMCPU *cpu = ARM_CPU(thread_cpu);
116 uint32_t hwcaps = 0;
118 GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES);
119 GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL);
120 GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1);
121 GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2);
122 GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32);
123 return hwcaps;
126 #undef GET_FEATURE
127 #undef GET_FEATURE_ID
129 #endif /* TARGET_ARCH_ELF_H */