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target-i386/ops_sse.h: Use MMX_Q macro
[qemu/ar7.git] / target-tilegx / translate.c
blob354f25a52bf040f65d141ad555677dc961e820fb
1 /*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "exec/cpu_ldst.h"
26 #include "linux-user/syscall_defs.h"
27
28 #include "opcode_tilegx.h"
29 #include "spr_def_64.h"
30
31 #define FMT64X "%016" PRIx64
32
33 static TCGv_ptr cpu_env;
34 static TCGv cpu_pc;
35 static TCGv cpu_regs[TILEGX_R_COUNT];
36
37 static const char * const reg_names[64] = {
38 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
39 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
40 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
41 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
42 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
43 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
44 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr",
45 "sn", "idn0", "idn1", "udn0", "udn1", "udn2", "udn2", "zero"
46 };
47
48 /* Modified registers are cached in temporaries until the end of the bundle. */
49 typedef struct {
50 unsigned reg;
51 TCGv val;
52 } DisasContextTemp;
53
54 #define MAX_WRITEBACK 4
55
56 /* This is the state at translation time. */
57 typedef struct {
58 uint64_t pc; /* Current pc */
59
60 TCGv zero; /* For zero register */
61
62 DisasContextTemp wb[MAX_WRITEBACK];
63 int num_wb;
64 int mmuidx;
65 bool exit_tb;
66 TileExcp atomic_excp;
67
68 struct {
69 TCGCond cond; /* branch condition */
70 TCGv dest; /* branch destination */
71 TCGv val1; /* value to be compared against zero, for cond */
72 } jmp; /* Jump object, only once in each TB block */
73 } DisasContext;
74
75 #include "exec/gen-icount.h"
76
77 /* Differentiate the various pipe encodings. */
78 #define TY_X0 0
79 #define TY_X1 1
80 #define TY_Y0 2
81 #define TY_Y1 3
82
83 /* Remerge the base opcode and extension fields for switching.
84 The X opcode fields are 3 bits; Y0/Y1 opcode fields are 4 bits;
85 Y2 opcode field is 2 bits. */
86 #define OE(OP, EXT, XY) (TY_##XY + OP * 4 + EXT * 64)
87
88 /* Similar, but for Y2 only. */
89 #define OEY2(OP, MODE) (OP + MODE * 4)
90
91 /* Similar, but make sure opcode names match up. */
92 #define OE_RR_X0(E) OE(RRR_0_OPCODE_X0, E##_UNARY_OPCODE_X0, X0)
93 #define OE_RR_X1(E) OE(RRR_0_OPCODE_X1, E##_UNARY_OPCODE_X1, X1)
94 #define OE_RR_Y0(E) OE(RRR_1_OPCODE_Y0, E##_UNARY_OPCODE_Y0, Y0)
95 #define OE_RR_Y1(E) OE(RRR_1_OPCODE_Y1, E##_UNARY_OPCODE_Y1, Y1)
96 #define OE_RRR(E,N,XY) OE(RRR_##N##_OPCODE_##XY, E##_RRR_##N##_OPCODE_##XY, XY)
97 #define OE_IM(E,XY) OE(IMM8_OPCODE_##XY, E##_IMM8_OPCODE_##XY, XY)
98 #define OE_SH(E,XY) OE(SHIFT_OPCODE_##XY, E##_SHIFT_OPCODE_##XY, XY)
99
100 #define V1_IMM(X) (((X) & 0xff) * 0x0101010101010101ull)
101 #define V2_IMM(X) (((X) & 0xffff) * 0x0001000100010001ull)
102
103
104 static void gen_exception(DisasContext *dc, TileExcp num)
105 {
106 TCGv_i32 tmp;
107
108 tcg_gen_movi_tl(cpu_pc, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
109
110 tmp = tcg_const_i32(num);
111 gen_helper_exception(cpu_env, tmp);
112 tcg_temp_free_i32(tmp);
113 dc->exit_tb = true;
114 }
115
116 static bool check_gr(DisasContext *dc, uint8_t reg)
117 {
118 if (likely(reg < TILEGX_R_COUNT)) {
119 return true;
120 }
121
122 switch (reg) {
123 case TILEGX_R_SN:
124 case TILEGX_R_ZERO:
125 break;
126 case TILEGX_R_IDN0:
127 case TILEGX_R_IDN1:
128 gen_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
129 break;
130 case TILEGX_R_UDN0:
131 case TILEGX_R_UDN1:
132 case TILEGX_R_UDN2:
133 case TILEGX_R_UDN3:
134 gen_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
135 break;
136 default:
137 g_assert_not_reached();
138 }
139 return false;
140 }
141
142 static TCGv load_zero(DisasContext *dc)
143 {
144 if (TCGV_IS_UNUSED_I64(dc->zero)) {
145 dc->zero = tcg_const_i64(0);
146 }
147 return dc->zero;
148 }
149
150 static TCGv load_gr(DisasContext *dc, unsigned reg)
151 {
152 if (check_gr(dc, reg)) {
153 return cpu_regs[reg];
154 }
155 return load_zero(dc);
156 }
157
158 static TCGv dest_gr(DisasContext *dc, unsigned reg)
159 {
160 int n;
161
162 /* Skip the result, mark the exception if necessary, and continue */
163 check_gr(dc, reg);
164
165 n = dc->num_wb++;
166 dc->wb[n].reg = reg;
167 return dc->wb[n].val = tcg_temp_new_i64();
168 }
169
170 static void gen_saturate_op(TCGv tdest, TCGv tsrca, TCGv tsrcb,
171 void (*operate)(TCGv, TCGv, TCGv))
172 {
173 TCGv t0 = tcg_temp_new();
174
175 tcg_gen_ext32s_tl(tdest, tsrca);
176 tcg_gen_ext32s_tl(t0, tsrcb);
177 operate(tdest, tdest, t0);
178
179 tcg_gen_movi_tl(t0, 0x7fffffff);
180 tcg_gen_movcond_tl(TCG_COND_GT, tdest, tdest, t0, t0, tdest);
181 tcg_gen_movi_tl(t0, -0x80000000LL);
182 tcg_gen_movcond_tl(TCG_COND_LT, tdest, tdest, t0, t0, tdest);
183
184 tcg_temp_free(t0);
185 }
186
187 static void gen_atomic_excp(DisasContext *dc, unsigned dest, TCGv tdest,
188 TCGv tsrca, TCGv tsrcb, TileExcp excp)
189 {
190 #ifdef CONFIG_USER_ONLY
191 TCGv_i32 t;
192
193 tcg_gen_st_tl(tsrca, cpu_env, offsetof(CPUTLGState, atomic_srca));
194 tcg_gen_st_tl(tsrcb, cpu_env, offsetof(CPUTLGState, atomic_srcb));
195 t = tcg_const_i32(dest);
196 tcg_gen_st_i32(t, cpu_env, offsetof(CPUTLGState, atomic_dstr));
197 tcg_temp_free_i32(t);
198
199 /* We're going to write the real result in the exception. But in
200 the meantime we've already created a writeback register, and
201 we don't want that to remain uninitialized. */
202 tcg_gen_movi_tl(tdest, 0);
203
204 /* Note that we need to delay issuing the exception that implements
205 the atomic operation until after writing back the results of the
206 instruction occupying the X0 pipe. */
207 dc->atomic_excp = excp;
208 #else
209 gen_exception(dc, TILEGX_EXCP_OPCODE_UNIMPLEMENTED);
210 #endif
211 }
212
213 /* Shift the 128-bit value TSRCA:TSRCD right by the number of bytes
214 specified by the bottom 3 bits of TSRCB, and set TDEST to the
215 low 64 bits of the resulting value. */
216 static void gen_dblalign(TCGv tdest, TCGv tsrcd, TCGv tsrca, TCGv tsrcb)
217 {
218 TCGv t0 = tcg_temp_new();
219
220 tcg_gen_andi_tl(t0, tsrcb, 7);
221 tcg_gen_shli_tl(t0, t0, 3);
222 tcg_gen_shr_tl(tdest, tsrcd, t0);
223
224 /* We want to do "t0 = tsrca << (64 - t0)". Two's complement
225 arithmetic on a 6-bit field tells us that 64 - t0 is equal
226 to (t0 ^ 63) + 1. So we can do the shift in two parts,
227 neither of which will be an invalid shift by 64. */
228 tcg_gen_xori_tl(t0, t0, 63);
229 tcg_gen_shl_tl(t0, tsrca, t0);
230 tcg_gen_shli_tl(t0, t0, 1);
231 tcg_gen_or_tl(tdest, tdest, t0);
232
233 tcg_temp_free(t0);
234 }
235
236 /* Similarly, except that the 128-bit value is TSRCA:TSRCB, and the
237 right shift is an immediate. */
238 static void gen_dblaligni(TCGv tdest, TCGv tsrca, TCGv tsrcb, int shr)
239 {
240 TCGv t0 = tcg_temp_new();
241
242 tcg_gen_shri_tl(t0, tsrcb, shr);
243 tcg_gen_shli_tl(tdest, tsrca, 64 - shr);
244 tcg_gen_or_tl(tdest, tdest, t0);
245
246 tcg_temp_free(t0);
247 }
248
249 typedef enum {
250 LU, LS, HU, HS
251 } MulHalf;
252
253 static void gen_ext_half(TCGv d, TCGv s, MulHalf h)
254 {
255 switch (h) {
256 case LU:
257 tcg_gen_ext32u_tl(d, s);
258 break;
259 case LS:
260 tcg_gen_ext32s_tl(d, s);
261 break;
262 case HU:
263 tcg_gen_shri_tl(d, s, 32);
264 break;
265 case HS:
266 tcg_gen_sari_tl(d, s, 32);
267 break;
268 }
269 }
270
271 static void gen_mul_half(TCGv tdest, TCGv tsrca, TCGv tsrcb,
272 MulHalf ha, MulHalf hb)
273 {
274 TCGv t = tcg_temp_new();
275 gen_ext_half(t, tsrca, ha);
276 gen_ext_half(tdest, tsrcb, hb);
277 tcg_gen_mul_tl(tdest, tdest, t);
278 tcg_temp_free(t);
279 }
280
281 static void gen_cmul2(TCGv tdest, TCGv tsrca, TCGv tsrcb, int sh, int rd)
282 {
283 TCGv_i32 tsh = tcg_const_i32(sh);
284 TCGv_i32 trd = tcg_const_i32(rd);
285 gen_helper_cmul2(tdest, tsrca, tsrcb, tsh, trd);
286 tcg_temp_free_i32(tsh);
287 tcg_temp_free_i32(trd);
288 }
289
290 static TileExcp gen_st_opcode(DisasContext *dc, unsigned dest, unsigned srca,
291 unsigned srcb, TCGMemOp memop, const char *name)
292 {
293 if (dest) {
294 return TILEGX_EXCP_OPCODE_UNKNOWN;
295 }
296
297 tcg_gen_qemu_st_tl(load_gr(dc, srcb), load_gr(dc, srca),
298 dc->mmuidx, memop);
299
300 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", name,
301 reg_names[srca], reg_names[srcb]);
302 return TILEGX_EXCP_NONE;
303 }
304
305 static TileExcp gen_st_add_opcode(DisasContext *dc, unsigned srca, unsigned srcb,
306 int imm, TCGMemOp memop, const char *name)
307 {
308 TCGv tsrca = load_gr(dc, srca);
309 TCGv tsrcb = load_gr(dc, srcb);
310
311 tcg_gen_qemu_st_tl(tsrcb, tsrca, dc->mmuidx, memop);
312 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
313
314 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", name,
315 reg_names[srca], reg_names[srcb], imm);
316 return TILEGX_EXCP_NONE;
317 }
318
319 /* Equality comparison with zero can be done quickly and efficiently. */
320 static void gen_v1cmpeq0(TCGv v)
321 {
322 TCGv m = tcg_const_tl(V1_IMM(0x7f));
323 TCGv c = tcg_temp_new();
324
325 /* ~(((v & m) + m) | m | v). Sets the msb for each byte == 0. */
326 tcg_gen_and_tl(c, v, m);
327 tcg_gen_add_tl(c, c, m);
328 tcg_gen_or_tl(c, c, m);
329 tcg_gen_nor_tl(c, c, v);
330 tcg_temp_free(m);
331
332 /* Shift the msb down to form the lsb boolean result. */
333 tcg_gen_shri_tl(v, c, 7);
334 tcg_temp_free(c);
335 }
336
337 static void gen_v1cmpne0(TCGv v)
338 {
339 TCGv m = tcg_const_tl(V1_IMM(0x7f));
340 TCGv c = tcg_temp_new();
341
342 /* (((v & m) + m) | v) & ~m. Sets the msb for each byte != 0. */
343 tcg_gen_and_tl(c, v, m);
344 tcg_gen_add_tl(c, c, m);
345 tcg_gen_or_tl(c, c, v);
346 tcg_gen_andc_tl(c, c, m);
347 tcg_temp_free(m);
348
349 /* Shift the msb down to form the lsb boolean result. */
350 tcg_gen_shri_tl(v, c, 7);
351 tcg_temp_free(c);
352 }
353
354 /* Vector addition can be performed via arithmetic plus masking. It is
355 efficient this way only for 4 or more elements. */
356 static void gen_v12add(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
357 {
358 TCGv tmask = tcg_const_tl(~sign);
359 TCGv t0 = tcg_temp_new();
360 TCGv t1 = tcg_temp_new();
361
362 /* ((a & ~sign) + (b & ~sign)) ^ ((a ^ b) & sign). */
363 tcg_gen_and_tl(t0, tsrca, tmask);
364 tcg_gen_and_tl(t1, tsrcb, tmask);
365 tcg_gen_add_tl(tdest, t0, t1);
366 tcg_gen_xor_tl(t0, tsrca, tsrcb);
367 tcg_gen_andc_tl(t0, t0, tmask);
368 tcg_gen_xor_tl(tdest, tdest, t0);
369
370 tcg_temp_free(t1);
371 tcg_temp_free(t0);
372 tcg_temp_free(tmask);
373 }
374
375 /* Similarly for vector subtraction. */
376 static void gen_v12sub(TCGv tdest, TCGv tsrca, TCGv tsrcb, uint64_t sign)
377 {
378 TCGv tsign = tcg_const_tl(sign);
379 TCGv t0 = tcg_temp_new();
380 TCGv t1 = tcg_temp_new();
381
382 /* ((a | sign) - (b & ~sign)) ^ ((a ^ ~b) & sign). */
383 tcg_gen_or_tl(t0, tsrca, tsign);
384 tcg_gen_andc_tl(t1, tsrcb, tsign);
385 tcg_gen_sub_tl(tdest, t0, t1);
386 tcg_gen_eqv_tl(t0, tsrca, tsrcb);
387 tcg_gen_and_tl(t0, t0, tsign);
388 tcg_gen_xor_tl(tdest, tdest, t0);
389
390 tcg_temp_free(t1);
391 tcg_temp_free(t0);
392 tcg_temp_free(tsign);
393 }
394
395 static void gen_v4sh(TCGv d64, TCGv a64, TCGv b64,
396 void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
397 {
398 TCGv_i32 al = tcg_temp_new_i32();
399 TCGv_i32 ah = tcg_temp_new_i32();
400 TCGv_i32 bl = tcg_temp_new_i32();
401
402 tcg_gen_extr_i64_i32(al, ah, a64);
403 tcg_gen_extrl_i64_i32(bl, b64);
404 tcg_gen_andi_i32(bl, bl, 31);
405 generate(al, al, bl);
406 generate(ah, ah, bl);
407 tcg_gen_concat_i32_i64(d64, al, ah);
408
409 tcg_temp_free_i32(al);
410 tcg_temp_free_i32(ah);
411 tcg_temp_free_i32(bl);
412 }
413
414 static void gen_v4op(TCGv d64, TCGv a64, TCGv b64,
415 void (*generate)(TCGv_i32, TCGv_i32, TCGv_i32))
416 {
417 TCGv_i32 al = tcg_temp_new_i32();
418 TCGv_i32 ah = tcg_temp_new_i32();
419 TCGv_i32 bl = tcg_temp_new_i32();
420 TCGv_i32 bh = tcg_temp_new_i32();
421
422 tcg_gen_extr_i64_i32(al, ah, a64);
423 tcg_gen_extr_i64_i32(bl, bh, b64);
424 generate(al, al, bl);
425 generate(ah, ah, bh);
426 tcg_gen_concat_i32_i64(d64, al, ah);
427
428 tcg_temp_free_i32(al);
429 tcg_temp_free_i32(ah);
430 tcg_temp_free_i32(bl);
431 tcg_temp_free_i32(bh);
432 }
433
434 static TileExcp gen_signal(DisasContext *dc, int signo, int sigcode,
435 const char *mnemonic)
436 {
437 TCGv_i32 t0 = tcg_const_i32(signo);
438 TCGv_i32 t1 = tcg_const_i32(sigcode);
439
440 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUTLGState, signo));
441 tcg_gen_st_i32(t1, cpu_env, offsetof(CPUTLGState, sigcode));
442
443 tcg_temp_free_i32(t1);
444 tcg_temp_free_i32(t0);
445
446 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
447 return TILEGX_EXCP_SIGNAL;
448 }
449
450 static bool parse_from_addli(uint64_t bundle, int *signo, int *sigcode)
451 {
452 int imm;
453
454 if ((get_Opcode_X0(bundle) != ADDLI_OPCODE_X0)
455 || (get_Dest_X0(bundle) != TILEGX_R_ZERO)
456 || (get_SrcA_X0(bundle) != TILEGX_R_ZERO)) {
457 return false;
458 }
459
460 imm = get_Imm16_X0(bundle);
461 *signo = imm & 0x3f;
462 *sigcode = (imm >> 6) & 0xf;
463
464 /* ??? The linux kernel validates both signo and the sigcode vs the
465 known max for each signal. Don't bother here. */
466 return true;
467 }
468
469 static TileExcp gen_specill(DisasContext *dc, unsigned dest, unsigned srca,
470 uint64_t bundle)
471 {
472 const char *mnemonic;
473 int signo;
474 int sigcode;
475
476 if (dest == 0x1c && srca == 0x25) {
477 signo = TARGET_SIGTRAP;
478 sigcode = TARGET_TRAP_BRKPT;
479 mnemonic = "bpt";
480 } else if (dest == 0x1d && srca == 0x25
481 && parse_from_addli(bundle, &signo, &sigcode)) {
482 mnemonic = "raise";
483 } else {
484 signo = TARGET_SIGILL;
485 sigcode = TARGET_ILL_ILLOPC;
486 mnemonic = "ill";
487 }
488
489 return gen_signal(dc, signo, sigcode, mnemonic);
490 }
491
492 static TileExcp gen_rr_opcode(DisasContext *dc, unsigned opext,
493 unsigned dest, unsigned srca, uint64_t bundle)
494 {
495 TCGv tdest, tsrca;
496 const char *mnemonic;
497 TCGMemOp memop;
498 TileExcp ret = TILEGX_EXCP_NONE;
499 bool prefetch_nofault = false;
500
501 /* Eliminate instructions with no output before doing anything else. */
502 switch (opext) {
503 case OE_RR_Y0(NOP):
504 case OE_RR_Y1(NOP):
505 case OE_RR_X0(NOP):
506 case OE_RR_X1(NOP):
507 mnemonic = "nop";
508 goto done0;
509 case OE_RR_Y0(FNOP):
510 case OE_RR_Y1(FNOP):
511 case OE_RR_X0(FNOP):
512 case OE_RR_X1(FNOP):
513 mnemonic = "fnop";
514 goto done0;
515 case OE_RR_X1(DRAIN):
516 mnemonic = "drain";
517 goto done0;
518 case OE_RR_X1(FLUSHWB):
519 mnemonic = "flushwb";
520 goto done0;
521 case OE_RR_X1(ILL):
522 return gen_specill(dc, dest, srca, bundle);
523 case OE_RR_Y1(ILL):
524 return gen_signal(dc, TARGET_SIGILL, TARGET_ILL_ILLOPC, "ill");
525 case OE_RR_X1(MF):
526 mnemonic = "mf";
527 goto done0;
528 case OE_RR_X1(NAP):
529 /* ??? This should yield, especially in system mode. */
530 mnemonic = "nap";
531 goto done0;
532 case OE_RR_X1(IRET):
533 gen_helper_ext01_ics(cpu_env);
534 dc->jmp.cond = TCG_COND_ALWAYS;
535 dc->jmp.dest = tcg_temp_new();
536 tcg_gen_ld_tl(dc->jmp.dest, cpu_env,
537 offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]));
538 tcg_gen_andi_tl(dc->jmp.dest, dc->jmp.dest, ~7);
539 mnemonic = "iret";
540 goto done0;
541 case OE_RR_X1(SWINT0):
542 case OE_RR_X1(SWINT2):
543 case OE_RR_X1(SWINT3):
544 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
545 case OE_RR_X1(SWINT1):
546 ret = TILEGX_EXCP_SYSCALL;
547 mnemonic = "swint1";
548 done0:
549 if (srca || dest) {
550 return TILEGX_EXCP_OPCODE_UNKNOWN;
551 }
552 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s", mnemonic);
553 return ret;
554
555 case OE_RR_X1(DTLBPR):
556 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
557 case OE_RR_X1(FINV):
558 mnemonic = "finv";
559 goto done1;
560 case OE_RR_X1(FLUSH):
561 mnemonic = "flush";
562 goto done1;
563 case OE_RR_X1(ICOH):
564 mnemonic = "icoh";
565 goto done1;
566 case OE_RR_X1(INV):
567 mnemonic = "inv";
568 goto done1;
569 case OE_RR_X1(WH64):
570 mnemonic = "wh64";
571 goto done1;
572 case OE_RR_X1(JRP):
573 case OE_RR_Y1(JRP):
574 mnemonic = "jrp";
575 goto do_jr;
576 case OE_RR_X1(JR):
577 case OE_RR_Y1(JR):
578 mnemonic = "jr";
579 goto do_jr;
580 case OE_RR_X1(JALRP):
581 case OE_RR_Y1(JALRP):
582 mnemonic = "jalrp";
583 goto do_jalr;
584 case OE_RR_X1(JALR):
585 case OE_RR_Y1(JALR):
586 mnemonic = "jalr";
587 do_jalr:
588 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
589 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
590 do_jr:
591 dc->jmp.cond = TCG_COND_ALWAYS;
592 dc->jmp.dest = tcg_temp_new();
593 tcg_gen_andi_tl(dc->jmp.dest, load_gr(dc, srca), ~7);
594 done1:
595 if (dest) {
596 return TILEGX_EXCP_OPCODE_UNKNOWN;
597 }
598 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s", mnemonic, reg_names[srca]);
599 return ret;
600 }
601
602 tdest = dest_gr(dc, dest);
603 tsrca = load_gr(dc, srca);
604
605 switch (opext) {
606 case OE_RR_X0(CNTLZ):
607 case OE_RR_Y0(CNTLZ):
608 gen_helper_cntlz(tdest, tsrca);
609 mnemonic = "cntlz";
610 break;
611 case OE_RR_X0(CNTTZ):
612 case OE_RR_Y0(CNTTZ):
613 gen_helper_cnttz(tdest, tsrca);
614 mnemonic = "cnttz";
615 break;
616 case OE_RR_X0(FSINGLE_PACK1):
617 case OE_RR_Y0(FSINGLE_PACK1):
618 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
619 case OE_RR_X1(LD1S):
620 memop = MO_SB;
621 mnemonic = "ld1s"; /* prefetch_l1_fault */
622 goto do_load;
623 case OE_RR_X1(LD1U):
624 memop = MO_UB;
625 mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
626 prefetch_nofault = (dest == TILEGX_R_ZERO);
627 goto do_load;
628 case OE_RR_X1(LD2S):
629 memop = MO_TESW;
630 mnemonic = "ld2s"; /* prefetch_l2_fault */
631 goto do_load;
632 case OE_RR_X1(LD2U):
633 memop = MO_TEUW;
634 mnemonic = "ld2u"; /* prefetch_l2 */
635 prefetch_nofault = (dest == TILEGX_R_ZERO);
636 goto do_load;
637 case OE_RR_X1(LD4S):
638 memop = MO_TESL;
639 mnemonic = "ld4s"; /* prefetch_l3_fault */
640 goto do_load;
641 case OE_RR_X1(LD4U):
642 memop = MO_TEUL;
643 mnemonic = "ld4u"; /* prefetch_l3 */
644 prefetch_nofault = (dest == TILEGX_R_ZERO);
645 goto do_load;
646 case OE_RR_X1(LDNT1S):
647 memop = MO_SB;
648 mnemonic = "ldnt1s";
649 goto do_load;
650 case OE_RR_X1(LDNT1U):
651 memop = MO_UB;
652 mnemonic = "ldnt1u";
653 goto do_load;
654 case OE_RR_X1(LDNT2S):
655 memop = MO_TESW;
656 mnemonic = "ldnt2s";
657 goto do_load;
658 case OE_RR_X1(LDNT2U):
659 memop = MO_TEUW;
660 mnemonic = "ldnt2u";
661 goto do_load;
662 case OE_RR_X1(LDNT4S):
663 memop = MO_TESL;
664 mnemonic = "ldnt4s";
665 goto do_load;
666 case OE_RR_X1(LDNT4U):
667 memop = MO_TEUL;
668 mnemonic = "ldnt4u";
669 goto do_load;
670 case OE_RR_X1(LDNT):
671 memop = MO_TEQ;
672 mnemonic = "ldnt";
673 goto do_load;
674 case OE_RR_X1(LD):
675 memop = MO_TEQ;
676 mnemonic = "ld";
677 do_load:
678 if (!prefetch_nofault) {
679 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
680 }
681 break;
682 case OE_RR_X1(LDNA):
683 tcg_gen_andi_tl(tdest, tsrca, ~7);
684 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
685 mnemonic = "ldna";
686 break;
687 case OE_RR_X1(LNK):
688 case OE_RR_Y1(LNK):
689 if (srca) {
690 return TILEGX_EXCP_OPCODE_UNKNOWN;
691 }
692 tcg_gen_movi_tl(tdest, dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
693 mnemonic = "lnk";
694 break;
695 case OE_RR_X0(PCNT):
696 case OE_RR_Y0(PCNT):
697 gen_helper_pcnt(tdest, tsrca);
698 mnemonic = "pcnt";
699 break;
700 case OE_RR_X0(REVBITS):
701 case OE_RR_Y0(REVBITS):
702 gen_helper_revbits(tdest, tsrca);
703 mnemonic = "revbits";
704 break;
705 case OE_RR_X0(REVBYTES):
706 case OE_RR_Y0(REVBYTES):
707 tcg_gen_bswap64_tl(tdest, tsrca);
708 mnemonic = "revbytes";
709 break;
710 case OE_RR_X0(TBLIDXB0):
711 case OE_RR_Y0(TBLIDXB0):
712 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tsrca, 2, 8);
713 mnemonic = "tblidxb0";
714 break;
715 case OE_RR_X0(TBLIDXB1):
716 case OE_RR_Y0(TBLIDXB1):
717 tcg_gen_shri_tl(tdest, tsrca, 8);
718 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
719 mnemonic = "tblidxb1";
720 break;
721 case OE_RR_X0(TBLIDXB2):
722 case OE_RR_Y0(TBLIDXB2):
723 tcg_gen_shri_tl(tdest, tsrca, 16);
724 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
725 mnemonic = "tblidxb2";
726 break;
727 case OE_RR_X0(TBLIDXB3):
728 case OE_RR_Y0(TBLIDXB3):
729 tcg_gen_shri_tl(tdest, tsrca, 24);
730 tcg_gen_deposit_tl(tdest, load_gr(dc, dest), tdest, 2, 8);
731 mnemonic = "tblidxb3";
732 break;
733 default:
734 return TILEGX_EXCP_OPCODE_UNKNOWN;
735 }
736
737 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
738 reg_names[dest], reg_names[srca]);
739 return ret;
740 }
741
742 static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext,
743 unsigned dest, unsigned srca, unsigned srcb)
744 {
745 TCGv tdest = dest_gr(dc, dest);
746 TCGv tsrca = load_gr(dc, srca);
747 TCGv tsrcb = load_gr(dc, srcb);
748 TCGv t0;
749 const char *mnemonic;
750
751 switch (opext) {
752 case OE_RRR(ADDXSC, 0, X0):
753 case OE_RRR(ADDXSC, 0, X1):
754 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_add_tl);
755 mnemonic = "addxsc";
756 break;
757 case OE_RRR(ADDX, 0, X0):
758 case OE_RRR(ADDX, 0, X1):
759 case OE_RRR(ADDX, 0, Y0):
760 case OE_RRR(ADDX, 0, Y1):
761 tcg_gen_add_tl(tdest, tsrca, tsrcb);
762 tcg_gen_ext32s_tl(tdest, tdest);
763 mnemonic = "addx";
764 break;
765 case OE_RRR(ADD, 0, X0):
766 case OE_RRR(ADD, 0, X1):
767 case OE_RRR(ADD, 0, Y0):
768 case OE_RRR(ADD, 0, Y1):
769 tcg_gen_add_tl(tdest, tsrca, tsrcb);
770 mnemonic = "add";
771 break;
772 case OE_RRR(AND, 0, X0):
773 case OE_RRR(AND, 0, X1):
774 case OE_RRR(AND, 5, Y0):
775 case OE_RRR(AND, 5, Y1):
776 tcg_gen_and_tl(tdest, tsrca, tsrcb);
777 mnemonic = "and";
778 break;
779 case OE_RRR(CMOVEQZ, 0, X0):
780 case OE_RRR(CMOVEQZ, 4, Y0):
781 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, load_zero(dc),
782 tsrcb, load_gr(dc, dest));
783 mnemonic = "cmoveqz";
784 break;
785 case OE_RRR(CMOVNEZ, 0, X0):
786 case OE_RRR(CMOVNEZ, 4, Y0):
787 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, load_zero(dc),
788 tsrcb, load_gr(dc, dest));
789 mnemonic = "cmovnez";
790 break;
791 case OE_RRR(CMPEQ, 0, X0):
792 case OE_RRR(CMPEQ, 0, X1):
793 case OE_RRR(CMPEQ, 3, Y0):
794 case OE_RRR(CMPEQ, 3, Y1):
795 tcg_gen_setcond_tl(TCG_COND_EQ, tdest, tsrca, tsrcb);
796 mnemonic = "cmpeq";
797 break;
798 case OE_RRR(CMPEXCH4, 0, X1):
799 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
800 TILEGX_EXCP_OPCODE_CMPEXCH4);
801 mnemonic = "cmpexch4";
802 break;
803 case OE_RRR(CMPEXCH, 0, X1):
804 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
805 TILEGX_EXCP_OPCODE_CMPEXCH);
806 mnemonic = "cmpexch";
807 break;
808 case OE_RRR(CMPLES, 0, X0):
809 case OE_RRR(CMPLES, 0, X1):
810 case OE_RRR(CMPLES, 2, Y0):
811 case OE_RRR(CMPLES, 2, Y1):
812 tcg_gen_setcond_tl(TCG_COND_LE, tdest, tsrca, tsrcb);
813 mnemonic = "cmples";
814 break;
815 case OE_RRR(CMPLEU, 0, X0):
816 case OE_RRR(CMPLEU, 0, X1):
817 case OE_RRR(CMPLEU, 2, Y0):
818 case OE_RRR(CMPLEU, 2, Y1):
819 tcg_gen_setcond_tl(TCG_COND_LEU, tdest, tsrca, tsrcb);
820 mnemonic = "cmpleu";
821 break;
822 case OE_RRR(CMPLTS, 0, X0):
823 case OE_RRR(CMPLTS, 0, X1):
824 case OE_RRR(CMPLTS, 2, Y0):
825 case OE_RRR(CMPLTS, 2, Y1):
826 tcg_gen_setcond_tl(TCG_COND_LT, tdest, tsrca, tsrcb);
827 mnemonic = "cmplts";
828 break;
829 case OE_RRR(CMPLTU, 0, X0):
830 case OE_RRR(CMPLTU, 0, X1):
831 case OE_RRR(CMPLTU, 2, Y0):
832 case OE_RRR(CMPLTU, 2, Y1):
833 tcg_gen_setcond_tl(TCG_COND_LTU, tdest, tsrca, tsrcb);
834 mnemonic = "cmpltu";
835 break;
836 case OE_RRR(CMPNE, 0, X0):
837 case OE_RRR(CMPNE, 0, X1):
838 case OE_RRR(CMPNE, 3, Y0):
839 case OE_RRR(CMPNE, 3, Y1):
840 tcg_gen_setcond_tl(TCG_COND_NE, tdest, tsrca, tsrcb);
841 mnemonic = "cmpne";
842 break;
843 case OE_RRR(CMULAF, 0, X0):
844 gen_helper_cmulaf(tdest, load_gr(dc, dest), tsrca, tsrcb);
845 mnemonic = "cmulaf";
846 break;
847 case OE_RRR(CMULA, 0, X0):
848 gen_helper_cmula(tdest, load_gr(dc, dest), tsrca, tsrcb);
849 mnemonic = "cmula";
850 break;
851 case OE_RRR(CMULFR, 0, X0):
852 gen_cmul2(tdest, tsrca, tsrcb, 15, 1 << 14);
853 mnemonic = "cmulfr";
854 break;
855 case OE_RRR(CMULF, 0, X0):
856 gen_cmul2(tdest, tsrca, tsrcb, 15, 0);
857 mnemonic = "cmulf";
858 break;
859 case OE_RRR(CMULHR, 0, X0):
860 gen_cmul2(tdest, tsrca, tsrcb, 16, 1 << 15);
861 mnemonic = "cmulhr";
862 break;
863 case OE_RRR(CMULH, 0, X0):
864 gen_cmul2(tdest, tsrca, tsrcb, 16, 0);
865 mnemonic = "cmulh";
866 break;
867 case OE_RRR(CMUL, 0, X0):
868 gen_helper_cmula(tdest, load_zero(dc), tsrca, tsrcb);
869 mnemonic = "cmul";
870 break;
871 case OE_RRR(CRC32_32, 0, X0):
872 gen_helper_crc32_32(tdest, tsrca, tsrcb);
873 mnemonic = "crc32_32";
874 break;
875 case OE_RRR(CRC32_8, 0, X0):
876 gen_helper_crc32_8(tdest, tsrca, tsrcb);
877 mnemonic = "crc32_8";
878 break;
879 case OE_RRR(DBLALIGN2, 0, X0):
880 case OE_RRR(DBLALIGN2, 0, X1):
881 gen_dblaligni(tdest, tsrca, tsrcb, 16);
882 mnemonic = "dblalign2";
883 break;
884 case OE_RRR(DBLALIGN4, 0, X0):
885 case OE_RRR(DBLALIGN4, 0, X1):
886 gen_dblaligni(tdest, tsrca, tsrcb, 32);
887 mnemonic = "dblalign4";
888 break;
889 case OE_RRR(DBLALIGN6, 0, X0):
890 case OE_RRR(DBLALIGN6, 0, X1):
891 gen_dblaligni(tdest, tsrca, tsrcb, 48);
892 mnemonic = "dblalign6";
893 break;
894 case OE_RRR(DBLALIGN, 0, X0):
895 gen_dblalign(tdest, load_gr(dc, dest), tsrca, tsrcb);
896 mnemonic = "dblalign";
897 break;
898 case OE_RRR(EXCH4, 0, X1):
899 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
900 TILEGX_EXCP_OPCODE_EXCH4);
901 mnemonic = "exch4";
902 break;
903 case OE_RRR(EXCH, 0, X1):
904 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
905 TILEGX_EXCP_OPCODE_EXCH);
906 mnemonic = "exch";
907 break;
908 case OE_RRR(FDOUBLE_ADDSUB, 0, X0):
909 case OE_RRR(FDOUBLE_ADD_FLAGS, 0, X0):
910 case OE_RRR(FDOUBLE_MUL_FLAGS, 0, X0):
911 case OE_RRR(FDOUBLE_PACK1, 0, X0):
912 case OE_RRR(FDOUBLE_PACK2, 0, X0):
913 case OE_RRR(FDOUBLE_SUB_FLAGS, 0, X0):
914 case OE_RRR(FDOUBLE_UNPACK_MAX, 0, X0):
915 case OE_RRR(FDOUBLE_UNPACK_MIN, 0, X0):
916 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
917 case OE_RRR(FETCHADD4, 0, X1):
918 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
919 TILEGX_EXCP_OPCODE_FETCHADD4);
920 mnemonic = "fetchadd4";
921 break;
922 case OE_RRR(FETCHADDGEZ4, 0, X1):
923 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
924 TILEGX_EXCP_OPCODE_FETCHADDGEZ4);
925 mnemonic = "fetchaddgez4";
926 break;
927 case OE_RRR(FETCHADDGEZ, 0, X1):
928 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
929 TILEGX_EXCP_OPCODE_FETCHADDGEZ);
930 mnemonic = "fetchaddgez";
931 break;
932 case OE_RRR(FETCHADD, 0, X1):
933 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
934 TILEGX_EXCP_OPCODE_FETCHADD);
935 mnemonic = "fetchadd";
936 break;
937 case OE_RRR(FETCHAND4, 0, X1):
938 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
939 TILEGX_EXCP_OPCODE_FETCHAND4);
940 mnemonic = "fetchand4";
941 break;
942 case OE_RRR(FETCHAND, 0, X1):
943 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
944 TILEGX_EXCP_OPCODE_FETCHAND);
945 mnemonic = "fetchand";
946 break;
947 case OE_RRR(FETCHOR4, 0, X1):
948 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
949 TILEGX_EXCP_OPCODE_FETCHOR4);
950 mnemonic = "fetchor4";
951 break;
952 case OE_RRR(FETCHOR, 0, X1):
953 gen_atomic_excp(dc, dest, tdest, tsrca, tsrcb,
954 TILEGX_EXCP_OPCODE_FETCHOR);
955 mnemonic = "fetchor";
956 break;
957 case OE_RRR(FSINGLE_ADD1, 0, X0):
958 case OE_RRR(FSINGLE_ADDSUB2, 0, X0):
959 case OE_RRR(FSINGLE_MUL1, 0, X0):
960 case OE_RRR(FSINGLE_MUL2, 0, X0):
961 case OE_RRR(FSINGLE_PACK2, 0, X0):
962 case OE_RRR(FSINGLE_SUB1, 0, X0):
963 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
964 case OE_RRR(MNZ, 0, X0):
965 case OE_RRR(MNZ, 0, X1):
966 case OE_RRR(MNZ, 4, Y0):
967 case OE_RRR(MNZ, 4, Y1):
968 t0 = load_zero(dc);
969 tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0);
970 mnemonic = "mnz";
971 break;
972 case OE_RRR(MULAX, 0, X0):
973 case OE_RRR(MULAX, 3, Y0):
974 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
975 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
976 tcg_gen_ext32s_tl(tdest, tdest);
977 mnemonic = "mulax";
978 break;
979 case OE_RRR(MULA_HS_HS, 0, X0):
980 case OE_RRR(MULA_HS_HS, 9, Y0):
981 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
982 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
983 mnemonic = "mula_hs_hs";
984 break;
985 case OE_RRR(MULA_HS_HU, 0, X0):
986 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
987 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
988 mnemonic = "mula_hs_hu";
989 break;
990 case OE_RRR(MULA_HS_LS, 0, X0):
991 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
992 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
993 mnemonic = "mula_hs_ls";
994 break;
995 case OE_RRR(MULA_HS_LU, 0, X0):
996 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
997 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
998 mnemonic = "mula_hs_lu";
999 break;
1000 case OE_RRR(MULA_HU_HU, 0, X0):
1001 case OE_RRR(MULA_HU_HU, 9, Y0):
1002 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
1003 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1004 mnemonic = "mula_hu_hu";
1005 break;
1006 case OE_RRR(MULA_HU_LS, 0, X0):
1007 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
1008 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1009 mnemonic = "mula_hu_ls";
1010 break;
1011 case OE_RRR(MULA_HU_LU, 0, X0):
1012 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
1013 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1014 mnemonic = "mula_hu_lu";
1015 break;
1016 case OE_RRR(MULA_LS_LS, 0, X0):
1017 case OE_RRR(MULA_LS_LS, 9, Y0):
1018 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
1019 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1020 mnemonic = "mula_ls_ls";
1021 break;
1022 case OE_RRR(MULA_LS_LU, 0, X0):
1023 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
1024 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1025 mnemonic = "mula_ls_lu";
1026 break;
1027 case OE_RRR(MULA_LU_LU, 0, X0):
1028 case OE_RRR(MULA_LU_LU, 9, Y0):
1029 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
1030 tcg_gen_add_tl(tdest, tdest, load_gr(dc, dest));
1031 mnemonic = "mula_lu_lu";
1032 break;
1033 case OE_RRR(MULX, 0, X0):
1034 case OE_RRR(MULX, 3, Y0):
1035 tcg_gen_mul_tl(tdest, tsrca, tsrcb);
1036 tcg_gen_ext32s_tl(tdest, tdest);
1037 mnemonic = "mulx";
1038 break;
1039 case OE_RRR(MUL_HS_HS, 0, X0):
1040 case OE_RRR(MUL_HS_HS, 8, Y0):
1041 gen_mul_half(tdest, tsrca, tsrcb, HS, HS);
1042 mnemonic = "mul_hs_hs";
1043 break;
1044 case OE_RRR(MUL_HS_HU, 0, X0):
1045 gen_mul_half(tdest, tsrca, tsrcb, HS, HU);
1046 mnemonic = "mul_hs_hu";
1047 break;
1048 case OE_RRR(MUL_HS_LS, 0, X0):
1049 gen_mul_half(tdest, tsrca, tsrcb, HS, LS);
1050 mnemonic = "mul_hs_ls";
1051 break;
1052 case OE_RRR(MUL_HS_LU, 0, X0):
1053 gen_mul_half(tdest, tsrca, tsrcb, HS, LU);
1054 mnemonic = "mul_hs_lu";
1055 break;
1056 case OE_RRR(MUL_HU_HU, 0, X0):
1057 case OE_RRR(MUL_HU_HU, 8, Y0):
1058 gen_mul_half(tdest, tsrca, tsrcb, HU, HU);
1059 mnemonic = "mul_hu_hu";
1060 break;
1061 case OE_RRR(MUL_HU_LS, 0, X0):
1062 gen_mul_half(tdest, tsrca, tsrcb, HU, LS);
1063 mnemonic = "mul_hu_ls";
1064 break;
1065 case OE_RRR(MUL_HU_LU, 0, X0):
1066 gen_mul_half(tdest, tsrca, tsrcb, HU, LU);
1067 mnemonic = "mul_hu_lu";
1068 break;
1069 case OE_RRR(MUL_LS_LS, 0, X0):
1070 case OE_RRR(MUL_LS_LS, 8, Y0):
1071 gen_mul_half(tdest, tsrca, tsrcb, LS, LS);
1072 mnemonic = "mul_ls_ls";
1073 break;
1074 case OE_RRR(MUL_LS_LU, 0, X0):
1075 gen_mul_half(tdest, tsrca, tsrcb, LS, LU);
1076 mnemonic = "mul_ls_lu";
1077 break;
1078 case OE_RRR(MUL_LU_LU, 0, X0):
1079 case OE_RRR(MUL_LU_LU, 8, Y0):
1080 gen_mul_half(tdest, tsrca, tsrcb, LU, LU);
1081 mnemonic = "mul_lu_lu";
1082 break;
1083 case OE_RRR(MZ, 0, X0):
1084 case OE_RRR(MZ, 0, X1):
1085 case OE_RRR(MZ, 4, Y0):
1086 case OE_RRR(MZ, 4, Y1):
1087 t0 = load_zero(dc);
1088 tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0);
1089 mnemonic = "mz";
1090 break;
1091 case OE_RRR(NOR, 0, X0):
1092 case OE_RRR(NOR, 0, X1):
1093 case OE_RRR(NOR, 5, Y0):
1094 case OE_RRR(NOR, 5, Y1):
1095 tcg_gen_nor_tl(tdest, tsrca, tsrcb);
1096 mnemonic = "nor";
1097 break;
1098 case OE_RRR(OR, 0, X0):
1099 case OE_RRR(OR, 0, X1):
1100 case OE_RRR(OR, 5, Y0):
1101 case OE_RRR(OR, 5, Y1):
1102 tcg_gen_or_tl(tdest, tsrca, tsrcb);
1103 mnemonic = "or";
1104 break;
1105 case OE_RRR(ROTL, 0, X0):
1106 case OE_RRR(ROTL, 0, X1):
1107 case OE_RRR(ROTL, 6, Y0):
1108 case OE_RRR(ROTL, 6, Y1):
1109 tcg_gen_andi_tl(tdest, tsrcb, 63);
1110 tcg_gen_rotl_tl(tdest, tsrca, tdest);
1111 mnemonic = "rotl";
1112 break;
1113 case OE_RRR(SHL1ADDX, 0, X0):
1114 case OE_RRR(SHL1ADDX, 0, X1):
1115 case OE_RRR(SHL1ADDX, 7, Y0):
1116 case OE_RRR(SHL1ADDX, 7, Y1):
1117 tcg_gen_shli_tl(tdest, tsrca, 1);
1118 tcg_gen_add_tl(tdest, tdest, tsrcb);
1119 tcg_gen_ext32s_tl(tdest, tdest);
1120 mnemonic = "shl1addx";
1121 break;
1122 case OE_RRR(SHL1ADD, 0, X0):
1123 case OE_RRR(SHL1ADD, 0, X1):
1124 case OE_RRR(SHL1ADD, 1, Y0):
1125 case OE_RRR(SHL1ADD, 1, Y1):
1126 tcg_gen_shli_tl(tdest, tsrca, 1);
1127 tcg_gen_add_tl(tdest, tdest, tsrcb);
1128 mnemonic = "shl1add";
1129 break;
1130 case OE_RRR(SHL2ADDX, 0, X0):
1131 case OE_RRR(SHL2ADDX, 0, X1):
1132 case OE_RRR(SHL2ADDX, 7, Y0):
1133 case OE_RRR(SHL2ADDX, 7, Y1):
1134 tcg_gen_shli_tl(tdest, tsrca, 2);
1135 tcg_gen_add_tl(tdest, tdest, tsrcb);
1136 tcg_gen_ext32s_tl(tdest, tdest);
1137 mnemonic = "shl2addx";
1138 break;
1139 case OE_RRR(SHL2ADD, 0, X0):
1140 case OE_RRR(SHL2ADD, 0, X1):
1141 case OE_RRR(SHL2ADD, 1, Y0):
1142 case OE_RRR(SHL2ADD, 1, Y1):
1143 tcg_gen_shli_tl(tdest, tsrca, 2);
1144 tcg_gen_add_tl(tdest, tdest, tsrcb);
1145 mnemonic = "shl2add";
1146 break;
1147 case OE_RRR(SHL3ADDX, 0, X0):
1148 case OE_RRR(SHL3ADDX, 0, X1):
1149 case OE_RRR(SHL3ADDX, 7, Y0):
1150 case OE_RRR(SHL3ADDX, 7, Y1):
1151 tcg_gen_shli_tl(tdest, tsrca, 3);
1152 tcg_gen_add_tl(tdest, tdest, tsrcb);
1153 tcg_gen_ext32s_tl(tdest, tdest);
1154 mnemonic = "shl3addx";
1155 break;
1156 case OE_RRR(SHL3ADD, 0, X0):
1157 case OE_RRR(SHL3ADD, 0, X1):
1158 case OE_RRR(SHL3ADD, 1, Y0):
1159 case OE_RRR(SHL3ADD, 1, Y1):
1160 tcg_gen_shli_tl(tdest, tsrca, 3);
1161 tcg_gen_add_tl(tdest, tdest, tsrcb);
1162 mnemonic = "shl3add";
1163 break;
1164 case OE_RRR(SHLX, 0, X0):
1165 case OE_RRR(SHLX, 0, X1):
1166 tcg_gen_andi_tl(tdest, tsrcb, 31);
1167 tcg_gen_shl_tl(tdest, tsrca, tdest);
1168 tcg_gen_ext32s_tl(tdest, tdest);
1169 mnemonic = "shlx";
1170 break;
1171 case OE_RRR(SHL, 0, X0):
1172 case OE_RRR(SHL, 0, X1):
1173 case OE_RRR(SHL, 6, Y0):
1174 case OE_RRR(SHL, 6, Y1):
1175 tcg_gen_andi_tl(tdest, tsrcb, 63);
1176 tcg_gen_shl_tl(tdest, tsrca, tdest);
1177 mnemonic = "shl";
1178 break;
1179 case OE_RRR(SHRS, 0, X0):
1180 case OE_RRR(SHRS, 0, X1):
1181 case OE_RRR(SHRS, 6, Y0):
1182 case OE_RRR(SHRS, 6, Y1):
1183 tcg_gen_andi_tl(tdest, tsrcb, 63);
1184 tcg_gen_sar_tl(tdest, tsrca, tdest);
1185 mnemonic = "shrs";
1186 break;
1187 case OE_RRR(SHRUX, 0, X0):
1188 case OE_RRR(SHRUX, 0, X1):
1189 t0 = tcg_temp_new();
1190 tcg_gen_andi_tl(t0, tsrcb, 31);
1191 tcg_gen_ext32u_tl(tdest, tsrca);
1192 tcg_gen_shr_tl(tdest, tdest, t0);
1193 tcg_gen_ext32s_tl(tdest, tdest);
1194 tcg_temp_free(t0);
1195 mnemonic = "shrux";
1196 break;
1197 case OE_RRR(SHRU, 0, X0):
1198 case OE_RRR(SHRU, 0, X1):
1199 case OE_RRR(SHRU, 6, Y0):
1200 case OE_RRR(SHRU, 6, Y1):
1201 tcg_gen_andi_tl(tdest, tsrcb, 63);
1202 tcg_gen_shr_tl(tdest, tsrca, tdest);
1203 mnemonic = "shru";
1204 break;
1205 case OE_RRR(SHUFFLEBYTES, 0, X0):
1206 gen_helper_shufflebytes(tdest, load_gr(dc, dest), tsrca, tsrca);
1207 mnemonic = "shufflebytes";
1208 break;
1209 case OE_RRR(SUBXSC, 0, X0):
1210 case OE_RRR(SUBXSC, 0, X1):
1211 gen_saturate_op(tdest, tsrca, tsrcb, tcg_gen_sub_tl);
1212 mnemonic = "subxsc";
1213 break;
1214 case OE_RRR(SUBX, 0, X0):
1215 case OE_RRR(SUBX, 0, X1):
1216 case OE_RRR(SUBX, 0, Y0):
1217 case OE_RRR(SUBX, 0, Y1):
1218 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
1219 tcg_gen_ext32s_tl(tdest, tdest);
1220 mnemonic = "subx";
1221 break;
1222 case OE_RRR(SUB, 0, X0):
1223 case OE_RRR(SUB, 0, X1):
1224 case OE_RRR(SUB, 0, Y0):
1225 case OE_RRR(SUB, 0, Y1):
1226 tcg_gen_sub_tl(tdest, tsrca, tsrcb);
1227 mnemonic = "sub";
1228 break;
1229 case OE_RRR(V1ADDUC, 0, X0):
1230 case OE_RRR(V1ADDUC, 0, X1):
1231 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1232 case OE_RRR(V1ADD, 0, X0):
1233 case OE_RRR(V1ADD, 0, X1):
1234 gen_v12add(tdest, tsrca, tsrcb, V1_IMM(0x80));
1235 mnemonic = "v1add";
1236 break;
1237 case OE_RRR(V1ADIFFU, 0, X0):
1238 case OE_RRR(V1AVGU, 0, X0):
1239 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1240 case OE_RRR(V1CMPEQ, 0, X0):
1241 case OE_RRR(V1CMPEQ, 0, X1):
1242 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1243 gen_v1cmpeq0(tdest);
1244 mnemonic = "v1cmpeq";
1245 break;
1246 case OE_RRR(V1CMPLES, 0, X0):
1247 case OE_RRR(V1CMPLES, 0, X1):
1248 case OE_RRR(V1CMPLEU, 0, X0):
1249 case OE_RRR(V1CMPLEU, 0, X1):
1250 case OE_RRR(V1CMPLTS, 0, X0):
1251 case OE_RRR(V1CMPLTS, 0, X1):
1252 case OE_RRR(V1CMPLTU, 0, X0):
1253 case OE_RRR(V1CMPLTU, 0, X1):
1254 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1255 case OE_RRR(V1CMPNE, 0, X0):
1256 case OE_RRR(V1CMPNE, 0, X1):
1257 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1258 gen_v1cmpne0(tdest);
1259 mnemonic = "v1cmpne";
1260 break;
1261 case OE_RRR(V1DDOTPUA, 0, X0):
1262 case OE_RRR(V1DDOTPUSA, 0, X0):
1263 case OE_RRR(V1DDOTPUS, 0, X0):
1264 case OE_RRR(V1DDOTPU, 0, X0):
1265 case OE_RRR(V1DOTPA, 0, X0):
1266 case OE_RRR(V1DOTPUA, 0, X0):
1267 case OE_RRR(V1DOTPUSA, 0, X0):
1268 case OE_RRR(V1DOTPUS, 0, X0):
1269 case OE_RRR(V1DOTPU, 0, X0):
1270 case OE_RRR(V1DOTP, 0, X0):
1271 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1272 case OE_RRR(V1INT_H, 0, X0):
1273 case OE_RRR(V1INT_H, 0, X1):
1274 gen_helper_v1int_h(tdest, tsrca, tsrcb);
1275 mnemonic = "v1int_h";
1276 break;
1277 case OE_RRR(V1INT_L, 0, X0):
1278 case OE_RRR(V1INT_L, 0, X1):
1279 gen_helper_v1int_l(tdest, tsrca, tsrcb);
1280 mnemonic = "v1int_l";
1281 break;
1282 case OE_RRR(V1MAXU, 0, X0):
1283 case OE_RRR(V1MAXU, 0, X1):
1284 case OE_RRR(V1MINU, 0, X0):
1285 case OE_RRR(V1MINU, 0, X1):
1286 case OE_RRR(V1MNZ, 0, X0):
1287 case OE_RRR(V1MNZ, 0, X1):
1288 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1289 case OE_RRR(V1MULTU, 0, X0):
1290 gen_helper_v1multu(tdest, tsrca, tsrcb);
1291 mnemonic = "v1multu";
1292 break;
1293 case OE_RRR(V1MULUS, 0, X0):
1294 case OE_RRR(V1MULU, 0, X0):
1295 case OE_RRR(V1MZ, 0, X0):
1296 case OE_RRR(V1MZ, 0, X1):
1297 case OE_RRR(V1SADAU, 0, X0):
1298 case OE_RRR(V1SADU, 0, X0):
1299 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1300 case OE_RRR(V1SHL, 0, X0):
1301 case OE_RRR(V1SHL, 0, X1):
1302 gen_helper_v1shl(tdest, tsrca, tsrcb);
1303 mnemonic = "v1shl";
1304 break;
1305 case OE_RRR(V1SHRS, 0, X0):
1306 case OE_RRR(V1SHRS, 0, X1):
1307 gen_helper_v1shrs(tdest, tsrca, tsrcb);
1308 mnemonic = "v1shrs";
1309 break;
1310 case OE_RRR(V1SHRU, 0, X0):
1311 case OE_RRR(V1SHRU, 0, X1):
1312 gen_helper_v1shru(tdest, tsrca, tsrcb);
1313 mnemonic = "v1shru";
1314 break;
1315 case OE_RRR(V1SUBUC, 0, X0):
1316 case OE_RRR(V1SUBUC, 0, X1):
1317 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1318 case OE_RRR(V1SUB, 0, X0):
1319 case OE_RRR(V1SUB, 0, X1):
1320 gen_v12sub(tdest, tsrca, tsrcb, V1_IMM(0x80));
1321 mnemonic = "v1sub";
1322 break;
1323 case OE_RRR(V2ADDSC, 0, X0):
1324 case OE_RRR(V2ADDSC, 0, X1):
1325 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1326 case OE_RRR(V2ADD, 0, X0):
1327 case OE_RRR(V2ADD, 0, X1):
1328 gen_v12add(tdest, tsrca, tsrcb, V2_IMM(0x8000));
1329 mnemonic = "v2add";
1330 break;
1331 case OE_RRR(V2ADIFFS, 0, X0):
1332 case OE_RRR(V2AVGS, 0, X0):
1333 case OE_RRR(V2CMPEQ, 0, X0):
1334 case OE_RRR(V2CMPEQ, 0, X1):
1335 case OE_RRR(V2CMPLES, 0, X0):
1336 case OE_RRR(V2CMPLES, 0, X1):
1337 case OE_RRR(V2CMPLEU, 0, X0):
1338 case OE_RRR(V2CMPLEU, 0, X1):
1339 case OE_RRR(V2CMPLTS, 0, X0):
1340 case OE_RRR(V2CMPLTS, 0, X1):
1341 case OE_RRR(V2CMPLTU, 0, X0):
1342 case OE_RRR(V2CMPLTU, 0, X1):
1343 case OE_RRR(V2CMPNE, 0, X0):
1344 case OE_RRR(V2CMPNE, 0, X1):
1345 case OE_RRR(V2DOTPA, 0, X0):
1346 case OE_RRR(V2DOTP, 0, X0):
1347 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1348 case OE_RRR(V2INT_H, 0, X0):
1349 case OE_RRR(V2INT_H, 0, X1):
1350 gen_helper_v2int_h(tdest, tsrca, tsrcb);
1351 mnemonic = "v2int_h";
1352 break;
1353 case OE_RRR(V2INT_L, 0, X0):
1354 case OE_RRR(V2INT_L, 0, X1):
1355 gen_helper_v2int_l(tdest, tsrca, tsrcb);
1356 mnemonic = "v2int_l";
1357 break;
1358 case OE_RRR(V2MAXS, 0, X0):
1359 case OE_RRR(V2MAXS, 0, X1):
1360 case OE_RRR(V2MINS, 0, X0):
1361 case OE_RRR(V2MINS, 0, X1):
1362 case OE_RRR(V2MNZ, 0, X0):
1363 case OE_RRR(V2MNZ, 0, X1):
1364 case OE_RRR(V2MULFSC, 0, X0):
1365 case OE_RRR(V2MULS, 0, X0):
1366 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1367 case OE_RRR(V2MULTS, 0, X0):
1368 gen_helper_v2mults(tdest, tsrca, tsrcb);
1369 mnemonic = "v2mults";
1370 break;
1371 case OE_RRR(V2MZ, 0, X0):
1372 case OE_RRR(V2MZ, 0, X1):
1373 case OE_RRR(V2PACKH, 0, X0):
1374 case OE_RRR(V2PACKH, 0, X1):
1375 case OE_RRR(V2PACKL, 0, X0):
1376 case OE_RRR(V2PACKL, 0, X1):
1377 case OE_RRR(V2PACKUC, 0, X0):
1378 case OE_RRR(V2PACKUC, 0, X1):
1379 case OE_RRR(V2SADAS, 0, X0):
1380 case OE_RRR(V2SADAU, 0, X0):
1381 case OE_RRR(V2SADS, 0, X0):
1382 case OE_RRR(V2SADU, 0, X0):
1383 case OE_RRR(V2SHLSC, 0, X0):
1384 case OE_RRR(V2SHLSC, 0, X1):
1385 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1386 case OE_RRR(V2SHL, 0, X0):
1387 case OE_RRR(V2SHL, 0, X1):
1388 gen_helper_v2shl(tdest, tsrca, tsrcb);
1389 mnemonic = "v2shl";
1390 break;
1391 case OE_RRR(V2SHRS, 0, X0):
1392 case OE_RRR(V2SHRS, 0, X1):
1393 gen_helper_v2shrs(tdest, tsrca, tsrcb);
1394 mnemonic = "v2shrs";
1395 break;
1396 case OE_RRR(V2SHRU, 0, X0):
1397 case OE_RRR(V2SHRU, 0, X1):
1398 gen_helper_v2shru(tdest, tsrca, tsrcb);
1399 mnemonic = "v2shru";
1400 break;
1401 case OE_RRR(V2SUBSC, 0, X0):
1402 case OE_RRR(V2SUBSC, 0, X1):
1403 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1404 case OE_RRR(V2SUB, 0, X0):
1405 case OE_RRR(V2SUB, 0, X1):
1406 gen_v12sub(tdest, tsrca, tsrcb, V2_IMM(0x8000));
1407 mnemonic = "v2sub";
1408 break;
1409 case OE_RRR(V4ADDSC, 0, X0):
1410 case OE_RRR(V4ADDSC, 0, X1):
1411 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1412 case OE_RRR(V4ADD, 0, X0):
1413 case OE_RRR(V4ADD, 0, X1):
1414 gen_v4op(tdest, tsrca, tsrcb, tcg_gen_add_i32);
1415 mnemonic = "v4add";
1416 break;
1417 case OE_RRR(V4INT_H, 0, X0):
1418 case OE_RRR(V4INT_H, 0, X1):
1419 tcg_gen_shri_tl(tdest, tsrcb, 32);
1420 tcg_gen_deposit_tl(tdest, tsrca, tdest, 0, 32);
1421 mnemonic = "v4int_h";
1422 break;
1423 case OE_RRR(V4INT_L, 0, X0):
1424 case OE_RRR(V4INT_L, 0, X1):
1425 tcg_gen_deposit_tl(tdest, tsrcb, tsrca, 32, 32);
1426 mnemonic = "v4int_l";
1427 break;
1428 case OE_RRR(V4PACKSC, 0, X0):
1429 case OE_RRR(V4PACKSC, 0, X1):
1430 case OE_RRR(V4SHLSC, 0, X0):
1431 case OE_RRR(V4SHLSC, 0, X1):
1432 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1433 case OE_RRR(V4SHL, 0, X0):
1434 case OE_RRR(V4SHL, 0, X1):
1435 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shl_i32);
1436 mnemonic = "v4shl";
1437 break;
1438 case OE_RRR(V4SHRS, 0, X0):
1439 case OE_RRR(V4SHRS, 0, X1):
1440 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_sar_i32);
1441 mnemonic = "v4shrs";
1442 break;
1443 case OE_RRR(V4SHRU, 0, X0):
1444 case OE_RRR(V4SHRU, 0, X1):
1445 gen_v4sh(tdest, tsrca, tsrcb, tcg_gen_shr_i32);
1446 mnemonic = "v4shru";
1447 break;
1448 case OE_RRR(V4SUBSC, 0, X0):
1449 case OE_RRR(V4SUBSC, 0, X1):
1450 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1451 case OE_RRR(V4SUB, 0, X0):
1452 case OE_RRR(V4SUB, 0, X1):
1453 gen_v4op(tdest, tsrca, tsrcb, tcg_gen_sub_i32);
1454 mnemonic = "v2sub";
1455 break;
1456 case OE_RRR(XOR, 0, X0):
1457 case OE_RRR(XOR, 0, X1):
1458 case OE_RRR(XOR, 5, Y0):
1459 case OE_RRR(XOR, 5, Y1):
1460 tcg_gen_xor_tl(tdest, tsrca, tsrcb);
1461 mnemonic = "xor";
1462 break;
1463 default:
1464 return TILEGX_EXCP_OPCODE_UNKNOWN;
1465 }
1466
1467 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %s", mnemonic,
1468 reg_names[dest], reg_names[srca], reg_names[srcb]);
1469 return TILEGX_EXCP_NONE;
1470 }
1471
1472 static TileExcp gen_rri_opcode(DisasContext *dc, unsigned opext,
1473 unsigned dest, unsigned srca, int imm)
1474 {
1475 TCGv tdest = dest_gr(dc, dest);
1476 TCGv tsrca = load_gr(dc, srca);
1477 bool prefetch_nofault = false;
1478 const char *mnemonic;
1479 TCGMemOp memop;
1480 int i2, i3;
1481 TCGv t0;
1482
1483 switch (opext) {
1484 case OE(ADDI_OPCODE_Y0, 0, Y0):
1485 case OE(ADDI_OPCODE_Y1, 0, Y1):
1486 case OE_IM(ADDI, X0):
1487 case OE_IM(ADDI, X1):
1488 tcg_gen_addi_tl(tdest, tsrca, imm);
1489 mnemonic = "addi";
1490 break;
1491 case OE(ADDXI_OPCODE_Y0, 0, Y0):
1492 case OE(ADDXI_OPCODE_Y1, 0, Y1):
1493 case OE_IM(ADDXI, X0):
1494 case OE_IM(ADDXI, X1):
1495 tcg_gen_addi_tl(tdest, tsrca, imm);
1496 tcg_gen_ext32s_tl(tdest, tdest);
1497 mnemonic = "addxi";
1498 break;
1499 case OE(ANDI_OPCODE_Y0, 0, Y0):
1500 case OE(ANDI_OPCODE_Y1, 0, Y1):
1501 case OE_IM(ANDI, X0):
1502 case OE_IM(ANDI, X1):
1503 tcg_gen_andi_tl(tdest, tsrca, imm);
1504 mnemonic = "andi";
1505 break;
1506 case OE(CMPEQI_OPCODE_Y0, 0, Y0):
1507 case OE(CMPEQI_OPCODE_Y1, 0, Y1):
1508 case OE_IM(CMPEQI, X0):
1509 case OE_IM(CMPEQI, X1):
1510 tcg_gen_setcondi_tl(TCG_COND_EQ, tdest, tsrca, imm);
1511 mnemonic = "cmpeqi";
1512 break;
1513 case OE(CMPLTSI_OPCODE_Y0, 0, Y0):
1514 case OE(CMPLTSI_OPCODE_Y1, 0, Y1):
1515 case OE_IM(CMPLTSI, X0):
1516 case OE_IM(CMPLTSI, X1):
1517 tcg_gen_setcondi_tl(TCG_COND_LT, tdest, tsrca, imm);
1518 mnemonic = "cmpltsi";
1519 break;
1520 case OE_IM(CMPLTUI, X0):
1521 case OE_IM(CMPLTUI, X1):
1522 tcg_gen_setcondi_tl(TCG_COND_LTU, tdest, tsrca, imm);
1523 mnemonic = "cmpltui";
1524 break;
1525 case OE_IM(LD1S_ADD, X1):
1526 memop = MO_SB;
1527 mnemonic = "ld1s_add"; /* prefetch_add_l1_fault */
1528 goto do_load_add;
1529 case OE_IM(LD1U_ADD, X1):
1530 memop = MO_UB;
1531 mnemonic = "ld1u_add"; /* prefetch_add_l1 */
1532 prefetch_nofault = (dest == TILEGX_R_ZERO);
1533 goto do_load_add;
1534 case OE_IM(LD2S_ADD, X1):
1535 memop = MO_TESW;
1536 mnemonic = "ld2s_add"; /* prefetch_add_l2_fault */
1537 goto do_load_add;
1538 case OE_IM(LD2U_ADD, X1):
1539 memop = MO_TEUW;
1540 mnemonic = "ld2u_add"; /* prefetch_add_l2 */
1541 prefetch_nofault = (dest == TILEGX_R_ZERO);
1542 goto do_load_add;
1543 case OE_IM(LD4S_ADD, X1):
1544 memop = MO_TESL;
1545 mnemonic = "ld4s_add"; /* prefetch_add_l3_fault */
1546 goto do_load_add;
1547 case OE_IM(LD4U_ADD, X1):
1548 memop = MO_TEUL;
1549 mnemonic = "ld4u_add"; /* prefetch_add_l3 */
1550 prefetch_nofault = (dest == TILEGX_R_ZERO);
1551 goto do_load_add;
1552 case OE_IM(LDNT1S_ADD, X1):
1553 memop = MO_SB;
1554 mnemonic = "ldnt1s_add";
1555 goto do_load_add;
1556 case OE_IM(LDNT1U_ADD, X1):
1557 memop = MO_UB;
1558 mnemonic = "ldnt1u_add";
1559 goto do_load_add;
1560 case OE_IM(LDNT2S_ADD, X1):
1561 memop = MO_TESW;
1562 mnemonic = "ldnt2s_add";
1563 goto do_load_add;
1564 case OE_IM(LDNT2U_ADD, X1):
1565 memop = MO_TEUW;
1566 mnemonic = "ldnt2u_add";
1567 goto do_load_add;
1568 case OE_IM(LDNT4S_ADD, X1):
1569 memop = MO_TESL;
1570 mnemonic = "ldnt4s_add";
1571 goto do_load_add;
1572 case OE_IM(LDNT4U_ADD, X1):
1573 memop = MO_TEUL;
1574 mnemonic = "ldnt4u_add";
1575 goto do_load_add;
1576 case OE_IM(LDNT_ADD, X1):
1577 memop = MO_TEQ;
1578 mnemonic = "ldnt_add";
1579 goto do_load_add;
1580 case OE_IM(LD_ADD, X1):
1581 memop = MO_TEQ;
1582 mnemonic = "ld_add";
1583 do_load_add:
1584 if (!prefetch_nofault) {
1585 tcg_gen_qemu_ld_tl(tdest, tsrca, dc->mmuidx, memop);
1586 }
1587 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1588 break;
1589 case OE_IM(LDNA_ADD, X1):
1590 tcg_gen_andi_tl(tdest, tsrca, ~7);
1591 tcg_gen_qemu_ld_tl(tdest, tdest, dc->mmuidx, MO_TEQ);
1592 tcg_gen_addi_tl(dest_gr(dc, srca), tsrca, imm);
1593 mnemonic = "ldna_add";
1594 break;
1595 case OE_IM(ORI, X0):
1596 case OE_IM(ORI, X1):
1597 tcg_gen_ori_tl(tdest, tsrca, imm);
1598 mnemonic = "ori";
1599 break;
1600 case OE_IM(V1ADDI, X0):
1601 case OE_IM(V1ADDI, X1):
1602 t0 = tcg_const_tl(V1_IMM(imm));
1603 gen_v12add(tdest, tsrca, t0, V1_IMM(0x80));
1604 tcg_temp_free(t0);
1605 mnemonic = "v1addi";
1606 break;
1607 case OE_IM(V1CMPEQI, X0):
1608 case OE_IM(V1CMPEQI, X1):
1609 tcg_gen_xori_tl(tdest, tsrca, V1_IMM(imm));
1610 gen_v1cmpeq0(tdest);
1611 mnemonic = "v1cmpeqi";
1612 break;
1613 case OE_IM(V1CMPLTSI, X0):
1614 case OE_IM(V1CMPLTSI, X1):
1615 case OE_IM(V1CMPLTUI, X0):
1616 case OE_IM(V1CMPLTUI, X1):
1617 case OE_IM(V1MAXUI, X0):
1618 case OE_IM(V1MAXUI, X1):
1619 case OE_IM(V1MINUI, X0):
1620 case OE_IM(V1MINUI, X1):
1621 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1622 case OE_IM(V2ADDI, X0):
1623 case OE_IM(V2ADDI, X1):
1624 t0 = tcg_const_tl(V2_IMM(imm));
1625 gen_v12add(tdest, tsrca, t0, V2_IMM(0x8000));
1626 tcg_temp_free(t0);
1627 mnemonic = "v2addi";
1628 break;
1629 case OE_IM(V2CMPEQI, X0):
1630 case OE_IM(V2CMPEQI, X1):
1631 case OE_IM(V2CMPLTSI, X0):
1632 case OE_IM(V2CMPLTSI, X1):
1633 case OE_IM(V2CMPLTUI, X0):
1634 case OE_IM(V2CMPLTUI, X1):
1635 case OE_IM(V2MAXSI, X0):
1636 case OE_IM(V2MAXSI, X1):
1637 case OE_IM(V2MINSI, X0):
1638 case OE_IM(V2MINSI, X1):
1639 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1640 case OE_IM(XORI, X0):
1641 case OE_IM(XORI, X1):
1642 tcg_gen_xori_tl(tdest, tsrca, imm);
1643 mnemonic = "xori";
1644 break;
1645
1646 case OE_SH(ROTLI, X0):
1647 case OE_SH(ROTLI, X1):
1648 case OE_SH(ROTLI, Y0):
1649 case OE_SH(ROTLI, Y1):
1650 tcg_gen_rotli_tl(tdest, tsrca, imm);
1651 mnemonic = "rotli";
1652 break;
1653 case OE_SH(SHLI, X0):
1654 case OE_SH(SHLI, X1):
1655 case OE_SH(SHLI, Y0):
1656 case OE_SH(SHLI, Y1):
1657 tcg_gen_shli_tl(tdest, tsrca, imm);
1658 mnemonic = "shli";
1659 break;
1660 case OE_SH(SHLXI, X0):
1661 case OE_SH(SHLXI, X1):
1662 tcg_gen_shli_tl(tdest, tsrca, imm & 31);
1663 tcg_gen_ext32s_tl(tdest, tdest);
1664 mnemonic = "shlxi";
1665 break;
1666 case OE_SH(SHRSI, X0):
1667 case OE_SH(SHRSI, X1):
1668 case OE_SH(SHRSI, Y0):
1669 case OE_SH(SHRSI, Y1):
1670 tcg_gen_sari_tl(tdest, tsrca, imm);
1671 mnemonic = "shrsi";
1672 break;
1673 case OE_SH(SHRUI, X0):
1674 case OE_SH(SHRUI, X1):
1675 case OE_SH(SHRUI, Y0):
1676 case OE_SH(SHRUI, Y1):
1677 tcg_gen_shri_tl(tdest, tsrca, imm);
1678 mnemonic = "shrui";
1679 break;
1680 case OE_SH(SHRUXI, X0):
1681 case OE_SH(SHRUXI, X1):
1682 if ((imm & 31) == 0) {
1683 tcg_gen_ext32s_tl(tdest, tsrca);
1684 } else {
1685 tcg_gen_ext32u_tl(tdest, tsrca);
1686 tcg_gen_shri_tl(tdest, tdest, imm & 31);
1687 }
1688 mnemonic = "shlxi";
1689 break;
1690 case OE_SH(V1SHLI, X0):
1691 case OE_SH(V1SHLI, X1):
1692 i2 = imm & 7;
1693 i3 = 0xff >> i2;
1694 tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
1695 tcg_gen_shli_tl(tdest, tdest, i2);
1696 mnemonic = "v1shli";
1697 break;
1698 case OE_SH(V1SHRSI, X0):
1699 case OE_SH(V1SHRSI, X1):
1700 t0 = tcg_const_tl(imm & 7);
1701 gen_helper_v1shrs(tdest, tsrca, t0);
1702 tcg_temp_free(t0);
1703 mnemonic = "v1shrsi";
1704 break;
1705 case OE_SH(V1SHRUI, X0):
1706 case OE_SH(V1SHRUI, X1):
1707 i2 = imm & 7;
1708 i3 = (0xff << i2) & 0xff;
1709 tcg_gen_andi_tl(tdest, tsrca, V1_IMM(i3));
1710 tcg_gen_shri_tl(tdest, tdest, i2);
1711 mnemonic = "v1shrui";
1712 break;
1713 case OE_SH(V2SHLI, X0):
1714 case OE_SH(V2SHLI, X1):
1715 i2 = imm & 15;
1716 i3 = 0xffff >> i2;
1717 tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3));
1718 tcg_gen_shli_tl(tdest, tdest, i2);
1719 mnemonic = "v2shli";
1720 break;
1721 case OE_SH(V2SHRSI, X0):
1722 case OE_SH(V2SHRSI, X1):
1723 t0 = tcg_const_tl(imm & 15);
1724 gen_helper_v2shrs(tdest, tsrca, t0);
1725 tcg_temp_free(t0);
1726 mnemonic = "v2shrsi";
1727 break;
1728 case OE_SH(V2SHRUI, X0):
1729 case OE_SH(V2SHRUI, X1):
1730 i2 = imm & 15;
1731 i3 = (0xffff << i2) & 0xffff;
1732 tcg_gen_andi_tl(tdest, tsrca, V2_IMM(i3));
1733 tcg_gen_shri_tl(tdest, tdest, i2);
1734 mnemonic = "v2shrui";
1735 break;
1736
1737 case OE(ADDLI_OPCODE_X0, 0, X0):
1738 case OE(ADDLI_OPCODE_X1, 0, X1):
1739 tcg_gen_addi_tl(tdest, tsrca, imm);
1740 mnemonic = "addli";
1741 break;
1742 case OE(ADDXLI_OPCODE_X0, 0, X0):
1743 case OE(ADDXLI_OPCODE_X1, 0, X1):
1744 tcg_gen_addi_tl(tdest, tsrca, imm);
1745 tcg_gen_ext32s_tl(tdest, tdest);
1746 mnemonic = "addxli";
1747 break;
1748 case OE(SHL16INSLI_OPCODE_X0, 0, X0):
1749 case OE(SHL16INSLI_OPCODE_X1, 0, X1):
1750 tcg_gen_shli_tl(tdest, tsrca, 16);
1751 tcg_gen_ori_tl(tdest, tdest, imm & 0xffff);
1752 mnemonic = "shl16insli";
1753 break;
1754
1755 default:
1756 return TILEGX_EXCP_OPCODE_UNKNOWN;
1757 }
1758
1759 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %d", mnemonic,
1760 reg_names[dest], reg_names[srca], imm);
1761 return TILEGX_EXCP_NONE;
1762 }
1763
1764 static TileExcp gen_bf_opcode_x0(DisasContext *dc, unsigned ext,
1765 unsigned dest, unsigned srca,
1766 unsigned bfs, unsigned bfe)
1767 {
1768 TCGv tdest = dest_gr(dc, dest);
1769 TCGv tsrca = load_gr(dc, srca);
1770 TCGv tsrcd;
1771 int len;
1772 const char *mnemonic;
1773
1774 /* The bitfield is either between E and S inclusive,
1775 or up from S and down from E inclusive. */
1776 if (bfs <= bfe) {
1777 len = bfe - bfs + 1;
1778 } else {
1779 len = (64 - bfs) + (bfe + 1);
1780 }
1781
1782 switch (ext) {
1783 case BFEXTU_BF_OPCODE_X0:
1784 if (bfs == 0 && bfe == 7) {
1785 tcg_gen_ext8u_tl(tdest, tsrca);
1786 } else if (bfs == 0 && bfe == 15) {
1787 tcg_gen_ext16u_tl(tdest, tsrca);
1788 } else if (bfs == 0 && bfe == 31) {
1789 tcg_gen_ext32u_tl(tdest, tsrca);
1790 } else {
1791 int rol = 63 - bfe;
1792 if (bfs <= bfe) {
1793 tcg_gen_shli_tl(tdest, tsrca, rol);
1794 } else {
1795 tcg_gen_rotli_tl(tdest, tsrca, rol);
1796 }
1797 tcg_gen_shri_tl(tdest, tdest, (bfs + rol) & 63);
1798 }
1799 mnemonic = "bfextu";
1800 break;
1801
1802 case BFEXTS_BF_OPCODE_X0:
1803 if (bfs == 0 && bfe == 7) {
1804 tcg_gen_ext8s_tl(tdest, tsrca);
1805 } else if (bfs == 0 && bfe == 15) {
1806 tcg_gen_ext16s_tl(tdest, tsrca);
1807 } else if (bfs == 0 && bfe == 31) {
1808 tcg_gen_ext32s_tl(tdest, tsrca);
1809 } else {
1810 int rol = 63 - bfe;
1811 if (bfs <= bfe) {
1812 tcg_gen_shli_tl(tdest, tsrca, rol);
1813 } else {
1814 tcg_gen_rotli_tl(tdest, tsrca, rol);
1815 }
1816 tcg_gen_sari_tl(tdest, tdest, (bfs + rol) & 63);
1817 }
1818 mnemonic = "bfexts";
1819 break;
1820
1821 case BFINS_BF_OPCODE_X0:
1822 tsrcd = load_gr(dc, dest);
1823 if (bfs <= bfe) {
1824 tcg_gen_deposit_tl(tdest, tsrcd, tsrca, bfs, len);
1825 } else {
1826 tcg_gen_rotri_tl(tdest, tsrcd, bfs);
1827 tcg_gen_deposit_tl(tdest, tdest, tsrca, 0, len);
1828 tcg_gen_rotli_tl(tdest, tdest, bfs);
1829 }
1830 mnemonic = "bfins";
1831 break;
1832
1833 case MM_BF_OPCODE_X0:
1834 tsrcd = load_gr(dc, dest);
1835 if (bfs == 0) {
1836 tcg_gen_deposit_tl(tdest, tsrca, tsrcd, 0, len);
1837 } else {
1838 uint64_t mask = len == 64 ? -1 : rol64((1ULL << len) - 1, bfs);
1839 TCGv tmp = tcg_const_tl(mask);
1840
1841 tcg_gen_and_tl(tdest, tsrcd, tmp);
1842 tcg_gen_andc_tl(tmp, tsrca, tmp);
1843 tcg_gen_or_tl(tdest, tdest, tmp);
1844 tcg_temp_free(tmp);
1845 }
1846 mnemonic = "mm";
1847 break;
1848
1849 default:
1850 return TILEGX_EXCP_OPCODE_UNKNOWN;
1851 }
1852
1853 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s, %u, %u", mnemonic,
1854 reg_names[dest], reg_names[srca], bfs, bfe);
1855 return TILEGX_EXCP_NONE;
1856 }
1857
1858 static TileExcp gen_branch_opcode_x1(DisasContext *dc, unsigned ext,
1859 unsigned srca, int off)
1860 {
1861 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1862 const char *mnemonic;
1863
1864 dc->jmp.dest = tcg_const_tl(tgt);
1865 dc->jmp.val1 = tcg_temp_new();
1866 tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
1867
1868 /* Note that the "predict taken" opcodes have bit 0 clear.
1869 Therefore, fold the two cases together by setting bit 0. */
1870 switch (ext | 1) {
1871 case BEQZ_BRANCH_OPCODE_X1:
1872 dc->jmp.cond = TCG_COND_EQ;
1873 mnemonic = "beqz";
1874 break;
1875 case BNEZ_BRANCH_OPCODE_X1:
1876 dc->jmp.cond = TCG_COND_NE;
1877 mnemonic = "bnez";
1878 break;
1879 case BGEZ_BRANCH_OPCODE_X1:
1880 dc->jmp.cond = TCG_COND_GE;
1881 mnemonic = "bgez";
1882 break;
1883 case BGTZ_BRANCH_OPCODE_X1:
1884 dc->jmp.cond = TCG_COND_GT;
1885 mnemonic = "bgtz";
1886 break;
1887 case BLEZ_BRANCH_OPCODE_X1:
1888 dc->jmp.cond = TCG_COND_LE;
1889 mnemonic = "blez";
1890 break;
1891 case BLTZ_BRANCH_OPCODE_X1:
1892 dc->jmp.cond = TCG_COND_LT;
1893 mnemonic = "bltz";
1894 break;
1895 case BLBC_BRANCH_OPCODE_X1:
1896 dc->jmp.cond = TCG_COND_EQ;
1897 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1898 mnemonic = "blbc";
1899 break;
1900 case BLBS_BRANCH_OPCODE_X1:
1901 dc->jmp.cond = TCG_COND_NE;
1902 tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
1903 mnemonic = "blbs";
1904 break;
1905 default:
1906 return TILEGX_EXCP_OPCODE_UNKNOWN;
1907 }
1908
1909 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1910 qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
1911 mnemonic, ext & 1 ? "" : "t",
1912 reg_names[srca], tgt, lookup_symbol(tgt));
1913 }
1914 return TILEGX_EXCP_NONE;
1915 }
1916
1917 static TileExcp gen_jump_opcode_x1(DisasContext *dc, unsigned ext, int off)
1918 {
1919 target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
1920 const char *mnemonic = "j";
1921
1922 /* The extension field is 1 bit, therefore we only have JAL and J. */
1923 if (ext == JAL_JUMP_OPCODE_X1) {
1924 tcg_gen_movi_tl(dest_gr(dc, TILEGX_R_LR),
1925 dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
1926 mnemonic = "jal";
1927 }
1928 dc->jmp.cond = TCG_COND_ALWAYS;
1929 dc->jmp.dest = tcg_const_tl(tgt);
1930
1931 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1932 qemu_log("%s " TARGET_FMT_lx " <%s>",
1933 mnemonic, tgt, lookup_symbol(tgt));
1934 }
1935 return TILEGX_EXCP_NONE;
1936 }
1937
1938 typedef struct {
1939 const char *name;
1940 intptr_t offset;
1941 void (*get)(TCGv, TCGv_ptr);
1942 void (*put)(TCGv_ptr, TCGv);
1943 } TileSPR;
1944
1945 static const TileSPR *find_spr(unsigned spr)
1946 {
1947 /* Allow the compiler to construct the binary search tree. */
1948 #define D(N, O, G, P) \
1949 case SPR_##N: { static const TileSPR x = { #N, O, G, P }; return &x; }
1950
1951 switch (spr) {
1952 D(CMPEXCH_VALUE,
1953 offsetof(CPUTLGState, spregs[TILEGX_SPR_CMPEXCH]), 0, 0)
1954 D(INTERRUPT_CRITICAL_SECTION,
1955 offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
1956 D(SIM_CONTROL,
1957 offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
1958 D(EX_CONTEXT_0_0,
1959 offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_0]), 0, 0)
1960 D(EX_CONTEXT_0_1,
1961 offsetof(CPUTLGState, spregs[TILEGX_SPR_EX_CONTEXT_0_1]), 0, 0)
1962 }
1963
1964 #undef D
1965
1966 qemu_log_mask(LOG_UNIMP, "UNIMP SPR %u\n", spr);
1967 return NULL;
1968 }
1969
1970 static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned spr, unsigned srca)
1971 {
1972 const TileSPR *def = find_spr(spr);
1973 TCGv tsrca;
1974
1975 if (def == NULL) {
1976 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr, reg_names[srca]);
1977 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1978 }
1979
1980 tsrca = load_gr(dc, srca);
1981 if (def->put) {
1982 def->put(cpu_env, tsrca);
1983 } else {
1984 tcg_gen_st_tl(tsrca, cpu_env, def->offset);
1985 }
1986 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name, reg_names[srca]);
1987 return TILEGX_EXCP_NONE;
1988 }
1989
1990 static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned dest, unsigned spr)
1991 {
1992 const TileSPR *def = find_spr(spr);
1993 TCGv tdest;
1994
1995 if (def == NULL) {
1996 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest], spr);
1997 return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
1998 }
1999
2000 tdest = dest_gr(dc, dest);
2001 if (def->get) {
2002 def->get(tdest, cpu_env);
2003 } else {
2004 tcg_gen_ld_tl(tdest, cpu_env, def->offset);
2005 }
2006 qemu_log_mask(CPU_LOG_TB_IN_ASM, "mfspr %s, %s", reg_names[dest], def->name);
2007 return TILEGX_EXCP_NONE;
2008 }
2009
2010 static TileExcp decode_y0(DisasContext *dc, tilegx_bundle_bits bundle)
2011 {
2012 unsigned opc = get_Opcode_Y0(bundle);
2013 unsigned ext = get_RRROpcodeExtension_Y0(bundle);
2014 unsigned dest = get_Dest_Y0(bundle);
2015 unsigned srca = get_SrcA_Y0(bundle);
2016 unsigned srcb;
2017 int imm;
2018
2019 switch (opc) {
2020 case RRR_1_OPCODE_Y0:
2021 if (ext == UNARY_RRR_1_OPCODE_Y0) {
2022 ext = get_UnaryOpcodeExtension_Y0(bundle);
2023 return gen_rr_opcode(dc, OE(opc, ext, Y0), dest, srca, bundle);
2024 }
2025 /* fallthru */
2026 case RRR_0_OPCODE_Y0:
2027 case RRR_2_OPCODE_Y0:
2028 case RRR_3_OPCODE_Y0:
2029 case RRR_4_OPCODE_Y0:
2030 case RRR_5_OPCODE_Y0:
2031 case RRR_6_OPCODE_Y0:
2032 case RRR_7_OPCODE_Y0:
2033 case RRR_8_OPCODE_Y0:
2034 case RRR_9_OPCODE_Y0:
2035 srcb = get_SrcB_Y0(bundle);
2036 return gen_rrr_opcode(dc, OE(opc, ext, Y0), dest, srca, srcb);
2037
2038 case SHIFT_OPCODE_Y0:
2039 ext = get_ShiftOpcodeExtension_Y0(bundle);
2040 imm = get_ShAmt_Y0(bundle);
2041 return gen_rri_opcode(dc, OE(opc, ext, Y0), dest, srca, imm);
2042
2043 case ADDI_OPCODE_Y0:
2044 case ADDXI_OPCODE_Y0:
2045 case ANDI_OPCODE_Y0:
2046 case CMPEQI_OPCODE_Y0:
2047 case CMPLTSI_OPCODE_Y0:
2048 imm = (int8_t)get_Imm8_Y0(bundle);
2049 return gen_rri_opcode(dc, OE(opc, 0, Y0), dest, srca, imm);
2050
2051 default:
2052 return TILEGX_EXCP_OPCODE_UNKNOWN;
2053 }
2054 }
2055
2056 static TileExcp decode_y1(DisasContext *dc, tilegx_bundle_bits bundle)
2057 {
2058 unsigned opc = get_Opcode_Y1(bundle);
2059 unsigned ext = get_RRROpcodeExtension_Y1(bundle);
2060 unsigned dest = get_Dest_Y1(bundle);
2061 unsigned srca = get_SrcA_Y1(bundle);
2062 unsigned srcb;
2063 int imm;
2064
2065 switch (get_Opcode_Y1(bundle)) {
2066 case RRR_1_OPCODE_Y1:
2067 if (ext == UNARY_RRR_1_OPCODE_Y0) {
2068 ext = get_UnaryOpcodeExtension_Y1(bundle);
2069 return gen_rr_opcode(dc, OE(opc, ext, Y1), dest, srca, bundle);
2070 }
2071 /* fallthru */
2072 case RRR_0_OPCODE_Y1:
2073 case RRR_2_OPCODE_Y1:
2074 case RRR_3_OPCODE_Y1:
2075 case RRR_4_OPCODE_Y1:
2076 case RRR_5_OPCODE_Y1:
2077 case RRR_6_OPCODE_Y1:
2078 case RRR_7_OPCODE_Y1:
2079 srcb = get_SrcB_Y1(bundle);
2080 return gen_rrr_opcode(dc, OE(opc, ext, Y1), dest, srca, srcb);
2081
2082 case SHIFT_OPCODE_Y1:
2083 ext = get_ShiftOpcodeExtension_Y1(bundle);
2084 imm = get_ShAmt_Y1(bundle);
2085 return gen_rri_opcode(dc, OE(opc, ext, Y1), dest, srca, imm);
2086
2087 case ADDI_OPCODE_Y1:
2088 case ADDXI_OPCODE_Y1:
2089 case ANDI_OPCODE_Y1:
2090 case CMPEQI_OPCODE_Y1:
2091 case CMPLTSI_OPCODE_Y1:
2092 imm = (int8_t)get_Imm8_Y1(bundle);
2093 return gen_rri_opcode(dc, OE(opc, 0, Y1), dest, srca, imm);
2094
2095 default:
2096 return TILEGX_EXCP_OPCODE_UNKNOWN;
2097 }
2098 }
2099
2100 static TileExcp decode_y2(DisasContext *dc, tilegx_bundle_bits bundle)
2101 {
2102 unsigned mode = get_Mode(bundle);
2103 unsigned opc = get_Opcode_Y2(bundle);
2104 unsigned srca = get_SrcA_Y2(bundle);
2105 unsigned srcbdest = get_SrcBDest_Y2(bundle);
2106 const char *mnemonic;
2107 TCGMemOp memop;
2108 bool prefetch_nofault = false;
2109
2110 switch (OEY2(opc, mode)) {
2111 case OEY2(LD1S_OPCODE_Y2, MODE_OPCODE_YA2):
2112 memop = MO_SB;
2113 mnemonic = "ld1s"; /* prefetch_l1_fault */
2114 goto do_load;
2115 case OEY2(LD1U_OPCODE_Y2, MODE_OPCODE_YA2):
2116 memop = MO_UB;
2117 mnemonic = "ld1u"; /* prefetch, prefetch_l1 */
2118 prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
2119 goto do_load;
2120 case OEY2(LD2S_OPCODE_Y2, MODE_OPCODE_YA2):
2121 memop = MO_TESW;
2122 mnemonic = "ld2s"; /* prefetch_l2_fault */
2123 goto do_load;
2124 case OEY2(LD2U_OPCODE_Y2, MODE_OPCODE_YA2):
2125 memop = MO_TEUW;
2126 mnemonic = "ld2u"; /* prefetch_l2 */
2127 prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
2128 goto do_load;
2129 case OEY2(LD4S_OPCODE_Y2, MODE_OPCODE_YB2):
2130 memop = MO_TESL;
2131 mnemonic = "ld4s"; /* prefetch_l3_fault */
2132 goto do_load;
2133 case OEY2(LD4U_OPCODE_Y2, MODE_OPCODE_YB2):
2134 memop = MO_TEUL;
2135 mnemonic = "ld4u"; /* prefetch_l3 */
2136 prefetch_nofault = (srcbdest == TILEGX_R_ZERO);
2137 goto do_load;
2138 case OEY2(LD_OPCODE_Y2, MODE_OPCODE_YB2):
2139 memop = MO_TEQ;
2140 mnemonic = "ld";
2141 do_load:
2142 if (!prefetch_nofault) {
2143 tcg_gen_qemu_ld_tl(dest_gr(dc, srcbdest), load_gr(dc, srca),
2144 dc->mmuidx, memop);
2145 }
2146 qemu_log_mask(CPU_LOG_TB_IN_ASM, "%s %s, %s", mnemonic,
2147 reg_names[srcbdest], reg_names[srca]);
2148 return TILEGX_EXCP_NONE;
2149
2150 case OEY2(ST1_OPCODE_Y2, MODE_OPCODE_YC2):
2151 return gen_st_opcode(dc, 0, srca, srcbdest, MO_UB, "st1");
2152 case OEY2(ST2_OPCODE_Y2, MODE_OPCODE_YC2):
2153 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUW, "st2");
2154 case OEY2(ST4_OPCODE_Y2, MODE_OPCODE_YC2):
2155 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEUL, "st4");
2156 case OEY2(ST_OPCODE_Y2, MODE_OPCODE_YC2):
2157 return gen_st_opcode(dc, 0, srca, srcbdest, MO_TEQ, "st");
2158
2159 default:
2160 return TILEGX_EXCP_OPCODE_UNKNOWN;
2161 }
2162 }
2163
2164 static TileExcp decode_x0(DisasContext *dc, tilegx_bundle_bits bundle)
2165 {
2166 unsigned opc = get_Opcode_X0(bundle);
2167 unsigned dest = get_Dest_X0(bundle);
2168 unsigned srca = get_SrcA_X0(bundle);
2169 unsigned ext, srcb, bfs, bfe;
2170 int imm;
2171
2172 switch (opc) {
2173 case RRR_0_OPCODE_X0:
2174 ext = get_RRROpcodeExtension_X0(bundle);
2175 if (ext == UNARY_RRR_0_OPCODE_X0) {
2176 ext = get_UnaryOpcodeExtension_X0(bundle);
2177 return gen_rr_opcode(dc, OE(opc, ext, X0), dest, srca, bundle);
2178 }
2179 srcb = get_SrcB_X0(bundle);
2180 return gen_rrr_opcode(dc, OE(opc, ext, X0), dest, srca, srcb);
2181
2182 case SHIFT_OPCODE_X0:
2183 ext = get_ShiftOpcodeExtension_X0(bundle);
2184 imm = get_ShAmt_X0(bundle);
2185 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
2186
2187 case IMM8_OPCODE_X0:
2188 ext = get_Imm8OpcodeExtension_X0(bundle);
2189 imm = (int8_t)get_Imm8_X0(bundle);
2190 return gen_rri_opcode(dc, OE(opc, ext, X0), dest, srca, imm);
2191
2192 case BF_OPCODE_X0:
2193 ext = get_BFOpcodeExtension_X0(bundle);
2194 bfs = get_BFStart_X0(bundle);
2195 bfe = get_BFEnd_X0(bundle);
2196 return gen_bf_opcode_x0(dc, ext, dest, srca, bfs, bfe);
2197
2198 case ADDLI_OPCODE_X0:
2199 case SHL16INSLI_OPCODE_X0:
2200 case ADDXLI_OPCODE_X0:
2201 imm = (int16_t)get_Imm16_X0(bundle);
2202 return gen_rri_opcode(dc, OE(opc, 0, X0), dest, srca, imm);
2203
2204 default:
2205 return TILEGX_EXCP_OPCODE_UNKNOWN;
2206 }
2207 }
2208
2209 static TileExcp decode_x1(DisasContext *dc, tilegx_bundle_bits bundle)
2210 {
2211 unsigned opc = get_Opcode_X1(bundle);
2212 unsigned dest = get_Dest_X1(bundle);
2213 unsigned srca = get_SrcA_X1(bundle);
2214 unsigned ext, srcb;
2215 int imm;
2216
2217 switch (opc) {
2218 case RRR_0_OPCODE_X1:
2219 ext = get_RRROpcodeExtension_X1(bundle);
2220 srcb = get_SrcB_X1(bundle);
2221 switch (ext) {
2222 case UNARY_RRR_0_OPCODE_X1:
2223 ext = get_UnaryOpcodeExtension_X1(bundle);
2224 return gen_rr_opcode(dc, OE(opc, ext, X1), dest, srca, bundle);
2225 case ST1_RRR_0_OPCODE_X1:
2226 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "st1");
2227 case ST2_RRR_0_OPCODE_X1:
2228 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "st2");
2229 case ST4_RRR_0_OPCODE_X1:
2230 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "st4");
2231 case STNT1_RRR_0_OPCODE_X1:
2232 return gen_st_opcode(dc, dest, srca, srcb, MO_UB, "stnt1");
2233 case STNT2_RRR_0_OPCODE_X1:
2234 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUW, "stnt2");
2235 case STNT4_RRR_0_OPCODE_X1:
2236 return gen_st_opcode(dc, dest, srca, srcb, MO_TEUL, "stnt4");
2237 case STNT_RRR_0_OPCODE_X1:
2238 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "stnt");
2239 case ST_RRR_0_OPCODE_X1:
2240 return gen_st_opcode(dc, dest, srca, srcb, MO_TEQ, "st");
2241 }
2242 return gen_rrr_opcode(dc, OE(opc, ext, X1), dest, srca, srcb);
2243
2244 case SHIFT_OPCODE_X1:
2245 ext = get_ShiftOpcodeExtension_X1(bundle);
2246 imm = get_ShAmt_X1(bundle);
2247 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
2248
2249 case IMM8_OPCODE_X1:
2250 ext = get_Imm8OpcodeExtension_X1(bundle);
2251 imm = (int8_t)get_Dest_Imm8_X1(bundle);
2252 srcb = get_SrcB_X1(bundle);
2253 switch (ext) {
2254 case ST1_ADD_IMM8_OPCODE_X1:
2255 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "st1_add");
2256 case ST2_ADD_IMM8_OPCODE_X1:
2257 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "st2_add");
2258 case ST4_ADD_IMM8_OPCODE_X1:
2259 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "st4_add");
2260 case STNT1_ADD_IMM8_OPCODE_X1:
2261 return gen_st_add_opcode(dc, srca, srcb, imm, MO_UB, "stnt1_add");
2262 case STNT2_ADD_IMM8_OPCODE_X1:
2263 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUW, "stnt2_add");
2264 case STNT4_ADD_IMM8_OPCODE_X1:
2265 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEUL, "stnt4_add");
2266 case STNT_ADD_IMM8_OPCODE_X1:
2267 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "stnt_add");
2268 case ST_ADD_IMM8_OPCODE_X1:
2269 return gen_st_add_opcode(dc, srca, srcb, imm, MO_TEQ, "st_add");
2270 case MFSPR_IMM8_OPCODE_X1:
2271 return gen_mfspr_x1(dc, dest, get_MF_Imm14_X1(bundle));
2272 case MTSPR_IMM8_OPCODE_X1:
2273 return gen_mtspr_x1(dc, get_MT_Imm14_X1(bundle), srca);
2274 }
2275 imm = (int8_t)get_Imm8_X1(bundle);
2276 return gen_rri_opcode(dc, OE(opc, ext, X1), dest, srca, imm);
2277
2278 case BRANCH_OPCODE_X1:
2279 ext = get_BrType_X1(bundle);
2280 imm = sextract32(get_BrOff_X1(bundle), 0, 17);
2281 return gen_branch_opcode_x1(dc, ext, srca, imm);
2282
2283 case JUMP_OPCODE_X1:
2284 ext = get_JumpOpcodeExtension_X1(bundle);
2285 imm = sextract32(get_JumpOff_X1(bundle), 0, 27);
2286 return gen_jump_opcode_x1(dc, ext, imm);
2287
2288 case ADDLI_OPCODE_X1:
2289 case SHL16INSLI_OPCODE_X1:
2290 case ADDXLI_OPCODE_X1:
2291 imm = (int16_t)get_Imm16_X1(bundle);
2292 return gen_rri_opcode(dc, OE(opc, 0, X1), dest, srca, imm);
2293
2294 default:
2295 return TILEGX_EXCP_OPCODE_UNKNOWN;
2296 }
2297 }
2298
2299 static void notice_excp(DisasContext *dc, uint64_t bundle,
2300 const char *type, TileExcp excp)
2301 {
2302 if (likely(excp == TILEGX_EXCP_NONE)) {
2303 return;
2304 }
2305 gen_exception(dc, excp);
2306 switch (excp) {
2307 case TILEGX_EXCP_OPCODE_UNIMPLEMENTED:
2308 qemu_log_mask(LOG_UNIMP, "UNIMP %s, [" FMT64X "]\n", type, bundle);
2309 break;
2310 case TILEGX_EXCP_OPCODE_UNKNOWN:
2311 qemu_log_mask(LOG_UNIMP, "UNKNOWN %s, [" FMT64X "]\n", type, bundle);
2312 break;
2313 default:
2314 break;
2315 }
2316 }
2317
2318 static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
2319 {
2320 int i;
2321
2322 for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
2323 DisasContextTemp *wb = &dc->wb[i];
2324 wb->reg = TILEGX_R_NOREG;
2325 TCGV_UNUSED_I64(wb->val);
2326 }
2327 dc->num_wb = 0;
2328
2329 qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);
2330 if (get_Mode(bundle)) {
2331 notice_excp(dc, bundle, "y0", decode_y0(dc, bundle));
2332 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2333 notice_excp(dc, bundle, "y1", decode_y1(dc, bundle));
2334 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2335 notice_excp(dc, bundle, "y2", decode_y2(dc, bundle));
2336 } else {
2337 notice_excp(dc, bundle, "x0", decode_x0(dc, bundle));
2338 qemu_log_mask(CPU_LOG_TB_IN_ASM, " ; ");
2339 notice_excp(dc, bundle, "x1", decode_x1(dc, bundle));
2340 }
2341 qemu_log_mask(CPU_LOG_TB_IN_ASM, " }\n");
2342
2343 for (i = dc->num_wb - 1; i >= 0; --i) {
2344 DisasContextTemp *wb = &dc->wb[i];
2345 if (wb->reg < TILEGX_R_COUNT) {
2346 tcg_gen_mov_i64(cpu_regs[wb->reg], wb->val);
2347 }
2348 tcg_temp_free_i64(wb->val);
2349 }
2350
2351 if (dc->jmp.cond != TCG_COND_NEVER) {
2352 if (dc->jmp.cond == TCG_COND_ALWAYS) {
2353 tcg_gen_mov_i64(cpu_pc, dc->jmp.dest);
2354 } else {
2355 TCGv next = tcg_const_i64(dc->pc + TILEGX_BUNDLE_SIZE_IN_BYTES);
2356 tcg_gen_movcond_i64(dc->jmp.cond, cpu_pc,
2357 dc->jmp.val1, load_zero(dc),
2358 dc->jmp.dest, next);
2359 tcg_temp_free_i64(dc->jmp.val1);
2360 tcg_temp_free_i64(next);
2361 }
2362 tcg_temp_free_i64(dc->jmp.dest);
2363 tcg_gen_exit_tb(0);
2364 dc->exit_tb = true;
2365 } else if (dc->atomic_excp != TILEGX_EXCP_NONE) {
2366 gen_exception(dc, dc->atomic_excp);
2367 }
2368 }
2369
2370 void gen_intermediate_code(CPUTLGState *env, struct TranslationBlock *tb)
2371 {
2372 TileGXCPU *cpu = tilegx_env_get_cpu(env);
2373 DisasContext ctx;
2374 DisasContext *dc = &ctx;
2375 CPUState *cs = CPU(cpu);
2376 uint64_t pc_start = tb->pc;
2377 uint64_t next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2378 int num_insns = 0;
2379 int max_insns = tb->cflags & CF_COUNT_MASK;
2380
2381 dc->pc = pc_start;
2382 dc->mmuidx = 0;
2383 dc->exit_tb = false;
2384 dc->atomic_excp = TILEGX_EXCP_NONE;
2385 dc->jmp.cond = TCG_COND_NEVER;
2386 TCGV_UNUSED_I64(dc->jmp.dest);
2387 TCGV_UNUSED_I64(dc->jmp.val1);
2388 TCGV_UNUSED_I64(dc->zero);
2389
2390 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
2391 qemu_log("IN: %s\n", lookup_symbol(pc_start));
2392 }
2393 if (!max_insns) {
2394 max_insns = CF_COUNT_MASK;
2395 }
2396 if (cs->singlestep_enabled || singlestep) {
2397 max_insns = 1;
2398 }
2399 if (max_insns > TCG_MAX_INSNS) {
2400 max_insns = TCG_MAX_INSNS;
2401 }
2402 gen_tb_start(tb);
2403
2404 while (1) {
2405 tcg_gen_insn_start(dc->pc);
2406 num_insns++;
2407
2408 translate_one_bundle(dc, cpu_ldq_data(env, dc->pc));
2409
2410 if (dc->exit_tb) {
2411 /* PC updated and EXIT_TB/GOTO_TB/exception emitted. */
2412 break;
2413 }
2414 dc->pc += TILEGX_BUNDLE_SIZE_IN_BYTES;
2415 if (num_insns >= max_insns
2416 || dc->pc >= next_page_start
2417 || tcg_op_buf_full()) {
2418 /* Ending the TB due to TB size or page boundary. Set PC. */
2419 tcg_gen_movi_tl(cpu_pc, dc->pc);
2420 tcg_gen_exit_tb(0);
2421 break;
2422 }
2423 }
2424
2425 gen_tb_end(tb, num_insns);
2426 tb->size = dc->pc - pc_start;
2427 tb->icount = num_insns;
2428
2429 qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
2430 }
2431
2432 void restore_state_to_opc(CPUTLGState *env, TranslationBlock *tb,
2433 target_ulong *data)
2434 {
2435 env->pc = data[0];
2436 }
2437
2438 void tilegx_tcg_init(void)
2439 {
2440 int i;
2441
2442 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
2443 cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUTLGState, pc), "pc");
2444 for (i = 0; i < TILEGX_R_COUNT; i++) {
2445 cpu_regs[i] = tcg_global_mem_new_i64(TCG_AREG0,
2446 offsetof(CPUTLGState, regs[i]),
2447 reg_names[i]);
2448 }
2449 }
AR7 emulation for QEMU