hw/timer/m48t59-isa.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/isa/isa.h"
  28 #include "hw/timer/m48t59.h"
  29 #include "m48t59-internal.h"
  30 #include "qemu/module.h"
  31
  32 #define TYPE_M48TXX_ISA "isa-m48txx"
  33 #define M48TXX_ISA_GET_CLASS(obj) \
  34     OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
  35 #define M48TXX_ISA_CLASS(klass) \
  36     OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
  37 #define M48TXX_ISA(obj) \
  38     OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
  39
  40 typedef struct M48txxISAState {
  41     ISADevice parent_obj;
  42     M48t59State state;
  43     uint32_t io_base;
  44     MemoryRegion io;
  45 } M48txxISAState;
  46
  47 typedef struct M48txxISADeviceClass {
  48     ISADeviceClass parent_class;
  49     M48txxInfo info;
  50 } M48txxISADeviceClass;
  51
  52 static M48txxInfo m48txx_isa_info[] = {
  53     {
  54         .bus_name = "isa-m48t59",
  55         .model = 59,
  56         .size = 0x2000,
  57     }
  58 };
  59
  60 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
  61                        int base_year, int model)
  62 {
  63     DeviceState *dev;
  64     int i;
  65
  66     for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
  67         if (m48txx_isa_info[i].size != size ||
  68             m48txx_isa_info[i].model != model) {
  69             continue;
  70         }
  71
  72         dev = DEVICE(isa_create(bus, m48txx_isa_info[i].bus_name));
  73         qdev_prop_set_uint32(dev, "iobase", io_base);
  74         qdev_prop_set_int32(dev, "base-year", base_year);
  75         qdev_init_nofail(dev);
  76         return NVRAM(dev);
  77     }
  78
  79     assert(false);
  80     return NULL;
  81 }
  82
  83 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
  84 {
  85     M48txxISAState *d = M48TXX_ISA(obj);
  86     return m48t59_read(&d->state, addr);
  87 }
  88
  89 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
  90 {
  91     M48txxISAState *d = M48TXX_ISA(obj);
  92     m48t59_write(&d->state, addr, val);
  93 }
  94
  95 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
  96 {
  97     M48txxISAState *d = M48TXX_ISA(obj);
  98     m48t59_toggle_lock(&d->state, lock);
  99 }
 100
 101 static Property m48t59_isa_properties[] = {
 102     DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
 103     DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
 104     DEFINE_PROP_END_OF_LIST(),
 105 };
 106
 107 static void m48t59_reset_isa(DeviceState *d)
 108 {
 109     M48txxISAState *isa = M48TXX_ISA(d);
 110     M48t59State *NVRAM = &isa->state;
 111
 112     m48t59_reset_common(NVRAM);
 113 }
 114
 115 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
 116 {
 117     M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
 118     ISADevice *isadev = ISA_DEVICE(dev);
 119     M48txxISAState *d = M48TXX_ISA(dev);
 120     M48t59State *s = &d->state;
 121
 122     s->model = u->info.model;
 123     s->size = u->info.size;
 124     isa_init_irq(isadev, &s->IRQ, 8);
 125     m48t59_realize_common(s, errp);
 126     memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
 127     if (d->io_base != 0) {
 128         isa_register_ioport(isadev, &d->io, d->io_base);
 129     }
 130 }
 131
 132 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
 133 {
 134     DeviceClass *dc = DEVICE_CLASS(klass);
 135     NvramClass *nc = NVRAM_CLASS(klass);
 136
 137     dc->realize = m48t59_isa_realize;
 138     dc->reset = m48t59_reset_isa;
 139     dc->props = m48t59_isa_properties;
 140     nc->read = m48txx_isa_read;
 141     nc->write = m48txx_isa_write;
 142     nc->toggle_lock = m48txx_isa_toggle_lock;
 143 }
 144
 145 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
 146 {
 147     M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
 148     M48txxInfo *info = data;
 149
 150     u->info = *info;
 151 }
 152
 153 static const TypeInfo m48txx_isa_type_info = {
 154     .name = TYPE_M48TXX_ISA,
 155     .parent = TYPE_ISA_DEVICE,
 156     .instance_size = sizeof(M48txxISAState),
 157     .abstract = true,
 158     .class_init = m48txx_isa_class_init,
 159     .interfaces = (InterfaceInfo[]) {
 160         { TYPE_NVRAM },
 161         { }
 162     }
 163 };
 164
 165 static void m48t59_isa_register_types(void)
 166 {
 167     TypeInfo isa_type_info = {
 168         .parent = TYPE_M48TXX_ISA,
 169         .class_size = sizeof(M48txxISADeviceClass),
 170         .class_init = m48txx_isa_concrete_class_init,
 171     };
 172     int i;
 173
 174     type_register_static(&m48txx_isa_type_info);
 175
 176     for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) {
 177         isa_type_info.name = m48txx_isa_info[i].bus_name;
 178         isa_type_info.class_data = &m48txx_isa_info[i];
 179         type_register(&isa_type_info);
 180     }
 181 }
 182
 183 type_init(m48t59_isa_register_types)