hw/ppc/pnv_occ.c

   1 /*
   2  * QEMU PowerPC PowerNV Emulation of a few OCC related registers
   3  *
   4  * Copyright (c) 2015-2017, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License, version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "hw/hw.h"
  21 #include "sysemu/sysemu.h"
  22 #include "target/ppc/cpu.h"
  23 #include "qapi/error.h"
  24 #include "qemu/log.h"
  25 #include "qemu/module.h"
  26
  27 #include "hw/ppc/pnv.h"
  28 #include "hw/ppc/pnv_xscom.h"
  29 #include "hw/ppc/pnv_occ.h"
  30
  31 #define OCB_OCI_OCCMISC         0x4020
  32 #define OCB_OCI_OCCMISC_AND     0x4021
  33 #define OCB_OCI_OCCMISC_OR      0x4022
  34
  35 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
  36 {
  37     bool irq_state;
  38     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
  39
  40     val &= 0xffff000000000000ull;
  41
  42     occ->occmisc = val;
  43     irq_state = !!(val >> 63);
  44     pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
  45 }
  46
  47 static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
  48                                           unsigned size)
  49 {
  50     PnvOCC *occ = PNV_OCC(opaque);
  51     uint32_t offset = addr >> 3;
  52     uint64_t val = 0;
  53
  54     switch (offset) {
  55     case OCB_OCI_OCCMISC:
  56         val = occ->occmisc;
  57         break;
  58     default:
  59         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
  60                       HWADDR_PRIx "\n", addr >> 3);
  61     }
  62     return val;
  63 }
  64
  65 static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr,
  66                                        uint64_t val, unsigned size)
  67 {
  68     PnvOCC *occ = PNV_OCC(opaque);
  69     uint32_t offset = addr >> 3;
  70
  71     switch (offset) {
  72     case OCB_OCI_OCCMISC_AND:
  73         pnv_occ_set_misc(occ, occ->occmisc & val);
  74         break;
  75     case OCB_OCI_OCCMISC_OR:
  76         pnv_occ_set_misc(occ, occ->occmisc | val);
  77         break;
  78     case OCB_OCI_OCCMISC:
  79         pnv_occ_set_misc(occ, val);
  80         break;
  81     default:
  82         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
  83                       HWADDR_PRIx "\n", addr >> 3);
  84     }
  85 }
  86
  87 static const MemoryRegionOps pnv_occ_power8_xscom_ops = {
  88     .read = pnv_occ_power8_xscom_read,
  89     .write = pnv_occ_power8_xscom_write,
  90     .valid.min_access_size = 8,
  91     .valid.max_access_size = 8,
  92     .impl.min_access_size = 8,
  93     .impl.max_access_size = 8,
  94     .endianness = DEVICE_BIG_ENDIAN,
  95 };
  96
  97 static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
  98 {
  99     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
 100
 101     poc->xscom_size = PNV_XSCOM_OCC_SIZE;
 102     poc->xscom_ops = &pnv_occ_power8_xscom_ops;
 103     poc->psi_irq = PSIHB_IRQ_OCC;
 104 }
 105
 106 static const TypeInfo pnv_occ_power8_type_info = {
 107     .name          = TYPE_PNV8_OCC,
 108     .parent        = TYPE_PNV_OCC,
 109     .instance_size = sizeof(PnvOCC),
 110     .class_init    = pnv_occ_power8_class_init,
 111 };
 112
 113 #define P9_OCB_OCI_OCCMISC              0x6080
 114 #define P9_OCB_OCI_OCCMISC_CLEAR        0x6081
 115 #define P9_OCB_OCI_OCCMISC_OR           0x6082
 116
 117
 118 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr,
 119                                           unsigned size)
 120 {
 121     PnvOCC *occ = PNV_OCC(opaque);
 122     uint32_t offset = addr >> 3;
 123     uint64_t val = 0;
 124
 125     switch (offset) {
 126     case P9_OCB_OCI_OCCMISC:
 127         val = occ->occmisc;
 128         break;
 129     default:
 130         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
 131                       HWADDR_PRIx "\n", addr >> 3);
 132     }
 133     return val;
 134 }
 135
 136 static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr,
 137                                        uint64_t val, unsigned size)
 138 {
 139     PnvOCC *occ = PNV_OCC(opaque);
 140     uint32_t offset = addr >> 3;
 141
 142     switch (offset) {
 143     case P9_OCB_OCI_OCCMISC_CLEAR:
 144         pnv_occ_set_misc(occ, 0);
 145         break;
 146     case P9_OCB_OCI_OCCMISC_OR:
 147         pnv_occ_set_misc(occ, occ->occmisc | val);
 148         break;
 149     case P9_OCB_OCI_OCCMISC:
 150         pnv_occ_set_misc(occ, val);
 151        break;
 152     default:
 153         qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%"
 154                       HWADDR_PRIx "\n", addr >> 3);
 155     }
 156 }
 157
 158 static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
 159     .read = pnv_occ_power9_xscom_read,
 160     .write = pnv_occ_power9_xscom_write,
 161     .valid.min_access_size = 8,
 162     .valid.max_access_size = 8,
 163     .impl.min_access_size = 8,
 164     .impl.max_access_size = 8,
 165     .endianness = DEVICE_BIG_ENDIAN,
 166 };
 167
 168 static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
 169 {
 170     PnvOCCClass *poc = PNV_OCC_CLASS(klass);
 171
 172     poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
 173     poc->xscom_ops = &pnv_occ_power9_xscom_ops;
 174     poc->psi_irq = PSIHB9_IRQ_OCC;
 175 }
 176
 177 static const TypeInfo pnv_occ_power9_type_info = {
 178     .name          = TYPE_PNV9_OCC,
 179     .parent        = TYPE_PNV_OCC,
 180     .instance_size = sizeof(PnvOCC),
 181     .class_init    = pnv_occ_power9_class_init,
 182 };
 183
 184 static void pnv_occ_realize(DeviceState *dev, Error **errp)
 185 {
 186     PnvOCC *occ = PNV_OCC(dev);
 187     PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
 188     Object *obj;
 189     Error *local_err = NULL;
 190
 191     occ->occmisc = 0;
 192
 193     obj = object_property_get_link(OBJECT(dev), "psi", &local_err);
 194     if (!obj) {
 195         error_propagate(errp, local_err);
 196         error_prepend(errp, "required link 'psi' not found: ");
 197         return;
 198     }
 199     occ->psi = PNV_PSI(obj);
 200
 201     /* XScom region for OCC registers */
 202     pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops,
 203                           occ, "xscom-occ", poc->xscom_size);
 204 }
 205
 206 static void pnv_occ_class_init(ObjectClass *klass, void *data)
 207 {
 208     DeviceClass *dc = DEVICE_CLASS(klass);
 209
 210     dc->realize = pnv_occ_realize;
 211     dc->desc = "PowerNV OCC Controller";
 212 }
 213
 214 static const TypeInfo pnv_occ_type_info = {
 215     .name          = TYPE_PNV_OCC,
 216     .parent        = TYPE_DEVICE,
 217     .instance_size = sizeof(PnvOCC),
 218     .class_init    = pnv_occ_class_init,
 219     .class_size    = sizeof(PnvOCCClass),
 220     .abstract      = true,
 221 };
 222
 223 static void pnv_occ_register_types(void)
 224 {
 225     type_register_static(&pnv_occ_type_info);
 226     type_register_static(&pnv_occ_power8_type_info);
 227     type_register_static(&pnv_occ_power9_type_info);
 228 }
 229
 230 type_init(pnv_occ_register_types);