hw/i2c/smbus_eeprom.c

   1 /*
   2  * QEMU SMBus EEPROM device
   3  *
   4  * Copyright (c) 2007 Arastra, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/units.h"
  27 #include "qapi/error.h"
  28 #include "hw/hw.h"
  29 #include "hw/boards.h"
  30 #include "hw/i2c/i2c.h"
  31 #include "hw/i2c/smbus_slave.h"
  32 #include "hw/i2c/smbus_eeprom.h"
  33
  34 //#define DEBUG
  35
  36 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
  37
  38 #define SMBUS_EEPROM(obj) \
  39     OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM)
  40
  41 #define SMBUS_EEPROM_SIZE 256
  42
  43 typedef struct SMBusEEPROMDevice {
  44     SMBusDevice smbusdev;
  45     uint8_t data[SMBUS_EEPROM_SIZE];
  46     void *init_data;
  47     uint8_t offset;
  48     bool accessed;
  49 } SMBusEEPROMDevice;
  50
  51 static uint8_t eeprom_receive_byte(SMBusDevice *dev)
  52 {
  53     SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
  54     uint8_t *data = eeprom->data;
  55     uint8_t val = data[eeprom->offset++];
  56
  57     eeprom->accessed = true;
  58 #ifdef DEBUG
  59     printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n",
  60            dev->i2c.address, val);
  61 #endif
  62     return val;
  63 }
  64
  65 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len)
  66 {
  67     SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
  68     uint8_t *data = eeprom->data;
  69
  70     eeprom->accessed = true;
  71 #ifdef DEBUG
  72     printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n",
  73            dev->i2c.address, buf[0], buf[1]);
  74 #endif
  75     /* len is guaranteed to be > 0 */
  76     eeprom->offset = buf[0];
  77     buf++;
  78     len--;
  79
  80     for (; len > 0; len--) {
  81         data[eeprom->offset] = *buf++;
  82         eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE;
  83     }
  84
  85     return 0;
  86 }
  87
  88 static bool smbus_eeprom_vmstate_needed(void *opaque)
  89 {
  90     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
  91     SMBusEEPROMDevice *eeprom = opaque;
  92
  93     return (eeprom->accessed || smbus_vmstate_needed(&eeprom->smbusdev)) &&
  94         !mc->smbus_no_migration_support;
  95 }
  96
  97 static const VMStateDescription vmstate_smbus_eeprom = {
  98     .name = "smbus-eeprom",
  99     .version_id = 1,
 100     .minimum_version_id = 1,
 101     .needed = smbus_eeprom_vmstate_needed,
 102     .fields      = (VMStateField[]) {
 103         VMSTATE_SMBUS_DEVICE(smbusdev, SMBusEEPROMDevice),
 104         VMSTATE_UINT8_ARRAY(data, SMBusEEPROMDevice, SMBUS_EEPROM_SIZE),
 105         VMSTATE_UINT8(offset, SMBusEEPROMDevice),
 106         VMSTATE_BOOL(accessed, SMBusEEPROMDevice),
 107         VMSTATE_END_OF_LIST()
 108     }
 109 };
 110
 111 /*
 112  * Reset the EEPROM contents to the initial state on a reset.  This
 113  * isn't really how an EEPROM works, of course, but the general
 114  * principle of QEMU is to restore function on reset to what it would
 115  * be if QEMU was stopped and started.
 116  *
 117  * The proper thing to do would be to have a backing blockdev to hold
 118  * the contents and restore that on startup, and not do this on reset.
 119  * But until that time, act as if we had been stopped and restarted.
 120  */
 121 static void smbus_eeprom_reset(DeviceState *dev)
 122 {
 123     SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
 124
 125     memcpy(eeprom->data, eeprom->init_data, SMBUS_EEPROM_SIZE);
 126     eeprom->offset = 0;
 127 }
 128
 129 static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
 130 {
 131     smbus_eeprom_reset(dev);
 132 }
 133
 134 static Property smbus_eeprom_properties[] = {
 135     DEFINE_PROP_PTR("data", SMBusEEPROMDevice, init_data),
 136     DEFINE_PROP_END_OF_LIST(),
 137 };
 138
 139 static void smbus_eeprom_class_initfn(ObjectClass *klass, void *data)
 140 {
 141     DeviceClass *dc = DEVICE_CLASS(klass);
 142     SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass);
 143
 144     dc->realize = smbus_eeprom_realize;
 145     dc->reset = smbus_eeprom_reset;
 146     sc->receive_byte = eeprom_receive_byte;
 147     sc->write_data = eeprom_write_data;
 148     dc->props = smbus_eeprom_properties;
 149     dc->vmsd = &vmstate_smbus_eeprom;
 150     /* Reason: pointer property "data" */
 151     dc->user_creatable = false;
 152 }
 153
 154 static const TypeInfo smbus_eeprom_info = {
 155     .name          = TYPE_SMBUS_EEPROM,
 156     .parent        = TYPE_SMBUS_DEVICE,
 157     .instance_size = sizeof(SMBusEEPROMDevice),
 158     .class_init    = smbus_eeprom_class_initfn,
 159 };
 160
 161 static void smbus_eeprom_register_types(void)
 162 {
 163     type_register_static(&smbus_eeprom_info);
 164 }
 165
 166 type_init(smbus_eeprom_register_types)
 167
 168 void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, uint8_t *eeprom_buf)
 169 {
 170     DeviceState *dev;
 171
 172     dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM);
 173     qdev_prop_set_uint8(dev, "address", address);
 174     qdev_prop_set_ptr(dev, "data", eeprom_buf);
 175     qdev_init_nofail(dev);
 176 }
 177
 178 void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
 179                        const uint8_t *eeprom_spd, int eeprom_spd_size)
 180 {
 181     int i;
 182      /* XXX: make this persistent */
 183
 184     assert(nb_eeprom <= 8);
 185     uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE);
 186     if (eeprom_spd_size > 0) {
 187         memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
 188     }
 189
 190     for (i = 0; i < nb_eeprom; i++) {
 191         smbus_eeprom_init_one(smbus, 0x50 + i,
 192                               eeprom_buf + (i * SMBUS_EEPROM_SIZE));
 193     }
 194 }
 195
 196 /* Generate SDRAM SPD EEPROM data describing a module of type and size */
 197 uint8_t *spd_data_generate(enum sdram_type type, ram_addr_t ram_size,
 198                            Error **errp)
 199 {
 200     uint8_t *spd;
 201     uint8_t nbanks;
 202     uint16_t density;
 203     uint32_t size;
 204     int min_log2, max_log2, sz_log2;
 205     int i;
 206
 207     switch (type) {
 208     case SDR:
 209         min_log2 = 2;
 210         max_log2 = 9;
 211         break;
 212     case DDR:
 213         min_log2 = 5;
 214         max_log2 = 12;
 215         break;
 216     case DDR2:
 217         min_log2 = 7;
 218         max_log2 = 14;
 219         break;
 220     default:
 221         g_assert_not_reached();
 222     }
 223     size = ram_size >> 20; /* work in terms of megabytes */
 224     if (size < 4) {
 225         error_setg(errp, "SDRAM size is too small");
 226         return NULL;
 227     }
 228     sz_log2 = 31 - clz32(size);
 229     size = 1U << sz_log2;
 230     if (ram_size > size * MiB) {
 231         error_setg(errp, "SDRAM size 0x"RAM_ADDR_FMT" is not a power of 2, "
 232                    "truncating to %u MB", ram_size, size);
 233     }
 234     if (sz_log2 < min_log2) {
 235         error_setg(errp,
 236                    "Memory size is too small for SDRAM type, adjusting type");
 237         if (size >= 32) {
 238             type = DDR;
 239             min_log2 = 5;
 240             max_log2 = 12;
 241         } else {
 242             type = SDR;
 243             min_log2 = 2;
 244             max_log2 = 9;
 245         }
 246     }
 247
 248     nbanks = 1;
 249     while (sz_log2 > max_log2 && nbanks < 8) {
 250         sz_log2--;
 251         nbanks++;
 252     }
 253
 254     if (size > (1ULL << sz_log2) * nbanks) {
 255         error_setg(errp, "Memory size is too big for SDRAM, truncating");
 256     }
 257
 258     /* split to 2 banks if possible to avoid a bug in MIPS Malta firmware */
 259     if (nbanks == 1 && sz_log2 > min_log2) {
 260         sz_log2--;
 261         nbanks++;
 262     }
 263
 264     density = 1ULL << (sz_log2 - 2);
 265     switch (type) {
 266     case DDR2:
 267         density = (density & 0xe0) | (density >> 8 & 0x1f);
 268         break;
 269     case DDR:
 270         density = (density & 0xf8) | (density >> 8 & 0x07);
 271         break;
 272     case SDR:
 273     default:
 274         density &= 0xff;
 275         break;
 276     }
 277
 278     spd = g_malloc0(256);
 279     spd[0] = 128;   /* data bytes in EEPROM */
 280     spd[1] = 8;     /* log2 size of EEPROM */
 281     spd[2] = type;
 282     spd[3] = 13;    /* row address bits */
 283     spd[4] = 10;    /* column address bits */
 284     spd[5] = (type == DDR2 ? nbanks - 1 : nbanks);
 285     spd[6] = 64;    /* module data width */
 286                     /* reserved / data width high */
 287     spd[8] = 4;     /* interface voltage level */
 288     spd[9] = 0x25;  /* highest CAS latency */
 289     spd[10] = 1;    /* access time */
 290                     /* DIMM configuration 0 = non-ECC */
 291     spd[12] = 0x82; /* refresh requirements */
 292     spd[13] = 8;    /* primary SDRAM width */
 293                     /* ECC SDRAM width */
 294     spd[15] = (type == DDR2 ? 0 : 1); /* reserved / delay for random col rd */
 295     spd[16] = 12;   /* burst lengths supported */
 296     spd[17] = 4;    /* banks per SDRAM device */
 297     spd[18] = 12;   /* ~CAS latencies supported */
 298     spd[19] = (type == DDR2 ? 0 : 1); /* reserved / ~CS latencies supported */
 299     spd[20] = 2;    /* DIMM type / ~WE latencies */
 300                     /* module features */
 301                     /* memory chip features */
 302     spd[23] = 0x12; /* clock cycle time @ medium CAS latency */
 303                     /* data access time */
 304                     /* clock cycle time @ short CAS latency */
 305                     /* data access time */
 306     spd[27] = 20;   /* min. row precharge time */
 307     spd[28] = 15;   /* min. row active row delay */
 308     spd[29] = 20;   /* min. ~RAS to ~CAS delay */
 309     spd[30] = 45;   /* min. active to precharge time */
 310     spd[31] = density;
 311     spd[32] = 20;   /* addr/cmd setup time */
 312     spd[33] = 8;    /* addr/cmd hold time */
 313     spd[34] = 20;   /* data input setup time */
 314     spd[35] = 8;    /* data input hold time */
 315
 316     /* checksum */
 317     for (i = 0; i < 63; i++) {
 318         spd[63] += spd[i];
 319     }
 320     return spd;
 321 }