hw/arm/nrf51_soc.c

   1 /*
   2  * Nordic Semiconductor nRF51 SoC
   3  * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
   4  *
   5  * Copyright 2018 Joel Stanley <joel@jms.id.au>
   6  *
   7  * This code is licensed under the GPL version 2 or later.  See
   8  * the COPYING file in the top-level directory.
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qapi/error.h"
  13 #include "hw/arm/boot.h"
  14 #include "hw/sysbus.h"
  15 #include "hw/boards.h"
  16 #include "hw/misc/unimp.h"
  17 #include "exec/address-spaces.h"
  18 #include "sysemu/sysemu.h"
  19 #include "qemu/log.h"
  20 #include "cpu.h"
  21
  22 #include "hw/arm/nrf51.h"
  23 #include "hw/arm/nrf51_soc.h"
  24
  25 /*
  26  * The size and base is for the NRF51822 part. If other parts
  27  * are supported in the future, add a sub-class of NRF51SoC for
  28  * the specific variants
  29  */
  30 #define NRF51822_FLASH_PAGES    256
  31 #define NRF51822_SRAM_PAGES     16
  32 #define NRF51822_FLASH_SIZE     (NRF51822_FLASH_PAGES * NRF51_PAGE_SIZE)
  33 #define NRF51822_SRAM_SIZE      (NRF51822_SRAM_PAGES * NRF51_PAGE_SIZE)
  34
  35 #define BASE_TO_IRQ(base) ((base >> 12) & 0x1F)
  36
  37 static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
  38 {
  39     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
  40                   __func__, addr, size);
  41     return 1;
  42 }
  43
  44 static void clock_write(void *opaque, hwaddr addr, uint64_t data,
  45                         unsigned int size)
  46 {
  47     qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]\n",
  48                   __func__, addr, data, size);
  49 }
  50
  51 static const MemoryRegionOps clock_ops = {
  52     .read = clock_read,
  53     .write = clock_write
  54 };
  55
  56
  57 static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp)
  58 {
  59     NRF51State *s = NRF51_SOC(dev_soc);
  60     MemoryRegion *mr;
  61     Error *err = NULL;
  62     uint8_t i = 0;
  63     hwaddr base_addr = 0;
  64
  65     if (!s->board_memory) {
  66         error_setg(errp, "memory property was not set");
  67         return;
  68     }
  69
  70     object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memory",
  71             &err);
  72     if (err) {
  73         error_propagate(errp, err);
  74         return;
  75     }
  76     object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
  77     if (err) {
  78         error_propagate(errp, err);
  79         return;
  80     }
  81
  82     memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -1);
  83
  84     memory_region_init_ram(&s->sram, OBJECT(s), "nrf51.sram", s->sram_size,
  85                            &err);
  86     if (err) {
  87         error_propagate(errp, err);
  88         return;
  89     }
  90     memory_region_add_subregion(&s->container, NRF51_SRAM_BASE, &s->sram);
  91
  92     /* UART */
  93     object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
  94     if (err) {
  95         error_propagate(errp, err);
  96         return;
  97     }
  98     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0);
  99     memory_region_add_subregion_overlap(&s->container, NRF51_UART_BASE, mr, 0);
 100     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0,
 101                        qdev_get_gpio_in(DEVICE(&s->cpu),
 102                        BASE_TO_IRQ(NRF51_UART_BASE)));
 103
 104     /* RNG */
 105     object_property_set_bool(OBJECT(&s->rng), true, "realized", &err);
 106     if (err) {
 107         error_propagate(errp, err);
 108         return;
 109     }
 110
 111     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0);
 112     memory_region_add_subregion_overlap(&s->container, NRF51_RNG_BASE, mr, 0);
 113     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0,
 114                        qdev_get_gpio_in(DEVICE(&s->cpu),
 115                        BASE_TO_IRQ(NRF51_RNG_BASE)));
 116
 117     /* UICR, FICR, NVMC, FLASH */
 118     object_property_set_uint(OBJECT(&s->nvm), s->flash_size, "flash-size",
 119                              &err);
 120     if (err) {
 121         error_propagate(errp, err);
 122         return;
 123     }
 124
 125     object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err);
 126     if (err) {
 127         error_propagate(errp, err);
 128         return;
 129     }
 130
 131     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0);
 132     memory_region_add_subregion_overlap(&s->container, NRF51_NVMC_BASE, mr, 0);
 133     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1);
 134     memory_region_add_subregion_overlap(&s->container, NRF51_FICR_BASE, mr, 0);
 135     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2);
 136     memory_region_add_subregion_overlap(&s->container, NRF51_UICR_BASE, mr, 0);
 137     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 3);
 138     memory_region_add_subregion_overlap(&s->container, NRF51_FLASH_BASE, mr, 0);
 139
 140     /* GPIO */
 141     object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
 142     if (err) {
 143         error_propagate(errp, err);
 144         return;
 145     }
 146
 147     mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0);
 148     memory_region_add_subregion_overlap(&s->container, NRF51_GPIO_BASE, mr, 0);
 149
 150     /* Pass all GPIOs to the SOC layer so they are available to the board */
 151     qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL);
 152
 153     /* TIMER */
 154     for (i = 0; i < NRF51_NUM_TIMERS; i++) {
 155         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 156         if (err) {
 157             error_propagate(errp, err);
 158             return;
 159         }
 160
 161         base_addr = NRF51_TIMER_BASE + i * NRF51_TIMER_SIZE;
 162
 163         sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, base_addr);
 164         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0,
 165                            qdev_get_gpio_in(DEVICE(&s->cpu),
 166                                             BASE_TO_IRQ(base_addr)));
 167     }
 168
 169     /* STUB Peripherals */
 170     memory_region_init_io(&s->clock, NULL, &clock_ops, NULL,
 171                           "nrf51_soc.clock", 0x1000);
 172     memory_region_add_subregion_overlap(&s->container,
 173                                         NRF51_IOMEM_BASE, &s->clock, -1);
 174
 175     create_unimplemented_device("nrf51_soc.io", NRF51_IOMEM_BASE,
 176                                 NRF51_IOMEM_SIZE);
 177     create_unimplemented_device("nrf51_soc.private",
 178                                 NRF51_PRIVATE_BASE, NRF51_PRIVATE_SIZE);
 179 }
 180
 181 static void nrf51_soc_init(Object *obj)
 182 {
 183     uint8_t i = 0;
 184
 185     NRF51State *s = NRF51_SOC(obj);
 186
 187     memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX);
 188
 189     sysbus_init_child_obj(OBJECT(s), "armv6m", OBJECT(&s->cpu), sizeof(s->cpu),
 190                           TYPE_ARMV7M);
 191     qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type",
 192                          ARM_CPU_TYPE_NAME("cortex-m0"));
 193     qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32);
 194
 195     sysbus_init_child_obj(obj, "uart", &s->uart, sizeof(s->uart),
 196                            TYPE_NRF51_UART);
 197     object_property_add_alias(obj, "serial0", OBJECT(&s->uart), "chardev",
 198                               &error_abort);
 199
 200     sysbus_init_child_obj(obj, "rng", &s->rng, sizeof(s->rng),
 201                            TYPE_NRF51_RNG);
 202
 203     sysbus_init_child_obj(obj, "nvm", &s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM);
 204
 205     sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio),
 206                           TYPE_NRF51_GPIO);
 207
 208     for (i = 0; i < NRF51_NUM_TIMERS; i++) {
 209         sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
 210                               sizeof(s->timer[i]), TYPE_NRF51_TIMER);
 211
 212     }
 213 }
 214
 215 static Property nrf51_soc_properties[] = {
 216     DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGION,
 217                      MemoryRegion *),
 218     DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE),
 219     DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size,
 220                        NRF51822_FLASH_SIZE),
 221     DEFINE_PROP_END_OF_LIST(),
 222 };
 223
 224 static void nrf51_soc_class_init(ObjectClass *klass, void *data)
 225 {
 226     DeviceClass *dc = DEVICE_CLASS(klass);
 227
 228     dc->realize = nrf51_soc_realize;
 229     dc->props = nrf51_soc_properties;
 230 }
 231
 232 static const TypeInfo nrf51_soc_info = {
 233     .name          = TYPE_NRF51_SOC,
 234     .parent        = TYPE_SYS_BUS_DEVICE,
 235     .instance_size = sizeof(NRF51State),
 236     .instance_init = nrf51_soc_init,
 237     .class_init    = nrf51_soc_class_init,
 238 };
 239
 240 static void nrf51_soc_types(void)
 241 {
 242     type_register_static(&nrf51_soc_info);
 243 }
 244 type_init(nrf51_soc_types)