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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170109' into...
[qemu/ar7.git] / target / i386 / kvm.c
blob10a9cd8f7f3d2d5fb2d2d559824d9c5871383d40
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/kvm_int.h"
27 #include "kvm_i386.h"
28 #include "hyperv.h"
29
30 #include "exec/gdbstub.h"
31 #include "qemu/host-utils.h"
32 #include "qemu/config-file.h"
33 #include "qemu/error-report.h"
34 #include "hw/i386/pc.h"
35 #include "hw/i386/apic.h"
36 #include "hw/i386/apic_internal.h"
37 #include "hw/i386/apic-msidef.h"
38 #include "hw/i386/intel_iommu.h"
39 #include "hw/i386/x86-iommu.h"
40
41 #include "exec/ioport.h"
42 #include "standard-headers/asm-x86/hyperv.h"
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "migration/migration.h"
46 #include "exec/memattrs.h"
47 #include "trace.h"
48
49 //#define DEBUG_KVM
50
51 #ifdef DEBUG_KVM
52 #define DPRINTF(fmt, ...) \
53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54 #else
55 #define DPRINTF(fmt, ...) \
56 do { } while (0)
57 #endif
58
59 #define MSR_KVM_WALL_CLOCK 0x11
60 #define MSR_KVM_SYSTEM_TIME 0x12
61
62 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64 #define MSR_BUF_SIZE 4096
65
66 #ifndef BUS_MCEERR_AR
67 #define BUS_MCEERR_AR 4
68 #endif
69 #ifndef BUS_MCEERR_AO
70 #define BUS_MCEERR_AO 5
71 #endif
72
73 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
74 KVM_CAP_INFO(SET_TSS_ADDR),
75 KVM_CAP_INFO(EXT_CPUID),
76 KVM_CAP_INFO(MP_STATE),
77 KVM_CAP_LAST_INFO
78 };
79
80 static bool has_msr_star;
81 static bool has_msr_hsave_pa;
82 static bool has_msr_tsc_aux;
83 static bool has_msr_tsc_adjust;
84 static bool has_msr_tsc_deadline;
85 static bool has_msr_feature_control;
86 static bool has_msr_misc_enable;
87 static bool has_msr_smbase;
88 static bool has_msr_bndcfgs;
89 static int lm_capable_kernel;
90 static bool has_msr_hv_hypercall;
91 static bool has_msr_hv_crash;
92 static bool has_msr_hv_reset;
93 static bool has_msr_hv_vpindex;
94 static bool has_msr_hv_runtime;
95 static bool has_msr_hv_synic;
96 static bool has_msr_hv_stimer;
97 static bool has_msr_xss;
98
99 static bool has_msr_architectural_pmu;
100 static uint32_t num_architectural_pmu_counters;
101
102 static int has_xsave;
103 static int has_xcrs;
104 static int has_pit_state2;
105
106 static bool has_msr_mcg_ext_ctl;
107
108 static struct kvm_cpuid2 *cpuid_cache;
109
110 int kvm_has_pit_state2(void)
111 {
112 return has_pit_state2;
113 }
114
115 bool kvm_has_smm(void)
116 {
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118 }
119
120 bool kvm_has_adjust_clock_stable(void)
121 {
122 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
123
124 return (ret == KVM_CLOCK_TSC_STABLE);
125 }
126
127 bool kvm_allows_irq0_override(void)
128 {
129 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
130 }
131
132 static bool kvm_x2apic_api_set_flags(uint64_t flags)
133 {
134 KVMState *s = KVM_STATE(current_machine->accelerator);
135
136 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
137 }
138
139 #define MEMORIZE(fn, _result) \
140 ({ \
141 static bool _memorized; \
142 \
143 if (_memorized) { \
144 return _result; \
145 } \
146 _memorized = true; \
147 _result = fn; \
148 })
149
150 static bool has_x2apic_api;
151
152 bool kvm_has_x2apic_api(void)
153 {
154 return has_x2apic_api;
155 }
156
157 bool kvm_enable_x2apic(void)
158 {
159 return MEMORIZE(
160 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
161 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
162 has_x2apic_api);
163 }
164
165 static int kvm_get_tsc(CPUState *cs)
166 {
167 X86CPU *cpu = X86_CPU(cs);
168 CPUX86State *env = &cpu->env;
169 struct {
170 struct kvm_msrs info;
171 struct kvm_msr_entry entries[1];
172 } msr_data;
173 int ret;
174
175 if (env->tsc_valid) {
176 return 0;
177 }
178
179 msr_data.info.nmsrs = 1;
180 msr_data.entries[0].index = MSR_IA32_TSC;
181 env->tsc_valid = !runstate_is_running();
182
183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
184 if (ret < 0) {
185 return ret;
186 }
187
188 assert(ret == 1);
189 env->tsc = msr_data.entries[0].data;
190 return 0;
191 }
192
193 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
194 {
195 kvm_get_tsc(cpu);
196 }
197
198 void kvm_synchronize_all_tsc(void)
199 {
200 CPUState *cpu;
201
202 if (kvm_enabled()) {
203 CPU_FOREACH(cpu) {
204 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
205 }
206 }
207 }
208
209 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
210 {
211 struct kvm_cpuid2 *cpuid;
212 int r, size;
213
214 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
215 cpuid = g_malloc0(size);
216 cpuid->nent = max;
217 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
218 if (r == 0 && cpuid->nent >= max) {
219 r = -E2BIG;
220 }
221 if (r < 0) {
222 if (r == -E2BIG) {
223 g_free(cpuid);
224 return NULL;
225 } else {
226 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
227 strerror(-r));
228 exit(1);
229 }
230 }
231 return cpuid;
232 }
233
234 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
235 * for all entries.
236 */
237 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
238 {
239 struct kvm_cpuid2 *cpuid;
240 int max = 1;
241
242 if (cpuid_cache != NULL) {
243 return cpuid_cache;
244 }
245 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
246 max *= 2;
247 }
248 cpuid_cache = cpuid;
249 return cpuid;
250 }
251
252 static const struct kvm_para_features {
253 int cap;
254 int feature;
255 } para_features[] = {
256 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
257 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
258 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
259 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
260 };
261
262 static int get_para_features(KVMState *s)
263 {
264 int i, features = 0;
265
266 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
267 if (kvm_check_extension(s, para_features[i].cap)) {
268 features |= (1 << para_features[i].feature);
269 }
270 }
271
272 return features;
273 }
274
275
276 /* Returns the value for a specific register on the cpuid entry
277 */
278 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
279 {
280 uint32_t ret = 0;
281 switch (reg) {
282 case R_EAX:
283 ret = entry->eax;
284 break;
285 case R_EBX:
286 ret = entry->ebx;
287 break;
288 case R_ECX:
289 ret = entry->ecx;
290 break;
291 case R_EDX:
292 ret = entry->edx;
293 break;
294 }
295 return ret;
296 }
297
298 /* Find matching entry for function/index on kvm_cpuid2 struct
299 */
300 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
301 uint32_t function,
302 uint32_t index)
303 {
304 int i;
305 for (i = 0; i < cpuid->nent; ++i) {
306 if (cpuid->entries[i].function == function &&
307 cpuid->entries[i].index == index) {
308 return &cpuid->entries[i];
309 }
310 }
311 /* not found: */
312 return NULL;
313 }
314
315 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
316 uint32_t index, int reg)
317 {
318 struct kvm_cpuid2 *cpuid;
319 uint32_t ret = 0;
320 uint32_t cpuid_1_edx;
321 bool found = false;
322
323 cpuid = get_supported_cpuid(s);
324
325 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
326 if (entry) {
327 found = true;
328 ret = cpuid_entry_get_reg(entry, reg);
329 }
330
331 /* Fixups for the data returned by KVM, below */
332
333 if (function == 1 && reg == R_EDX) {
334 /* KVM before 2.6.30 misreports the following features */
335 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
336 } else if (function == 1 && reg == R_ECX) {
337 /* We can set the hypervisor flag, even if KVM does not return it on
338 * GET_SUPPORTED_CPUID
339 */
340 ret |= CPUID_EXT_HYPERVISOR;
341 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
342 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
343 * and the irqchip is in the kernel.
344 */
345 if (kvm_irqchip_in_kernel() &&
346 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
347 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
348 }
349
350 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
351 * without the in-kernel irqchip
352 */
353 if (!kvm_irqchip_in_kernel()) {
354 ret &= ~CPUID_EXT_X2APIC;
355 }
356 } else if (function == 6 && reg == R_EAX) {
357 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
358 } else if (function == 0x80000001 && reg == R_EDX) {
359 /* On Intel, kvm returns cpuid according to the Intel spec,
360 * so add missing bits according to the AMD spec:
361 */
362 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
363 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
364 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
365 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
366 * be enabled without the in-kernel irqchip
367 */
368 if (!kvm_irqchip_in_kernel()) {
369 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
370 }
371 }
372
373 /* fallback for older kernels */
374 if ((function == KVM_CPUID_FEATURES) && !found) {
375 ret = get_para_features(s);
376 }
377
378 return ret;
379 }
380
381 typedef struct HWPoisonPage {
382 ram_addr_t ram_addr;
383 QLIST_ENTRY(HWPoisonPage) list;
384 } HWPoisonPage;
385
386 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
387 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
388
389 static void kvm_unpoison_all(void *param)
390 {
391 HWPoisonPage *page, *next_page;
392
393 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
394 QLIST_REMOVE(page, list);
395 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
396 g_free(page);
397 }
398 }
399
400 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
401 {
402 HWPoisonPage *page;
403
404 QLIST_FOREACH(page, &hwpoison_page_list, list) {
405 if (page->ram_addr == ram_addr) {
406 return;
407 }
408 }
409 page = g_new(HWPoisonPage, 1);
410 page->ram_addr = ram_addr;
411 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
412 }
413
414 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
415 int *max_banks)
416 {
417 int r;
418
419 r = kvm_check_extension(s, KVM_CAP_MCE);
420 if (r > 0) {
421 *max_banks = r;
422 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
423 }
424 return -ENOSYS;
425 }
426
427 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
428 {
429 CPUState *cs = CPU(cpu);
430 CPUX86State *env = &cpu->env;
431 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
432 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
433 uint64_t mcg_status = MCG_STATUS_MCIP;
434 int flags = 0;
435
436 if (code == BUS_MCEERR_AR) {
437 status |= MCI_STATUS_AR | 0x134;
438 mcg_status |= MCG_STATUS_EIPV;
439 } else {
440 status |= 0xc0;
441 mcg_status |= MCG_STATUS_RIPV;
442 }
443
444 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
445 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
446 * guest kernel back into env->mcg_ext_ctl.
447 */
448 cpu_synchronize_state(cs);
449 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
450 mcg_status |= MCG_STATUS_LMCE;
451 flags = 0;
452 }
453
454 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
455 (MCM_ADDR_PHYS << 6) | 0xc, flags);
456 }
457
458 static void hardware_memory_error(void)
459 {
460 fprintf(stderr, "Hardware memory error!\n");
461 exit(1);
462 }
463
464 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
465 {
466 X86CPU *cpu = X86_CPU(c);
467 CPUX86State *env = &cpu->env;
468 ram_addr_t ram_addr;
469 hwaddr paddr;
470
471 if ((env->mcg_cap & MCG_SER_P) && addr
472 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
473 ram_addr = qemu_ram_addr_from_host(addr);
474 if (ram_addr == RAM_ADDR_INVALID ||
475 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
476 fprintf(stderr, "Hardware memory error for memory used by "
477 "QEMU itself instead of guest system!\n");
478 /* Hope we are lucky for AO MCE */
479 if (code == BUS_MCEERR_AO) {
480 return 0;
481 } else {
482 hardware_memory_error();
483 }
484 }
485 kvm_hwpoison_page_add(ram_addr);
486 kvm_mce_inject(cpu, paddr, code);
487 } else {
488 if (code == BUS_MCEERR_AO) {
489 return 0;
490 } else if (code == BUS_MCEERR_AR) {
491 hardware_memory_error();
492 } else {
493 return 1;
494 }
495 }
496 return 0;
497 }
498
499 int kvm_arch_on_sigbus(int code, void *addr)
500 {
501 X86CPU *cpu = X86_CPU(first_cpu);
502
503 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
504 ram_addr_t ram_addr;
505 hwaddr paddr;
506
507 /* Hope we are lucky for AO MCE */
508 ram_addr = qemu_ram_addr_from_host(addr);
509 if (ram_addr == RAM_ADDR_INVALID ||
510 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
511 addr, &paddr)) {
512 fprintf(stderr, "Hardware memory error for memory used by "
513 "QEMU itself instead of guest system!: %p\n", addr);
514 return 0;
515 }
516 kvm_hwpoison_page_add(ram_addr);
517 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
518 } else {
519 if (code == BUS_MCEERR_AO) {
520 return 0;
521 } else if (code == BUS_MCEERR_AR) {
522 hardware_memory_error();
523 } else {
524 return 1;
525 }
526 }
527 return 0;
528 }
529
530 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
531 {
532 CPUX86State *env = &cpu->env;
533
534 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
535 unsigned int bank, bank_num = env->mcg_cap & 0xff;
536 struct kvm_x86_mce mce;
537
538 env->exception_injected = -1;
539
540 /*
541 * There must be at least one bank in use if an MCE is pending.
542 * Find it and use its values for the event injection.
543 */
544 for (bank = 0; bank < bank_num; bank++) {
545 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
546 break;
547 }
548 }
549 assert(bank < bank_num);
550
551 mce.bank = bank;
552 mce.status = env->mce_banks[bank * 4 + 1];
553 mce.mcg_status = env->mcg_status;
554 mce.addr = env->mce_banks[bank * 4 + 2];
555 mce.misc = env->mce_banks[bank * 4 + 3];
556
557 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
558 }
559 return 0;
560 }
561
562 static void cpu_update_state(void *opaque, int running, RunState state)
563 {
564 CPUX86State *env = opaque;
565
566 if (running) {
567 env->tsc_valid = false;
568 }
569 }
570
571 unsigned long kvm_arch_vcpu_id(CPUState *cs)
572 {
573 X86CPU *cpu = X86_CPU(cs);
574 return cpu->apic_id;
575 }
576
577 #ifndef KVM_CPUID_SIGNATURE_NEXT
578 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
579 #endif
580
581 static bool hyperv_hypercall_available(X86CPU *cpu)
582 {
583 return cpu->hyperv_vapic ||
584 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
585 }
586
587 static bool hyperv_enabled(X86CPU *cpu)
588 {
589 CPUState *cs = CPU(cpu);
590 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
591 (hyperv_hypercall_available(cpu) ||
592 cpu->hyperv_time ||
593 cpu->hyperv_relaxed_timing ||
594 cpu->hyperv_crash ||
595 cpu->hyperv_reset ||
596 cpu->hyperv_vpindex ||
597 cpu->hyperv_runtime ||
598 cpu->hyperv_synic ||
599 cpu->hyperv_stimer);
600 }
601
602 static int kvm_arch_set_tsc_khz(CPUState *cs)
603 {
604 X86CPU *cpu = X86_CPU(cs);
605 CPUX86State *env = &cpu->env;
606 int r;
607
608 if (!env->tsc_khz) {
609 return 0;
610 }
611
612 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
613 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
614 -ENOTSUP;
615 if (r < 0) {
616 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
617 * TSC frequency doesn't match the one we want.
618 */
619 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
620 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
621 -ENOTSUP;
622 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
623 error_report("warning: TSC frequency mismatch between "
624 "VM (%" PRId64 " kHz) and host (%d kHz), "
625 "and TSC scaling unavailable",
626 env->tsc_khz, cur_freq);
627 return r;
628 }
629 }
630
631 return 0;
632 }
633
634 static int hyperv_handle_properties(CPUState *cs)
635 {
636 X86CPU *cpu = X86_CPU(cs);
637 CPUX86State *env = &cpu->env;
638
639 if (cpu->hyperv_time &&
640 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
641 cpu->hyperv_time = false;
642 }
643
644 if (cpu->hyperv_relaxed_timing) {
645 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
646 }
647 if (cpu->hyperv_vapic) {
648 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
649 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
650 }
651 if (cpu->hyperv_time) {
652 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_HYPERCALL_AVAILABLE;
653 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE;
654 env->features[FEAT_HYPERV_EAX] |= 0x200;
655 }
656 if (cpu->hyperv_crash && has_msr_hv_crash) {
657 env->features[FEAT_HYPERV_EDX] |= HV_X64_GUEST_CRASH_MSR_AVAILABLE;
658 }
659 env->features[FEAT_HYPERV_EDX] |= HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
660 if (cpu->hyperv_reset && has_msr_hv_reset) {
661 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_RESET_AVAILABLE;
662 }
663 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
664 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_INDEX_AVAILABLE;
665 }
666 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
667 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_VP_RUNTIME_AVAILABLE;
668 }
669 if (cpu->hyperv_synic) {
670 int sint;
671
672 if (!has_msr_hv_synic ||
673 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
674 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
675 return -ENOSYS;
676 }
677
678 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNIC_AVAILABLE;
679 env->msr_hv_synic_version = HV_SYNIC_VERSION_1;
680 for (sint = 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); sint++) {
681 env->msr_hv_synic_sint[sint] = HV_SYNIC_SINT_MASKED;
682 }
683 }
684 if (cpu->hyperv_stimer) {
685 if (!has_msr_hv_stimer) {
686 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
687 return -ENOSYS;
688 }
689 env->features[FEAT_HYPERV_EAX] |= HV_X64_MSR_SYNTIMER_AVAILABLE;
690 }
691 return 0;
692 }
693
694 static Error *invtsc_mig_blocker;
695
696 #define KVM_MAX_CPUID_ENTRIES 100
697
698 int kvm_arch_init_vcpu(CPUState *cs)
699 {
700 struct {
701 struct kvm_cpuid2 cpuid;
702 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
703 } QEMU_PACKED cpuid_data;
704 X86CPU *cpu = X86_CPU(cs);
705 CPUX86State *env = &cpu->env;
706 uint32_t limit, i, j, cpuid_i;
707 uint32_t unused;
708 struct kvm_cpuid_entry2 *c;
709 uint32_t signature[3];
710 int kvm_base = KVM_CPUID_SIGNATURE;
711 int r;
712
713 memset(&cpuid_data, 0, sizeof(cpuid_data));
714
715 cpuid_i = 0;
716
717 /* Paravirtualization CPUIDs */
718 if (hyperv_enabled(cpu)) {
719 c = &cpuid_data.entries[cpuid_i++];
720 c->function = HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
721 if (!cpu->hyperv_vendor_id) {
722 memcpy(signature, "Microsoft Hv", 12);
723 } else {
724 size_t len = strlen(cpu->hyperv_vendor_id);
725
726 if (len > 12) {
727 error_report("hv-vendor-id truncated to 12 characters");
728 len = 12;
729 }
730 memset(signature, 0, 12);
731 memcpy(signature, cpu->hyperv_vendor_id, len);
732 }
733 c->eax = HYPERV_CPUID_MIN;
734 c->ebx = signature[0];
735 c->ecx = signature[1];
736 c->edx = signature[2];
737
738 c = &cpuid_data.entries[cpuid_i++];
739 c->function = HYPERV_CPUID_INTERFACE;
740 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
741 c->eax = signature[0];
742 c->ebx = 0;
743 c->ecx = 0;
744 c->edx = 0;
745
746 c = &cpuid_data.entries[cpuid_i++];
747 c->function = HYPERV_CPUID_VERSION;
748 c->eax = 0x00001bbc;
749 c->ebx = 0x00060001;
750
751 c = &cpuid_data.entries[cpuid_i++];
752 c->function = HYPERV_CPUID_FEATURES;
753 r = hyperv_handle_properties(cs);
754 if (r) {
755 return r;
756 }
757 c->eax = env->features[FEAT_HYPERV_EAX];
758 c->ebx = env->features[FEAT_HYPERV_EBX];
759 c->edx = env->features[FEAT_HYPERV_EDX];
760
761 c = &cpuid_data.entries[cpuid_i++];
762 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
763 if (cpu->hyperv_relaxed_timing) {
764 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
765 }
766 if (cpu->hyperv_vapic) {
767 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
768 }
769 c->ebx = cpu->hyperv_spinlock_attempts;
770
771 c = &cpuid_data.entries[cpuid_i++];
772 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
773 c->eax = 0x40;
774 c->ebx = 0x40;
775
776 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
777 has_msr_hv_hypercall = true;
778 }
779
780 if (cpu->expose_kvm) {
781 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
782 c = &cpuid_data.entries[cpuid_i++];
783 c->function = KVM_CPUID_SIGNATURE | kvm_base;
784 c->eax = KVM_CPUID_FEATURES | kvm_base;
785 c->ebx = signature[0];
786 c->ecx = signature[1];
787 c->edx = signature[2];
788
789 c = &cpuid_data.entries[cpuid_i++];
790 c->function = KVM_CPUID_FEATURES | kvm_base;
791 c->eax = env->features[FEAT_KVM];
792 }
793
794 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
795
796 for (i = 0; i <= limit; i++) {
797 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
798 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
799 abort();
800 }
801 c = &cpuid_data.entries[cpuid_i++];
802
803 switch (i) {
804 case 2: {
805 /* Keep reading function 2 till all the input is received */
806 int times;
807
808 c->function = i;
809 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
810 KVM_CPUID_FLAG_STATE_READ_NEXT;
811 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
812 times = c->eax & 0xff;
813
814 for (j = 1; j < times; ++j) {
815 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
816 fprintf(stderr, "cpuid_data is full, no space for "
817 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
818 abort();
819 }
820 c = &cpuid_data.entries[cpuid_i++];
821 c->function = i;
822 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
823 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
824 }
825 break;
826 }
827 case 4:
828 case 0xb:
829 case 0xd:
830 for (j = 0; ; j++) {
831 if (i == 0xd && j == 64) {
832 break;
833 }
834 c->function = i;
835 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
836 c->index = j;
837 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
838
839 if (i == 4 && c->eax == 0) {
840 break;
841 }
842 if (i == 0xb && !(c->ecx & 0xff00)) {
843 break;
844 }
845 if (i == 0xd && c->eax == 0) {
846 continue;
847 }
848 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
849 fprintf(stderr, "cpuid_data is full, no space for "
850 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
851 abort();
852 }
853 c = &cpuid_data.entries[cpuid_i++];
854 }
855 break;
856 default:
857 c->function = i;
858 c->flags = 0;
859 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
860 break;
861 }
862 }
863
864 if (limit >= 0x0a) {
865 uint32_t ver;
866
867 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
868 if ((ver & 0xff) > 0) {
869 has_msr_architectural_pmu = true;
870 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
871
872 /* Shouldn't be more than 32, since that's the number of bits
873 * available in EBX to tell us _which_ counters are available.
874 * Play it safe.
875 */
876 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
877 num_architectural_pmu_counters = MAX_GP_COUNTERS;
878 }
879 }
880 }
881
882 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
883
884 for (i = 0x80000000; i <= limit; i++) {
885 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
886 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
887 abort();
888 }
889 c = &cpuid_data.entries[cpuid_i++];
890
891 c->function = i;
892 c->flags = 0;
893 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
894 }
895
896 /* Call Centaur's CPUID instructions they are supported. */
897 if (env->cpuid_xlevel2 > 0) {
898 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
899
900 for (i = 0xC0000000; i <= limit; i++) {
901 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
902 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
903 abort();
904 }
905 c = &cpuid_data.entries[cpuid_i++];
906
907 c->function = i;
908 c->flags = 0;
909 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
910 }
911 }
912
913 cpuid_data.cpuid.nent = cpuid_i;
914
915 if (((env->cpuid_version >> 8)&0xF) >= 6
916 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
917 (CPUID_MCE | CPUID_MCA)
918 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
919 uint64_t mcg_cap, unsupported_caps;
920 int banks;
921 int ret;
922
923 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
924 if (ret < 0) {
925 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
926 return ret;
927 }
928
929 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
930 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
931 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
932 return -ENOTSUP;
933 }
934
935 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
936 if (unsupported_caps) {
937 if (unsupported_caps & MCG_LMCE_P) {
938 error_report("kvm: LMCE not supported");
939 return -ENOTSUP;
940 }
941 error_report("warning: Unsupported MCG_CAP bits: 0x%" PRIx64,
942 unsupported_caps);
943 }
944
945 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
946 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
947 if (ret < 0) {
948 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
949 return ret;
950 }
951 }
952
953 qemu_add_vm_change_state_handler(cpu_update_state, env);
954
955 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
956 if (c) {
957 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
958 !!(c->ecx & CPUID_EXT_SMX);
959 }
960
961 if (env->mcg_cap & MCG_LMCE_P) {
962 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
963 }
964
965 c = cpuid_find_entry(&cpuid_data.cpuid, 0x80000007, 0);
966 if (c && (c->edx & 1<<8) && invtsc_mig_blocker == NULL) {
967 /* for migration */
968 error_setg(&invtsc_mig_blocker,
969 "State blocked by non-migratable CPU device"
970 " (invtsc flag)");
971 migrate_add_blocker(invtsc_mig_blocker);
972 /* for savevm */
973 vmstate_x86_cpu.unmigratable = 1;
974 }
975
976 cpuid_data.cpuid.padding = 0;
977 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
978 if (r) {
979 return r;
980 }
981
982 r = kvm_arch_set_tsc_khz(cs);
983 if (r < 0) {
984 return r;
985 }
986
987 /* vcpu's TSC frequency is either specified by user, or following
988 * the value used by KVM if the former is not present. In the
989 * latter case, we query it from KVM and record in env->tsc_khz,
990 * so that vcpu's TSC frequency can be migrated later via this field.
991 */
992 if (!env->tsc_khz) {
993 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
994 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
995 -ENOTSUP;
996 if (r > 0) {
997 env->tsc_khz = r;
998 }
999 }
1000
1001 if (has_xsave) {
1002 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1003 }
1004 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1005
1006 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1007 has_msr_tsc_aux = false;
1008 }
1009
1010 return 0;
1011 }
1012
1013 void kvm_arch_reset_vcpu(X86CPU *cpu)
1014 {
1015 CPUX86State *env = &cpu->env;
1016
1017 env->exception_injected = -1;
1018 env->interrupt_injected = -1;
1019 env->xcr0 = 1;
1020 if (kvm_irqchip_in_kernel()) {
1021 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1022 KVM_MP_STATE_UNINITIALIZED;
1023 } else {
1024 env->mp_state = KVM_MP_STATE_RUNNABLE;
1025 }
1026 }
1027
1028 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1029 {
1030 CPUX86State *env = &cpu->env;
1031
1032 /* APs get directly into wait-for-SIPI state. */
1033 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1034 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1035 }
1036 }
1037
1038 static int kvm_get_supported_msrs(KVMState *s)
1039 {
1040 static int kvm_supported_msrs;
1041 int ret = 0;
1042
1043 /* first time */
1044 if (kvm_supported_msrs == 0) {
1045 struct kvm_msr_list msr_list, *kvm_msr_list;
1046
1047 kvm_supported_msrs = -1;
1048
1049 /* Obtain MSR list from KVM. These are the MSRs that we must
1050 * save/restore */
1051 msr_list.nmsrs = 0;
1052 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1053 if (ret < 0 && ret != -E2BIG) {
1054 return ret;
1055 }
1056 /* Old kernel modules had a bug and could write beyond the provided
1057 memory. Allocate at least a safe amount of 1K. */
1058 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1059 msr_list.nmsrs *
1060 sizeof(msr_list.indices[0])));
1061
1062 kvm_msr_list->nmsrs = msr_list.nmsrs;
1063 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1064 if (ret >= 0) {
1065 int i;
1066
1067 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1068 if (kvm_msr_list->indices[i] == MSR_STAR) {
1069 has_msr_star = true;
1070 continue;
1071 }
1072 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
1073 has_msr_hsave_pa = true;
1074 continue;
1075 }
1076 if (kvm_msr_list->indices[i] == MSR_TSC_AUX) {
1077 has_msr_tsc_aux = true;
1078 continue;
1079 }
1080 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
1081 has_msr_tsc_adjust = true;
1082 continue;
1083 }
1084 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1085 has_msr_tsc_deadline = true;
1086 continue;
1087 }
1088 if (kvm_msr_list->indices[i] == MSR_IA32_SMBASE) {
1089 has_msr_smbase = true;
1090 continue;
1091 }
1092 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
1093 has_msr_misc_enable = true;
1094 continue;
1095 }
1096 if (kvm_msr_list->indices[i] == MSR_IA32_BNDCFGS) {
1097 has_msr_bndcfgs = true;
1098 continue;
1099 }
1100 if (kvm_msr_list->indices[i] == MSR_IA32_XSS) {
1101 has_msr_xss = true;
1102 continue;
1103 }
1104 if (kvm_msr_list->indices[i] == HV_X64_MSR_CRASH_CTL) {
1105 has_msr_hv_crash = true;
1106 continue;
1107 }
1108 if (kvm_msr_list->indices[i] == HV_X64_MSR_RESET) {
1109 has_msr_hv_reset = true;
1110 continue;
1111 }
1112 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_INDEX) {
1113 has_msr_hv_vpindex = true;
1114 continue;
1115 }
1116 if (kvm_msr_list->indices[i] == HV_X64_MSR_VP_RUNTIME) {
1117 has_msr_hv_runtime = true;
1118 continue;
1119 }
1120 if (kvm_msr_list->indices[i] == HV_X64_MSR_SCONTROL) {
1121 has_msr_hv_synic = true;
1122 continue;
1123 }
1124 if (kvm_msr_list->indices[i] == HV_X64_MSR_STIMER0_CONFIG) {
1125 has_msr_hv_stimer = true;
1126 continue;
1127 }
1128 }
1129 }
1130
1131 g_free(kvm_msr_list);
1132 }
1133
1134 return ret;
1135 }
1136
1137 static Notifier smram_machine_done;
1138 static KVMMemoryListener smram_listener;
1139 static AddressSpace smram_address_space;
1140 static MemoryRegion smram_as_root;
1141 static MemoryRegion smram_as_mem;
1142
1143 static void register_smram_listener(Notifier *n, void *unused)
1144 {
1145 MemoryRegion *smram =
1146 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1147
1148 /* Outer container... */
1149 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1150 memory_region_set_enabled(&smram_as_root, true);
1151
1152 /* ... with two regions inside: normal system memory with low
1153 * priority, and...
1154 */
1155 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1156 get_system_memory(), 0, ~0ull);
1157 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1158 memory_region_set_enabled(&smram_as_mem, true);
1159
1160 if (smram) {
1161 /* ... SMRAM with higher priority */
1162 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1163 memory_region_set_enabled(smram, true);
1164 }
1165
1166 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1167 kvm_memory_listener_register(kvm_state, &smram_listener,
1168 &smram_address_space, 1);
1169 }
1170
1171 int kvm_arch_init(MachineState *ms, KVMState *s)
1172 {
1173 uint64_t identity_base = 0xfffbc000;
1174 uint64_t shadow_mem;
1175 int ret;
1176 struct utsname utsname;
1177
1178 #ifdef KVM_CAP_XSAVE
1179 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1180 #endif
1181
1182 #ifdef KVM_CAP_XCRS
1183 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1184 #endif
1185
1186 #ifdef KVM_CAP_PIT_STATE2
1187 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1188 #endif
1189
1190 ret = kvm_get_supported_msrs(s);
1191 if (ret < 0) {
1192 return ret;
1193 }
1194
1195 uname(&utsname);
1196 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1197
1198 /*
1199 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1200 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1201 * Since these must be part of guest physical memory, we need to allocate
1202 * them, both by setting their start addresses in the kernel and by
1203 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1204 *
1205 * Older KVM versions may not support setting the identity map base. In
1206 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1207 * size.
1208 */
1209 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1210 /* Allows up to 16M BIOSes. */
1211 identity_base = 0xfeffc000;
1212
1213 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1214 if (ret < 0) {
1215 return ret;
1216 }
1217 }
1218
1219 /* Set TSS base one page after EPT identity map. */
1220 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1221 if (ret < 0) {
1222 return ret;
1223 }
1224
1225 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1226 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1227 if (ret < 0) {
1228 fprintf(stderr, "e820_add_entry() table is full\n");
1229 return ret;
1230 }
1231 qemu_register_reset(kvm_unpoison_all, NULL);
1232
1233 shadow_mem = machine_kvm_shadow_mem(ms);
1234 if (shadow_mem != -1) {
1235 shadow_mem /= 4096;
1236 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1237 if (ret < 0) {
1238 return ret;
1239 }
1240 }
1241
1242 if (kvm_check_extension(s, KVM_CAP_X86_SMM)) {
1243 smram_machine_done.notify = register_smram_listener;
1244 qemu_add_machine_init_done_notifier(&smram_machine_done);
1245 }
1246 return 0;
1247 }
1248
1249 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1250 {
1251 lhs->selector = rhs->selector;
1252 lhs->base = rhs->base;
1253 lhs->limit = rhs->limit;
1254 lhs->type = 3;
1255 lhs->present = 1;
1256 lhs->dpl = 3;
1257 lhs->db = 0;
1258 lhs->s = 1;
1259 lhs->l = 0;
1260 lhs->g = 0;
1261 lhs->avl = 0;
1262 lhs->unusable = 0;
1263 }
1264
1265 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1266 {
1267 unsigned flags = rhs->flags;
1268 lhs->selector = rhs->selector;
1269 lhs->base = rhs->base;
1270 lhs->limit = rhs->limit;
1271 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1272 lhs->present = (flags & DESC_P_MASK) != 0;
1273 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1274 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1275 lhs->s = (flags & DESC_S_MASK) != 0;
1276 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1277 lhs->g = (flags & DESC_G_MASK) != 0;
1278 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1279 lhs->unusable = !lhs->present;
1280 lhs->padding = 0;
1281 }
1282
1283 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1284 {
1285 lhs->selector = rhs->selector;
1286 lhs->base = rhs->base;
1287 lhs->limit = rhs->limit;
1288 if (rhs->unusable) {
1289 lhs->flags = 0;
1290 } else {
1291 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1292 (rhs->present * DESC_P_MASK) |
1293 (rhs->dpl << DESC_DPL_SHIFT) |
1294 (rhs->db << DESC_B_SHIFT) |
1295 (rhs->s * DESC_S_MASK) |
1296 (rhs->l << DESC_L_SHIFT) |
1297 (rhs->g * DESC_G_MASK) |
1298 (rhs->avl * DESC_AVL_MASK);
1299 }
1300 }
1301
1302 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1303 {
1304 if (set) {
1305 *kvm_reg = *qemu_reg;
1306 } else {
1307 *qemu_reg = *kvm_reg;
1308 }
1309 }
1310
1311 static int kvm_getput_regs(X86CPU *cpu, int set)
1312 {
1313 CPUX86State *env = &cpu->env;
1314 struct kvm_regs regs;
1315 int ret = 0;
1316
1317 if (!set) {
1318 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1319 if (ret < 0) {
1320 return ret;
1321 }
1322 }
1323
1324 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1325 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1326 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1327 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1328 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1329 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1330 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1331 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1332 #ifdef TARGET_X86_64
1333 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1334 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1335 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1336 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1337 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1338 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1339 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1340 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1341 #endif
1342
1343 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1344 kvm_getput_reg(&regs.rip, &env->eip, set);
1345
1346 if (set) {
1347 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1348 }
1349
1350 return ret;
1351 }
1352
1353 static int kvm_put_fpu(X86CPU *cpu)
1354 {
1355 CPUX86State *env = &cpu->env;
1356 struct kvm_fpu fpu;
1357 int i;
1358
1359 memset(&fpu, 0, sizeof fpu);
1360 fpu.fsw = env->fpus & ~(7 << 11);
1361 fpu.fsw |= (env->fpstt & 7) << 11;
1362 fpu.fcw = env->fpuc;
1363 fpu.last_opcode = env->fpop;
1364 fpu.last_ip = env->fpip;
1365 fpu.last_dp = env->fpdp;
1366 for (i = 0; i < 8; ++i) {
1367 fpu.ftwx |= (!env->fptags[i]) << i;
1368 }
1369 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1370 for (i = 0; i < CPU_NB_REGS; i++) {
1371 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1372 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1373 }
1374 fpu.mxcsr = env->mxcsr;
1375
1376 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1377 }
1378
1379 #define XSAVE_FCW_FSW 0
1380 #define XSAVE_FTW_FOP 1
1381 #define XSAVE_CWD_RIP 2
1382 #define XSAVE_CWD_RDP 4
1383 #define XSAVE_MXCSR 6
1384 #define XSAVE_ST_SPACE 8
1385 #define XSAVE_XMM_SPACE 40
1386 #define XSAVE_XSTATE_BV 128
1387 #define XSAVE_YMMH_SPACE 144
1388 #define XSAVE_BNDREGS 240
1389 #define XSAVE_BNDCSR 256
1390 #define XSAVE_OPMASK 272
1391 #define XSAVE_ZMM_Hi256 288
1392 #define XSAVE_Hi16_ZMM 416
1393 #define XSAVE_PKRU 672
1394
1395 #define XSAVE_BYTE_OFFSET(word_offset) \
1396 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1397
1398 #define ASSERT_OFFSET(word_offset, field) \
1399 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1400 offsetof(X86XSaveArea, field))
1401
1402 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1403 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1404 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1405 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1406 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1407 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1408 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1409 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1410 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1411 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1412 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1413 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1414 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1415 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1416 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1417
1418 static int kvm_put_xsave(X86CPU *cpu)
1419 {
1420 CPUX86State *env = &cpu->env;
1421 X86XSaveArea *xsave = env->kvm_xsave_buf;
1422 uint16_t cwd, swd, twd;
1423 int i;
1424
1425 if (!has_xsave) {
1426 return kvm_put_fpu(cpu);
1427 }
1428
1429 memset(xsave, 0, sizeof(struct kvm_xsave));
1430 twd = 0;
1431 swd = env->fpus & ~(7 << 11);
1432 swd |= (env->fpstt & 7) << 11;
1433 cwd = env->fpuc;
1434 for (i = 0; i < 8; ++i) {
1435 twd |= (!env->fptags[i]) << i;
1436 }
1437 xsave->legacy.fcw = cwd;
1438 xsave->legacy.fsw = swd;
1439 xsave->legacy.ftw = twd;
1440 xsave->legacy.fpop = env->fpop;
1441 xsave->legacy.fpip = env->fpip;
1442 xsave->legacy.fpdp = env->fpdp;
1443 memcpy(&xsave->legacy.fpregs, env->fpregs,
1444 sizeof env->fpregs);
1445 xsave->legacy.mxcsr = env->mxcsr;
1446 xsave->header.xstate_bv = env->xstate_bv;
1447 memcpy(&xsave->bndreg_state.bnd_regs, env->bnd_regs,
1448 sizeof env->bnd_regs);
1449 xsave->bndcsr_state.bndcsr = env->bndcs_regs;
1450 memcpy(&xsave->opmask_state.opmask_regs, env->opmask_regs,
1451 sizeof env->opmask_regs);
1452
1453 for (i = 0; i < CPU_NB_REGS; i++) {
1454 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1455 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1456 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1457 stq_p(xmm, env->xmm_regs[i].ZMM_Q(0));
1458 stq_p(xmm+8, env->xmm_regs[i].ZMM_Q(1));
1459 stq_p(ymmh, env->xmm_regs[i].ZMM_Q(2));
1460 stq_p(ymmh+8, env->xmm_regs[i].ZMM_Q(3));
1461 stq_p(zmmh, env->xmm_regs[i].ZMM_Q(4));
1462 stq_p(zmmh+8, env->xmm_regs[i].ZMM_Q(5));
1463 stq_p(zmmh+16, env->xmm_regs[i].ZMM_Q(6));
1464 stq_p(zmmh+24, env->xmm_regs[i].ZMM_Q(7));
1465 }
1466
1467 #ifdef TARGET_X86_64
1468 memcpy(&xsave->hi16_zmm_state.hi16_zmm, &env->xmm_regs[16],
1469 16 * sizeof env->xmm_regs[16]);
1470 memcpy(&xsave->pkru_state, &env->pkru, sizeof env->pkru);
1471 #endif
1472 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1473 }
1474
1475 static int kvm_put_xcrs(X86CPU *cpu)
1476 {
1477 CPUX86State *env = &cpu->env;
1478 struct kvm_xcrs xcrs = {};
1479
1480 if (!has_xcrs) {
1481 return 0;
1482 }
1483
1484 xcrs.nr_xcrs = 1;
1485 xcrs.flags = 0;
1486 xcrs.xcrs[0].xcr = 0;
1487 xcrs.xcrs[0].value = env->xcr0;
1488 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1489 }
1490
1491 static int kvm_put_sregs(X86CPU *cpu)
1492 {
1493 CPUX86State *env = &cpu->env;
1494 struct kvm_sregs sregs;
1495
1496 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1497 if (env->interrupt_injected >= 0) {
1498 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1499 (uint64_t)1 << (env->interrupt_injected % 64);
1500 }
1501
1502 if ((env->eflags & VM_MASK)) {
1503 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1504 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1505 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1506 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1507 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1508 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1509 } else {
1510 set_seg(&sregs.cs, &env->segs[R_CS]);
1511 set_seg(&sregs.ds, &env->segs[R_DS]);
1512 set_seg(&sregs.es, &env->segs[R_ES]);
1513 set_seg(&sregs.fs, &env->segs[R_FS]);
1514 set_seg(&sregs.gs, &env->segs[R_GS]);
1515 set_seg(&sregs.ss, &env->segs[R_SS]);
1516 }
1517
1518 set_seg(&sregs.tr, &env->tr);
1519 set_seg(&sregs.ldt, &env->ldt);
1520
1521 sregs.idt.limit = env->idt.limit;
1522 sregs.idt.base = env->idt.base;
1523 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1524 sregs.gdt.limit = env->gdt.limit;
1525 sregs.gdt.base = env->gdt.base;
1526 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1527
1528 sregs.cr0 = env->cr[0];
1529 sregs.cr2 = env->cr[2];
1530 sregs.cr3 = env->cr[3];
1531 sregs.cr4 = env->cr[4];
1532
1533 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1534 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1535
1536 sregs.efer = env->efer;
1537
1538 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1539 }
1540
1541 static void kvm_msr_buf_reset(X86CPU *cpu)
1542 {
1543 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1544 }
1545
1546 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1547 {
1548 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1549 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1550 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1551
1552 assert((void *)(entry + 1) <= limit);
1553
1554 entry->index = index;
1555 entry->reserved = 0;
1556 entry->data = value;
1557 msrs->nmsrs++;
1558 }
1559
1560 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1561 {
1562 kvm_msr_buf_reset(cpu);
1563 kvm_msr_entry_add(cpu, index, value);
1564
1565 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1566 }
1567
1568 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1569 {
1570 int ret;
1571
1572 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1573 assert(ret == 1);
1574 }
1575
1576 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1577 {
1578 CPUX86State *env = &cpu->env;
1579 int ret;
1580
1581 if (!has_msr_tsc_deadline) {
1582 return 0;
1583 }
1584
1585 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1586 if (ret < 0) {
1587 return ret;
1588 }
1589
1590 assert(ret == 1);
1591 return 0;
1592 }
1593
1594 /*
1595 * Provide a separate write service for the feature control MSR in order to
1596 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1597 * before writing any other state because forcibly leaving nested mode
1598 * invalidates the VCPU state.
1599 */
1600 static int kvm_put_msr_feature_control(X86CPU *cpu)
1601 {
1602 int ret;
1603
1604 if (!has_msr_feature_control) {
1605 return 0;
1606 }
1607
1608 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1609 cpu->env.msr_ia32_feature_control);
1610 if (ret < 0) {
1611 return ret;
1612 }
1613
1614 assert(ret == 1);
1615 return 0;
1616 }
1617
1618 static int kvm_put_msrs(X86CPU *cpu, int level)
1619 {
1620 CPUX86State *env = &cpu->env;
1621 int i;
1622 int ret;
1623
1624 kvm_msr_buf_reset(cpu);
1625
1626 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1627 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1628 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1629 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1630 if (has_msr_star) {
1631 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1632 }
1633 if (has_msr_hsave_pa) {
1634 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1635 }
1636 if (has_msr_tsc_aux) {
1637 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1638 }
1639 if (has_msr_tsc_adjust) {
1640 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1641 }
1642 if (has_msr_misc_enable) {
1643 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1644 env->msr_ia32_misc_enable);
1645 }
1646 if (has_msr_smbase) {
1647 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1648 }
1649 if (has_msr_bndcfgs) {
1650 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1651 }
1652 if (has_msr_xss) {
1653 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1654 }
1655 #ifdef TARGET_X86_64
1656 if (lm_capable_kernel) {
1657 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1658 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1659 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1660 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1661 }
1662 #endif
1663 /*
1664 * The following MSRs have side effects on the guest or are too heavy
1665 * for normal writeback. Limit them to reset or full state updates.
1666 */
1667 if (level >= KVM_PUT_RESET_STATE) {
1668 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1669 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1670 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1671 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1672 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1673 }
1674 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
1675 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
1676 }
1677 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
1678 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
1679 }
1680 if (has_msr_architectural_pmu) {
1681 /* Stop the counter. */
1682 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1683 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1684
1685 /* Set the counter values. */
1686 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1687 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
1688 env->msr_fixed_counters[i]);
1689 }
1690 for (i = 0; i < num_architectural_pmu_counters; i++) {
1691 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
1692 env->msr_gp_counters[i]);
1693 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
1694 env->msr_gp_evtsel[i]);
1695 }
1696 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1697 env->msr_global_status);
1698 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1699 env->msr_global_ovf_ctrl);
1700
1701 /* Now start the PMU. */
1702 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1703 env->msr_fixed_ctr_ctrl);
1704 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1705 env->msr_global_ctrl);
1706 }
1707 if (has_msr_hv_hypercall) {
1708 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1709 env->msr_hv_guest_os_id);
1710 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1711 env->msr_hv_hypercall);
1712 }
1713 if (cpu->hyperv_vapic) {
1714 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
1715 env->msr_hv_vapic);
1716 }
1717 if (cpu->hyperv_time) {
1718 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, env->msr_hv_tsc);
1719 }
1720 if (has_msr_hv_crash) {
1721 int j;
1722
1723 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++)
1724 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
1725 env->msr_hv_crash_params[j]);
1726
1727 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL,
1728 HV_X64_MSR_CRASH_CTL_NOTIFY);
1729 }
1730 if (has_msr_hv_runtime) {
1731 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
1732 }
1733 if (cpu->hyperv_synic) {
1734 int j;
1735
1736 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
1737 env->msr_hv_synic_control);
1738 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION,
1739 env->msr_hv_synic_version);
1740 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
1741 env->msr_hv_synic_evt_page);
1742 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
1743 env->msr_hv_synic_msg_page);
1744
1745 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
1746 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
1747 env->msr_hv_synic_sint[j]);
1748 }
1749 }
1750 if (has_msr_hv_stimer) {
1751 int j;
1752
1753 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
1754 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
1755 env->msr_hv_stimer_config[j]);
1756 }
1757
1758 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
1759 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
1760 env->msr_hv_stimer_count[j]);
1761 }
1762 }
1763 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
1764 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1765
1766 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1767 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1768 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1769 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1770 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1771 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1772 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1773 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1774 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1775 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1776 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1777 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
1778 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
1779 /* The CPU GPs if we write to a bit above the physical limit of
1780 * the host CPU (and KVM emulates that)
1781 */
1782 uint64_t mask = env->mtrr_var[i].mask;
1783 mask &= phys_mask;
1784
1785 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1786 env->mtrr_var[i].base);
1787 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
1788 }
1789 }
1790
1791 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1792 * kvm_put_msr_feature_control. */
1793 }
1794 if (env->mcg_cap) {
1795 int i;
1796
1797 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1798 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
1799 if (has_msr_mcg_ext_ctl) {
1800 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1801 }
1802 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1803 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
1804 }
1805 }
1806
1807 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1808 if (ret < 0) {
1809 return ret;
1810 }
1811
1812 assert(ret == cpu->kvm_msr_buf->nmsrs);
1813 return 0;
1814 }
1815
1816
1817 static int kvm_get_fpu(X86CPU *cpu)
1818 {
1819 CPUX86State *env = &cpu->env;
1820 struct kvm_fpu fpu;
1821 int i, ret;
1822
1823 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1824 if (ret < 0) {
1825 return ret;
1826 }
1827
1828 env->fpstt = (fpu.fsw >> 11) & 7;
1829 env->fpus = fpu.fsw;
1830 env->fpuc = fpu.fcw;
1831 env->fpop = fpu.last_opcode;
1832 env->fpip = fpu.last_ip;
1833 env->fpdp = fpu.last_dp;
1834 for (i = 0; i < 8; ++i) {
1835 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1836 }
1837 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1838 for (i = 0; i < CPU_NB_REGS; i++) {
1839 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1840 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
1841 }
1842 env->mxcsr = fpu.mxcsr;
1843
1844 return 0;
1845 }
1846
1847 static int kvm_get_xsave(X86CPU *cpu)
1848 {
1849 CPUX86State *env = &cpu->env;
1850 X86XSaveArea *xsave = env->kvm_xsave_buf;
1851 int ret, i;
1852 uint16_t cwd, swd, twd;
1853
1854 if (!has_xsave) {
1855 return kvm_get_fpu(cpu);
1856 }
1857
1858 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1859 if (ret < 0) {
1860 return ret;
1861 }
1862
1863 cwd = xsave->legacy.fcw;
1864 swd = xsave->legacy.fsw;
1865 twd = xsave->legacy.ftw;
1866 env->fpop = xsave->legacy.fpop;
1867 env->fpstt = (swd >> 11) & 7;
1868 env->fpus = swd;
1869 env->fpuc = cwd;
1870 for (i = 0; i < 8; ++i) {
1871 env->fptags[i] = !((twd >> i) & 1);
1872 }
1873 env->fpip = xsave->legacy.fpip;
1874 env->fpdp = xsave->legacy.fpdp;
1875 env->mxcsr = xsave->legacy.mxcsr;
1876 memcpy(env->fpregs, &xsave->legacy.fpregs,
1877 sizeof env->fpregs);
1878 env->xstate_bv = xsave->header.xstate_bv;
1879 memcpy(env->bnd_regs, &xsave->bndreg_state.bnd_regs,
1880 sizeof env->bnd_regs);
1881 env->bndcs_regs = xsave->bndcsr_state.bndcsr;
1882 memcpy(env->opmask_regs, &xsave->opmask_state.opmask_regs,
1883 sizeof env->opmask_regs);
1884
1885 for (i = 0; i < CPU_NB_REGS; i++) {
1886 uint8_t *xmm = xsave->legacy.xmm_regs[i];
1887 uint8_t *ymmh = xsave->avx_state.ymmh[i];
1888 uint8_t *zmmh = xsave->zmm_hi256_state.zmm_hi256[i];
1889 env->xmm_regs[i].ZMM_Q(0) = ldq_p(xmm);
1890 env->xmm_regs[i].ZMM_Q(1) = ldq_p(xmm+8);
1891 env->xmm_regs[i].ZMM_Q(2) = ldq_p(ymmh);
1892 env->xmm_regs[i].ZMM_Q(3) = ldq_p(ymmh+8);
1893 env->xmm_regs[i].ZMM_Q(4) = ldq_p(zmmh);
1894 env->xmm_regs[i].ZMM_Q(5) = ldq_p(zmmh+8);
1895 env->xmm_regs[i].ZMM_Q(6) = ldq_p(zmmh+16);
1896 env->xmm_regs[i].ZMM_Q(7) = ldq_p(zmmh+24);
1897 }
1898
1899 #ifdef TARGET_X86_64
1900 memcpy(&env->xmm_regs[16], &xsave->hi16_zmm_state.hi16_zmm,
1901 16 * sizeof env->xmm_regs[16]);
1902 memcpy(&env->pkru, &xsave->pkru_state, sizeof env->pkru);
1903 #endif
1904 return 0;
1905 }
1906
1907 static int kvm_get_xcrs(X86CPU *cpu)
1908 {
1909 CPUX86State *env = &cpu->env;
1910 int i, ret;
1911 struct kvm_xcrs xcrs;
1912
1913 if (!has_xcrs) {
1914 return 0;
1915 }
1916
1917 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1918 if (ret < 0) {
1919 return ret;
1920 }
1921
1922 for (i = 0; i < xcrs.nr_xcrs; i++) {
1923 /* Only support xcr0 now */
1924 if (xcrs.xcrs[i].xcr == 0) {
1925 env->xcr0 = xcrs.xcrs[i].value;
1926 break;
1927 }
1928 }
1929 return 0;
1930 }
1931
1932 static int kvm_get_sregs(X86CPU *cpu)
1933 {
1934 CPUX86State *env = &cpu->env;
1935 struct kvm_sregs sregs;
1936 uint32_t hflags;
1937 int bit, i, ret;
1938
1939 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1940 if (ret < 0) {
1941 return ret;
1942 }
1943
1944 /* There can only be one pending IRQ set in the bitmap at a time, so try
1945 to find it and save its number instead (-1 for none). */
1946 env->interrupt_injected = -1;
1947 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1948 if (sregs.interrupt_bitmap[i]) {
1949 bit = ctz64(sregs.interrupt_bitmap[i]);
1950 env->interrupt_injected = i * 64 + bit;
1951 break;
1952 }
1953 }
1954
1955 get_seg(&env->segs[R_CS], &sregs.cs);
1956 get_seg(&env->segs[R_DS], &sregs.ds);
1957 get_seg(&env->segs[R_ES], &sregs.es);
1958 get_seg(&env->segs[R_FS], &sregs.fs);
1959 get_seg(&env->segs[R_GS], &sregs.gs);
1960 get_seg(&env->segs[R_SS], &sregs.ss);
1961
1962 get_seg(&env->tr, &sregs.tr);
1963 get_seg(&env->ldt, &sregs.ldt);
1964
1965 env->idt.limit = sregs.idt.limit;
1966 env->idt.base = sregs.idt.base;
1967 env->gdt.limit = sregs.gdt.limit;
1968 env->gdt.base = sregs.gdt.base;
1969
1970 env->cr[0] = sregs.cr0;
1971 env->cr[2] = sregs.cr2;
1972 env->cr[3] = sregs.cr3;
1973 env->cr[4] = sregs.cr4;
1974
1975 env->efer = sregs.efer;
1976
1977 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1978
1979 #define HFLAG_COPY_MASK \
1980 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1981 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1982 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1983 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1984
1985 hflags = env->hflags & HFLAG_COPY_MASK;
1986 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1987 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1988 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1989 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1990 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1991
1992 if (env->cr[4] & CR4_OSFXSR_MASK) {
1993 hflags |= HF_OSFXSR_MASK;
1994 }
1995
1996 if (env->efer & MSR_EFER_LMA) {
1997 hflags |= HF_LMA_MASK;
1998 }
1999
2000 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
2001 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
2002 } else {
2003 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
2004 (DESC_B_SHIFT - HF_CS32_SHIFT);
2005 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
2006 (DESC_B_SHIFT - HF_SS32_SHIFT);
2007 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
2008 !(hflags & HF_CS32_MASK)) {
2009 hflags |= HF_ADDSEG_MASK;
2010 } else {
2011 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
2012 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
2013 }
2014 }
2015 env->hflags = hflags;
2016
2017 return 0;
2018 }
2019
2020 static int kvm_get_msrs(X86CPU *cpu)
2021 {
2022 CPUX86State *env = &cpu->env;
2023 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2024 int ret, i;
2025 uint64_t mtrr_top_bits;
2026
2027 kvm_msr_buf_reset(cpu);
2028
2029 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2030 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2031 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2032 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2033 if (has_msr_star) {
2034 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2035 }
2036 if (has_msr_hsave_pa) {
2037 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2038 }
2039 if (has_msr_tsc_aux) {
2040 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2041 }
2042 if (has_msr_tsc_adjust) {
2043 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2044 }
2045 if (has_msr_tsc_deadline) {
2046 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2047 }
2048 if (has_msr_misc_enable) {
2049 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2050 }
2051 if (has_msr_smbase) {
2052 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2053 }
2054 if (has_msr_feature_control) {
2055 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2056 }
2057 if (has_msr_bndcfgs) {
2058 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2059 }
2060 if (has_msr_xss) {
2061 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2062 }
2063
2064
2065 if (!env->tsc_valid) {
2066 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2067 env->tsc_valid = !runstate_is_running();
2068 }
2069
2070 #ifdef TARGET_X86_64
2071 if (lm_capable_kernel) {
2072 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2073 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2074 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2075 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2076 }
2077 #endif
2078 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2079 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2080 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2081 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2082 }
2083 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2084 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2085 }
2086 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2087 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2088 }
2089 if (has_msr_architectural_pmu) {
2090 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2091 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2092 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2093 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2094 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
2095 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2096 }
2097 for (i = 0; i < num_architectural_pmu_counters; i++) {
2098 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2099 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2100 }
2101 }
2102
2103 if (env->mcg_cap) {
2104 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2105 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2106 if (has_msr_mcg_ext_ctl) {
2107 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2108 }
2109 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2110 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2111 }
2112 }
2113
2114 if (has_msr_hv_hypercall) {
2115 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2116 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2117 }
2118 if (cpu->hyperv_vapic) {
2119 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2120 }
2121 if (cpu->hyperv_time) {
2122 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2123 }
2124 if (has_msr_hv_crash) {
2125 int j;
2126
2127 for (j = 0; j < HV_X64_MSR_CRASH_PARAMS; j++) {
2128 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2129 }
2130 }
2131 if (has_msr_hv_runtime) {
2132 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2133 }
2134 if (cpu->hyperv_synic) {
2135 uint32_t msr;
2136
2137 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2138 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, 0);
2139 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2140 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2141 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2142 kvm_msr_entry_add(cpu, msr, 0);
2143 }
2144 }
2145 if (has_msr_hv_stimer) {
2146 uint32_t msr;
2147
2148 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2149 msr++) {
2150 kvm_msr_entry_add(cpu, msr, 0);
2151 }
2152 }
2153 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2154 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2155 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2156 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2157 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2158 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2159 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2160 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2161 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2162 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2163 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2164 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2165 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2166 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2167 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2168 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2169 }
2170 }
2171
2172 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2173 if (ret < 0) {
2174 return ret;
2175 }
2176
2177 assert(ret == cpu->kvm_msr_buf->nmsrs);
2178 /*
2179 * MTRR masks: Each mask consists of 5 parts
2180 * a 10..0: must be zero
2181 * b 11 : valid bit
2182 * c n-1.12: actual mask bits
2183 * d 51..n: reserved must be zero
2184 * e 63.52: reserved must be zero
2185 *
2186 * 'n' is the number of physical bits supported by the CPU and is
2187 * apparently always <= 52. We know our 'n' but don't know what
2188 * the destinations 'n' is; it might be smaller, in which case
2189 * it masks (c) on loading. It might be larger, in which case
2190 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2191 * we're migrating to.
2192 */
2193
2194 if (cpu->fill_mtrr_mask) {
2195 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2196 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2197 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2198 } else {
2199 mtrr_top_bits = 0;
2200 }
2201
2202 for (i = 0; i < ret; i++) {
2203 uint32_t index = msrs[i].index;
2204 switch (index) {
2205 case MSR_IA32_SYSENTER_CS:
2206 env->sysenter_cs = msrs[i].data;
2207 break;
2208 case MSR_IA32_SYSENTER_ESP:
2209 env->sysenter_esp = msrs[i].data;
2210 break;
2211 case MSR_IA32_SYSENTER_EIP:
2212 env->sysenter_eip = msrs[i].data;
2213 break;
2214 case MSR_PAT:
2215 env->pat = msrs[i].data;
2216 break;
2217 case MSR_STAR:
2218 env->star = msrs[i].data;
2219 break;
2220 #ifdef TARGET_X86_64
2221 case MSR_CSTAR:
2222 env->cstar = msrs[i].data;
2223 break;
2224 case MSR_KERNELGSBASE:
2225 env->kernelgsbase = msrs[i].data;
2226 break;
2227 case MSR_FMASK:
2228 env->fmask = msrs[i].data;
2229 break;
2230 case MSR_LSTAR:
2231 env->lstar = msrs[i].data;
2232 break;
2233 #endif
2234 case MSR_IA32_TSC:
2235 env->tsc = msrs[i].data;
2236 break;
2237 case MSR_TSC_AUX:
2238 env->tsc_aux = msrs[i].data;
2239 break;
2240 case MSR_TSC_ADJUST:
2241 env->tsc_adjust = msrs[i].data;
2242 break;
2243 case MSR_IA32_TSCDEADLINE:
2244 env->tsc_deadline = msrs[i].data;
2245 break;
2246 case MSR_VM_HSAVE_PA:
2247 env->vm_hsave = msrs[i].data;
2248 break;
2249 case MSR_KVM_SYSTEM_TIME:
2250 env->system_time_msr = msrs[i].data;
2251 break;
2252 case MSR_KVM_WALL_CLOCK:
2253 env->wall_clock_msr = msrs[i].data;
2254 break;
2255 case MSR_MCG_STATUS:
2256 env->mcg_status = msrs[i].data;
2257 break;
2258 case MSR_MCG_CTL:
2259 env->mcg_ctl = msrs[i].data;
2260 break;
2261 case MSR_MCG_EXT_CTL:
2262 env->mcg_ext_ctl = msrs[i].data;
2263 break;
2264 case MSR_IA32_MISC_ENABLE:
2265 env->msr_ia32_misc_enable = msrs[i].data;
2266 break;
2267 case MSR_IA32_SMBASE:
2268 env->smbase = msrs[i].data;
2269 break;
2270 case MSR_IA32_FEATURE_CONTROL:
2271 env->msr_ia32_feature_control = msrs[i].data;
2272 break;
2273 case MSR_IA32_BNDCFGS:
2274 env->msr_bndcfgs = msrs[i].data;
2275 break;
2276 case MSR_IA32_XSS:
2277 env->xss = msrs[i].data;
2278 break;
2279 default:
2280 if (msrs[i].index >= MSR_MC0_CTL &&
2281 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2282 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2283 }
2284 break;
2285 case MSR_KVM_ASYNC_PF_EN:
2286 env->async_pf_en_msr = msrs[i].data;
2287 break;
2288 case MSR_KVM_PV_EOI_EN:
2289 env->pv_eoi_en_msr = msrs[i].data;
2290 break;
2291 case MSR_KVM_STEAL_TIME:
2292 env->steal_time_msr = msrs[i].data;
2293 break;
2294 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2295 env->msr_fixed_ctr_ctrl = msrs[i].data;
2296 break;
2297 case MSR_CORE_PERF_GLOBAL_CTRL:
2298 env->msr_global_ctrl = msrs[i].data;
2299 break;
2300 case MSR_CORE_PERF_GLOBAL_STATUS:
2301 env->msr_global_status = msrs[i].data;
2302 break;
2303 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2304 env->msr_global_ovf_ctrl = msrs[i].data;
2305 break;
2306 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2307 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2308 break;
2309 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2310 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2311 break;
2312 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2313 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2314 break;
2315 case HV_X64_MSR_HYPERCALL:
2316 env->msr_hv_hypercall = msrs[i].data;
2317 break;
2318 case HV_X64_MSR_GUEST_OS_ID:
2319 env->msr_hv_guest_os_id = msrs[i].data;
2320 break;
2321 case HV_X64_MSR_APIC_ASSIST_PAGE:
2322 env->msr_hv_vapic = msrs[i].data;
2323 break;
2324 case HV_X64_MSR_REFERENCE_TSC:
2325 env->msr_hv_tsc = msrs[i].data;
2326 break;
2327 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2328 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2329 break;
2330 case HV_X64_MSR_VP_RUNTIME:
2331 env->msr_hv_runtime = msrs[i].data;
2332 break;
2333 case HV_X64_MSR_SCONTROL:
2334 env->msr_hv_synic_control = msrs[i].data;
2335 break;
2336 case HV_X64_MSR_SVERSION:
2337 env->msr_hv_synic_version = msrs[i].data;
2338 break;
2339 case HV_X64_MSR_SIEFP:
2340 env->msr_hv_synic_evt_page = msrs[i].data;
2341 break;
2342 case HV_X64_MSR_SIMP:
2343 env->msr_hv_synic_msg_page = msrs[i].data;
2344 break;
2345 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2346 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2347 break;
2348 case HV_X64_MSR_STIMER0_CONFIG:
2349 case HV_X64_MSR_STIMER1_CONFIG:
2350 case HV_X64_MSR_STIMER2_CONFIG:
2351 case HV_X64_MSR_STIMER3_CONFIG:
2352 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2353 msrs[i].data;
2354 break;
2355 case HV_X64_MSR_STIMER0_COUNT:
2356 case HV_X64_MSR_STIMER1_COUNT:
2357 case HV_X64_MSR_STIMER2_COUNT:
2358 case HV_X64_MSR_STIMER3_COUNT:
2359 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2360 msrs[i].data;
2361 break;
2362 case MSR_MTRRdefType:
2363 env->mtrr_deftype = msrs[i].data;
2364 break;
2365 case MSR_MTRRfix64K_00000:
2366 env->mtrr_fixed[0] = msrs[i].data;
2367 break;
2368 case MSR_MTRRfix16K_80000:
2369 env->mtrr_fixed[1] = msrs[i].data;
2370 break;
2371 case MSR_MTRRfix16K_A0000:
2372 env->mtrr_fixed[2] = msrs[i].data;
2373 break;
2374 case MSR_MTRRfix4K_C0000:
2375 env->mtrr_fixed[3] = msrs[i].data;
2376 break;
2377 case MSR_MTRRfix4K_C8000:
2378 env->mtrr_fixed[4] = msrs[i].data;
2379 break;
2380 case MSR_MTRRfix4K_D0000:
2381 env->mtrr_fixed[5] = msrs[i].data;
2382 break;
2383 case MSR_MTRRfix4K_D8000:
2384 env->mtrr_fixed[6] = msrs[i].data;
2385 break;
2386 case MSR_MTRRfix4K_E0000:
2387 env->mtrr_fixed[7] = msrs[i].data;
2388 break;
2389 case MSR_MTRRfix4K_E8000:
2390 env->mtrr_fixed[8] = msrs[i].data;
2391 break;
2392 case MSR_MTRRfix4K_F0000:
2393 env->mtrr_fixed[9] = msrs[i].data;
2394 break;
2395 case MSR_MTRRfix4K_F8000:
2396 env->mtrr_fixed[10] = msrs[i].data;
2397 break;
2398 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2399 if (index & 1) {
2400 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2401 mtrr_top_bits;
2402 } else {
2403 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2404 }
2405 break;
2406 }
2407 }
2408
2409 return 0;
2410 }
2411
2412 static int kvm_put_mp_state(X86CPU *cpu)
2413 {
2414 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2415
2416 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2417 }
2418
2419 static int kvm_get_mp_state(X86CPU *cpu)
2420 {
2421 CPUState *cs = CPU(cpu);
2422 CPUX86State *env = &cpu->env;
2423 struct kvm_mp_state mp_state;
2424 int ret;
2425
2426 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2427 if (ret < 0) {
2428 return ret;
2429 }
2430 env->mp_state = mp_state.mp_state;
2431 if (kvm_irqchip_in_kernel()) {
2432 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2433 }
2434 return 0;
2435 }
2436
2437 static int kvm_get_apic(X86CPU *cpu)
2438 {
2439 DeviceState *apic = cpu->apic_state;
2440 struct kvm_lapic_state kapic;
2441 int ret;
2442
2443 if (apic && kvm_irqchip_in_kernel()) {
2444 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2445 if (ret < 0) {
2446 return ret;
2447 }
2448
2449 kvm_get_apic_state(apic, &kapic);
2450 }
2451 return 0;
2452 }
2453
2454 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2455 {
2456 CPUState *cs = CPU(cpu);
2457 CPUX86State *env = &cpu->env;
2458 struct kvm_vcpu_events events = {};
2459
2460 if (!kvm_has_vcpu_events()) {
2461 return 0;
2462 }
2463
2464 events.exception.injected = (env->exception_injected >= 0);
2465 events.exception.nr = env->exception_injected;
2466 events.exception.has_error_code = env->has_error_code;
2467 events.exception.error_code = env->error_code;
2468 events.exception.pad = 0;
2469
2470 events.interrupt.injected = (env->interrupt_injected >= 0);
2471 events.interrupt.nr = env->interrupt_injected;
2472 events.interrupt.soft = env->soft_interrupt;
2473
2474 events.nmi.injected = env->nmi_injected;
2475 events.nmi.pending = env->nmi_pending;
2476 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2477 events.nmi.pad = 0;
2478
2479 events.sipi_vector = env->sipi_vector;
2480 events.flags = 0;
2481
2482 if (has_msr_smbase) {
2483 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2484 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2485 if (kvm_irqchip_in_kernel()) {
2486 /* As soon as these are moved to the kernel, remove them
2487 * from cs->interrupt_request.
2488 */
2489 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2490 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2491 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2492 } else {
2493 /* Keep these in cs->interrupt_request. */
2494 events.smi.pending = 0;
2495 events.smi.latched_init = 0;
2496 }
2497 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2498 }
2499
2500 if (level >= KVM_PUT_RESET_STATE) {
2501 events.flags |=
2502 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2503 }
2504
2505 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2506 }
2507
2508 static int kvm_get_vcpu_events(X86CPU *cpu)
2509 {
2510 CPUX86State *env = &cpu->env;
2511 struct kvm_vcpu_events events;
2512 int ret;
2513
2514 if (!kvm_has_vcpu_events()) {
2515 return 0;
2516 }
2517
2518 memset(&events, 0, sizeof(events));
2519 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2520 if (ret < 0) {
2521 return ret;
2522 }
2523 env->exception_injected =
2524 events.exception.injected ? events.exception.nr : -1;
2525 env->has_error_code = events.exception.has_error_code;
2526 env->error_code = events.exception.error_code;
2527
2528 env->interrupt_injected =
2529 events.interrupt.injected ? events.interrupt.nr : -1;
2530 env->soft_interrupt = events.interrupt.soft;
2531
2532 env->nmi_injected = events.nmi.injected;
2533 env->nmi_pending = events.nmi.pending;
2534 if (events.nmi.masked) {
2535 env->hflags2 |= HF2_NMI_MASK;
2536 } else {
2537 env->hflags2 &= ~HF2_NMI_MASK;
2538 }
2539
2540 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2541 if (events.smi.smm) {
2542 env->hflags |= HF_SMM_MASK;
2543 } else {
2544 env->hflags &= ~HF_SMM_MASK;
2545 }
2546 if (events.smi.pending) {
2547 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2548 } else {
2549 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2550 }
2551 if (events.smi.smm_inside_nmi) {
2552 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2553 } else {
2554 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2555 }
2556 if (events.smi.latched_init) {
2557 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2558 } else {
2559 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2560 }
2561 }
2562
2563 env->sipi_vector = events.sipi_vector;
2564
2565 return 0;
2566 }
2567
2568 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2569 {
2570 CPUState *cs = CPU(cpu);
2571 CPUX86State *env = &cpu->env;
2572 int ret = 0;
2573 unsigned long reinject_trap = 0;
2574
2575 if (!kvm_has_vcpu_events()) {
2576 if (env->exception_injected == 1) {
2577 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2578 } else if (env->exception_injected == 3) {
2579 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2580 }
2581 env->exception_injected = -1;
2582 }
2583
2584 /*
2585 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2586 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2587 * by updating the debug state once again if single-stepping is on.
2588 * Another reason to call kvm_update_guest_debug here is a pending debug
2589 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2590 * reinject them via SET_GUEST_DEBUG.
2591 */
2592 if (reinject_trap ||
2593 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2594 ret = kvm_update_guest_debug(cs, reinject_trap);
2595 }
2596 return ret;
2597 }
2598
2599 static int kvm_put_debugregs(X86CPU *cpu)
2600 {
2601 CPUX86State *env = &cpu->env;
2602 struct kvm_debugregs dbgregs;
2603 int i;
2604
2605 if (!kvm_has_debugregs()) {
2606 return 0;
2607 }
2608
2609 for (i = 0; i < 4; i++) {
2610 dbgregs.db[i] = env->dr[i];
2611 }
2612 dbgregs.dr6 = env->dr[6];
2613 dbgregs.dr7 = env->dr[7];
2614 dbgregs.flags = 0;
2615
2616 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2617 }
2618
2619 static int kvm_get_debugregs(X86CPU *cpu)
2620 {
2621 CPUX86State *env = &cpu->env;
2622 struct kvm_debugregs dbgregs;
2623 int i, ret;
2624
2625 if (!kvm_has_debugregs()) {
2626 return 0;
2627 }
2628
2629 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2630 if (ret < 0) {
2631 return ret;
2632 }
2633 for (i = 0; i < 4; i++) {
2634 env->dr[i] = dbgregs.db[i];
2635 }
2636 env->dr[4] = env->dr[6] = dbgregs.dr6;
2637 env->dr[5] = env->dr[7] = dbgregs.dr7;
2638
2639 return 0;
2640 }
2641
2642 int kvm_arch_put_registers(CPUState *cpu, int level)
2643 {
2644 X86CPU *x86_cpu = X86_CPU(cpu);
2645 int ret;
2646
2647 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
2648
2649 if (level >= KVM_PUT_RESET_STATE) {
2650 ret = kvm_put_msr_feature_control(x86_cpu);
2651 if (ret < 0) {
2652 return ret;
2653 }
2654 }
2655
2656 if (level == KVM_PUT_FULL_STATE) {
2657 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2658 * because TSC frequency mismatch shouldn't abort migration,
2659 * unless the user explicitly asked for a more strict TSC
2660 * setting (e.g. using an explicit "tsc-freq" option).
2661 */
2662 kvm_arch_set_tsc_khz(cpu);
2663 }
2664
2665 ret = kvm_getput_regs(x86_cpu, 1);
2666 if (ret < 0) {
2667 return ret;
2668 }
2669 ret = kvm_put_xsave(x86_cpu);
2670 if (ret < 0) {
2671 return ret;
2672 }
2673 ret = kvm_put_xcrs(x86_cpu);
2674 if (ret < 0) {
2675 return ret;
2676 }
2677 ret = kvm_put_sregs(x86_cpu);
2678 if (ret < 0) {
2679 return ret;
2680 }
2681 /* must be before kvm_put_msrs */
2682 ret = kvm_inject_mce_oldstyle(x86_cpu);
2683 if (ret < 0) {
2684 return ret;
2685 }
2686 ret = kvm_put_msrs(x86_cpu, level);
2687 if (ret < 0) {
2688 return ret;
2689 }
2690 if (level >= KVM_PUT_RESET_STATE) {
2691 ret = kvm_put_mp_state(x86_cpu);
2692 if (ret < 0) {
2693 return ret;
2694 }
2695 }
2696
2697 ret = kvm_put_tscdeadline_msr(x86_cpu);
2698 if (ret < 0) {
2699 return ret;
2700 }
2701
2702 ret = kvm_put_vcpu_events(x86_cpu, level);
2703 if (ret < 0) {
2704 return ret;
2705 }
2706 ret = kvm_put_debugregs(x86_cpu);
2707 if (ret < 0) {
2708 return ret;
2709 }
2710 /* must be last */
2711 ret = kvm_guest_debug_workarounds(x86_cpu);
2712 if (ret < 0) {
2713 return ret;
2714 }
2715 return 0;
2716 }
2717
2718 int kvm_arch_get_registers(CPUState *cs)
2719 {
2720 X86CPU *cpu = X86_CPU(cs);
2721 int ret;
2722
2723 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
2724
2725 ret = kvm_getput_regs(cpu, 0);
2726 if (ret < 0) {
2727 goto out;
2728 }
2729 ret = kvm_get_xsave(cpu);
2730 if (ret < 0) {
2731 goto out;
2732 }
2733 ret = kvm_get_xcrs(cpu);
2734 if (ret < 0) {
2735 goto out;
2736 }
2737 ret = kvm_get_sregs(cpu);
2738 if (ret < 0) {
2739 goto out;
2740 }
2741 ret = kvm_get_msrs(cpu);
2742 if (ret < 0) {
2743 goto out;
2744 }
2745 ret = kvm_get_mp_state(cpu);
2746 if (ret < 0) {
2747 goto out;
2748 }
2749 ret = kvm_get_apic(cpu);
2750 if (ret < 0) {
2751 goto out;
2752 }
2753 ret = kvm_get_vcpu_events(cpu);
2754 if (ret < 0) {
2755 goto out;
2756 }
2757 ret = kvm_get_debugregs(cpu);
2758 if (ret < 0) {
2759 goto out;
2760 }
2761 ret = 0;
2762 out:
2763 cpu_sync_bndcs_hflags(&cpu->env);
2764 return ret;
2765 }
2766
2767 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
2768 {
2769 X86CPU *x86_cpu = X86_CPU(cpu);
2770 CPUX86State *env = &x86_cpu->env;
2771 int ret;
2772
2773 /* Inject NMI */
2774 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2775 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2776 qemu_mutex_lock_iothread();
2777 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2778 qemu_mutex_unlock_iothread();
2779 DPRINTF("injected NMI\n");
2780 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2781 if (ret < 0) {
2782 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2783 strerror(-ret));
2784 }
2785 }
2786 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2787 qemu_mutex_lock_iothread();
2788 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2789 qemu_mutex_unlock_iothread();
2790 DPRINTF("injected SMI\n");
2791 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2792 if (ret < 0) {
2793 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2794 strerror(-ret));
2795 }
2796 }
2797 }
2798
2799 if (!kvm_pic_in_kernel()) {
2800 qemu_mutex_lock_iothread();
2801 }
2802
2803 /* Force the VCPU out of its inner loop to process any INIT requests
2804 * or (for userspace APIC, but it is cheap to combine the checks here)
2805 * pending TPR access reports.
2806 */
2807 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
2808 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2809 !(env->hflags & HF_SMM_MASK)) {
2810 cpu->exit_request = 1;
2811 }
2812 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2813 cpu->exit_request = 1;
2814 }
2815 }
2816
2817 if (!kvm_pic_in_kernel()) {
2818 /* Try to inject an interrupt if the guest can accept it */
2819 if (run->ready_for_interrupt_injection &&
2820 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
2821 (env->eflags & IF_MASK)) {
2822 int irq;
2823
2824 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
2825 irq = cpu_get_pic_interrupt(env);
2826 if (irq >= 0) {
2827 struct kvm_interrupt intr;
2828
2829 intr.irq = irq;
2830 DPRINTF("injected interrupt %d\n", irq);
2831 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
2832 if (ret < 0) {
2833 fprintf(stderr,
2834 "KVM: injection failed, interrupt lost (%s)\n",
2835 strerror(-ret));
2836 }
2837 }
2838 }
2839
2840 /* If we have an interrupt but the guest is not ready to receive an
2841 * interrupt, request an interrupt window exit. This will
2842 * cause a return to userspace as soon as the guest is ready to
2843 * receive interrupts. */
2844 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
2845 run->request_interrupt_window = 1;
2846 } else {
2847 run->request_interrupt_window = 0;
2848 }
2849
2850 DPRINTF("setting tpr\n");
2851 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
2852
2853 qemu_mutex_unlock_iothread();
2854 }
2855 }
2856
2857 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
2858 {
2859 X86CPU *x86_cpu = X86_CPU(cpu);
2860 CPUX86State *env = &x86_cpu->env;
2861
2862 if (run->flags & KVM_RUN_X86_SMM) {
2863 env->hflags |= HF_SMM_MASK;
2864 } else {
2865 env->hflags &= ~HF_SMM_MASK;
2866 }
2867 if (run->if_flag) {
2868 env->eflags |= IF_MASK;
2869 } else {
2870 env->eflags &= ~IF_MASK;
2871 }
2872
2873 /* We need to protect the apic state against concurrent accesses from
2874 * different threads in case the userspace irqchip is used. */
2875 if (!kvm_irqchip_in_kernel()) {
2876 qemu_mutex_lock_iothread();
2877 }
2878 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2879 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
2880 if (!kvm_irqchip_in_kernel()) {
2881 qemu_mutex_unlock_iothread();
2882 }
2883 return cpu_get_mem_attrs(env);
2884 }
2885
2886 int kvm_arch_process_async_events(CPUState *cs)
2887 {
2888 X86CPU *cpu = X86_CPU(cs);
2889 CPUX86State *env = &cpu->env;
2890
2891 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
2892 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2893 assert(env->mcg_cap);
2894
2895 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
2896
2897 kvm_cpu_synchronize_state(cs);
2898
2899 if (env->exception_injected == EXCP08_DBLE) {
2900 /* this means triple fault */
2901 qemu_system_reset_request();
2902 cs->exit_request = 1;
2903 return 0;
2904 }
2905 env->exception_injected = EXCP12_MCHK;
2906 env->has_error_code = 0;
2907
2908 cs->halted = 0;
2909 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2910 env->mp_state = KVM_MP_STATE_RUNNABLE;
2911 }
2912 }
2913
2914 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2915 !(env->hflags & HF_SMM_MASK)) {
2916 kvm_cpu_synchronize_state(cs);
2917 do_cpu_init(cpu);
2918 }
2919
2920 if (kvm_irqchip_in_kernel()) {
2921 return 0;
2922 }
2923
2924 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2925 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2926 apic_poll_irq(cpu->apic_state);
2927 }
2928 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2929 (env->eflags & IF_MASK)) ||
2930 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2931 cs->halted = 0;
2932 }
2933 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2934 kvm_cpu_synchronize_state(cs);
2935 do_cpu_sipi(cpu);
2936 }
2937 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2938 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2939 kvm_cpu_synchronize_state(cs);
2940 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
2941 env->tpr_access_type);
2942 }
2943
2944 return cs->halted;
2945 }
2946
2947 static int kvm_handle_halt(X86CPU *cpu)
2948 {
2949 CPUState *cs = CPU(cpu);
2950 CPUX86State *env = &cpu->env;
2951
2952 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2953 (env->eflags & IF_MASK)) &&
2954 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2955 cs->halted = 1;
2956 return EXCP_HLT;
2957 }
2958
2959 return 0;
2960 }
2961
2962 static int kvm_handle_tpr_access(X86CPU *cpu)
2963 {
2964 CPUState *cs = CPU(cpu);
2965 struct kvm_run *run = cs->kvm_run;
2966
2967 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
2968 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2969 : TPR_ACCESS_READ);
2970 return 1;
2971 }
2972
2973 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2974 {
2975 static const uint8_t int3 = 0xcc;
2976
2977 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2978 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2979 return -EINVAL;
2980 }
2981 return 0;
2982 }
2983
2984 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2985 {
2986 uint8_t int3;
2987
2988 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2989 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2990 return -EINVAL;
2991 }
2992 return 0;
2993 }
2994
2995 static struct {
2996 target_ulong addr;
2997 int len;
2998 int type;
2999 } hw_breakpoint[4];
3000
3001 static int nb_hw_breakpoint;
3002
3003 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3004 {
3005 int n;
3006
3007 for (n = 0; n < nb_hw_breakpoint; n++) {
3008 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3009 (hw_breakpoint[n].len == len || len == -1)) {
3010 return n;
3011 }
3012 }
3013 return -1;
3014 }
3015
3016 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3017 target_ulong len, int type)
3018 {
3019 switch (type) {
3020 case GDB_BREAKPOINT_HW:
3021 len = 1;
3022 break;
3023 case GDB_WATCHPOINT_WRITE:
3024 case GDB_WATCHPOINT_ACCESS:
3025 switch (len) {
3026 case 1:
3027 break;
3028 case 2:
3029 case 4:
3030 case 8:
3031 if (addr & (len - 1)) {
3032 return -EINVAL;
3033 }
3034 break;
3035 default:
3036 return -EINVAL;
3037 }
3038 break;
3039 default:
3040 return -ENOSYS;
3041 }
3042
3043 if (nb_hw_breakpoint == 4) {
3044 return -ENOBUFS;
3045 }
3046 if (find_hw_breakpoint(addr, len, type) >= 0) {
3047 return -EEXIST;
3048 }
3049 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3050 hw_breakpoint[nb_hw_breakpoint].len = len;
3051 hw_breakpoint[nb_hw_breakpoint].type = type;
3052 nb_hw_breakpoint++;
3053
3054 return 0;
3055 }
3056
3057 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3058 target_ulong len, int type)
3059 {
3060 int n;
3061
3062 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3063 if (n < 0) {
3064 return -ENOENT;
3065 }
3066 nb_hw_breakpoint--;
3067 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3068
3069 return 0;
3070 }
3071
3072 void kvm_arch_remove_all_hw_breakpoints(void)
3073 {
3074 nb_hw_breakpoint = 0;
3075 }
3076
3077 static CPUWatchpoint hw_watchpoint;
3078
3079 static int kvm_handle_debug(X86CPU *cpu,
3080 struct kvm_debug_exit_arch *arch_info)
3081 {
3082 CPUState *cs = CPU(cpu);
3083 CPUX86State *env = &cpu->env;
3084 int ret = 0;
3085 int n;
3086
3087 if (arch_info->exception == 1) {
3088 if (arch_info->dr6 & (1 << 14)) {
3089 if (cs->singlestep_enabled) {
3090 ret = EXCP_DEBUG;
3091 }
3092 } else {
3093 for (n = 0; n < 4; n++) {
3094 if (arch_info->dr6 & (1 << n)) {
3095 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3096 case 0x0:
3097 ret = EXCP_DEBUG;
3098 break;
3099 case 0x1:
3100 ret = EXCP_DEBUG;
3101 cs->watchpoint_hit = &hw_watchpoint;
3102 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3103 hw_watchpoint.flags = BP_MEM_WRITE;
3104 break;
3105 case 0x3:
3106 ret = EXCP_DEBUG;
3107 cs->watchpoint_hit = &hw_watchpoint;
3108 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3109 hw_watchpoint.flags = BP_MEM_ACCESS;
3110 break;
3111 }
3112 }
3113 }
3114 }
3115 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3116 ret = EXCP_DEBUG;
3117 }
3118 if (ret == 0) {
3119 cpu_synchronize_state(cs);
3120 assert(env->exception_injected == -1);
3121
3122 /* pass to guest */
3123 env->exception_injected = arch_info->exception;
3124 env->has_error_code = 0;
3125 }
3126
3127 return ret;
3128 }
3129
3130 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3131 {
3132 const uint8_t type_code[] = {
3133 [GDB_BREAKPOINT_HW] = 0x0,
3134 [GDB_WATCHPOINT_WRITE] = 0x1,
3135 [GDB_WATCHPOINT_ACCESS] = 0x3
3136 };
3137 const uint8_t len_code[] = {
3138 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3139 };
3140 int n;
3141
3142 if (kvm_sw_breakpoints_active(cpu)) {
3143 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3144 }
3145 if (nb_hw_breakpoint > 0) {
3146 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3147 dbg->arch.debugreg[7] = 0x0600;
3148 for (n = 0; n < nb_hw_breakpoint; n++) {
3149 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3150 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3151 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3152 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3153 }
3154 }
3155 }
3156
3157 static bool host_supports_vmx(void)
3158 {
3159 uint32_t ecx, unused;
3160
3161 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3162 return ecx & CPUID_EXT_VMX;
3163 }
3164
3165 #define VMX_INVALID_GUEST_STATE 0x80000021
3166
3167 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3168 {
3169 X86CPU *cpu = X86_CPU(cs);
3170 uint64_t code;
3171 int ret;
3172
3173 switch (run->exit_reason) {
3174 case KVM_EXIT_HLT:
3175 DPRINTF("handle_hlt\n");
3176 qemu_mutex_lock_iothread();
3177 ret = kvm_handle_halt(cpu);
3178 qemu_mutex_unlock_iothread();
3179 break;
3180 case KVM_EXIT_SET_TPR:
3181 ret = 0;
3182 break;
3183 case KVM_EXIT_TPR_ACCESS:
3184 qemu_mutex_lock_iothread();
3185 ret = kvm_handle_tpr_access(cpu);
3186 qemu_mutex_unlock_iothread();
3187 break;
3188 case KVM_EXIT_FAIL_ENTRY:
3189 code = run->fail_entry.hardware_entry_failure_reason;
3190 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3191 code);
3192 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3193 fprintf(stderr,
3194 "\nIf you're running a guest on an Intel machine without "
3195 "unrestricted mode\n"
3196 "support, the failure can be most likely due to the guest "
3197 "entering an invalid\n"
3198 "state for Intel VT. For example, the guest maybe running "
3199 "in big real mode\n"
3200 "which is not supported on less recent Intel processors."
3201 "\n\n");
3202 }
3203 ret = -1;
3204 break;
3205 case KVM_EXIT_EXCEPTION:
3206 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3207 run->ex.exception, run->ex.error_code);
3208 ret = -1;
3209 break;
3210 case KVM_EXIT_DEBUG:
3211 DPRINTF("kvm_exit_debug\n");
3212 qemu_mutex_lock_iothread();
3213 ret = kvm_handle_debug(cpu, &run->debug.arch);
3214 qemu_mutex_unlock_iothread();
3215 break;
3216 case KVM_EXIT_HYPERV:
3217 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3218 break;
3219 case KVM_EXIT_IOAPIC_EOI:
3220 ioapic_eoi_broadcast(run->eoi.vector);
3221 ret = 0;
3222 break;
3223 default:
3224 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3225 ret = -1;
3226 break;
3227 }
3228
3229 return ret;
3230 }
3231
3232 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3233 {
3234 X86CPU *cpu = X86_CPU(cs);
3235 CPUX86State *env = &cpu->env;
3236
3237 kvm_cpu_synchronize_state(cs);
3238 return !(env->cr[0] & CR0_PE_MASK) ||
3239 ((env->segs[R_CS].selector & 3) != 3);
3240 }
3241
3242 void kvm_arch_init_irq_routing(KVMState *s)
3243 {
3244 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3245 /* If kernel can't do irq routing, interrupt source
3246 * override 0->2 cannot be set up as required by HPET.
3247 * So we have to disable it.
3248 */
3249 no_hpet = 1;
3250 }
3251 /* We know at this point that we're using the in-kernel
3252 * irqchip, so we can use irqfds, and on x86 we know
3253 * we can use msi via irqfd and GSI routing.
3254 */
3255 kvm_msi_via_irqfd_allowed = true;
3256 kvm_gsi_routing_allowed = true;
3257
3258 if (kvm_irqchip_is_split()) {
3259 int i;
3260
3261 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3262 MSI routes for signaling interrupts to the local apics. */
3263 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3264 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3265 error_report("Could not enable split IRQ mode.");
3266 exit(1);
3267 }
3268 }
3269 }
3270 }
3271
3272 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3273 {
3274 int ret;
3275 if (machine_kernel_irqchip_split(ms)) {
3276 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3277 if (ret) {
3278 error_report("Could not enable split irqchip mode: %s",
3279 strerror(-ret));
3280 exit(1);
3281 } else {
3282 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3283 kvm_split_irqchip = true;
3284 return 1;
3285 }
3286 } else {
3287 return 0;
3288 }
3289 }
3290
3291 /* Classic KVM device assignment interface. Will remain x86 only. */
3292 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3293 uint32_t flags, uint32_t *dev_id)
3294 {
3295 struct kvm_assigned_pci_dev dev_data = {
3296 .segnr = dev_addr->domain,
3297 .busnr = dev_addr->bus,
3298 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3299 .flags = flags,
3300 };
3301 int ret;
3302
3303 dev_data.assigned_dev_id =
3304 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3305
3306 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3307 if (ret < 0) {
3308 return ret;
3309 }
3310
3311 *dev_id = dev_data.assigned_dev_id;
3312
3313 return 0;
3314 }
3315
3316 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3317 {
3318 struct kvm_assigned_pci_dev dev_data = {
3319 .assigned_dev_id = dev_id,
3320 };
3321
3322 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3323 }
3324
3325 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3326 uint32_t irq_type, uint32_t guest_irq)
3327 {
3328 struct kvm_assigned_irq assigned_irq = {
3329 .assigned_dev_id = dev_id,
3330 .guest_irq = guest_irq,
3331 .flags = irq_type,
3332 };
3333
3334 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3335 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3336 } else {
3337 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3338 }
3339 }
3340
3341 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3342 uint32_t guest_irq)
3343 {
3344 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3345 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3346
3347 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3348 }
3349
3350 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3351 {
3352 struct kvm_assigned_pci_dev dev_data = {
3353 .assigned_dev_id = dev_id,
3354 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3355 };
3356
3357 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3358 }
3359
3360 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3361 uint32_t type)
3362 {
3363 struct kvm_assigned_irq assigned_irq = {
3364 .assigned_dev_id = dev_id,
3365 .flags = type,
3366 };
3367
3368 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3369 }
3370
3371 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3372 {
3373 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3374 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3375 }
3376
3377 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3378 {
3379 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3380 KVM_DEV_IRQ_GUEST_MSI, virq);
3381 }
3382
3383 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3384 {
3385 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3386 KVM_DEV_IRQ_HOST_MSI);
3387 }
3388
3389 bool kvm_device_msix_supported(KVMState *s)
3390 {
3391 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3392 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3393 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3394 }
3395
3396 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3397 uint32_t nr_vectors)
3398 {
3399 struct kvm_assigned_msix_nr msix_nr = {
3400 .assigned_dev_id = dev_id,
3401 .entry_nr = nr_vectors,
3402 };
3403
3404 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3405 }
3406
3407 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3408 int virq)
3409 {
3410 struct kvm_assigned_msix_entry msix_entry = {
3411 .assigned_dev_id = dev_id,
3412 .gsi = virq,
3413 .entry = vector,
3414 };
3415
3416 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3417 }
3418
3419 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3420 {
3421 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3422 KVM_DEV_IRQ_GUEST_MSIX, 0);
3423 }
3424
3425 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3426 {
3427 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3428 KVM_DEV_IRQ_HOST_MSIX);
3429 }
3430
3431 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3432 uint64_t address, uint32_t data, PCIDevice *dev)
3433 {
3434 X86IOMMUState *iommu = x86_iommu_get_default();
3435
3436 if (iommu) {
3437 int ret;
3438 MSIMessage src, dst;
3439 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3440
3441 src.address = route->u.msi.address_hi;
3442 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3443 src.address |= route->u.msi.address_lo;
3444 src.data = route->u.msi.data;
3445
3446 ret = class->int_remap(iommu, &src, &dst, dev ? \
3447 pci_requester_id(dev) : \
3448 X86_IOMMU_SID_INVALID);
3449 if (ret) {
3450 trace_kvm_x86_fixup_msi_error(route->gsi);
3451 return 1;
3452 }
3453
3454 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3455 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3456 route->u.msi.data = dst.data;
3457 }
3458
3459 return 0;
3460 }
3461
3462 typedef struct MSIRouteEntry MSIRouteEntry;
3463
3464 struct MSIRouteEntry {
3465 PCIDevice *dev; /* Device pointer */
3466 int vector; /* MSI/MSIX vector index */
3467 int virq; /* Virtual IRQ index */
3468 QLIST_ENTRY(MSIRouteEntry) list;
3469 };
3470
3471 /* List of used GSI routes */
3472 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3473 QLIST_HEAD_INITIALIZER(msi_route_list);
3474
3475 static void kvm_update_msi_routes_all(void *private, bool global,
3476 uint32_t index, uint32_t mask)
3477 {
3478 int cnt = 0;
3479 MSIRouteEntry *entry;
3480 MSIMessage msg;
3481 /* TODO: explicit route update */
3482 QLIST_FOREACH(entry, &msi_route_list, list) {
3483 cnt++;
3484 msg = pci_get_msi_message(entry->dev, entry->vector);
3485 kvm_irqchip_update_msi_route(kvm_state, entry->virq,
3486 msg, entry->dev);
3487 }
3488 kvm_irqchip_commit_routes(kvm_state);
3489 trace_kvm_x86_update_msi_routes(cnt);
3490 }
3491
3492 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3493 int vector, PCIDevice *dev)
3494 {
3495 static bool notify_list_inited = false;
3496 MSIRouteEntry *entry;
3497
3498 if (!dev) {
3499 /* These are (possibly) IOAPIC routes only used for split
3500 * kernel irqchip mode, while what we are housekeeping are
3501 * PCI devices only. */
3502 return 0;
3503 }
3504
3505 entry = g_new0(MSIRouteEntry, 1);
3506 entry->dev = dev;
3507 entry->vector = vector;
3508 entry->virq = route->gsi;
3509 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3510
3511 trace_kvm_x86_add_msi_route(route->gsi);
3512
3513 if (!notify_list_inited) {
3514 /* For the first time we do add route, add ourselves into
3515 * IOMMU's IEC notify list if needed. */
3516 X86IOMMUState *iommu = x86_iommu_get_default();
3517 if (iommu) {
3518 x86_iommu_iec_register_notifier(iommu,
3519 kvm_update_msi_routes_all,
3520 NULL);
3521 }
3522 notify_list_inited = true;
3523 }
3524 return 0;
3525 }
3526
3527 int kvm_arch_release_virq_post(int virq)
3528 {
3529 MSIRouteEntry *entry, *next;
3530 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3531 if (entry->virq == virq) {
3532 trace_kvm_x86_remove_msi_route(virq);
3533 QLIST_REMOVE(entry, list);
3534 break;
3535 }
3536 }
3537 return 0;
3538 }
3539
3540 int kvm_arch_msi_data_to_gsi(uint32_t data)
3541 {
3542 abort();
3543 }
AR7 emulation for QEMU