2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
34 #include "hw/fw-path-provider.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
41 #include "migration/misc.h"
42 #include "migration/global_state.h"
43 #include "migration/register.h"
44 #include "mmu-hash64.h"
45 #include "mmu-book3s-v3.h"
46 #include "cpu-models.h"
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/ppc/xics.h"
58 #include "hw/pci/msi.h"
60 #include "hw/pci/pci.h"
61 #include "hw/scsi/scsi.h"
62 #include "hw/virtio/virtio-scsi.h"
63 #include "hw/virtio/vhost-scsi-common.h"
65 #include "exec/address-spaces.h"
66 #include "exec/ram_addr.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
72 #include "hw/intc/intc.h"
74 #include "hw/compat.h"
75 #include "qemu/cutils.h"
76 #include "hw/ppc/spapr_cpu_core.h"
77 #include "hw/mem/memory-device.h"
81 /* SLOF memory layout:
83 * SLOF raw image loaded at 0, copies its romfs right below the flat
84 * device-tree, then position SLOF itself 31M below that
86 * So we set FW_OVERHEAD to 40MB which should account for all of that
89 * We load our kernel at 4M, leaving space for SLOF initial image
91 #define FDT_MAX_SIZE 0x100000
92 #define RTAS_MAX_SIZE 0x10000
93 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
94 #define FW_MAX_SIZE 0x400000
95 #define FW_FILE_NAME "slof.bin"
96 #define FW_OVERHEAD 0x2800000
97 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
99 #define MIN_RMA_SLOF 128UL
101 #define PHANDLE_XICP 0x00001111
103 /* These two functions implement the VCPU id numbering: one to compute them
104 * all and one to identify thread 0 of a VCORE. Any change to the first one
105 * is likely to have an impact on the second one, so let's keep them close.
107 static int spapr_vcpu_id(sPAPRMachineState
*spapr
, int cpu_index
)
111 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
113 static bool spapr_is_thread0_in_vcore(sPAPRMachineState
*spapr
,
117 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
120 static ICSState
*spapr_ics_create(sPAPRMachineState
*spapr
,
121 const char *type_ics
,
122 int nr_irqs
, Error
**errp
)
124 Error
*local_err
= NULL
;
127 obj
= object_new(type_ics
);
128 object_property_add_child(OBJECT(spapr
), "ics", obj
, &error_abort
);
129 object_property_add_const_link(obj
, ICS_PROP_XICS
, OBJECT(spapr
),
131 object_property_set_int(obj
, nr_irqs
, "nr-irqs", &local_err
);
135 object_property_set_bool(obj
, true, "realized", &local_err
);
140 return ICS_BASE(obj
);
143 error_propagate(errp
, local_err
);
147 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
149 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
150 * and newer QEMUs don't even have them. In both cases, we don't want
151 * to send anything on the wire.
156 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
157 .name
= "icp/server",
159 .minimum_version_id
= 1,
160 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
161 .fields
= (VMStateField
[]) {
162 VMSTATE_UNUSED(4), /* uint32_t xirr */
163 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
164 VMSTATE_UNUSED(1), /* uint8_t mfrr */
165 VMSTATE_END_OF_LIST()
169 static void pre_2_10_vmstate_register_dummy_icp(int i
)
171 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
172 (void *)(uintptr_t) i
);
175 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
177 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
178 (void *)(uintptr_t) i
);
181 static int xics_max_server_number(sPAPRMachineState
*spapr
)
184 return DIV_ROUND_UP(max_cpus
* spapr
->vsmt
, smp_threads
);
187 static void xics_system_init(MachineState
*machine
, int nr_irqs
, Error
**errp
)
189 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
190 Error
*local_err
= NULL
;
192 /* Initialize the MSI IRQ allocator. */
193 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
194 spapr_irq_msi_init(spapr
, XICS_IRQ_BASE
+ nr_irqs
- SPAPR_IRQ_MSI
);
198 if (machine_kernel_irqchip_allowed(machine
) &&
199 !xics_kvm_init(spapr
, &local_err
)) {
200 spapr
->icp_type
= TYPE_KVM_ICP
;
201 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_KVM
, nr_irqs
,
204 if (machine_kernel_irqchip_required(machine
) && !spapr
->ics
) {
205 error_prepend(&local_err
,
206 "kernel_irqchip requested but unavailable: ");
209 error_free(local_err
);
214 xics_spapr_init(spapr
);
215 spapr
->icp_type
= TYPE_ICP
;
216 spapr
->ics
= spapr_ics_create(spapr
, TYPE_ICS_SIMPLE
, nr_irqs
,
221 error_propagate(errp
, local_err
);
224 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
228 uint32_t servers_prop
[smt_threads
];
229 uint32_t gservers_prop
[smt_threads
* 2];
230 int index
= spapr_get_vcpu_id(cpu
);
232 if (cpu
->compat_pvr
) {
233 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
239 /* Build interrupt servers and gservers properties */
240 for (i
= 0; i
< smt_threads
; i
++) {
241 servers_prop
[i
] = cpu_to_be32(index
+ i
);
242 /* Hack, direct the group queues back to cpu 0 */
243 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
244 gservers_prop
[i
*2 + 1] = 0;
246 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
247 servers_prop
, sizeof(servers_prop
));
251 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
252 gservers_prop
, sizeof(gservers_prop
));
257 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
259 int index
= spapr_get_vcpu_id(cpu
);
260 uint32_t associativity
[] = {cpu_to_be32(0x5),
264 cpu_to_be32(cpu
->node_id
),
267 /* Advertise NUMA via ibm,associativity */
268 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
269 sizeof(associativity
));
272 /* Populate the "ibm,pa-features" property */
273 static void spapr_populate_pa_features(sPAPRMachineState
*spapr
,
275 void *fdt
, int offset
,
278 uint8_t pa_features_206
[] = { 6, 0,
279 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
280 uint8_t pa_features_207
[] = { 24, 0,
281 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
282 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
283 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
284 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
285 uint8_t pa_features_300
[] = { 66, 0,
286 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
287 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
288 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
290 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
292 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
293 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
294 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
295 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
296 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
297 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
298 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
299 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
300 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
301 /* 42: PM, 44: PC RA, 46: SC vec'd */
302 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
303 /* 48: SIMD, 50: QP BFP, 52: String */
304 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
305 /* 54: DecFP, 56: DecI, 58: SHA */
306 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
307 /* 60: NM atomic, 62: RNG */
308 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
310 uint8_t *pa_features
= NULL
;
313 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
314 pa_features
= pa_features_206
;
315 pa_size
= sizeof(pa_features_206
);
317 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
318 pa_features
= pa_features_207
;
319 pa_size
= sizeof(pa_features_207
);
321 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
322 pa_features
= pa_features_300
;
323 pa_size
= sizeof(pa_features_300
);
329 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
331 * Note: we keep CI large pages off by default because a 64K capable
332 * guest provisioned with large pages might otherwise try to map a qemu
333 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
334 * even if that qemu runs on a 4k host.
335 * We dd this bit back here if we are confident this is not an issue
337 pa_features
[3] |= 0x20;
339 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
340 pa_features
[24] |= 0x80; /* Transactional memory support */
342 if (legacy_guest
&& pa_size
> 40) {
343 /* Workaround for broken kernels that attempt (guest) radix
344 * mode when they can't handle it, if they see the radix bit set
345 * in pa-features. So hide it from them. */
346 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
349 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
352 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
354 int ret
= 0, offset
, cpus_offset
;
357 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
360 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
361 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
362 int index
= spapr_get_vcpu_id(cpu
);
363 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
365 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
369 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
371 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
372 if (cpus_offset
< 0) {
373 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
374 if (cpus_offset
< 0) {
378 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
380 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
386 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
387 pft_size_prop
, sizeof(pft_size_prop
));
392 if (nb_numa_nodes
> 1) {
393 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
399 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
404 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
,
405 spapr
->cas_legacy_guest_workaround
);
410 static hwaddr
spapr_node0_size(MachineState
*machine
)
414 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
415 if (numa_info
[i
].node_mem
) {
416 return MIN(pow2floor(numa_info
[i
].node_mem
),
421 return machine
->ram_size
;
424 static void add_str(GString
*s
, const gchar
*s1
)
426 g_string_append_len(s
, s1
, strlen(s1
) + 1);
429 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
432 uint32_t associativity
[] = {
433 cpu_to_be32(0x4), /* length */
434 cpu_to_be32(0x0), cpu_to_be32(0x0),
435 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
438 uint64_t mem_reg_property
[2];
441 mem_reg_property
[0] = cpu_to_be64(start
);
442 mem_reg_property
[1] = cpu_to_be64(size
);
444 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
445 off
= fdt_add_subnode(fdt
, 0, mem_name
);
447 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
448 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
449 sizeof(mem_reg_property
))));
450 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
451 sizeof(associativity
))));
455 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
457 MachineState
*machine
= MACHINE(spapr
);
458 hwaddr mem_start
, node_size
;
459 int i
, nb_nodes
= nb_numa_nodes
;
460 NodeInfo
*nodes
= numa_info
;
463 /* No NUMA nodes, assume there is just one node with whole RAM */
464 if (!nb_numa_nodes
) {
466 ramnode
.node_mem
= machine
->ram_size
;
470 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
471 if (!nodes
[i
].node_mem
) {
474 if (mem_start
>= machine
->ram_size
) {
477 node_size
= nodes
[i
].node_mem
;
478 if (node_size
> machine
->ram_size
- mem_start
) {
479 node_size
= machine
->ram_size
- mem_start
;
483 /* spapr_machine_init() checks for rma_size <= node0_size
485 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
486 mem_start
+= spapr
->rma_size
;
487 node_size
-= spapr
->rma_size
;
489 for ( ; node_size
; ) {
490 hwaddr sizetmp
= pow2floor(node_size
);
492 /* mem_start != 0 here */
493 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
494 sizetmp
= 1ULL << ctzl(mem_start
);
497 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
498 node_size
-= sizetmp
;
499 mem_start
+= sizetmp
;
506 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
507 sPAPRMachineState
*spapr
)
509 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
510 CPUPPCState
*env
= &cpu
->env
;
511 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
512 int index
= spapr_get_vcpu_id(cpu
);
513 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
514 0xffffffff, 0xffffffff};
515 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
516 : SPAPR_TIMEBASE_FREQ
;
517 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
518 uint32_t page_sizes_prop
[64];
519 size_t page_sizes_prop_size
;
520 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
521 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
522 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
523 sPAPRDRConnector
*drc
;
525 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
528 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
530 drc_index
= spapr_drc_index(drc
);
531 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
534 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
535 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
537 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
538 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
539 env
->dcache_line_size
)));
540 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
541 env
->dcache_line_size
)));
542 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
543 env
->icache_line_size
)));
544 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
545 env
->icache_line_size
)));
547 if (pcc
->l1_dcache_size
) {
548 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
549 pcc
->l1_dcache_size
)));
551 warn_report("Unknown L1 dcache size for cpu");
553 if (pcc
->l1_icache_size
) {
554 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
555 pcc
->l1_icache_size
)));
557 warn_report("Unknown L1 icache size for cpu");
560 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
561 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
562 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
563 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
564 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
565 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
567 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
568 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
571 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
572 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
573 segs
, sizeof(segs
))));
576 /* Advertise VSX (vector extensions) if available
577 * 1 == VMX / Altivec available
580 * Only CPUs for which we create core types in spapr_cpu_core.c
581 * are possible, and all of those have VMX */
582 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
583 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
585 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
588 /* Advertise DFP (Decimal Floating Point) if available
589 * 0 / no property == no DFP
590 * 1 == DFP available */
591 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
592 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
595 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
596 sizeof(page_sizes_prop
));
597 if (page_sizes_prop_size
) {
598 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
599 page_sizes_prop
, page_sizes_prop_size
)));
602 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
, false);
604 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
605 cs
->cpu_index
/ vcpus_per_socket
)));
607 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
608 pft_size_prop
, sizeof(pft_size_prop
))));
610 if (nb_numa_nodes
> 1) {
611 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
614 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
616 if (pcc
->radix_page_info
) {
617 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
618 radix_AP_encodings
[i
] =
619 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
621 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
623 pcc
->radix_page_info
->count
*
624 sizeof(radix_AP_encodings
[0]))));
628 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
634 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
636 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
637 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
640 * We walk the CPUs in reverse order to ensure that CPU DT nodes
641 * created by fdt_add_subnode() end up in the right order in FDT
642 * for the guest kernel the enumerate the CPUs correctly.
644 CPU_FOREACH_REVERSE(cs
) {
645 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
646 int index
= spapr_get_vcpu_id(cpu
);
647 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
650 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
654 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
655 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
658 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
663 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
665 MemoryDeviceInfoList
*info
;
667 for (info
= list
; info
; info
= info
->next
) {
668 MemoryDeviceInfo
*value
= info
->value
;
670 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
671 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
673 if (addr
>= pcdimm_info
->addr
&&
674 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
675 return pcdimm_info
->node
;
683 struct sPAPRDrconfCellV2
{
691 typedef struct DrconfCellQueue
{
692 struct sPAPRDrconfCellV2 cell
;
693 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
696 static DrconfCellQueue
*
697 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
698 uint32_t drc_index
, uint32_t aa_index
,
701 DrconfCellQueue
*elem
;
703 elem
= g_malloc0(sizeof(*elem
));
704 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
705 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
706 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
707 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
708 elem
->cell
.flags
= cpu_to_be32(flags
);
713 /* ibm,dynamic-memory-v2 */
714 static int spapr_populate_drmem_v2(sPAPRMachineState
*spapr
, void *fdt
,
715 int offset
, MemoryDeviceInfoList
*dimms
)
717 MachineState
*machine
= MACHINE(spapr
);
718 uint8_t *int_buf
, *cur_index
, buf_len
;
720 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
721 uint64_t addr
, cur_addr
, size
;
722 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
723 uint64_t mem_end
= machine
->device_memory
->base
+
724 memory_region_size(&machine
->device_memory
->mr
);
725 uint32_t node
, nr_entries
= 0;
726 sPAPRDRConnector
*drc
;
727 DrconfCellQueue
*elem
, *next
;
728 MemoryDeviceInfoList
*info
;
729 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
730 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
732 /* Entry to cover RAM and the gap area */
733 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
734 SPAPR_LMB_FLAGS_RESERVED
|
735 SPAPR_LMB_FLAGS_DRC_INVALID
);
736 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
739 cur_addr
= machine
->device_memory
->base
;
740 for (info
= dimms
; info
; info
= info
->next
) {
741 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
747 /* Entry for hot-pluggable area */
748 if (cur_addr
< addr
) {
749 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
751 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
752 cur_addr
, spapr_drc_index(drc
), -1, 0);
753 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
758 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
760 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
761 spapr_drc_index(drc
), node
,
762 SPAPR_LMB_FLAGS_ASSIGNED
);
763 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
765 cur_addr
= addr
+ size
;
768 /* Entry for remaining hotpluggable area */
769 if (cur_addr
< mem_end
) {
770 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
772 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
773 cur_addr
, spapr_drc_index(drc
), -1, 0);
774 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
778 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
779 int_buf
= cur_index
= g_malloc0(buf_len
);
780 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
781 cur_index
+= sizeof(nr_entries
);
783 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
784 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
785 cur_index
+= sizeof(elem
->cell
);
786 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
790 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
798 /* ibm,dynamic-memory */
799 static int spapr_populate_drmem_v1(sPAPRMachineState
*spapr
, void *fdt
,
800 int offset
, MemoryDeviceInfoList
*dimms
)
802 MachineState
*machine
= MACHINE(spapr
);
804 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
805 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
806 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
807 memory_region_size(&machine
->device_memory
->mr
)) /
809 uint32_t *int_buf
, *cur_index
, buf_len
;
812 * Allocate enough buffer size to fit in ibm,dynamic-memory
814 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
815 cur_index
= int_buf
= g_malloc0(buf_len
);
816 int_buf
[0] = cpu_to_be32(nr_lmbs
);
818 for (i
= 0; i
< nr_lmbs
; i
++) {
819 uint64_t addr
= i
* lmb_size
;
820 uint32_t *dynamic_memory
= cur_index
;
822 if (i
>= device_lmb_start
) {
823 sPAPRDRConnector
*drc
;
825 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
828 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
829 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
830 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
831 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
832 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
833 if (memory_region_present(get_system_memory(), addr
)) {
834 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
836 dynamic_memory
[5] = cpu_to_be32(0);
840 * LMB information for RMA, boot time RAM and gap b/n RAM and
841 * device memory region -- all these are marked as reserved
842 * and as having no valid DRC.
844 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
845 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
846 dynamic_memory
[2] = cpu_to_be32(0);
847 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
848 dynamic_memory
[4] = cpu_to_be32(-1);
849 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
850 SPAPR_LMB_FLAGS_DRC_INVALID
);
853 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
855 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
864 * Adds ibm,dynamic-reconfiguration-memory node.
865 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
866 * of this device tree node.
868 static int spapr_populate_drconf_memory(sPAPRMachineState
*spapr
, void *fdt
)
870 MachineState
*machine
= MACHINE(spapr
);
872 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
873 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
874 uint32_t *int_buf
, *cur_index
, buf_len
;
875 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
876 MemoryDeviceInfoList
*dimms
= NULL
;
879 * Don't create the node if there is no device memory
881 if (machine
->ram_size
== machine
->maxram_size
) {
885 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
887 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
888 sizeof(prop_lmb_size
));
893 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
898 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
903 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
904 dimms
= qmp_memory_device_list();
905 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
906 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
908 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
910 qapi_free_MemoryDeviceInfoList(dimms
);
916 /* ibm,associativity-lookup-arrays */
917 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
918 cur_index
= int_buf
= g_malloc0(buf_len
);
921 int_buf
[0] = cpu_to_be32(nr_nodes
);
922 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
924 for (i
= 0; i
< nr_nodes
; i
++) {
925 uint32_t associativity
[] = {
931 memcpy(cur_index
, associativity
, sizeof(associativity
));
934 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
935 (cur_index
- int_buf
) * sizeof(uint32_t));
941 static int spapr_dt_cas_updates(sPAPRMachineState
*spapr
, void *fdt
,
942 sPAPROptionVector
*ov5_updates
)
944 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
947 /* Generate ibm,dynamic-reconfiguration-memory node if required */
948 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
949 g_assert(smc
->dr_lmb_enabled
);
950 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
956 offset
= fdt_path_offset(fdt
, "/chosen");
958 offset
= fdt_add_subnode(fdt
, 0, "chosen");
963 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
964 "ibm,architecture-vec-5");
970 static bool spapr_hotplugged_dev_before_cas(void)
972 Object
*drc_container
, *obj
;
973 ObjectProperty
*prop
;
974 ObjectPropertyIterator iter
;
976 drc_container
= container_get(object_get_root(), "/dr-connector");
977 object_property_iter_init(&iter
, drc_container
);
978 while ((prop
= object_property_iter_next(&iter
))) {
979 if (!strstart(prop
->type
, "link<", NULL
)) {
982 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
983 if (spapr_drc_needed(obj
)) {
990 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
991 target_ulong addr
, target_ulong size
,
992 sPAPROptionVector
*ov5_updates
)
994 void *fdt
, *fdt_skel
;
995 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
997 if (spapr_hotplugged_dev_before_cas()) {
1001 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
1002 error_report("SLOF provided an unexpected CAS buffer size "
1003 TARGET_FMT_lu
" (min: %zu, max: %u)",
1004 size
, sizeof(hdr
), FW_MAX_SIZE
);
1008 size
-= sizeof(hdr
);
1010 /* Create skeleton */
1011 fdt_skel
= g_malloc0(size
);
1012 _FDT((fdt_create(fdt_skel
, size
)));
1013 _FDT((fdt_finish_reservemap(fdt_skel
)));
1014 _FDT((fdt_begin_node(fdt_skel
, "")));
1015 _FDT((fdt_end_node(fdt_skel
)));
1016 _FDT((fdt_finish(fdt_skel
)));
1017 fdt
= g_malloc0(size
);
1018 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
1021 /* Fixup cpu nodes */
1022 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
1024 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
1028 /* Pack resulting tree */
1029 _FDT((fdt_pack(fdt
)));
1031 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1032 trace_spapr_cas_failed(size
);
1036 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1037 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1038 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1044 static void spapr_dt_rtas(sPAPRMachineState
*spapr
, void *fdt
)
1047 GString
*hypertas
= g_string_sized_new(256);
1048 GString
*qemu_hypertas
= g_string_sized_new(256);
1049 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1050 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1051 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1052 uint32_t lrdr_capacity
[] = {
1053 cpu_to_be32(max_device_addr
>> 32),
1054 cpu_to_be32(max_device_addr
& 0xffffffff),
1055 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1056 cpu_to_be32(max_cpus
/ smp_threads
),
1058 uint32_t maxdomains
[] = {
1063 cpu_to_be32(nb_numa_nodes
? nb_numa_nodes
- 1 : 0),
1066 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1069 add_str(hypertas
, "hcall-pft");
1070 add_str(hypertas
, "hcall-term");
1071 add_str(hypertas
, "hcall-dabr");
1072 add_str(hypertas
, "hcall-interrupt");
1073 add_str(hypertas
, "hcall-tce");
1074 add_str(hypertas
, "hcall-vio");
1075 add_str(hypertas
, "hcall-splpar");
1076 add_str(hypertas
, "hcall-bulk");
1077 add_str(hypertas
, "hcall-set-mode");
1078 add_str(hypertas
, "hcall-sprg0");
1079 add_str(hypertas
, "hcall-copy");
1080 add_str(hypertas
, "hcall-debug");
1081 add_str(qemu_hypertas
, "hcall-memop1");
1083 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1084 add_str(hypertas
, "hcall-multi-tce");
1087 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1088 add_str(hypertas
, "hcall-hpt-resize");
1091 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1092 hypertas
->str
, hypertas
->len
));
1093 g_string_free(hypertas
, TRUE
);
1094 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1095 qemu_hypertas
->str
, qemu_hypertas
->len
));
1096 g_string_free(qemu_hypertas
, TRUE
);
1098 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1099 refpoints
, sizeof(refpoints
)));
1101 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1102 maxdomains
, sizeof(maxdomains
)));
1104 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1105 RTAS_ERROR_LOG_MAX
));
1106 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1107 RTAS_EVENT_SCAN_RATE
));
1109 g_assert(msi_nonbroken
);
1110 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1113 * According to PAPR, rtas ibm,os-term does not guarantee a return
1114 * back to the guest cpu.
1116 * While an additional ibm,extended-os-term property indicates
1117 * that rtas call return will always occur. Set this property.
1119 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1121 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1122 lrdr_capacity
, sizeof(lrdr_capacity
)));
1124 spapr_dt_rtas_tokens(fdt
, rtas
);
1127 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
1128 * that the guest may request and thus the valid values for bytes 24..26 of
1129 * option vector 5: */
1130 static void spapr_dt_ov5_platform_support(void *fdt
, int chosen
)
1132 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1135 23, 0x00, /* Xive mode, filled in below. */
1136 24, 0x00, /* Hash/Radix, filled in below. */
1137 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1138 26, 0x40, /* Radix options: GTSE == yes. */
1141 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1142 first_ppc_cpu
->compat_pvr
)) {
1143 /* If we're in a pre POWER9 compat mode then the guest should do hash */
1144 val
[3] = 0x00; /* Hash */
1145 } else if (kvm_enabled()) {
1146 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1147 val
[3] = 0x80; /* OV5_MMU_BOTH */
1148 } else if (kvmppc_has_cap_mmu_radix()) {
1149 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1151 val
[3] = 0x00; /* Hash */
1154 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1157 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1161 static void spapr_dt_chosen(sPAPRMachineState
*spapr
, void *fdt
)
1163 MachineState
*machine
= MACHINE(spapr
);
1165 const char *boot_device
= machine
->boot_order
;
1166 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1168 char *bootlist
= get_boot_devices_list(&cb
);
1170 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1172 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
1173 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1174 spapr
->initrd_base
));
1175 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1176 spapr
->initrd_base
+ spapr
->initrd_size
));
1178 if (spapr
->kernel_size
) {
1179 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1180 cpu_to_be64(spapr
->kernel_size
) };
1182 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1183 &kprop
, sizeof(kprop
)));
1184 if (spapr
->kernel_le
) {
1185 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1189 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1191 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1192 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1193 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1195 if (cb
&& bootlist
) {
1198 for (i
= 0; i
< cb
; i
++) {
1199 if (bootlist
[i
] == '\n') {
1203 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1206 if (boot_device
&& strlen(boot_device
)) {
1207 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1210 if (!spapr
->has_graphics
&& stdout_path
) {
1212 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1213 * kernel. New platforms should only use the "stdout-path" property. Set
1214 * the new property and continue using older property to remain
1215 * compatible with the existing firmware.
1217 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1218 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1221 spapr_dt_ov5_platform_support(fdt
, chosen
);
1223 g_free(stdout_path
);
1227 static void spapr_dt_hypervisor(sPAPRMachineState
*spapr
, void *fdt
)
1229 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1230 * KVM to work under pHyp with some guest co-operation */
1232 uint8_t hypercall
[16];
1234 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1235 /* indicate KVM hypercall interface */
1236 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1237 if (kvmppc_has_cap_fixup_hcalls()) {
1239 * Older KVM versions with older guest kernels were broken
1240 * with the magic page, don't allow the guest to map it.
1242 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1243 sizeof(hypercall
))) {
1244 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1245 hypercall
, sizeof(hypercall
)));
1250 static void *spapr_build_fdt(sPAPRMachineState
*spapr
,
1254 MachineState
*machine
= MACHINE(spapr
);
1255 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1256 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1262 fdt
= g_malloc0(FDT_MAX_SIZE
);
1263 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1266 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1267 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1268 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1271 * Add info to guest to indentify which host is it being run on
1272 * and what is the uuid of the guest
1274 if (kvmppc_get_host_model(&buf
)) {
1275 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1278 if (kvmppc_get_host_serial(&buf
)) {
1279 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1283 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1285 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1286 if (qemu_uuid_set
) {
1287 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1291 if (qemu_get_vm_name()) {
1292 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1293 qemu_get_vm_name()));
1296 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1297 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1299 /* /interrupt controller */
1300 spapr_dt_xics(xics_max_server_number(spapr
), fdt
, PHANDLE_XICP
);
1302 ret
= spapr_populate_memory(spapr
, fdt
);
1304 error_report("couldn't setup memory nodes in fdt");
1309 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1311 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1312 ret
= spapr_rng_populate_dt(fdt
);
1314 error_report("could not set up rng device in the fdt");
1319 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1320 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
);
1322 error_report("couldn't setup PCI devices in fdt");
1328 spapr_populate_cpus_dt_node(fdt
, spapr
);
1330 if (smc
->dr_lmb_enabled
) {
1331 _FDT(spapr_drc_populate_dt(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1334 if (mc
->has_hotpluggable_cpus
) {
1335 int offset
= fdt_path_offset(fdt
, "/cpus");
1336 ret
= spapr_drc_populate_dt(fdt
, offset
, NULL
,
1337 SPAPR_DR_CONNECTOR_TYPE_CPU
);
1339 error_report("Couldn't set up CPU DR device tree properties");
1344 /* /event-sources */
1345 spapr_dt_events(spapr
, fdt
);
1348 spapr_dt_rtas(spapr
, fdt
);
1351 spapr_dt_chosen(spapr
, fdt
);
1354 if (kvm_enabled()) {
1355 spapr_dt_hypervisor(spapr
, fdt
);
1358 /* Build memory reserve map */
1359 if (spapr
->kernel_size
) {
1360 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1362 if (spapr
->initrd_size
) {
1363 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1366 /* ibm,client-architecture-support updates */
1367 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1369 error_report("couldn't setup CAS properties fdt");
1376 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1378 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1381 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1384 CPUPPCState
*env
= &cpu
->env
;
1386 /* The TCG path should also be holding the BQL at this point */
1387 g_assert(qemu_mutex_iothread_locked());
1390 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1391 env
->gpr
[3] = H_PRIVILEGE
;
1393 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1397 static uint64_t spapr_get_patbe(PPCVirtualHypervisor
*vhyp
)
1399 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1401 return spapr
->patb_entry
;
1404 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1405 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1406 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1407 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1408 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1411 * Get the fd to access the kernel htab, re-opening it if necessary
1413 static int get_htab_fd(sPAPRMachineState
*spapr
)
1415 Error
*local_err
= NULL
;
1417 if (spapr
->htab_fd
>= 0) {
1418 return spapr
->htab_fd
;
1421 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1422 if (spapr
->htab_fd
< 0) {
1423 error_report_err(local_err
);
1426 return spapr
->htab_fd
;
1429 void close_htab_fd(sPAPRMachineState
*spapr
)
1431 if (spapr
->htab_fd
>= 0) {
1432 close(spapr
->htab_fd
);
1434 spapr
->htab_fd
= -1;
1437 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1439 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1441 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1444 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1446 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1448 assert(kvm_enabled());
1454 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1457 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1460 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1461 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1465 * HTAB is controlled by KVM. Fetch into temporary buffer
1467 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1468 kvmppc_read_hptes(hptes
, ptex
, n
);
1473 * HTAB is controlled by QEMU. Just point to the internally
1476 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1479 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1480 const ppc_hash_pte64_t
*hptes
,
1483 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1486 g_free((void *)hptes
);
1489 /* Nothing to do for qemu managed HPT */
1492 static void spapr_store_hpte(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1493 uint64_t pte0
, uint64_t pte1
)
1495 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1496 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1499 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1501 stq_p(spapr
->htab
+ offset
, pte0
);
1502 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1506 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1510 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1511 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1512 * that's much more than is needed for Linux guests */
1513 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1514 shift
= MAX(shift
, 18); /* Minimum architected size */
1515 shift
= MIN(shift
, 46); /* Maximum architected size */
1519 void spapr_free_hpt(sPAPRMachineState
*spapr
)
1521 g_free(spapr
->htab
);
1523 spapr
->htab_shift
= 0;
1524 close_htab_fd(spapr
);
1527 void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
1532 /* Clean up any HPT info from a previous boot */
1533 spapr_free_hpt(spapr
);
1535 rc
= kvmppc_reset_htab(shift
);
1537 /* kernel-side HPT needed, but couldn't allocate one */
1538 error_setg_errno(errp
, errno
,
1539 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1541 /* This is almost certainly fatal, but if the caller really
1542 * wants to carry on with shift == 0, it's welcome to try */
1543 } else if (rc
> 0) {
1544 /* kernel-side HPT allocated */
1547 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1551 spapr
->htab_shift
= shift
;
1554 /* kernel-side HPT not needed, allocate in userspace instead */
1555 size_t size
= 1ULL << shift
;
1558 spapr
->htab
= qemu_memalign(size
, size
);
1560 error_setg_errno(errp
, errno
,
1561 "Could not allocate HPT of order %d", shift
);
1565 memset(spapr
->htab
, 0, size
);
1566 spapr
->htab_shift
= shift
;
1568 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1569 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1572 /* We're setting up a hash table, so that means we're not radix */
1573 spapr
->patb_entry
= 0;
1576 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
)
1580 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1581 || (spapr
->cas_reboot
1582 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1583 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1585 uint64_t current_ram_size
;
1587 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1588 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1590 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1592 if (spapr
->vrma_adjust
) {
1593 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1598 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1600 sPAPRDRConnector
*drc
=
1601 (sPAPRDRConnector
*) object_dynamic_cast(child
,
1602 TYPE_SPAPR_DR_CONNECTOR
);
1605 spapr_drc_reset(drc
);
1611 static void spapr_machine_reset(void)
1613 MachineState
*machine
= MACHINE(qdev_get_machine());
1614 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1615 PowerPCCPU
*first_ppc_cpu
;
1616 uint32_t rtas_limit
;
1617 hwaddr rtas_addr
, fdt_addr
;
1621 spapr_caps_apply(spapr
);
1623 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1624 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1625 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1626 spapr
->max_compat_pvr
)) {
1627 /* If using KVM with radix mode available, VCPUs can be started
1628 * without a HPT because KVM will start them in radix mode.
1629 * Set the GR bit in PATB so that we know there is no HPT. */
1630 spapr
->patb_entry
= PATBE1_GR
;
1632 spapr_setup_hpt_and_vrma(spapr
);
1635 /* if this reset wasn't generated by CAS, we should reset our
1636 * negotiated options and start from scratch */
1637 if (!spapr
->cas_reboot
) {
1638 spapr_ovec_cleanup(spapr
->ov5_cas
);
1639 spapr
->ov5_cas
= spapr_ovec_new();
1641 ppc_set_compat(first_ppc_cpu
, spapr
->max_compat_pvr
, &error_fatal
);
1644 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
1645 spapr_irq_msi_reset(spapr
);
1648 qemu_devices_reset();
1650 /* DRC reset may cause a device to be unplugged. This will cause troubles
1651 * if this device is used by another device (eg, a running vhost backend
1652 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1653 * situations, we reset DRCs after all devices have been reset.
1655 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1657 spapr_clear_pending_events(spapr
);
1660 * We place the device tree and RTAS just below either the top of the RMA,
1661 * or just below 2GB, whichever is lowere, so that it can be
1662 * processed with 32-bit real mode code if necessary
1664 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1665 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1666 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1668 fdt
= spapr_build_fdt(spapr
, rtas_addr
, spapr
->rtas_size
);
1670 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1674 /* Should only fail if we've built a corrupted tree */
1677 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1678 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1679 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1684 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1685 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1688 /* Set up the entry state */
1689 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1690 first_ppc_cpu
->env
.gpr
[5] = 0;
1692 spapr
->cas_reboot
= false;
1695 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1697 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1698 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1701 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1705 qdev_init_nofail(dev
);
1707 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1710 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1712 object_initialize(&spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
);
1713 object_property_add_child(OBJECT(spapr
), "rtc", OBJECT(&spapr
->rtc
),
1715 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1717 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1718 "date", &error_fatal
);
1721 /* Returns whether we want to use VGA or not */
1722 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1724 switch (vga_interface_type
) {
1731 return pci_vga_init(pci_bus
) != NULL
;
1734 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1739 static int spapr_pre_load(void *opaque
)
1743 rc
= spapr_caps_pre_load(opaque
);
1751 static int spapr_post_load(void *opaque
, int version_id
)
1753 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1756 err
= spapr_caps_post_migration(spapr
);
1761 if (!object_dynamic_cast(OBJECT(spapr
->ics
), TYPE_ICS_KVM
)) {
1764 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1765 icp_resend(ICP(cpu
->intc
));
1769 /* In earlier versions, there was no separate qdev for the PAPR
1770 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1771 * So when migrating from those versions, poke the incoming offset
1772 * value into the RTC device */
1773 if (version_id
< 3) {
1774 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1777 if (kvm_enabled() && spapr
->patb_entry
) {
1778 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1779 bool radix
= !!(spapr
->patb_entry
& PATBE1_GR
);
1780 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1782 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1784 error_report("Process table config unsupported by the host");
1792 static int spapr_pre_save(void *opaque
)
1796 rc
= spapr_caps_pre_save(opaque
);
1804 static bool version_before_3(void *opaque
, int version_id
)
1806 return version_id
< 3;
1809 static bool spapr_pending_events_needed(void *opaque
)
1811 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1812 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1815 static const VMStateDescription vmstate_spapr_event_entry
= {
1816 .name
= "spapr_event_log_entry",
1818 .minimum_version_id
= 1,
1819 .fields
= (VMStateField
[]) {
1820 VMSTATE_UINT32(summary
, sPAPREventLogEntry
),
1821 VMSTATE_UINT32(extended_length
, sPAPREventLogEntry
),
1822 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, sPAPREventLogEntry
, 0,
1823 NULL
, extended_length
),
1824 VMSTATE_END_OF_LIST()
1828 static const VMStateDescription vmstate_spapr_pending_events
= {
1829 .name
= "spapr_pending_events",
1831 .minimum_version_id
= 1,
1832 .needed
= spapr_pending_events_needed
,
1833 .fields
= (VMStateField
[]) {
1834 VMSTATE_QTAILQ_V(pending_events
, sPAPRMachineState
, 1,
1835 vmstate_spapr_event_entry
, sPAPREventLogEntry
, next
),
1836 VMSTATE_END_OF_LIST()
1840 static bool spapr_ov5_cas_needed(void *opaque
)
1842 sPAPRMachineState
*spapr
= opaque
;
1843 sPAPROptionVector
*ov5_mask
= spapr_ovec_new();
1844 sPAPROptionVector
*ov5_legacy
= spapr_ovec_new();
1845 sPAPROptionVector
*ov5_removed
= spapr_ovec_new();
1848 /* Prior to the introduction of sPAPROptionVector, we had two option
1849 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1850 * Both of these options encode machine topology into the device-tree
1851 * in such a way that the now-booted OS should still be able to interact
1852 * appropriately with QEMU regardless of what options were actually
1853 * negotiatied on the source side.
1855 * As such, we can avoid migrating the CAS-negotiated options if these
1856 * are the only options available on the current machine/platform.
1857 * Since these are the only options available for pseries-2.7 and
1858 * earlier, this allows us to maintain old->new/new->old migration
1861 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1862 * via default pseries-2.8 machines and explicit command-line parameters.
1863 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1864 * of the actual CAS-negotiated values to continue working properly. For
1865 * example, availability of memory unplug depends on knowing whether
1866 * OV5_HP_EVT was negotiated via CAS.
1868 * Thus, for any cases where the set of available CAS-negotiatable
1869 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1870 * include the CAS-negotiated options in the migration stream, unless
1871 * if they affect boot time behaviour only.
1873 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1874 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1875 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1877 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1878 * the mask itself since in the future it's possible "legacy" bits may be
1879 * removed via machine options, which could generate a false positive
1880 * that breaks migration.
1882 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1883 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1885 spapr_ovec_cleanup(ov5_mask
);
1886 spapr_ovec_cleanup(ov5_legacy
);
1887 spapr_ovec_cleanup(ov5_removed
);
1892 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1893 .name
= "spapr_option_vector_ov5_cas",
1895 .minimum_version_id
= 1,
1896 .needed
= spapr_ov5_cas_needed
,
1897 .fields
= (VMStateField
[]) {
1898 VMSTATE_STRUCT_POINTER_V(ov5_cas
, sPAPRMachineState
, 1,
1899 vmstate_spapr_ovec
, sPAPROptionVector
),
1900 VMSTATE_END_OF_LIST()
1904 static bool spapr_patb_entry_needed(void *opaque
)
1906 sPAPRMachineState
*spapr
= opaque
;
1908 return !!spapr
->patb_entry
;
1911 static const VMStateDescription vmstate_spapr_patb_entry
= {
1912 .name
= "spapr_patb_entry",
1914 .minimum_version_id
= 1,
1915 .needed
= spapr_patb_entry_needed
,
1916 .fields
= (VMStateField
[]) {
1917 VMSTATE_UINT64(patb_entry
, sPAPRMachineState
),
1918 VMSTATE_END_OF_LIST()
1922 static bool spapr_irq_map_needed(void *opaque
)
1924 sPAPRMachineState
*spapr
= opaque
;
1926 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1929 static const VMStateDescription vmstate_spapr_irq_map
= {
1930 .name
= "spapr_irq_map",
1932 .minimum_version_id
= 1,
1933 .needed
= spapr_irq_map_needed
,
1934 .fields
= (VMStateField
[]) {
1935 VMSTATE_BITMAP(irq_map
, sPAPRMachineState
, 0, irq_map_nr
),
1936 VMSTATE_END_OF_LIST()
1940 static const VMStateDescription vmstate_spapr
= {
1943 .minimum_version_id
= 1,
1944 .pre_load
= spapr_pre_load
,
1945 .post_load
= spapr_post_load
,
1946 .pre_save
= spapr_pre_save
,
1947 .fields
= (VMStateField
[]) {
1948 /* used to be @next_irq */
1949 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1952 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
1954 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
1955 VMSTATE_END_OF_LIST()
1957 .subsections
= (const VMStateDescription
*[]) {
1958 &vmstate_spapr_ov5_cas
,
1959 &vmstate_spapr_patb_entry
,
1960 &vmstate_spapr_pending_events
,
1961 &vmstate_spapr_cap_htm
,
1962 &vmstate_spapr_cap_vsx
,
1963 &vmstate_spapr_cap_dfp
,
1964 &vmstate_spapr_cap_cfpc
,
1965 &vmstate_spapr_cap_sbbc
,
1966 &vmstate_spapr_cap_ibs
,
1967 &vmstate_spapr_irq_map
,
1972 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
1974 sPAPRMachineState
*spapr
= opaque
;
1976 /* "Iteration" header */
1977 if (!spapr
->htab_shift
) {
1978 qemu_put_be32(f
, -1);
1980 qemu_put_be32(f
, spapr
->htab_shift
);
1984 spapr
->htab_save_index
= 0;
1985 spapr
->htab_first_pass
= true;
1987 if (spapr
->htab_shift
) {
1988 assert(kvm_enabled());
1996 static void htab_save_chunk(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1997 int chunkstart
, int n_valid
, int n_invalid
)
1999 qemu_put_be32(f
, chunkstart
);
2000 qemu_put_be16(f
, n_valid
);
2001 qemu_put_be16(f
, n_invalid
);
2002 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
2003 HASH_PTE_SIZE_64
* n_valid
);
2006 static void htab_save_end_marker(QEMUFile
*f
)
2008 qemu_put_be32(f
, 0);
2009 qemu_put_be16(f
, 0);
2010 qemu_put_be16(f
, 0);
2013 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2016 bool has_timeout
= max_ns
!= -1;
2017 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2018 int index
= spapr
->htab_save_index
;
2019 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2021 assert(spapr
->htab_first_pass
);
2026 /* Consume invalid HPTEs */
2027 while ((index
< htabslots
)
2028 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2029 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2033 /* Consume valid HPTEs */
2035 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2036 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2037 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2041 if (index
> chunkstart
) {
2042 int n_valid
= index
- chunkstart
;
2044 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2047 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2051 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2053 if (index
>= htabslots
) {
2054 assert(index
== htabslots
);
2056 spapr
->htab_first_pass
= false;
2058 spapr
->htab_save_index
= index
;
2061 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2064 bool final
= max_ns
< 0;
2065 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2066 int examined
= 0, sent
= 0;
2067 int index
= spapr
->htab_save_index
;
2068 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2070 assert(!spapr
->htab_first_pass
);
2073 int chunkstart
, invalidstart
;
2075 /* Consume non-dirty HPTEs */
2076 while ((index
< htabslots
)
2077 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2083 /* Consume valid dirty HPTEs */
2084 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2085 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2086 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2087 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2092 invalidstart
= index
;
2093 /* Consume invalid dirty HPTEs */
2094 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2095 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2096 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2097 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2102 if (index
> chunkstart
) {
2103 int n_valid
= invalidstart
- chunkstart
;
2104 int n_invalid
= index
- invalidstart
;
2106 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2107 sent
+= index
- chunkstart
;
2109 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2114 if (examined
>= htabslots
) {
2118 if (index
>= htabslots
) {
2119 assert(index
== htabslots
);
2122 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2124 if (index
>= htabslots
) {
2125 assert(index
== htabslots
);
2129 spapr
->htab_save_index
= index
;
2131 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2134 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2135 #define MAX_KVM_BUF_SIZE 2048
2137 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2139 sPAPRMachineState
*spapr
= opaque
;
2143 /* Iteration header */
2144 if (!spapr
->htab_shift
) {
2145 qemu_put_be32(f
, -1);
2148 qemu_put_be32(f
, 0);
2152 assert(kvm_enabled());
2154 fd
= get_htab_fd(spapr
);
2159 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2163 } else if (spapr
->htab_first_pass
) {
2164 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2166 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2169 htab_save_end_marker(f
);
2174 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2176 sPAPRMachineState
*spapr
= opaque
;
2179 /* Iteration header */
2180 if (!spapr
->htab_shift
) {
2181 qemu_put_be32(f
, -1);
2184 qemu_put_be32(f
, 0);
2190 assert(kvm_enabled());
2192 fd
= get_htab_fd(spapr
);
2197 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2202 if (spapr
->htab_first_pass
) {
2203 htab_save_first_pass(f
, spapr
, -1);
2205 htab_save_later_pass(f
, spapr
, -1);
2209 htab_save_end_marker(f
);
2214 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2216 sPAPRMachineState
*spapr
= opaque
;
2217 uint32_t section_hdr
;
2219 Error
*local_err
= NULL
;
2221 if (version_id
< 1 || version_id
> 1) {
2222 error_report("htab_load() bad version");
2226 section_hdr
= qemu_get_be32(f
);
2228 if (section_hdr
== -1) {
2229 spapr_free_hpt(spapr
);
2234 /* First section gives the htab size */
2235 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2237 error_report_err(local_err
);
2244 assert(kvm_enabled());
2246 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2248 error_report_err(local_err
);
2255 uint16_t n_valid
, n_invalid
;
2257 index
= qemu_get_be32(f
);
2258 n_valid
= qemu_get_be16(f
);
2259 n_invalid
= qemu_get_be16(f
);
2261 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2266 if ((index
+ n_valid
+ n_invalid
) >
2267 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2268 /* Bad index in stream */
2270 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2271 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2277 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2278 HASH_PTE_SIZE_64
* n_valid
);
2281 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2282 HASH_PTE_SIZE_64
* n_invalid
);
2289 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2304 static void htab_save_cleanup(void *opaque
)
2306 sPAPRMachineState
*spapr
= opaque
;
2308 close_htab_fd(spapr
);
2311 static SaveVMHandlers savevm_htab_handlers
= {
2312 .save_setup
= htab_save_setup
,
2313 .save_live_iterate
= htab_save_iterate
,
2314 .save_live_complete_precopy
= htab_save_complete
,
2315 .save_cleanup
= htab_save_cleanup
,
2316 .load_state
= htab_load
,
2319 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2322 MachineState
*machine
= MACHINE(opaque
);
2323 machine
->boot_order
= g_strdup(boot_device
);
2326 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
2328 MachineState
*machine
= MACHINE(spapr
);
2329 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2330 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2333 for (i
= 0; i
< nr_lmbs
; i
++) {
2336 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2337 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2343 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2344 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2345 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2347 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2351 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2352 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2353 " is not aligned to %" PRIu64
" MiB",
2355 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2359 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2360 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2361 " is not aligned to %" PRIu64
" MiB",
2363 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2367 for (i
= 0; i
< nb_numa_nodes
; i
++) {
2368 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2370 "Node %d memory size 0x%" PRIx64
2371 " is not aligned to %" PRIu64
" MiB",
2372 i
, numa_info
[i
].node_mem
,
2373 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2379 /* find cpu slot in machine->possible_cpus by core_id */
2380 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2382 int index
= id
/ smp_threads
;
2384 if (index
>= ms
->possible_cpus
->len
) {
2390 return &ms
->possible_cpus
->cpus
[index
];
2393 static void spapr_set_vsmt_mode(sPAPRMachineState
*spapr
, Error
**errp
)
2395 Error
*local_err
= NULL
;
2396 bool vsmt_user
= !!spapr
->vsmt
;
2397 int kvm_smt
= kvmppc_smt_threads();
2400 if (!kvm_enabled() && (smp_threads
> 1)) {
2401 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2402 "on a pseries machine");
2405 if (!is_power_of_2(smp_threads
)) {
2406 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2407 "machine because it must be a power of 2", smp_threads
);
2411 /* Detemine the VSMT mode to use: */
2413 if (spapr
->vsmt
< smp_threads
) {
2414 error_setg(&local_err
, "Cannot support VSMT mode %d"
2415 " because it must be >= threads/core (%d)",
2416 spapr
->vsmt
, smp_threads
);
2419 /* In this case, spapr->vsmt has been set by the command line */
2422 * Default VSMT value is tricky, because we need it to be as
2423 * consistent as possible (for migration), but this requires
2424 * changing it for at least some existing cases. We pick 8 as
2425 * the value that we'd get with KVM on POWER8, the
2426 * overwhelmingly common case in production systems.
2428 spapr
->vsmt
= MAX(8, smp_threads
);
2431 /* KVM: If necessary, set the SMT mode: */
2432 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2433 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2435 /* Looks like KVM isn't able to change VSMT mode */
2436 error_setg(&local_err
,
2437 "Failed to set KVM's VSMT mode to %d (errno %d)",
2439 /* We can live with that if the default one is big enough
2440 * for the number of threads, and a submultiple of the one
2441 * we want. In this case we'll waste some vcpu ids, but
2442 * behaviour will be correct */
2443 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2444 warn_report_err(local_err
);
2449 error_append_hint(&local_err
,
2450 "On PPC, a VM with %d threads/core"
2451 " on a host with %d threads/core"
2452 " requires the use of VSMT mode %d.\n",
2453 smp_threads
, kvm_smt
, spapr
->vsmt
);
2455 kvmppc_hint_smt_possible(&local_err
);
2460 /* else TCG: nothing to do currently */
2462 error_propagate(errp
, local_err
);
2465 static void spapr_init_cpus(sPAPRMachineState
*spapr
)
2467 MachineState
*machine
= MACHINE(spapr
);
2468 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2469 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2470 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2471 const CPUArchIdList
*possible_cpus
;
2472 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2475 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2476 if (mc
->has_hotpluggable_cpus
) {
2477 if (smp_cpus
% smp_threads
) {
2478 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2479 smp_cpus
, smp_threads
);
2482 if (max_cpus
% smp_threads
) {
2483 error_report("max_cpus (%u) must be multiple of threads (%u)",
2484 max_cpus
, smp_threads
);
2488 if (max_cpus
!= smp_cpus
) {
2489 error_report("This machine version does not support CPU hotplug");
2492 boot_cores_nr
= possible_cpus
->len
;
2495 /* VSMT must be set in order to be able to compute VCPU ids, ie to
2496 * call xics_max_server_number() or spapr_vcpu_id().
2498 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2500 if (smc
->pre_2_10_has_unused_icps
) {
2503 for (i
= 0; i
< xics_max_server_number(spapr
); i
++) {
2504 /* Dummy entries get deregistered when real ICPState objects
2505 * are registered during CPU core hotplug.
2507 pre_2_10_vmstate_register_dummy_icp(i
);
2511 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2512 int core_id
= i
* smp_threads
;
2514 if (mc
->has_hotpluggable_cpus
) {
2515 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2516 spapr_vcpu_id(spapr
, core_id
));
2519 if (i
< boot_cores_nr
) {
2520 Object
*core
= object_new(type
);
2521 int nr_threads
= smp_threads
;
2523 /* Handle the partially filled core for older machine types */
2524 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2525 nr_threads
= smp_cpus
- i
* smp_threads
;
2528 object_property_set_int(core
, nr_threads
, "nr-threads",
2530 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2532 object_property_set_bool(core
, true, "realized", &error_fatal
);
2537 /* pSeries LPAR / sPAPR hardware init */
2538 static void spapr_machine_init(MachineState
*machine
)
2540 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
2541 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2542 const char *kernel_filename
= machine
->kernel_filename
;
2543 const char *initrd_filename
= machine
->initrd_filename
;
2546 MemoryRegion
*sysmem
= get_system_memory();
2547 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2548 hwaddr node0_size
= spapr_node0_size(machine
);
2549 long load_limit
, fw_size
;
2551 Error
*resize_hpt_err
= NULL
;
2553 msi_nonbroken
= true;
2555 QLIST_INIT(&spapr
->phbs
);
2556 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2558 /* Determine capabilities to run with */
2559 spapr_caps_init(spapr
);
2561 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2562 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2564 * If the user explicitly requested a mode we should either
2565 * supply it, or fail completely (which we do below). But if
2566 * it's not set explicitly, we reset our mode to something
2569 if (resize_hpt_err
) {
2570 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2571 error_free(resize_hpt_err
);
2572 resize_hpt_err
= NULL
;
2574 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2578 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2580 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2582 * User requested HPT resize, but this host can't supply it. Bail out
2584 error_report_err(resize_hpt_err
);
2588 spapr
->rma_size
= node0_size
;
2590 /* With KVM, we don't actually know whether KVM supports an
2591 * unbounded RMA (PR KVM) or is limited by the hash table size
2592 * (HV KVM using VRMA), so we always assume the latter
2594 * In that case, we also limit the initial allocations for RTAS
2595 * etc... to 256M since we have no way to know what the VRMA size
2596 * is going to be as it depends on the size of the hash table
2597 * which isn't determined yet.
2599 if (kvm_enabled()) {
2600 spapr
->vrma_adjust
= 1;
2601 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2604 /* Actually we don't support unbounded RMA anymore since we added
2605 * proper emulation of HV mode. The max we can get is 16G which
2606 * also happens to be what we configure for PAPR mode so make sure
2607 * we don't do anything bigger than that
2609 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2611 if (spapr
->rma_size
> node0_size
) {
2612 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2617 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2618 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2620 /* Set up Interrupt Controller before we create the VCPUs */
2621 xics_system_init(machine
, XICS_IRQS_SPAPR
, &error_fatal
);
2623 /* Set up containers for ibm,client-architecture-support negotiated options
2625 spapr
->ov5
= spapr_ovec_new();
2626 spapr
->ov5_cas
= spapr_ovec_new();
2628 if (smc
->dr_lmb_enabled
) {
2629 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2630 spapr_validate_node_memory(machine
, &error_fatal
);
2633 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2635 /* advertise support for dedicated HP event source to guests */
2636 if (spapr
->use_hotplug_event_source
) {
2637 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2640 /* advertise support for HPT resizing */
2641 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2642 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2645 /* advertise support for ibm,dyamic-memory-v2 */
2646 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2649 spapr_init_cpus(spapr
);
2651 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2652 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2653 spapr
->max_compat_pvr
)) {
2654 /* KVM and TCG always allow GTSE with radix... */
2655 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2657 /* ... but not with hash (currently). */
2659 if (kvm_enabled()) {
2660 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2661 kvmppc_enable_logical_ci_hcalls();
2662 kvmppc_enable_set_mode_hcall();
2664 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2665 kvmppc_enable_clear_ref_mod_hcalls();
2669 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2671 memory_region_add_subregion(sysmem
, 0, ram
);
2673 /* always allocate the device memory information */
2674 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2676 /* initialize hotplug memory address space */
2677 if (machine
->ram_size
< machine
->maxram_size
) {
2678 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2680 * Limit the number of hotpluggable memory slots to half the number
2681 * slots that KVM supports, leaving the other half for PCI and other
2682 * devices. However ensure that number of slots doesn't drop below 32.
2684 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2685 SPAPR_MAX_RAM_SLOTS
;
2687 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2688 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2690 if (machine
->ram_slots
> max_memslots
) {
2691 error_report("Specified number of memory slots %"
2692 PRIu64
" exceeds max supported %d",
2693 machine
->ram_slots
, max_memslots
);
2697 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2698 SPAPR_DEVICE_MEM_ALIGN
);
2699 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2700 "device-memory", device_mem_size
);
2701 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2702 &machine
->device_memory
->mr
);
2705 if (smc
->dr_lmb_enabled
) {
2706 spapr_create_lmb_dr_connectors(spapr
);
2709 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2711 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2714 spapr
->rtas_size
= get_image_size(filename
);
2715 if (spapr
->rtas_size
< 0) {
2716 error_report("Could not get size of LPAR rtas '%s'", filename
);
2719 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2720 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2721 error_report("Could not load LPAR rtas '%s'", filename
);
2724 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2725 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2726 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2731 /* Set up RTAS event infrastructure */
2732 spapr_events_init(spapr
);
2734 /* Set up the RTC RTAS interfaces */
2735 spapr_rtc_create(spapr
);
2737 /* Set up VIO bus */
2738 spapr
->vio_bus
= spapr_vio_bus_init();
2740 for (i
= 0; i
< serial_max_hds(); i
++) {
2742 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2746 /* We always have at least the nvram device on VIO */
2747 spapr_create_nvram(spapr
);
2750 spapr_pci_rtas_init();
2752 phb
= spapr_create_phb(spapr
, 0);
2754 for (i
= 0; i
< nb_nics
; i
++) {
2755 NICInfo
*nd
= &nd_table
[i
];
2758 nd
->model
= g_strdup("spapr-vlan");
2761 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2762 g_str_equal(nd
->model
, "ibmveth")) {
2763 spapr_vlan_create(spapr
->vio_bus
, nd
);
2765 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2769 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2770 spapr_vscsi_create(spapr
->vio_bus
);
2774 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2775 spapr
->has_graphics
= true;
2776 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2780 if (smc
->use_ohci_by_default
) {
2781 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2783 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2786 if (spapr
->has_graphics
) {
2787 USBBus
*usb_bus
= usb_bus_find(-1);
2789 usb_create_simple(usb_bus
, "usb-kbd");
2790 usb_create_simple(usb_bus
, "usb-mouse");
2794 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2796 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2801 if (kernel_filename
) {
2802 uint64_t lowaddr
= 0;
2804 spapr
->kernel_size
= load_elf(kernel_filename
, translate_kernel_address
,
2805 NULL
, NULL
, &lowaddr
, NULL
, 1,
2806 PPC_ELF_MACHINE
, 0, 0);
2807 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2808 spapr
->kernel_size
= load_elf(kernel_filename
,
2809 translate_kernel_address
, NULL
, NULL
,
2810 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2812 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2814 if (spapr
->kernel_size
< 0) {
2815 error_report("error loading %s: %s", kernel_filename
,
2816 load_elf_strerror(spapr
->kernel_size
));
2821 if (initrd_filename
) {
2822 /* Try to locate the initrd in the gap between the kernel
2823 * and the firmware. Add a bit of space just in case
2825 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2826 + 0x1ffff) & ~0xffff;
2827 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2830 - spapr
->initrd_base
);
2831 if (spapr
->initrd_size
< 0) {
2832 error_report("could not load initial ram disk '%s'",
2839 if (bios_name
== NULL
) {
2840 bios_name
= FW_FILE_NAME
;
2842 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2844 error_report("Could not find LPAR firmware '%s'", bios_name
);
2847 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2849 error_report("Could not load LPAR firmware '%s'", filename
);
2854 /* FIXME: Should register things through the MachineState's qdev
2855 * interface, this is a legacy from the sPAPREnvironment structure
2856 * which predated MachineState but had a similar function */
2857 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2858 register_savevm_live(NULL
, "spapr/htab", -1, 1,
2859 &savevm_htab_handlers
, spapr
);
2861 qemu_register_boot_set(spapr_boot_set
, spapr
);
2863 if (kvm_enabled()) {
2864 /* to stop and start vmclock */
2865 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2868 kvmppc_spapr_enable_inkernel_multitce();
2872 static int spapr_kvm_type(const char *vm_type
)
2878 if (!strcmp(vm_type
, "HV")) {
2882 if (!strcmp(vm_type
, "PR")) {
2886 error_report("Unknown kvm-type specified '%s'", vm_type
);
2891 * Implementation of an interface to adjust firmware path
2892 * for the bootindex property handling.
2894 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
2897 #define CAST(type, obj, name) \
2898 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2899 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
2900 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2901 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
2904 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
2905 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
2906 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
2910 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2911 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2912 * in the top 16 bits of the 64-bit LUN
2914 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
2915 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2916 (uint64_t)id
<< 48);
2917 } else if (virtio
) {
2919 * We use SRP luns of the form 01000000 | (target << 8) | lun
2920 * in the top 32 bits of the 64-bit LUN
2921 * Note: the quote above is from SLOF and it is wrong,
2922 * the actual binding is:
2923 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2925 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
2926 if (d
->lun
>= 256) {
2927 /* Use the LUN "flat space addressing method" */
2930 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2931 (uint64_t)id
<< 32);
2934 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2935 * in the top 32 bits of the 64-bit LUN
2937 unsigned usb_port
= atoi(usb
->port
->path
);
2938 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
2939 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2940 (uint64_t)id
<< 32);
2945 * SLOF probes the USB devices, and if it recognizes that the device is a
2946 * storage device, it changes its name to "storage" instead of "usb-host",
2947 * and additionally adds a child node for the SCSI LUN, so the correct
2948 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2950 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
2951 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
2952 if (usb_host_dev_is_scsi_storage(usbdev
)) {
2953 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
2958 /* Replace "pci" with "pci@800000020000000" */
2959 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
2963 /* Same logic as virtio above */
2964 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
2965 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
2968 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
2969 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2970 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
2971 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
2977 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
2979 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2981 return g_strdup(spapr
->kvm_type
);
2984 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
2986 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2988 g_free(spapr
->kvm_type
);
2989 spapr
->kvm_type
= g_strdup(value
);
2992 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
2994 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2996 return spapr
->use_hotplug_event_source
;
2999 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3002 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3004 spapr
->use_hotplug_event_source
= value
;
3007 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3012 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3014 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3016 switch (spapr
->resize_hpt
) {
3017 case SPAPR_RESIZE_HPT_DEFAULT
:
3018 return g_strdup("default");
3019 case SPAPR_RESIZE_HPT_DISABLED
:
3020 return g_strdup("disabled");
3021 case SPAPR_RESIZE_HPT_ENABLED
:
3022 return g_strdup("enabled");
3023 case SPAPR_RESIZE_HPT_REQUIRED
:
3024 return g_strdup("required");
3026 g_assert_not_reached();
3029 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3031 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3033 if (strcmp(value
, "default") == 0) {
3034 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3035 } else if (strcmp(value
, "disabled") == 0) {
3036 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3037 } else if (strcmp(value
, "enabled") == 0) {
3038 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3039 } else if (strcmp(value
, "required") == 0) {
3040 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3042 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3046 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3047 void *opaque
, Error
**errp
)
3049 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3052 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3053 void *opaque
, Error
**errp
)
3055 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3058 static void spapr_instance_init(Object
*obj
)
3060 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3062 spapr
->htab_fd
= -1;
3063 spapr
->use_hotplug_event_source
= true;
3064 object_property_add_str(obj
, "kvm-type",
3065 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3066 object_property_set_description(obj
, "kvm-type",
3067 "Specifies the KVM virtualization mode (HV, PR)",
3069 object_property_add_bool(obj
, "modern-hotplug-events",
3070 spapr_get_modern_hotplug_events
,
3071 spapr_set_modern_hotplug_events
,
3073 object_property_set_description(obj
, "modern-hotplug-events",
3074 "Use dedicated hotplug event mechanism in"
3075 " place of standard EPOW events when possible"
3076 " (required for memory hot-unplug support)",
3078 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3079 "Maximum permitted CPU compatibility mode",
3082 object_property_add_str(obj
, "resize-hpt",
3083 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3084 object_property_set_description(obj
, "resize-hpt",
3085 "Resizing of the Hash Page Table (enabled, disabled, required)",
3087 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3088 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3089 object_property_set_description(obj
, "vsmt",
3090 "Virtual SMT: KVM behaves as if this were"
3091 " the host's SMT mode", &error_abort
);
3092 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3093 spapr_get_msix_emulation
, NULL
, NULL
);
3096 static void spapr_machine_finalizefn(Object
*obj
)
3098 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3100 g_free(spapr
->kvm_type
);
3103 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3105 cpu_synchronize_state(cs
);
3106 ppc_cpu_do_system_reset(cs
);
3109 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3114 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3118 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3119 uint32_t node
, bool dedicated_hp_event_source
,
3122 sPAPRDRConnector
*drc
;
3123 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3124 int i
, fdt_offset
, fdt_size
;
3126 uint64_t addr
= addr_start
;
3127 bool hotplugged
= spapr_drc_hotplugged(dev
);
3128 Error
*local_err
= NULL
;
3130 for (i
= 0; i
< nr_lmbs
; i
++) {
3131 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3132 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3135 fdt
= create_device_tree(&fdt_size
);
3136 fdt_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3137 SPAPR_MEMORY_BLOCK_SIZE
);
3139 spapr_drc_attach(drc
, dev
, fdt
, fdt_offset
, &local_err
);
3141 while (addr
> addr_start
) {
3142 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3143 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3144 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3145 spapr_drc_detach(drc
);
3148 error_propagate(errp
, local_err
);
3152 spapr_drc_reset(drc
);
3154 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3156 /* send hotplug notification to the
3157 * guest only in case of hotplugged memory
3160 if (dedicated_hp_event_source
) {
3161 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3162 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3163 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3165 spapr_drc_index(drc
));
3167 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3173 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3176 Error
*local_err
= NULL
;
3177 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3178 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3179 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3180 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
, &error_abort
);
3181 uint64_t align
, size
, addr
;
3184 align
= memory_region_get_alignment(mr
);
3185 size
= memory_region_size(mr
);
3187 pc_dimm_plug(dev
, MACHINE(ms
), align
, &local_err
);
3192 addr
= object_property_get_uint(OBJECT(dimm
),
3193 PC_DIMM_ADDR_PROP
, &local_err
);
3198 node
= object_property_get_uint(OBJECT(dev
), PC_DIMM_NODE_PROP
,
3200 spapr_add_lmbs(dev
, addr
, size
, node
,
3201 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3210 pc_dimm_unplug(dev
, MACHINE(ms
));
3212 error_propagate(errp
, local_err
);
3215 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3218 const sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3219 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3220 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3221 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3227 if (!smc
->dr_lmb_enabled
) {
3228 error_setg(errp
, "Memory hotplug not supported for this machine");
3232 mr
= ddc
->get_memory_region(dimm
, errp
);
3236 size
= memory_region_size(mr
);
3238 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3239 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3240 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3244 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3246 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3247 spapr_check_pagesize(spapr
, pagesize
, errp
);
3250 struct sPAPRDIMMState
{
3253 QTAILQ_ENTRY(sPAPRDIMMState
) next
;
3256 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_find(sPAPRMachineState
*s
,
3259 sPAPRDIMMState
*dimm_state
= NULL
;
3261 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3262 if (dimm_state
->dimm
== dimm
) {
3269 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_add(sPAPRMachineState
*spapr
,
3273 sPAPRDIMMState
*ds
= NULL
;
3276 * If this request is for a DIMM whose removal had failed earlier
3277 * (due to guest's refusal to remove the LMBs), we would have this
3278 * dimm already in the pending_dimm_unplugs list. In that
3279 * case don't add again.
3281 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3283 ds
= g_malloc0(sizeof(sPAPRDIMMState
));
3284 ds
->nr_lmbs
= nr_lmbs
;
3286 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3291 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState
*spapr
,
3292 sPAPRDIMMState
*dimm_state
)
3294 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3298 static sPAPRDIMMState
*spapr_recover_pending_dimm_state(sPAPRMachineState
*ms
,
3301 sPAPRDRConnector
*drc
;
3302 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3303 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
, &error_abort
);
3304 uint64_t size
= memory_region_size(mr
);
3305 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3306 uint32_t avail_lmbs
= 0;
3307 uint64_t addr_start
, addr
;
3310 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3314 for (i
= 0; i
< nr_lmbs
; i
++) {
3315 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3316 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3321 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3324 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3327 /* Callback to be called during DRC release. */
3328 void spapr_lmb_release(DeviceState
*dev
)
3330 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3331 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3332 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3334 /* This information will get lost if a migration occurs
3335 * during the unplug process. In this case recover it. */
3337 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3339 /* The DRC being examined by the caller at least must be counted */
3340 g_assert(ds
->nr_lmbs
);
3343 if (--ds
->nr_lmbs
) {
3348 * Now that all the LMBs have been removed by the guest, call the
3349 * unplug handler chain. This can never fail.
3351 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3354 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3356 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3357 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3359 pc_dimm_unplug(dev
, MACHINE(hotplug_dev
));
3360 object_unparent(OBJECT(dev
));
3361 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3364 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3365 DeviceState
*dev
, Error
**errp
)
3367 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3368 Error
*local_err
= NULL
;
3369 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3370 PCDIMMDeviceClass
*ddc
= PC_DIMM_GET_CLASS(dimm
);
3371 MemoryRegion
*mr
= ddc
->get_memory_region(dimm
, &error_abort
);
3373 uint64_t size
, addr_start
, addr
;
3375 sPAPRDRConnector
*drc
;
3377 size
= memory_region_size(mr
);
3378 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3380 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3387 * An existing pending dimm state for this DIMM means that there is an
3388 * unplug operation in progress, waiting for the spapr_lmb_release
3389 * callback to complete the job (BQL can't cover that far). In this case,
3390 * bail out to avoid detaching DRCs that were already released.
3392 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3393 error_setg(&local_err
,
3394 "Memory unplug already in progress for device %s",
3399 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3402 for (i
= 0; i
< nr_lmbs
; i
++) {
3403 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3404 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3407 spapr_drc_detach(drc
);
3408 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3411 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3412 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3413 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3414 nr_lmbs
, spapr_drc_index(drc
));
3416 error_propagate(errp
, local_err
);
3419 static void *spapr_populate_hotplug_cpu_dt(CPUState
*cs
, int *fdt_offset
,
3420 sPAPRMachineState
*spapr
)
3422 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3423 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3424 int id
= spapr_get_vcpu_id(cpu
);
3426 int offset
, fdt_size
;
3429 fdt
= create_device_tree(&fdt_size
);
3430 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3431 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3433 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3436 *fdt_offset
= offset
;
3440 /* Callback to be called during DRC release. */
3441 void spapr_core_release(DeviceState
*dev
)
3443 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3445 /* Call the unplug handler chain. This can never fail. */
3446 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3449 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3451 MachineState
*ms
= MACHINE(hotplug_dev
);
3452 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3453 CPUCore
*cc
= CPU_CORE(dev
);
3454 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3456 if (smc
->pre_2_10_has_unused_icps
) {
3457 sPAPRCPUCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3460 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3461 CPUState
*cs
= CPU(sc
->threads
[i
]);
3463 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3468 core_slot
->cpu
= NULL
;
3469 object_unparent(OBJECT(dev
));
3473 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3476 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3478 sPAPRDRConnector
*drc
;
3479 CPUCore
*cc
= CPU_CORE(dev
);
3481 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3482 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3487 error_setg(errp
, "Boot CPU core may not be unplugged");
3491 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3492 spapr_vcpu_id(spapr
, cc
->core_id
));
3495 spapr_drc_detach(drc
);
3497 spapr_hotplug_req_remove_by_index(drc
);
3500 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3503 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3504 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3505 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3506 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3507 CPUCore
*cc
= CPU_CORE(dev
);
3508 CPUState
*cs
= CPU(core
->threads
[0]);
3509 sPAPRDRConnector
*drc
;
3510 Error
*local_err
= NULL
;
3511 CPUArchId
*core_slot
;
3513 bool hotplugged
= spapr_drc_hotplugged(dev
);
3515 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3517 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3521 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3522 spapr_vcpu_id(spapr
, cc
->core_id
));
3524 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3530 fdt
= spapr_populate_hotplug_cpu_dt(cs
, &fdt_offset
, spapr
);
3532 spapr_drc_attach(drc
, dev
, fdt
, fdt_offset
, &local_err
);
3535 error_propagate(errp
, local_err
);
3541 * Send hotplug notification interrupt to the guest only
3542 * in case of hotplugged CPUs.
3544 spapr_hotplug_req_add_by_index(drc
);
3546 spapr_drc_reset(drc
);
3550 core_slot
->cpu
= OBJECT(dev
);
3552 if (smc
->pre_2_10_has_unused_icps
) {
3555 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3556 cs
= CPU(core
->threads
[i
]);
3557 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3562 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3565 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3566 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3567 Error
*local_err
= NULL
;
3568 CPUCore
*cc
= CPU_CORE(dev
);
3569 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3570 const char *type
= object_get_typename(OBJECT(dev
));
3571 CPUArchId
*core_slot
;
3574 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3575 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3579 if (strcmp(base_core_type
, type
)) {
3580 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3584 if (cc
->core_id
% smp_threads
) {
3585 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3590 * In general we should have homogeneous threads-per-core, but old
3591 * (pre hotplug support) machine types allow the last core to have
3592 * reduced threads as a compatibility hack for when we allowed
3593 * total vcpus not a multiple of threads-per-core.
3595 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3596 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3597 cc
->nr_threads
, smp_threads
);
3601 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3603 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3607 if (core_slot
->cpu
) {
3608 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3612 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3615 error_propagate(errp
, local_err
);
3618 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
3619 DeviceState
*dev
, Error
**errp
)
3621 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3622 spapr_memory_plug(hotplug_dev
, dev
, errp
);
3623 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3624 spapr_core_plug(hotplug_dev
, dev
, errp
);
3628 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
3629 DeviceState
*dev
, Error
**errp
)
3631 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3632 spapr_memory_unplug(hotplug_dev
, dev
);
3633 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3634 spapr_core_unplug(hotplug_dev
, dev
);
3638 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
3639 DeviceState
*dev
, Error
**errp
)
3641 sPAPRMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3642 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
3644 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3645 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
3646 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
3648 /* NOTE: this means there is a window after guest reset, prior to
3649 * CAS negotiation, where unplug requests will fail due to the
3650 * capability not being detected yet. This is a bit different than
3651 * the case with PCI unplug, where the events will be queued and
3652 * eventually handled by the guest after boot
3654 error_setg(errp
, "Memory hot unplug not supported for this guest");
3656 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3657 if (!mc
->has_hotpluggable_cpus
) {
3658 error_setg(errp
, "CPU hot unplug not supported on this machine");
3661 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
3665 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
3666 DeviceState
*dev
, Error
**errp
)
3668 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3669 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
3670 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3671 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
3675 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
3678 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
3679 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3680 return HOTPLUG_HANDLER(machine
);
3685 static CpuInstanceProperties
3686 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
3688 CPUArchId
*core_slot
;
3689 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3691 /* make sure possible_cpu are intialized */
3692 mc
->possible_cpu_arch_ids(machine
);
3693 /* get CPU core slot containing thread that matches cpu_index */
3694 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
3696 return core_slot
->props
;
3699 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
3701 return idx
/ smp_cores
% nb_numa_nodes
;
3704 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
3707 const char *core_type
;
3708 int spapr_max_cores
= max_cpus
/ smp_threads
;
3709 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3711 if (!mc
->has_hotpluggable_cpus
) {
3712 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
3714 if (machine
->possible_cpus
) {
3715 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
3716 return machine
->possible_cpus
;
3719 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3721 error_report("Unable to find sPAPR CPU Core definition");
3725 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3726 sizeof(CPUArchId
) * spapr_max_cores
);
3727 machine
->possible_cpus
->len
= spapr_max_cores
;
3728 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
3729 int core_id
= i
* smp_threads
;
3731 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
3732 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
3733 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
3734 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3735 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
3737 return machine
->possible_cpus
;
3740 static void spapr_phb_placement(sPAPRMachineState
*spapr
, uint32_t index
,
3741 uint64_t *buid
, hwaddr
*pio
,
3742 hwaddr
*mmio32
, hwaddr
*mmio64
,
3743 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3746 * New-style PHB window placement.
3748 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3749 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3752 * Some guest kernels can't work with MMIO windows above 1<<46
3753 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3755 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3756 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3757 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3758 * 1TiB 64-bit MMIO windows for each PHB.
3760 const uint64_t base_buid
= 0x800000020000000ULL
;
3761 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3762 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3765 /* Sanity check natural alignments */
3766 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3767 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3768 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
3769 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
3770 /* Sanity check bounds */
3771 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
3772 SPAPR_PCI_MEM32_WIN_SIZE
);
3773 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
3774 SPAPR_PCI_MEM64_WIN_SIZE
);
3776 if (index
>= SPAPR_MAX_PHBS
) {
3777 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
3778 SPAPR_MAX_PHBS
- 1);
3782 *buid
= base_buid
+ index
;
3783 for (i
= 0; i
< n_dma
; ++i
) {
3784 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3787 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
3788 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
3789 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
3792 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
3794 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3796 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
3799 static void spapr_ics_resend(XICSFabric
*dev
)
3801 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3803 ics_resend(spapr
->ics
);
3806 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
3808 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
3810 return cpu
? ICP(cpu
->intc
) : NULL
;
3813 #define ICS_IRQ_FREE(ics, srcno) \
3814 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3816 static int ics_find_free_block(ICSState
*ics
, int num
, int alignnum
)
3820 for (first
= 0; first
< ics
->nr_irqs
; first
+= alignnum
) {
3821 if (num
> (ics
->nr_irqs
- first
)) {
3824 for (i
= first
; i
< first
+ num
; ++i
) {
3825 if (!ICS_IRQ_FREE(ics
, i
)) {
3829 if (i
== (first
+ num
)) {
3837 int spapr_irq_find(sPAPRMachineState
*spapr
, int num
, bool align
, Error
**errp
)
3839 ICSState
*ics
= spapr
->ics
;
3845 * MSIMesage::data is used for storing VIRQ so
3846 * it has to be aligned to num to support multiple
3847 * MSI vectors. MSI-X is not affected by this.
3848 * The hint is used for the first IRQ, the rest should
3849 * be allocated continuously.
3852 assert((num
== 1) || (num
== 2) || (num
== 4) ||
3853 (num
== 8) || (num
== 16) || (num
== 32));
3854 first
= ics_find_free_block(ics
, num
, num
);
3856 first
= ics_find_free_block(ics
, num
, 1);
3860 error_setg(errp
, "can't find a free %d-IRQ block", num
);
3864 return first
+ ics
->offset
;
3867 int spapr_irq_claim(sPAPRMachineState
*spapr
, int irq
, bool lsi
, Error
**errp
)
3869 ICSState
*ics
= spapr
->ics
;
3873 if (!ics_valid_irq(ics
, irq
)) {
3874 error_setg(errp
, "IRQ %d is invalid", irq
);
3878 if (!ICS_IRQ_FREE(ics
, irq
- ics
->offset
)) {
3879 error_setg(errp
, "IRQ %d is not free", irq
);
3883 ics_set_irq_type(ics
, irq
- ics
->offset
, lsi
);
3887 void spapr_irq_free(sPAPRMachineState
*spapr
, int irq
, int num
)
3889 ICSState
*ics
= spapr
->ics
;
3890 int srcno
= irq
- ics
->offset
;
3893 if (ics_valid_irq(ics
, irq
)) {
3894 trace_spapr_irq_free(0, irq
, num
);
3895 for (i
= srcno
; i
< srcno
+ num
; ++i
) {
3896 if (ICS_IRQ_FREE(ics
, i
)) {
3897 trace_spapr_irq_free_warn(0, i
+ ics
->offset
);
3899 memset(&ics
->irqs
[i
], 0, sizeof(ICSIRQState
));
3904 qemu_irq
spapr_qirq(sPAPRMachineState
*spapr
, int irq
)
3906 ICSState
*ics
= spapr
->ics
;
3908 if (ics_valid_irq(ics
, irq
)) {
3909 return ics
->qirqs
[irq
- ics
->offset
];
3915 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
3918 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3922 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3924 icp_pic_print_info(ICP(cpu
->intc
), mon
);
3927 ics_pic_print_info(spapr
->ics
, mon
);
3930 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
3932 return cpu
->vcpu_id
;
3935 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
3937 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3940 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
3942 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
3943 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
3944 error_append_hint(errp
, "Adjust the number of cpus to %d "
3945 "or try to raise the number of threads per core\n",
3946 vcpu_id
* smp_threads
/ spapr
->vsmt
);
3950 cpu
->vcpu_id
= vcpu_id
;
3953 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
3958 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3960 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
3968 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
3970 MachineClass
*mc
= MACHINE_CLASS(oc
);
3971 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
3972 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
3973 NMIClass
*nc
= NMI_CLASS(oc
);
3974 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3975 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
3976 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
3977 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
3979 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
3980 mc
->ignore_boot_device_suffixes
= true;
3983 * We set up the default / latest behaviour here. The class_init
3984 * functions for the specific versioned machine types can override
3985 * these details for backwards compatibility
3987 mc
->init
= spapr_machine_init
;
3988 mc
->reset
= spapr_machine_reset
;
3989 mc
->block_default_type
= IF_SCSI
;
3990 mc
->max_cpus
= 1024;
3991 mc
->no_parallel
= 1;
3992 mc
->default_boot_order
= "";
3993 mc
->default_ram_size
= 512 * MiB
;
3994 mc
->default_display
= "std";
3995 mc
->kvm_type
= spapr_kvm_type
;
3996 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3997 mc
->pci_allow_0_address
= true;
3998 assert(!mc
->get_hotplug_handler
);
3999 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
4000 hc
->pre_plug
= spapr_machine_device_pre_plug
;
4001 hc
->plug
= spapr_machine_device_plug
;
4002 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
4003 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
4004 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
4005 hc
->unplug_request
= spapr_machine_device_unplug_request
;
4006 hc
->unplug
= spapr_machine_device_unplug
;
4008 smc
->dr_lmb_enabled
= true;
4009 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4010 mc
->has_hotpluggable_cpus
= true;
4011 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
4012 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
4013 nc
->nmi_monitor_handler
= spapr_nmi
;
4014 smc
->phb_placement
= spapr_phb_placement
;
4015 vhc
->hypercall
= emulate_spapr_hypercall
;
4016 vhc
->hpt_mask
= spapr_hpt_mask
;
4017 vhc
->map_hptes
= spapr_map_hptes
;
4018 vhc
->unmap_hptes
= spapr_unmap_hptes
;
4019 vhc
->store_hpte
= spapr_store_hpte
;
4020 vhc
->get_patbe
= spapr_get_patbe
;
4021 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
4022 xic
->ics_get
= spapr_ics_get
;
4023 xic
->ics_resend
= spapr_ics_resend
;
4024 xic
->icp_get
= spapr_icp_get
;
4025 ispc
->print_info
= spapr_pic_print_info
;
4026 /* Force NUMA node memory size to be a multiple of
4027 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
4028 * in which LMBs are represented and hot-added
4030 mc
->numa_mem_align_shift
= 28;
4032 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
4033 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
4034 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
4035 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
4036 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
4037 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
4038 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
4039 spapr_caps_add_properties(smc
, &error_abort
);
4042 static const TypeInfo spapr_machine_info
= {
4043 .name
= TYPE_SPAPR_MACHINE
,
4044 .parent
= TYPE_MACHINE
,
4046 .instance_size
= sizeof(sPAPRMachineState
),
4047 .instance_init
= spapr_instance_init
,
4048 .instance_finalize
= spapr_machine_finalizefn
,
4049 .class_size
= sizeof(sPAPRMachineClass
),
4050 .class_init
= spapr_machine_class_init
,
4051 .interfaces
= (InterfaceInfo
[]) {
4052 { TYPE_FW_PATH_PROVIDER
},
4054 { TYPE_HOTPLUG_HANDLER
},
4055 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
4056 { TYPE_XICS_FABRIC
},
4057 { TYPE_INTERRUPT_STATS_PROVIDER
},
4062 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
4063 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
4066 MachineClass *mc = MACHINE_CLASS(oc); \
4067 spapr_machine_##suffix##_class_options(mc); \
4069 mc->alias = "pseries"; \
4070 mc->is_default = 1; \
4073 static void spapr_machine_##suffix##_instance_init(Object *obj) \
4075 MachineState *machine = MACHINE(obj); \
4076 spapr_machine_##suffix##_instance_options(machine); \
4078 static const TypeInfo spapr_machine_##suffix##_info = { \
4079 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4080 .parent = TYPE_SPAPR_MACHINE, \
4081 .class_init = spapr_machine_##suffix##_class_init, \
4082 .instance_init = spapr_machine_##suffix##_instance_init, \
4084 static void spapr_machine_register_##suffix(void) \
4086 type_register(&spapr_machine_##suffix##_info); \
4088 type_init(spapr_machine_register_##suffix)
4093 static void spapr_machine_3_1_instance_options(MachineState
*machine
)
4097 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4099 /* Defaults for the latest behaviour inherited from the base class */
4102 DEFINE_SPAPR_MACHINE(3_1
, "3.1", true);
4107 #define SPAPR_COMPAT_3_0 \
4110 static void spapr_machine_3_0_instance_options(MachineState
*machine
)
4112 spapr_machine_3_1_instance_options(machine
);
4115 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4117 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4119 spapr_machine_3_1_class_options(mc
);
4120 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_3_0
);
4122 smc
->legacy_irq_allocation
= true;
4125 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4130 #define SPAPR_COMPAT_2_12 \
4133 .driver = TYPE_POWERPC_CPU, \
4134 .property = "pre-3.0-migration", \
4138 .driver = TYPE_SPAPR_CPU_CORE, \
4139 .property = "pre-3.0-migration", \
4143 static void spapr_machine_2_12_instance_options(MachineState
*machine
)
4145 spapr_machine_3_0_instance_options(machine
);
4148 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4150 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4152 spapr_machine_3_0_class_options(mc
);
4153 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_12
);
4155 /* We depend on kvm_enabled() to choose a default value for the
4156 * hpt-max-page-size capability. Of course we can't do it here
4157 * because this is too early and the HW accelerator isn't initialzed
4158 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4160 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4163 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4165 static void spapr_machine_2_12_sxxm_instance_options(MachineState
*machine
)
4167 spapr_machine_2_12_instance_options(machine
);
4170 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4172 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4174 spapr_machine_2_12_class_options(mc
);
4175 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4176 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4177 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4180 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4185 #define SPAPR_COMPAT_2_11 \
4188 static void spapr_machine_2_11_instance_options(MachineState
*machine
)
4190 spapr_machine_2_12_instance_options(machine
);
4193 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4195 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4197 spapr_machine_2_12_class_options(mc
);
4198 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4199 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_11
);
4202 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4207 #define SPAPR_COMPAT_2_10 \
4210 static void spapr_machine_2_10_instance_options(MachineState
*machine
)
4212 spapr_machine_2_11_instance_options(machine
);
4215 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4217 spapr_machine_2_11_class_options(mc
);
4218 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_10
);
4221 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4226 #define SPAPR_COMPAT_2_9 \
4229 .driver = TYPE_POWERPC_CPU, \
4230 .property = "pre-2.10-migration", \
4234 static void spapr_machine_2_9_instance_options(MachineState *machine)
4236 spapr_machine_2_10_instance_options(machine
);
4239 static void spapr_machine_2_9_class_options(MachineClass
*mc
)
4241 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4243 spapr_machine_2_10_class_options(mc
);
4244 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_9
);
4245 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4246 smc
->pre_2_10_has_unused_icps
= true;
4247 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4250 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4255 #define SPAPR_COMPAT_2_8 \
4258 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4259 .property = "pcie-extended-configuration-space", \
4263 static void spapr_machine_2_8_instance_options(MachineState
*machine
)
4265 spapr_machine_2_9_instance_options(machine
);
4268 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4270 spapr_machine_2_9_class_options(mc
);
4271 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_8
);
4272 mc
->numa_mem_align_shift
= 23;
4275 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4280 #define SPAPR_COMPAT_2_7 \
4283 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4284 .property = "mem_win_size", \
4285 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4288 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4289 .property = "mem64_win_size", \
4293 .driver = TYPE_POWERPC_CPU, \
4294 .property = "pre-2.8-migration", \
4298 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4299 .property = "pre-2.8-migration", \
4303 static void phb_placement_2_7(sPAPRMachineState
*spapr
, uint32_t index
,
4304 uint64_t *buid
, hwaddr
*pio
,
4305 hwaddr
*mmio32
, hwaddr
*mmio64
,
4306 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
4308 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4309 const uint64_t base_buid
= 0x800000020000000ULL
;
4310 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4311 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4312 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4313 const uint32_t max_index
= 255;
4314 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4316 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4317 hwaddr phb0_base
, phb_base
;
4320 /* Do we have device memory? */
4321 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4322 /* Can't just use maxram_size, because there may be an
4323 * alignment gap between normal and device memory regions
4325 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4326 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4329 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4331 if (index
> max_index
) {
4332 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4337 *buid
= base_buid
+ index
;
4338 for (i
= 0; i
< n_dma
; ++i
) {
4339 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4342 phb_base
= phb0_base
+ index
* phb_spacing
;
4343 *pio
= phb_base
+ pio_offset
;
4344 *mmio32
= phb_base
+ mmio_offset
;
4346 * We don't set the 64-bit MMIO window, relying on the PHB's
4347 * fallback behaviour of automatically splitting a large "32-bit"
4348 * window into contiguous 32-bit and 64-bit windows
4352 static void spapr_machine_2_7_instance_options(MachineState
*machine
)
4354 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
4356 spapr_machine_2_8_instance_options(machine
);
4357 spapr
->use_hotplug_event_source
= false;
4360 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4362 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4364 spapr_machine_2_8_class_options(mc
);
4365 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4366 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_7
);
4367 smc
->phb_placement
= phb_placement_2_7
;
4370 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4375 #define SPAPR_COMPAT_2_6 \
4378 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4380 .value = stringify(off),\
4383 static void spapr_machine_2_6_instance_options(MachineState
*machine
)
4385 spapr_machine_2_7_instance_options(machine
);
4388 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4390 spapr_machine_2_7_class_options(mc
);
4391 mc
->has_hotpluggable_cpus
= false;
4392 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_6
);
4395 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4400 #define SPAPR_COMPAT_2_5 \
4403 .driver = "spapr-vlan", \
4404 .property = "use-rx-buffer-pools", \
4408 static void spapr_machine_2_5_instance_options(MachineState
*machine
)
4410 spapr_machine_2_6_instance_options(machine
);
4413 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4415 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4417 spapr_machine_2_6_class_options(mc
);
4418 smc
->use_ohci_by_default
= true;
4419 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_5
);
4422 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4427 #define SPAPR_COMPAT_2_4 \
4430 static void spapr_machine_2_4_instance_options(MachineState
*machine
)
4432 spapr_machine_2_5_instance_options(machine
);
4435 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4437 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4439 spapr_machine_2_5_class_options(mc
);
4440 smc
->dr_lmb_enabled
= false;
4441 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_4
);
4444 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4449 #define SPAPR_COMPAT_2_3 \
4452 .driver = "spapr-pci-host-bridge",\
4453 .property = "dynamic-reconfiguration",\
4457 static void spapr_machine_2_3_instance_options(MachineState
*machine
)
4459 spapr_machine_2_4_instance_options(machine
);
4462 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4464 spapr_machine_2_4_class_options(mc
);
4465 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_3
);
4467 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4473 #define SPAPR_COMPAT_2_2 \
4476 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4477 .property = "mem_win_size",\
4478 .value = "0x20000000",\
4481 static void spapr_machine_2_2_instance_options(MachineState
*machine
)
4483 spapr_machine_2_3_instance_options(machine
);
4484 machine
->suppress_vmdesc
= true;
4487 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4489 spapr_machine_2_3_class_options(mc
);
4490 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_2
);
4492 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4497 #define SPAPR_COMPAT_2_1 \
4500 static void spapr_machine_2_1_instance_options(MachineState
*machine
)
4502 spapr_machine_2_2_instance_options(machine
);
4505 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4507 spapr_machine_2_2_class_options(mc
);
4508 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_1
);
4510 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4512 static void spapr_machine_register_types(void)
4514 type_register_static(&spapr_machine_info
);
4517 type_init(spapr_machine_register_types
)