4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu/timer.h"
25 #include "exec/page-vary.h"
26 #include "target/arm/idau.h"
27 #include "qemu/module.h"
28 #include "qapi/error.h"
31 #include "hw/core/tcg-cpu-ops.h"
32 #endif /* CONFIG_TCG */
33 #include "internals.h"
34 #include "cpu-features.h"
35 #include "exec/exec-all.h"
36 #include "hw/qdev-properties.h"
37 #if !defined(CONFIG_USER_ONLY)
38 #include "hw/loader.h"
39 #include "hw/boards.h"
41 #include "hw/intc/armv7m_nvic.h"
42 #endif /* CONFIG_TCG */
43 #endif /* !CONFIG_USER_ONLY */
44 #include "sysemu/tcg.h"
45 #include "sysemu/qtest.h"
46 #include "sysemu/hw_accel.h"
48 #include "disas/capstone.h"
49 #include "fpu/softfloat.h"
51 #include "target/arm/cpu-qom.h"
52 #include "target/arm/gtimer.h"
54 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
56 ARMCPU
*cpu
= ARM_CPU(cs
);
57 CPUARMState
*env
= &cpu
->env
;
63 env
->regs
[15] = value
& ~1;
64 env
->thumb
= value
& 1;
68 static vaddr
arm_cpu_get_pc(CPUState
*cs
)
70 ARMCPU
*cpu
= ARM_CPU(cs
);
71 CPUARMState
*env
= &cpu
->env
;
81 void arm_cpu_synchronize_from_tb(CPUState
*cs
,
82 const TranslationBlock
*tb
)
84 /* The program counter is always up to date with CF_PCREL. */
85 if (!(tb_cflags(tb
) & CF_PCREL
)) {
86 CPUARMState
*env
= cpu_env(cs
);
88 * It's OK to look at env for the current mode here, because it's
89 * never possible for an AArch64 TB to chain to an AArch32 TB.
94 env
->regs
[15] = tb
->pc
;
99 void arm_restore_state_to_opc(CPUState
*cs
,
100 const TranslationBlock
*tb
,
101 const uint64_t *data
)
103 CPUARMState
*env
= cpu_env(cs
);
106 if (tb_cflags(tb
) & CF_PCREL
) {
107 env
->pc
= (env
->pc
& TARGET_PAGE_MASK
) | data
[0];
111 env
->condexec_bits
= 0;
112 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
114 if (tb_cflags(tb
) & CF_PCREL
) {
115 env
->regs
[15] = (env
->regs
[15] & TARGET_PAGE_MASK
) | data
[0];
117 env
->regs
[15] = data
[0];
119 env
->condexec_bits
= data
[1];
120 env
->exception
.syndrome
= data
[2] << ARM_INSN_START_WORD2_SHIFT
;
123 #endif /* CONFIG_TCG */
125 static bool arm_cpu_has_work(CPUState
*cs
)
127 ARMCPU
*cpu
= ARM_CPU(cs
);
129 return (cpu
->power_state
!= PSCI_OFF
)
130 && cs
->interrupt_request
&
131 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
132 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
| CPU_INTERRUPT_VSERR
133 | CPU_INTERRUPT_EXITTB
);
136 static int arm_cpu_mmu_index(CPUState
*cs
, bool ifetch
)
138 return arm_env_mmu_index(cpu_env(cs
));
141 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
144 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
147 entry
->opaque
= opaque
;
149 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
152 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
155 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
158 entry
->opaque
= opaque
;
160 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
163 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
165 /* Reset a single ARMCPRegInfo register */
166 ARMCPRegInfo
*ri
= value
;
167 ARMCPU
*cpu
= opaque
;
169 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
)) {
174 ri
->resetfn(&cpu
->env
, ri
);
178 /* A zero offset is never possible as it would be regs[0]
179 * so we use it to indicate that reset is being handled elsewhere.
180 * This is basically only used for fields in non-core coprocessors
181 * (like the pxa2xx ones).
183 if (!ri
->fieldoffset
) {
187 if (cpreg_field_is_64bit(ri
)) {
188 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
190 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
194 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
196 /* Purely an assertion check: we've already done reset once,
197 * so now check that running the reset for the cpreg doesn't
198 * change its value. This traps bugs where two different cpregs
199 * both try to reset the same state field but to different values.
201 ARMCPRegInfo
*ri
= value
;
202 ARMCPU
*cpu
= opaque
;
203 uint64_t oldvalue
, newvalue
;
205 if (ri
->type
& (ARM_CP_SPECIAL_MASK
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
209 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
210 cp_reg_reset(key
, value
, opaque
);
211 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
212 assert(oldvalue
== newvalue
);
215 static void arm_cpu_reset_hold(Object
*obj
)
217 CPUState
*s
= CPU(obj
);
218 ARMCPU
*cpu
= ARM_CPU(s
);
219 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
220 CPUARMState
*env
= &cpu
->env
;
222 if (acc
->parent_phases
.hold
) {
223 acc
->parent_phases
.hold(obj
);
226 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
228 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
229 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
231 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
232 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
233 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
234 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
236 cpu
->power_state
= s
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
238 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
239 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
242 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
243 /* 64 bit CPUs always start in 64 bit mode */
245 #if defined(CONFIG_USER_ONLY)
246 env
->pstate
= PSTATE_MODE_EL0t
;
247 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
248 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
249 /* Enable all PAC keys. */
250 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
251 SCTLR_EnDA
| SCTLR_EnDB
);
252 /* Trap on btype=3 for PACIxSP. */
253 env
->cp15
.sctlr_el
[1] |= SCTLR_BT0
;
254 /* Trap on implementation defined registers. */
255 if (cpu_isar_feature(aa64_tidcp1
, cpu
)) {
256 env
->cp15
.sctlr_el
[1] |= SCTLR_TIDCP
;
258 /* and to the FP/Neon instructions */
259 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
261 /* and to the SVE instructions, with default vector length */
262 if (cpu_isar_feature(aa64_sve
, cpu
)) {
263 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
265 env
->vfp
.zcr_el
[1] = cpu
->sve_default_vq
- 1;
267 /* and for SME instructions, with default vector length, and TPIDR2 */
268 if (cpu_isar_feature(aa64_sme
, cpu
)) {
269 env
->cp15
.sctlr_el
[1] |= SCTLR_EnTP2
;
270 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
272 env
->vfp
.smcr_el
[1] = cpu
->sme_default_vq
- 1;
273 if (cpu_isar_feature(aa64_sme_fa64
, cpu
)) {
274 env
->vfp
.smcr_el
[1] = FIELD_DP64(env
->vfp
.smcr_el
[1],
279 * Enable 48-bit address space (TODO: take reserved_va into account).
280 * Enable TBI0 but not TBI1.
281 * Note that this must match useronly_clean_ptr.
283 env
->cp15
.tcr_el
[1] = 5 | (1ULL << 37);
286 if (cpu_isar_feature(aa64_mte
, cpu
)) {
287 /* Enable tag access, but leave TCF0 as No Effect (0). */
288 env
->cp15
.sctlr_el
[1] |= SCTLR_ATA0
;
290 * Exclude all tags, so that tag 0 is always used.
291 * This corresponds to Linux current->thread.gcr_incl = 0.
293 * Set RRND, so that helper_irg() will generate a seed later.
294 * Here in cpu_reset(), the crypto subsystem has not yet been
297 env
->cp15
.gcr_el1
= 0x1ffff;
300 * Disable access to SCXTNUM_EL0 from CSV2_1p2.
301 * This is not yet exposed from the Linux kernel in any way.
303 env
->cp15
.sctlr_el
[1] |= SCTLR_TSCXT
;
304 /* Disable access to Debug Communication Channel (DCC). */
305 env
->cp15
.mdscr_el1
|= 1 << 12;
306 /* Enable FEAT_MOPS */
307 env
->cp15
.sctlr_el
[1] |= SCTLR_MSCEN
;
309 /* Reset into the highest available EL */
310 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
311 env
->pstate
= PSTATE_MODE_EL3h
;
312 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
313 env
->pstate
= PSTATE_MODE_EL2h
;
315 env
->pstate
= PSTATE_MODE_EL1h
;
318 /* Sample rvbar at reset. */
319 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
320 env
->pc
= env
->cp15
.rvbar
;
323 #if defined(CONFIG_USER_ONLY)
324 /* Userspace expects access to cp10 and cp11 for FP/Neon */
325 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
327 env
->cp15
.cpacr_el1
= FIELD_DP64(env
->cp15
.cpacr_el1
,
330 if (arm_feature(env
, ARM_FEATURE_V8
)) {
331 env
->cp15
.rvbar
= cpu
->rvbar_prop
;
332 env
->regs
[15] = cpu
->rvbar_prop
;
336 #if defined(CONFIG_USER_ONLY)
337 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
338 /* For user mode we must enable access to coprocessors */
339 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
340 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
341 env
->cp15
.c15_cpar
= 3;
342 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
343 env
->cp15
.c15_cpar
= 1;
348 * If the highest available EL is EL2, AArch32 will start in Hyp
349 * mode; otherwise it starts in SVC. Note that if we start in
350 * AArch64 then these values in the uncached_cpsr will be ignored.
352 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
353 !arm_feature(env
, ARM_FEATURE_EL3
)) {
354 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
356 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
358 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
360 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
361 * executing as AArch32 then check if highvecs are enabled and
362 * adjust the PC accordingly.
364 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
365 env
->regs
[15] = 0xFFFF0000;
368 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
371 if (arm_feature(env
, ARM_FEATURE_M
)) {
372 #ifndef CONFIG_USER_ONLY
373 uint32_t initial_msp
; /* Loaded from 0x0 */
374 uint32_t initial_pc
; /* Loaded from 0x4 */
379 if (cpu_isar_feature(aa32_lob
, cpu
)) {
381 * LTPSIZE is constant 4 if MVE not implemented, and resets
382 * to an UNKNOWN value if MVE is implemented. We choose to
385 env
->v7m
.ltpsize
= 4;
386 /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
387 env
->v7m
.fpdscr
[M_REG_NS
] = 4 << FPCR_LTPSIZE_SHIFT
;
388 env
->v7m
.fpdscr
[M_REG_S
] = 4 << FPCR_LTPSIZE_SHIFT
;
391 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
392 env
->v7m
.secure
= true;
394 /* This bit resets to 0 if security is supported, but 1 if
395 * it is not. The bit is not present in v7M, but we set it
396 * here so we can avoid having to make checks on it conditional
397 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
399 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
401 * Set NSACR to indicate "NS access permitted to everything";
402 * this avoids having to have all the tests of it being
403 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
404 * v8.1M the guest-visible value of NSACR in a CPU without the
405 * Security Extension is 0xcff.
407 env
->v7m
.nsacr
= 0xcff;
410 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
411 * that it resets to 1, so QEMU always does that rather than making
412 * it dependent on CPU model. In v8M it is RES1.
414 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
415 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
416 if (arm_feature(env
, ARM_FEATURE_V8
)) {
417 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
418 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
419 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
421 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
422 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
423 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
426 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
427 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
428 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
429 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
432 #ifndef CONFIG_USER_ONLY
433 /* Unlike A/R profile, M profile defines the reset LR value */
434 env
->regs
[14] = 0xffffffff;
436 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
437 env
->v7m
.vecbase
[M_REG_NS
] = cpu
->init_nsvtor
& 0xffffff80;
439 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
440 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
441 rom
= rom_ptr_for_as(s
->as
, vecbase
, 8);
443 /* Address zero is covered by ROM which hasn't yet been
444 * copied into physical memory.
446 initial_msp
= ldl_p(rom
);
447 initial_pc
= ldl_p(rom
+ 4);
449 /* Address zero not covered by a ROM blob, or the ROM blob
450 * is in non-modifiable memory and this is a second reset after
451 * it got copied into memory. In the latter case, rom_ptr
452 * will return a NULL pointer and we should use ldl_phys instead.
454 initial_msp
= ldl_phys(s
->as
, vecbase
);
455 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
458 qemu_log_mask(CPU_LOG_INT
,
459 "Loaded reset SP 0x%x PC 0x%x from vector table\n",
460 initial_msp
, initial_pc
);
462 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
463 env
->regs
[15] = initial_pc
& ~1;
464 env
->thumb
= initial_pc
& 1;
467 * For user mode we run non-secure and with access to the FPU.
468 * The FPU context is active (ie does not need further setup)
469 * and is owned by non-secure.
471 env
->v7m
.secure
= false;
472 env
->v7m
.nsacr
= 0xcff;
473 env
->v7m
.cpacr
[M_REG_NS
] = 0xf0ffff;
474 env
->v7m
.fpccr
[M_REG_S
] &=
475 ~(R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
);
476 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_FPCA_MASK
;
480 /* M profile requires that reset clears the exclusive monitor;
481 * A profile does not, but clearing it makes more sense than having it
482 * set with an exclusive access on address zero.
484 arm_clear_exclusive(env
);
486 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
487 if (cpu
->pmsav7_dregion
> 0) {
488 if (arm_feature(env
, ARM_FEATURE_V8
)) {
489 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
490 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
491 * cpu
->pmsav7_dregion
);
492 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
493 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
494 * cpu
->pmsav7_dregion
);
495 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
496 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
497 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
498 * cpu
->pmsav7_dregion
);
499 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
500 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
501 * cpu
->pmsav7_dregion
);
503 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
504 memset(env
->pmsav7
.drbar
, 0,
505 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
506 memset(env
->pmsav7
.drsr
, 0,
507 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
508 memset(env
->pmsav7
.dracr
, 0,
509 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
513 if (cpu
->pmsav8r_hdregion
> 0) {
514 memset(env
->pmsav8
.hprbar
, 0,
515 sizeof(*env
->pmsav8
.hprbar
) * cpu
->pmsav8r_hdregion
);
516 memset(env
->pmsav8
.hprlar
, 0,
517 sizeof(*env
->pmsav8
.hprlar
) * cpu
->pmsav8r_hdregion
);
520 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
521 env
->pmsav7
.rnr
[M_REG_S
] = 0;
522 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
523 env
->pmsav8
.mair0
[M_REG_S
] = 0;
524 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
525 env
->pmsav8
.mair1
[M_REG_S
] = 0;
528 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
529 if (cpu
->sau_sregion
> 0) {
530 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
531 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
534 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
535 * the Cortex-M33 does.
540 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
541 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
542 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
543 set_default_nan_mode(1, &env
->vfp
.standard_fp_status_f16
);
544 set_float_detect_tininess(float_tininess_before_rounding
,
545 &env
->vfp
.fp_status
);
546 set_float_detect_tininess(float_tininess_before_rounding
,
547 &env
->vfp
.standard_fp_status
);
548 set_float_detect_tininess(float_tininess_before_rounding
,
549 &env
->vfp
.fp_status_f16
);
550 set_float_detect_tininess(float_tininess_before_rounding
,
551 &env
->vfp
.standard_fp_status_f16
);
552 #ifndef CONFIG_USER_ONLY
554 kvm_arm_reset_vcpu(cpu
);
559 hw_breakpoint_update_all(cpu
);
560 hw_watchpoint_update_all(cpu
);
562 arm_rebuild_hflags(env
);
566 void arm_emulate_firmware_reset(CPUState
*cpustate
, int target_el
)
568 ARMCPU
*cpu
= ARM_CPU(cpustate
);
569 CPUARMState
*env
= &cpu
->env
;
570 bool have_el3
= arm_feature(env
, ARM_FEATURE_EL3
);
571 bool have_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
574 * Check we have the EL we're aiming for. If that is the
575 * highest implemented EL, then cpu_reset has already done
589 if (!have_el3
&& !have_el2
) {
594 g_assert_not_reached();
599 * Set the EL3 state so code can run at EL2. This should match
600 * the requirements set by Linux in its booting spec.
603 env
->cp15
.scr_el3
|= SCR_RW
;
604 if (cpu_isar_feature(aa64_pauth
, cpu
)) {
605 env
->cp15
.scr_el3
|= SCR_API
| SCR_APK
;
607 if (cpu_isar_feature(aa64_mte
, cpu
)) {
608 env
->cp15
.scr_el3
|= SCR_ATA
;
610 if (cpu_isar_feature(aa64_sve
, cpu
)) {
611 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_EZ_MASK
;
612 env
->vfp
.zcr_el
[3] = 0xf;
614 if (cpu_isar_feature(aa64_sme
, cpu
)) {
615 env
->cp15
.cptr_el
[3] |= R_CPTR_EL3_ESM_MASK
;
616 env
->cp15
.scr_el3
|= SCR_ENTP2
;
617 env
->vfp
.smcr_el
[3] = 0xf;
619 if (cpu_isar_feature(aa64_hcx
, cpu
)) {
620 env
->cp15
.scr_el3
|= SCR_HXEN
;
622 if (cpu_isar_feature(aa64_fgt
, cpu
)) {
623 env
->cp15
.scr_el3
|= SCR_FGTEN
;
627 if (target_el
== 2) {
628 /* If the guest is at EL2 then Linux expects the HVC insn to work */
629 env
->cp15
.scr_el3
|= SCR_HCE
;
632 /* Put CPU into non-secure state */
633 env
->cp15
.scr_el3
|= SCR_NS
;
634 /* Set NSACR.{CP11,CP10} so NS can access the FPU */
635 env
->cp15
.nsacr
|= 3 << 10;
638 if (have_el2
&& target_el
< 2) {
639 /* Set EL2 state so code can run at EL1. */
641 env
->cp15
.hcr_el2
|= HCR_RW
;
645 /* Set the CPU to the desired state */
647 env
->pstate
= aarch64_pstate_mode(target_el
, true);
649 static const uint32_t mode_for_el
[] = {
656 cpsr_write(env
, mode_for_el
[target_el
], CPSR_M
, CPSRWriteRaw
);
661 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
663 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
664 unsigned int target_el
,
665 unsigned int cur_el
, bool secure
,
668 CPUARMState
*env
= cpu_env(cs
);
669 bool pstate_unmasked
;
670 bool unmasked
= false;
673 * Don't take exceptions if they target a lower EL.
674 * This check should catch any exceptions that would not be taken
677 if (cur_el
> target_el
) {
683 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
687 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
691 if (!(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
692 /* VFIQs are only taken when hypervized. */
695 return !(env
->daif
& PSTATE_F
);
697 if (!(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
698 /* VIRQs are only taken when hypervized. */
701 return !(env
->daif
& PSTATE_I
);
703 if (!(hcr_el2
& HCR_AMO
) || (hcr_el2
& HCR_TGE
)) {
704 /* VIRQs are only taken when hypervized. */
707 return !(env
->daif
& PSTATE_A
);
709 g_assert_not_reached();
713 * Use the target EL, current execution state and SCR/HCR settings to
714 * determine whether the corresponding CPSR bit is used to mask the
717 if ((target_el
> cur_el
) && (target_el
!= 1)) {
718 /* Exceptions targeting a higher EL may not be maskable */
719 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
723 * According to ARM DDI 0487H.a, an interrupt can be masked
724 * when HCR_E2H and HCR_TGE are both set regardless of the
725 * current Security state. Note that we need to revisit this
726 * part again once we need to support NMI.
728 if ((hcr_el2
& (HCR_E2H
| HCR_TGE
)) != (HCR_E2H
| HCR_TGE
)) {
733 /* Interrupt cannot be masked when the target EL is 3 */
737 g_assert_not_reached();
741 * The old 32-bit-only environment has a more complicated
742 * masking setup. HCR and SCR bits not only affect interrupt
743 * routing but also change the behaviour of masking.
750 * If FIQs are routed to EL3 or EL2 then there are cases where
751 * we override the CPSR.F in determining if the exception is
752 * masked or not. If neither of these are set then we fall back
753 * to the CPSR.F setting otherwise we further assess the state
756 hcr
= hcr_el2
& HCR_FMO
;
757 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
760 * When EL3 is 32-bit, the SCR.FW bit controls whether the
761 * CPSR.F bit masks FIQ interrupts when taken in non-secure
762 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
763 * when non-secure but only when FIQs are only routed to EL3.
765 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
769 * When EL3 execution state is 32-bit, if HCR.IMO is set then
770 * we may override the CPSR.I masking when in non-secure state.
771 * The SCR.IRQ setting has already been taken into consideration
772 * when setting the target EL, so it does not have a further
775 hcr
= hcr_el2
& HCR_IMO
;
779 g_assert_not_reached();
782 if ((scr
|| hcr
) && !secure
) {
789 * The PSTATE bits only mask the interrupt if we have not overridden the
792 return unmasked
|| pstate_unmasked
;
795 static bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
797 CPUClass
*cc
= CPU_GET_CLASS(cs
);
798 CPUARMState
*env
= cpu_env(cs
);
799 uint32_t cur_el
= arm_current_el(env
);
800 bool secure
= arm_is_secure(env
);
801 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
805 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
807 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
809 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
810 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
811 cur_el
, secure
, hcr_el2
)) {
815 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
817 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
818 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
819 cur_el
, secure
, hcr_el2
)) {
823 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
824 excp_idx
= EXCP_VIRQ
;
826 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
827 cur_el
, secure
, hcr_el2
)) {
831 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
832 excp_idx
= EXCP_VFIQ
;
834 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
835 cur_el
, secure
, hcr_el2
)) {
839 if (interrupt_request
& CPU_INTERRUPT_VSERR
) {
840 excp_idx
= EXCP_VSERR
;
842 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
843 cur_el
, secure
, hcr_el2
)) {
844 /* Taking a virtual abort clears HCR_EL2.VSE */
845 env
->cp15
.hcr_el2
&= ~HCR_VSE
;
846 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
853 cs
->exception_index
= excp_idx
;
854 env
->exception
.target_el
= target_el
;
855 cc
->tcg_ops
->do_interrupt(cs
);
859 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
861 void arm_cpu_update_virq(ARMCPU
*cpu
)
864 * Update the interrupt level for VIRQ, which is the logical OR of
865 * the HCR_EL2.VI bit and the input line level from the GIC.
867 CPUARMState
*env
= &cpu
->env
;
868 CPUState
*cs
= CPU(cpu
);
870 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
871 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
873 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
875 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
877 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
882 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
885 * Update the interrupt level for VFIQ, which is the logical OR of
886 * the HCR_EL2.VF bit and the input line level from the GIC.
888 CPUARMState
*env
= &cpu
->env
;
889 CPUState
*cs
= CPU(cpu
);
891 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
892 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
894 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
896 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
898 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
903 void arm_cpu_update_vserr(ARMCPU
*cpu
)
906 * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit.
908 CPUARMState
*env
= &cpu
->env
;
909 CPUState
*cs
= CPU(cpu
);
911 bool new_state
= env
->cp15
.hcr_el2
& HCR_VSE
;
913 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VSERR
) != 0)) {
915 cpu_interrupt(cs
, CPU_INTERRUPT_VSERR
);
917 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VSERR
);
922 #ifndef CONFIG_USER_ONLY
923 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
925 ARMCPU
*cpu
= opaque
;
926 CPUARMState
*env
= &cpu
->env
;
927 CPUState
*cs
= CPU(cpu
);
928 static const int mask
[] = {
929 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
930 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
931 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
932 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
935 if (!arm_feature(env
, ARM_FEATURE_EL2
) &&
936 (irq
== ARM_CPU_VIRQ
|| irq
== ARM_CPU_VFIQ
)) {
938 * The GIC might tell us about VIRQ and VFIQ state, but if we don't
939 * have EL2 support we don't care. (Unless the guest is doing something
940 * silly this will only be calls saying "level is still 0".)
946 env
->irq_line_state
|= mask
[irq
];
948 env
->irq_line_state
&= ~mask
[irq
];
953 arm_cpu_update_virq(cpu
);
956 arm_cpu_update_vfiq(cpu
);
961 cpu_interrupt(cs
, mask
[irq
]);
963 cpu_reset_interrupt(cs
, mask
[irq
]);
967 g_assert_not_reached();
971 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
974 ARMCPU
*cpu
= opaque
;
975 CPUARMState
*env
= &cpu
->env
;
976 CPUState
*cs
= CPU(cpu
);
977 uint32_t linestate_bit
;
982 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
983 linestate_bit
= CPU_INTERRUPT_HARD
;
986 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
987 linestate_bit
= CPU_INTERRUPT_FIQ
;
990 g_assert_not_reached();
994 env
->irq_line_state
|= linestate_bit
;
996 env
->irq_line_state
&= ~linestate_bit
;
998 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
1002 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
1004 ARMCPU
*cpu
= ARM_CPU(cs
);
1005 CPUARMState
*env
= &cpu
->env
;
1007 cpu_synchronize_state(cs
);
1008 return arm_cpu_data_is_big_endian(env
);
1013 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
1015 ARMCPU
*ac
= ARM_CPU(cpu
);
1016 CPUARMState
*env
= &ac
->env
;
1020 info
->cap_arch
= CS_ARCH_ARM64
;
1021 info
->cap_insn_unit
= 4;
1022 info
->cap_insn_split
= 4;
1026 info
->cap_insn_unit
= 2;
1027 info
->cap_insn_split
= 4;
1028 cap_mode
= CS_MODE_THUMB
;
1030 info
->cap_insn_unit
= 4;
1031 info
->cap_insn_split
= 4;
1032 cap_mode
= CS_MODE_ARM
;
1034 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1035 cap_mode
|= CS_MODE_V8
;
1037 if (arm_feature(env
, ARM_FEATURE_M
)) {
1038 cap_mode
|= CS_MODE_MCLASS
;
1040 info
->cap_arch
= CS_ARCH_ARM
;
1041 info
->cap_mode
= cap_mode
;
1044 sctlr_b
= arm_sctlr_b(env
);
1045 if (bswap_code(sctlr_b
)) {
1046 #if TARGET_BIG_ENDIAN
1047 info
->endian
= BFD_ENDIAN_LITTLE
;
1049 info
->endian
= BFD_ENDIAN_BIG
;
1052 info
->flags
&= ~INSN_ARM_BE32
;
1053 #ifndef CONFIG_USER_ONLY
1055 info
->flags
|= INSN_ARM_BE32
;
1060 #ifdef TARGET_AARCH64
1062 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1064 ARMCPU
*cpu
= ARM_CPU(cs
);
1065 CPUARMState
*env
= &cpu
->env
;
1066 uint32_t psr
= pstate_read(env
);
1068 int el
= arm_current_el(env
);
1069 uint64_t hcr
= arm_hcr_el2_eff(env
);
1070 const char *ns_status
;
1073 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
1074 for (i
= 0; i
< 32; i
++) {
1076 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
1078 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
1079 (i
+ 2) % 3 ? " " : "\n");
1083 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
1084 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1088 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
1090 psr
& PSTATE_N
? 'N' : '-',
1091 psr
& PSTATE_Z
? 'Z' : '-',
1092 psr
& PSTATE_C
? 'C' : '-',
1093 psr
& PSTATE_V
? 'V' : '-',
1096 psr
& PSTATE_SP
? 'h' : 't');
1098 if (cpu_isar_feature(aa64_sme
, cpu
)) {
1099 qemu_fprintf(f
, " SVCR=%08" PRIx64
" %c%c",
1101 (FIELD_EX64(env
->svcr
, SVCR
, ZA
) ? 'Z' : '-'),
1102 (FIELD_EX64(env
->svcr
, SVCR
, SM
) ? 'S' : '-'));
1104 if (cpu_isar_feature(aa64_bti
, cpu
)) {
1105 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
1107 qemu_fprintf(f
, "%s%s%s",
1108 (hcr
& HCR_NV
) ? " NV" : "",
1109 (hcr
& HCR_NV1
) ? " NV1" : "",
1110 (hcr
& HCR_NV2
) ? " NV2" : "");
1111 if (!(flags
& CPU_DUMP_FPU
)) {
1112 qemu_fprintf(f
, "\n");
1115 if (fp_exception_el(env
, el
) != 0) {
1116 qemu_fprintf(f
, " FPU disabled\n");
1119 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
1120 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
1122 if (cpu_isar_feature(aa64_sme
, cpu
) && FIELD_EX64(env
->svcr
, SVCR
, SM
)) {
1123 sve
= sme_exception_el(env
, el
) == 0;
1124 } else if (cpu_isar_feature(aa64_sve
, cpu
)) {
1125 sve
= sve_exception_el(env
, el
) == 0;
1131 int zcr_len
= sve_vqm1_for_el(env
, el
);
1133 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
1135 if (i
== FFR_PRED_NUM
) {
1136 qemu_fprintf(f
, "FFR=");
1137 /* It's last, so end the line. */
1140 qemu_fprintf(f
, "P%02d=", i
);
1153 /* More than one quadword per predicate. */
1158 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
1160 if (j
* 4 + 4 <= zcr_len
+ 1) {
1163 digits
= (zcr_len
% 4 + 1) * 4;
1165 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
1166 env
->vfp
.pregs
[i
].p
[j
],
1167 j
? ":" : eol
? "\n" : " ");
1173 * With vl=16, there are only 37 columns per register,
1174 * so output two registers per line.
1176 for (i
= 0; i
< 32; i
++) {
1177 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
1178 i
, env
->vfp
.zregs
[i
].d
[1],
1179 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
1182 for (i
= 0; i
< 32; i
++) {
1183 qemu_fprintf(f
, "Z%02d=", i
);
1184 for (j
= zcr_len
; j
>= 0; j
--) {
1185 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
1186 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
1187 env
->vfp
.zregs
[i
].d
[j
* 2 + 0],
1193 for (i
= 0; i
< 32; i
++) {
1194 uint64_t *q
= aa64_vfp_qreg(env
, i
);
1195 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
1196 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
1200 if (cpu_isar_feature(aa64_sme
, cpu
) &&
1201 FIELD_EX64(env
->svcr
, SVCR
, ZA
) &&
1202 sme_exception_el(env
, el
) == 0) {
1203 int zcr_len
= sve_vqm1_for_el_sm(env
, el
, true);
1204 int svl
= (zcr_len
+ 1) * 16;
1205 int svl_lg10
= svl
< 100 ? 2 : 3;
1207 for (i
= 0; i
< svl
; i
++) {
1208 qemu_fprintf(f
, "ZA[%0*d]=", svl_lg10
, i
);
1209 for (j
= zcr_len
; j
>= 0; --j
) {
1210 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%c",
1211 env
->zarray
[i
].d
[2 * j
+ 1],
1212 env
->zarray
[i
].d
[2 * j
],
1221 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1223 g_assert_not_reached();
1228 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
1230 ARMCPU
*cpu
= ARM_CPU(cs
);
1231 CPUARMState
*env
= &cpu
->env
;
1235 aarch64_cpu_dump_state(cs
, f
, flags
);
1239 for (i
= 0; i
< 16; i
++) {
1240 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
1242 qemu_fprintf(f
, "\n");
1244 qemu_fprintf(f
, " ");
1248 if (arm_feature(env
, ARM_FEATURE_M
)) {
1249 uint32_t xpsr
= xpsr_read(env
);
1251 const char *ns_status
= "";
1253 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1254 ns_status
= env
->v7m
.secure
? "S " : "NS ";
1257 if (xpsr
& XPSR_EXCP
) {
1260 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
1261 mode
= "unpriv-thread";
1263 mode
= "priv-thread";
1267 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
1269 xpsr
& XPSR_N
? 'N' : '-',
1270 xpsr
& XPSR_Z
? 'Z' : '-',
1271 xpsr
& XPSR_C
? 'C' : '-',
1272 xpsr
& XPSR_V
? 'V' : '-',
1273 xpsr
& XPSR_T
? 'T' : 'A',
1277 uint32_t psr
= cpsr_read(env
);
1278 const char *ns_status
= "";
1280 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
1281 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
1282 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
1285 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
1287 psr
& CPSR_N
? 'N' : '-',
1288 psr
& CPSR_Z
? 'Z' : '-',
1289 psr
& CPSR_C
? 'C' : '-',
1290 psr
& CPSR_V
? 'V' : '-',
1291 psr
& CPSR_T
? 'T' : 'A',
1293 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1296 if (flags
& CPU_DUMP_FPU
) {
1298 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1300 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1303 for (i
= 0; i
< numvfpregs
; i
++) {
1304 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1305 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1307 i
* 2 + 1, (uint32_t)(v
>> 32),
1310 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1311 if (cpu_isar_feature(aa32_mve
, cpu
)) {
1312 qemu_fprintf(f
, "VPR: %08x\n", env
->v7m
.vpr
);
1317 uint64_t arm_build_mp_affinity(int idx
, uint8_t clustersz
)
1319 uint32_t Aff1
= idx
/ clustersz
;
1320 uint32_t Aff0
= idx
% clustersz
;
1321 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1324 uint64_t arm_cpu_mp_affinity(ARMCPU
*cpu
)
1326 return cpu
->mp_affinity
;
1329 static void arm_cpu_initfn(Object
*obj
)
1331 ARMCPU
*cpu
= ARM_CPU(obj
);
1333 cpu
->cp_regs
= g_hash_table_new_full(g_direct_hash
, g_direct_equal
,
1336 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1337 QLIST_INIT(&cpu
->el_change_hooks
);
1339 #ifdef CONFIG_USER_ONLY
1340 # ifdef TARGET_AARCH64
1342 * The linux kernel defaults to 512-bit for SVE, and 256-bit for SME.
1343 * These values were chosen to fit within the default signal frame.
1344 * See documentation for /proc/sys/abi/{sve,sme}_default_vector_length,
1345 * and our corresponding cpu property.
1347 cpu
->sve_default_vq
= 4;
1348 cpu
->sme_default_vq
= 2;
1351 /* Our inbound IRQ and FIQ lines */
1352 if (kvm_enabled()) {
1353 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1354 * the same interface as non-KVM CPUs.
1356 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1358 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1361 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1362 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1364 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1365 "gicv3-maintenance-interrupt", 1);
1366 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1367 "pmu-interrupt", 1);
1370 /* DTB consumers generally don't in fact care what the 'compatible'
1371 * string is, so always provide some string and trust that a hypothetical
1372 * picky DTB consumer will also provide a helpful error message.
1374 cpu
->dtb_compatible
= "qemu,unknown";
1375 cpu
->psci_version
= QEMU_PSCI_VERSION_0_1
; /* By default assume PSCI v0.1 */
1376 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1378 if (tcg_enabled() || hvf_enabled()) {
1379 /* TCG and HVF implement PSCI 1.1 */
1380 cpu
->psci_version
= QEMU_PSCI_VERSION_1_1
;
1384 static Property arm_cpu_gt_cntfrq_property
=
1385 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1386 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1388 static Property arm_cpu_reset_cbar_property
=
1389 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1391 static Property arm_cpu_reset_hivecs_property
=
1392 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1394 #ifndef CONFIG_USER_ONLY
1395 static Property arm_cpu_has_el2_property
=
1396 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1398 static Property arm_cpu_has_el3_property
=
1399 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1402 static Property arm_cpu_cfgend_property
=
1403 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1405 static Property arm_cpu_has_vfp_property
=
1406 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1408 static Property arm_cpu_has_vfp_d32_property
=
1409 DEFINE_PROP_BOOL("vfp-d32", ARMCPU
, has_vfp_d32
, true);
1411 static Property arm_cpu_has_neon_property
=
1412 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1414 static Property arm_cpu_has_dsp_property
=
1415 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1417 static Property arm_cpu_has_mpu_property
=
1418 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1420 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1421 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1422 * the right value for that particular CPU type, and we don't want
1423 * to override that with an incorrect constant value.
1425 static Property arm_cpu_pmsav7_dregion_property
=
1426 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1428 qdev_prop_uint32
, uint32_t);
1430 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1432 ARMCPU
*cpu
= ARM_CPU(obj
);
1434 return cpu
->has_pmu
;
1437 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1439 ARMCPU
*cpu
= ARM_CPU(obj
);
1442 if (kvm_enabled() && !kvm_arm_pmu_supported()) {
1443 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1446 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1448 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1450 cpu
->has_pmu
= value
;
1453 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1456 * The exact approach to calculating guest ticks is:
1458 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1459 * NANOSECONDS_PER_SECOND);
1461 * We don't do that. Rather we intentionally use integer division
1462 * truncation below and in the caller for the conversion of host monotonic
1463 * time to guest ticks to provide the exact inverse for the semantics of
1464 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1465 * it loses precision when representing frequencies where
1466 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1467 * provide an exact inverse leads to scheduling timers with negative
1468 * periods, which in turn leads to sticky behaviour in the guest.
1470 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1471 * cannot become zero.
1473 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1474 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1477 static void arm_cpu_propagate_feature_implications(ARMCPU
*cpu
)
1479 CPUARMState
*env
= &cpu
->env
;
1480 bool no_aa32
= false;
1483 * Some features automatically imply others: set the feature
1484 * bits explicitly for these cases.
1487 if (arm_feature(env
, ARM_FEATURE_M
)) {
1488 set_feature(env
, ARM_FEATURE_PMSA
);
1491 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1492 if (arm_feature(env
, ARM_FEATURE_M
)) {
1493 set_feature(env
, ARM_FEATURE_V7
);
1495 set_feature(env
, ARM_FEATURE_V7VE
);
1500 * There exist AArch64 cpus without AArch32 support. When KVM
1501 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1502 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1503 * As a general principle, we also do not make ID register
1504 * consistency checks anywhere unless using TCG, because only
1505 * for TCG would a consistency-check failure be a QEMU bug.
1507 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1508 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1511 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1513 * v7 Virtualization Extensions. In real hardware this implies
1514 * EL2 and also the presence of the Security Extensions.
1515 * For QEMU, for backwards-compatibility we implement some
1516 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1517 * include the various other features that V7VE implies.
1518 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1519 * Security Extensions is ARM_FEATURE_EL3.
1521 assert(!tcg_enabled() || no_aa32
||
1522 cpu_isar_feature(aa32_arm_div
, cpu
));
1523 set_feature(env
, ARM_FEATURE_LPAE
);
1524 set_feature(env
, ARM_FEATURE_V7
);
1526 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1527 set_feature(env
, ARM_FEATURE_VAPA
);
1528 set_feature(env
, ARM_FEATURE_THUMB2
);
1529 set_feature(env
, ARM_FEATURE_MPIDR
);
1530 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1531 set_feature(env
, ARM_FEATURE_V6K
);
1533 set_feature(env
, ARM_FEATURE_V6
);
1537 * Always define VBAR for V7 CPUs even if it doesn't exist in
1538 * non-EL3 configs. This is needed by some legacy boards.
1540 set_feature(env
, ARM_FEATURE_VBAR
);
1542 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1543 set_feature(env
, ARM_FEATURE_V6
);
1544 set_feature(env
, ARM_FEATURE_MVFR
);
1546 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1547 set_feature(env
, ARM_FEATURE_V5
);
1548 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1549 assert(!tcg_enabled() || no_aa32
||
1550 cpu_isar_feature(aa32_jazelle
, cpu
));
1551 set_feature(env
, ARM_FEATURE_AUXCR
);
1554 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1555 set_feature(env
, ARM_FEATURE_V4T
);
1557 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1558 set_feature(env
, ARM_FEATURE_V7MP
);
1560 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1561 set_feature(env
, ARM_FEATURE_CBAR
);
1563 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1564 !arm_feature(env
, ARM_FEATURE_M
)) {
1565 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1569 void arm_cpu_post_init(Object
*obj
)
1571 ARMCPU
*cpu
= ARM_CPU(obj
);
1574 * Some features imply others. Figure this out now, because we
1575 * are going to look at the feature bits in deciding which
1576 * properties to add.
1578 arm_cpu_propagate_feature_implications(cpu
);
1580 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1581 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1582 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1585 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1586 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1589 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1590 object_property_add_uint64_ptr(obj
, "rvbar",
1592 OBJ_PROP_FLAG_READWRITE
);
1595 #ifndef CONFIG_USER_ONLY
1596 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1597 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1598 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1600 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1602 object_property_add_link(obj
, "secure-memory",
1604 (Object
**)&cpu
->secure_memory
,
1605 qdev_prop_allow_set_link_before_realize
,
1606 OBJ_PROP_LINK_STRONG
);
1609 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1610 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1614 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1615 cpu
->has_pmu
= true;
1616 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
);
1620 * Allow user to turn off VFP and Neon support, but only for TCG --
1621 * KVM does not currently allow us to lie to the guest about its
1622 * ID/feature registers, so the guest always sees what the host has.
1624 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1625 if (cpu_isar_feature(aa64_fp_simd
, cpu
)) {
1626 cpu
->has_vfp
= true;
1627 cpu
->has_vfp_d32
= true;
1628 if (tcg_enabled() || qtest_enabled()) {
1629 qdev_property_add_static(DEVICE(obj
),
1630 &arm_cpu_has_vfp_property
);
1633 } else if (cpu_isar_feature(aa32_vfp
, cpu
)) {
1634 cpu
->has_vfp
= true;
1635 if (tcg_enabled() || qtest_enabled()) {
1636 qdev_property_add_static(DEVICE(obj
),
1637 &arm_cpu_has_vfp_property
);
1639 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1640 cpu
->has_vfp_d32
= true;
1642 * The permitted values of the SIMDReg bits [3:0] on
1643 * Armv8-A are either 0b0000 and 0b0010. On such CPUs,
1644 * make sure that has_vfp_d32 can not be set to false.
1646 if ((tcg_enabled() || qtest_enabled())
1647 && !(arm_feature(&cpu
->env
, ARM_FEATURE_V8
)
1648 && !arm_feature(&cpu
->env
, ARM_FEATURE_M
))) {
1649 qdev_property_add_static(DEVICE(obj
),
1650 &arm_cpu_has_vfp_d32_property
);
1655 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1656 cpu
->has_neon
= true;
1657 if (!kvm_enabled()) {
1658 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1662 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1663 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1664 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1667 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1668 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1669 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1670 qdev_property_add_static(DEVICE(obj
),
1671 &arm_cpu_pmsav7_dregion_property
);
1675 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1676 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1677 qdev_prop_allow_set_link_before_realize
,
1678 OBJ_PROP_LINK_STRONG
);
1680 * M profile: initial value of the Secure VTOR. We can't just use
1681 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1682 * the property to be set after realize.
1684 object_property_add_uint32_ptr(obj
, "init-svtor",
1686 OBJ_PROP_FLAG_READWRITE
);
1688 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1690 * Initial value of the NS VTOR (for cores without the Security
1691 * extension, this is the only VTOR)
1693 object_property_add_uint32_ptr(obj
, "init-nsvtor",
1695 OBJ_PROP_FLAG_READWRITE
);
1698 /* Not DEFINE_PROP_UINT32: we want this to be settable after realize */
1699 object_property_add_uint32_ptr(obj
, "psci-conduit",
1701 OBJ_PROP_FLAG_READWRITE
);
1703 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1705 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1706 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1709 if (kvm_enabled()) {
1710 kvm_arm_add_vcpu_properties(cpu
);
1713 #ifndef CONFIG_USER_ONLY
1714 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) &&
1715 cpu_isar_feature(aa64_mte
, cpu
)) {
1716 object_property_add_link(obj
, "tag-memory",
1718 (Object
**)&cpu
->tag_memory
,
1719 qdev_prop_allow_set_link_before_realize
,
1720 OBJ_PROP_LINK_STRONG
);
1722 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1723 object_property_add_link(obj
, "secure-tag-memory",
1725 (Object
**)&cpu
->secure_tag_memory
,
1726 qdev_prop_allow_set_link_before_realize
,
1727 OBJ_PROP_LINK_STRONG
);
1733 static void arm_cpu_finalizefn(Object
*obj
)
1735 ARMCPU
*cpu
= ARM_CPU(obj
);
1736 ARMELChangeHook
*hook
, *next
;
1738 g_hash_table_destroy(cpu
->cp_regs
);
1740 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1741 QLIST_REMOVE(hook
, node
);
1744 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1745 QLIST_REMOVE(hook
, node
);
1748 #ifndef CONFIG_USER_ONLY
1749 if (cpu
->pmu_timer
) {
1750 timer_free(cpu
->pmu_timer
);
1755 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1757 Error
*local_err
= NULL
;
1759 #ifdef TARGET_AARCH64
1760 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1761 arm_cpu_sve_finalize(cpu
, &local_err
);
1762 if (local_err
!= NULL
) {
1763 error_propagate(errp
, local_err
);
1768 * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
1769 * FEAT_SME_FA64 is present). However our implementation currently
1770 * assumes it, so if the user asked for sve=off then turn off SME also.
1771 * (KVM doesn't currently support SME at all.)
1773 if (cpu_isar_feature(aa64_sme
, cpu
) && !cpu_isar_feature(aa64_sve
, cpu
)) {
1774 object_property_set_bool(OBJECT(cpu
), "sme", false, &error_abort
);
1777 arm_cpu_sme_finalize(cpu
, &local_err
);
1778 if (local_err
!= NULL
) {
1779 error_propagate(errp
, local_err
);
1783 arm_cpu_pauth_finalize(cpu
, &local_err
);
1784 if (local_err
!= NULL
) {
1785 error_propagate(errp
, local_err
);
1789 arm_cpu_lpa2_finalize(cpu
, &local_err
);
1790 if (local_err
!= NULL
) {
1791 error_propagate(errp
, local_err
);
1797 if (kvm_enabled()) {
1798 kvm_arm_steal_time_finalize(cpu
, &local_err
);
1799 if (local_err
!= NULL
) {
1800 error_propagate(errp
, local_err
);
1806 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1808 CPUState
*cs
= CPU(dev
);
1809 ARMCPU
*cpu
= ARM_CPU(dev
);
1810 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1811 CPUARMState
*env
= &cpu
->env
;
1812 Error
*local_err
= NULL
;
1814 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
1815 /* Use pc-relative instructions in system-mode */
1816 cs
->tcg_cflags
|= CF_PCREL
;
1819 /* If we needed to query the host kernel for the CPU features
1820 * then it's possible that might have failed in the initfn, but
1821 * this is the first point where we can report it.
1823 if (cpu
->host_cpu_probe_failed
) {
1824 if (!kvm_enabled() && !hvf_enabled()) {
1825 error_setg(errp
, "The 'host' CPU type can only be used with KVM or HVF");
1827 error_setg(errp
, "Failed to retrieve host CPU features");
1832 #ifndef CONFIG_USER_ONLY
1833 /* The NVIC and M-profile CPU are two halves of a single piece of
1834 * hardware; trying to use one without the other is a command line
1835 * error and will result in segfaults if not caught here.
1837 if (arm_feature(env
, ARM_FEATURE_M
)) {
1839 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1844 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1849 if (!tcg_enabled() && !qtest_enabled()) {
1851 * We assume that no accelerator except TCG (and the "not really an
1852 * accelerator" qtest) can handle these features, because Arm hardware
1853 * virtualization can't virtualize them.
1855 * Catch all the cases which might cause us to create more than one
1856 * address space for the CPU (otherwise we will assert() later in
1857 * cpu_address_space_init()).
1859 if (arm_feature(env
, ARM_FEATURE_M
)) {
1861 "Cannot enable %s when using an M-profile guest CPU",
1862 current_accel_name());
1867 "Cannot enable %s when guest CPU has EL3 enabled",
1868 current_accel_name());
1871 if (cpu
->tag_memory
) {
1873 "Cannot enable %s when guest CPUs has MTE enabled",
1874 current_accel_name());
1882 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1883 if (!cpu
->gt_cntfrq_hz
) {
1884 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1888 scale
= gt_cntfrq_period_ns(cpu
);
1890 scale
= GTIMER_SCALE
;
1893 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1894 arm_gt_ptimer_cb
, cpu
);
1895 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1896 arm_gt_vtimer_cb
, cpu
);
1897 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1898 arm_gt_htimer_cb
, cpu
);
1899 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1900 arm_gt_stimer_cb
, cpu
);
1901 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1902 arm_gt_hvtimer_cb
, cpu
);
1906 cpu_exec_realizefn(cs
, &local_err
);
1907 if (local_err
!= NULL
) {
1908 error_propagate(errp
, local_err
);
1912 arm_cpu_finalize_features(cpu
, &local_err
);
1913 if (local_err
!= NULL
) {
1914 error_propagate(errp
, local_err
);
1918 #ifdef CONFIG_USER_ONLY
1920 * User mode relies on IC IVAU instructions to catch modification of
1923 * Clear CTR_EL0.DIC to ensure that software that honors these flags uses
1924 * IC IVAU even if the emulated processor does not normally require it.
1926 cpu
->ctr
= FIELD_DP64(cpu
->ctr
, CTR_EL0
, DIC
, 0);
1929 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1930 cpu
->has_vfp
!= cpu
->has_neon
) {
1932 * This is an architectural requirement for AArch64; AArch32 is
1933 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1936 "AArch64 CPUs must have both VFP and Neon or neither");
1940 if (cpu
->has_vfp_d32
!= cpu
->has_neon
) {
1941 error_setg(errp
, "ARM CPUs must have both VFP-D32 and Neon or neither");
1945 if (!cpu
->has_vfp_d32
) {
1948 u
= cpu
->isar
.mvfr0
;
1949 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 1); /* 16 registers */
1950 cpu
->isar
.mvfr0
= u
;
1953 if (!cpu
->has_vfp
) {
1957 t
= cpu
->isar
.id_aa64isar1
;
1958 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1959 cpu
->isar
.id_aa64isar1
= t
;
1961 t
= cpu
->isar
.id_aa64pfr0
;
1962 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1963 cpu
->isar
.id_aa64pfr0
= t
;
1965 u
= cpu
->isar
.id_isar6
;
1966 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1967 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
1968 cpu
->isar
.id_isar6
= u
;
1970 u
= cpu
->isar
.mvfr0
;
1971 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1972 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1973 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1974 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1975 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1976 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1977 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1978 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1980 cpu
->isar
.mvfr0
= u
;
1982 u
= cpu
->isar
.mvfr1
;
1983 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1984 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1985 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1986 if (arm_feature(env
, ARM_FEATURE_M
)) {
1987 u
= FIELD_DP32(u
, MVFR1
, FP16
, 0);
1989 cpu
->isar
.mvfr1
= u
;
1991 u
= cpu
->isar
.mvfr2
;
1992 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1993 cpu
->isar
.mvfr2
= u
;
1996 if (!cpu
->has_neon
) {
2000 unset_feature(env
, ARM_FEATURE_NEON
);
2002 t
= cpu
->isar
.id_aa64isar0
;
2003 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 0);
2004 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 0);
2005 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 0);
2006 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 0);
2007 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 0);
2008 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 0);
2009 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
2010 cpu
->isar
.id_aa64isar0
= t
;
2012 t
= cpu
->isar
.id_aa64isar1
;
2013 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
2014 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 0);
2015 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 0);
2016 cpu
->isar
.id_aa64isar1
= t
;
2018 t
= cpu
->isar
.id_aa64pfr0
;
2019 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
2020 cpu
->isar
.id_aa64pfr0
= t
;
2022 u
= cpu
->isar
.id_isar5
;
2023 u
= FIELD_DP32(u
, ID_ISAR5
, AES
, 0);
2024 u
= FIELD_DP32(u
, ID_ISAR5
, SHA1
, 0);
2025 u
= FIELD_DP32(u
, ID_ISAR5
, SHA2
, 0);
2026 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
2027 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
2028 cpu
->isar
.id_isar5
= u
;
2030 u
= cpu
->isar
.id_isar6
;
2031 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
2032 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
2033 u
= FIELD_DP32(u
, ID_ISAR6
, BF16
, 0);
2034 u
= FIELD_DP32(u
, ID_ISAR6
, I8MM
, 0);
2035 cpu
->isar
.id_isar6
= u
;
2037 if (!arm_feature(env
, ARM_FEATURE_M
)) {
2038 u
= cpu
->isar
.mvfr1
;
2039 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
2040 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
2041 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
2042 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
2043 cpu
->isar
.mvfr1
= u
;
2045 u
= cpu
->isar
.mvfr2
;
2046 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
2047 cpu
->isar
.mvfr2
= u
;
2051 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
2055 t
= cpu
->isar
.id_aa64isar0
;
2056 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
2057 cpu
->isar
.id_aa64isar0
= t
;
2059 t
= cpu
->isar
.id_aa64isar1
;
2060 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
2061 cpu
->isar
.id_aa64isar1
= t
;
2063 u
= cpu
->isar
.mvfr0
;
2064 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
2065 cpu
->isar
.mvfr0
= u
;
2067 /* Despite the name, this field covers both VFP and Neon */
2068 u
= cpu
->isar
.mvfr1
;
2069 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
2070 cpu
->isar
.mvfr1
= u
;
2073 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
2076 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
2078 u
= cpu
->isar
.id_isar1
;
2079 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
2080 cpu
->isar
.id_isar1
= u
;
2082 u
= cpu
->isar
.id_isar2
;
2083 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
2084 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
2085 cpu
->isar
.id_isar2
= u
;
2087 u
= cpu
->isar
.id_isar3
;
2088 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
2089 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
2090 cpu
->isar
.id_isar3
= u
;
2095 * We rely on no XScale CPU having VFP so we can use the same bits in the
2096 * TB flags field for VECSTRIDE and XSCALE_CPAR.
2098 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
2099 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
2100 !arm_feature(env
, ARM_FEATURE_XSCALE
));
2102 #ifndef CONFIG_USER_ONLY
2105 if (arm_feature(env
, ARM_FEATURE_V7
) &&
2106 !arm_feature(env
, ARM_FEATURE_M
) &&
2107 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
2109 * v7VMSA drops support for the old ARMv5 tiny pages,
2110 * so we can use 4K pages.
2115 * For CPUs which might have tiny 1K pages, or which have an
2116 * MPU and might have small region sizes, stick with 1K pages.
2120 if (!set_preferred_target_page_bits(pagebits
)) {
2122 * This can only ever happen for hotplugging a CPU, or if
2123 * the board code incorrectly creates a CPU which it has
2124 * promised via minimum_page_size that it will not.
2126 error_setg(errp
, "This CPU requires a smaller page size "
2127 "than the system is using");
2133 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
2134 * We don't support setting cluster ID ([16..23]) (known as Aff2
2135 * in later ARM ARM versions), or any of the higher affinity level fields,
2136 * so these bits always RAZ.
2138 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
2139 cpu
->mp_affinity
= arm_build_mp_affinity(cs
->cpu_index
,
2140 ARM_DEFAULT_CPUS_PER_CLUSTER
);
2143 if (cpu
->reset_hivecs
) {
2144 cpu
->reset_sctlr
|= (1 << 13);
2148 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
2149 cpu
->reset_sctlr
|= SCTLR_EE
;
2151 cpu
->reset_sctlr
|= SCTLR_B
;
2155 if (!arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_el3
) {
2156 /* If the has_el3 CPU property is disabled then we need to disable the
2159 unset_feature(env
, ARM_FEATURE_EL3
);
2162 * Disable the security extension feature bits in the processor
2163 * feature registers as well.
2165 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
, ID_PFR1
, SECURITY
, 0);
2166 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPSDBG
, 0);
2167 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2168 ID_AA64PFR0
, EL3
, 0);
2170 /* Disable the realm management extension, which requires EL3. */
2171 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2172 ID_AA64PFR0
, RME
, 0);
2175 if (!cpu
->has_el2
) {
2176 unset_feature(env
, ARM_FEATURE_EL2
);
2179 if (!cpu
->has_pmu
) {
2180 unset_feature(env
, ARM_FEATURE_PMU
);
2182 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
2185 if (!kvm_enabled()) {
2186 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
2187 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
2190 #ifndef CONFIG_USER_ONLY
2191 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
2195 cpu
->isar
.id_aa64dfr0
=
2196 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
2197 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
2202 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
2204 * Disable the hypervisor feature bits in the processor feature
2205 * registers if we don't have EL2.
2207 cpu
->isar
.id_aa64pfr0
= FIELD_DP64(cpu
->isar
.id_aa64pfr0
,
2208 ID_AA64PFR0
, EL2
, 0);
2209 cpu
->isar
.id_pfr1
= FIELD_DP32(cpu
->isar
.id_pfr1
,
2210 ID_PFR1
, VIRTUALIZATION
, 0);
2213 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2215 * The architectural range of GM blocksize is 2-6, however qemu
2216 * doesn't support blocksize of 2 (see HELPER(ldgm)).
2218 if (tcg_enabled()) {
2219 assert(cpu
->gm_blocksize
>= 3 && cpu
->gm_blocksize
<= 6);
2222 #ifndef CONFIG_USER_ONLY
2224 * If we do not have tag-memory provided by the machine,
2225 * reduce MTE support to instructions enabled at EL0.
2226 * This matches Cortex-A710 BROADCASTMTE input being LOW.
2228 if (cpu
->tag_memory
== NULL
) {
2229 cpu
->isar
.id_aa64pfr1
=
2230 FIELD_DP64(cpu
->isar
.id_aa64pfr1
, ID_AA64PFR1
, MTE
, 1);
2235 if (tcg_enabled()) {
2237 * Don't report some architectural features in the ID registers
2238 * where TCG does not yet implement it (not even a minimal
2239 * stub version). This avoids guests falling over when they
2240 * try to access the non-existent system registers for them.
2242 /* FEAT_SPE (Statistical Profiling Extension) */
2243 cpu
->isar
.id_aa64dfr0
=
2244 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMSVER
, 0);
2245 /* FEAT_TRBE (Trace Buffer Extension) */
2246 cpu
->isar
.id_aa64dfr0
=
2247 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEBUFFER
, 0);
2248 /* FEAT_TRF (Self-hosted Trace Extension) */
2249 cpu
->isar
.id_aa64dfr0
=
2250 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEFILT
, 0);
2252 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, TRACEFILT
, 0);
2253 /* Trace Macrocell system register access */
2254 cpu
->isar
.id_aa64dfr0
=
2255 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, TRACEVER
, 0);
2257 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, COPTRC
, 0);
2258 /* Memory mapped trace */
2260 FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, MMAPTRC
, 0);
2261 /* FEAT_AMU (Activity Monitors Extension) */
2262 cpu
->isar
.id_aa64pfr0
=
2263 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, AMU
, 0);
2265 FIELD_DP32(cpu
->isar
.id_pfr0
, ID_PFR0
, AMU
, 0);
2266 /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
2267 cpu
->isar
.id_aa64pfr0
=
2268 FIELD_DP64(cpu
->isar
.id_aa64pfr0
, ID_AA64PFR0
, MPAM
, 0);
2271 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
2272 * to false or by setting pmsav7-dregion to 0.
2274 if (!cpu
->has_mpu
|| cpu
->pmsav7_dregion
== 0) {
2275 cpu
->has_mpu
= false;
2276 cpu
->pmsav7_dregion
= 0;
2277 cpu
->pmsav8r_hdregion
= 0;
2280 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
2281 arm_feature(env
, ARM_FEATURE_V7
)) {
2282 uint32_t nr
= cpu
->pmsav7_dregion
;
2285 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
2290 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2292 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2293 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
2294 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2295 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
2296 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
2299 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
2300 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
2301 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
2305 if (cpu
->pmsav8r_hdregion
> 0xff) {
2306 error_setg(errp
, "PMSAv8 MPU EL2 #regions invalid %" PRIu32
,
2307 cpu
->pmsav8r_hdregion
);
2311 if (cpu
->pmsav8r_hdregion
) {
2312 env
->pmsav8
.hprbar
= g_new0(uint32_t,
2313 cpu
->pmsav8r_hdregion
);
2314 env
->pmsav8
.hprlar
= g_new0(uint32_t,
2315 cpu
->pmsav8r_hdregion
);
2319 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
2320 uint32_t nr
= cpu
->sau_sregion
;
2323 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
2328 env
->sau
.rbar
= g_new0(uint32_t, nr
);
2329 env
->sau
.rlar
= g_new0(uint32_t, nr
);
2333 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2334 set_feature(env
, ARM_FEATURE_VBAR
);
2337 #ifndef CONFIG_USER_ONLY
2338 if (tcg_enabled() && cpu_isar_feature(aa64_rme
, cpu
)) {
2339 arm_register_el_change_hook(cpu
, >_rme_post_el_change
, 0);
2343 register_cp_regs_for_features(cpu
);
2344 arm_cpu_register_gdb_regs_for_features(cpu
);
2346 init_cpreg_list(cpu
);
2348 #ifndef CONFIG_USER_ONLY
2349 MachineState
*ms
= MACHINE(qdev_get_machine());
2350 unsigned int smp_cpus
= ms
->smp
.cpus
;
2351 bool has_secure
= cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
);
2354 * We must set cs->num_ases to the final value before
2355 * the first call to cpu_address_space_init.
2357 if (cpu
->tag_memory
!= NULL
) {
2358 cs
->num_ases
= 3 + has_secure
;
2360 cs
->num_ases
= 1 + has_secure
;
2364 if (!cpu
->secure_memory
) {
2365 cpu
->secure_memory
= cs
->memory
;
2367 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
2368 cpu
->secure_memory
);
2371 if (cpu
->tag_memory
!= NULL
) {
2372 cpu_address_space_init(cs
, ARMASIdx_TagNS
, "cpu-tag-memory",
2375 cpu_address_space_init(cs
, ARMASIdx_TagS
, "cpu-tag-memory",
2376 cpu
->secure_tag_memory
);
2380 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
2382 /* No core_count specified, default to smp_cpus. */
2383 if (cpu
->core_count
== -1) {
2384 cpu
->core_count
= smp_cpus
;
2388 if (tcg_enabled()) {
2389 int dcz_blocklen
= 4 << cpu
->dcz_blocksize
;
2392 * We only support DCZ blocklen that fits on one page.
2394 * Architectually this is always true. However TARGET_PAGE_SIZE
2395 * is variable and, for compatibility with -machine virt-2.7,
2396 * is only 1KiB, as an artifact of legacy ARMv5 subpage support.
2397 * But even then, while the largest architectural DCZ blocklen
2398 * is 2KiB, no cpu actually uses such a large blocklen.
2400 assert(dcz_blocklen
<= TARGET_PAGE_SIZE
);
2403 * We only support DCZ blocksize >= 2*TAG_GRANULE, which is to say
2404 * both nibbles of each byte storing tag data may be written at once.
2405 * Since TAG_GRANULE is 16, this means that blocklen must be >= 32.
2407 if (cpu_isar_feature(aa64_mte
, cpu
)) {
2408 assert(dcz_blocklen
>= 2 * TAG_GRANULE
);
2415 acc
->parent_realize(dev
, errp
);
2418 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
2423 const char *cpunamestr
;
2425 cpuname
= g_strsplit(cpu_model
, ",", 1);
2426 cpunamestr
= cpuname
[0];
2427 #ifdef CONFIG_USER_ONLY
2428 /* For backwards compatibility usermode emulation allows "-cpu any",
2429 * which has the same semantics as "-cpu max".
2431 if (!strcmp(cpunamestr
, "any")) {
2435 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
2436 oc
= object_class_by_name(typename
);
2437 g_strfreev(cpuname
);
2443 static Property arm_cpu_properties
[] = {
2444 DEFINE_PROP_UINT64("midr", ARMCPU
, midr
, 0),
2445 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2446 mp_affinity
, ARM64_AFFINITY_INVALID
),
2447 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2448 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2449 DEFINE_PROP_END_OF_LIST()
2452 static const gchar
*arm_gdb_arch_name(CPUState
*cs
)
2454 ARMCPU
*cpu
= ARM_CPU(cs
);
2455 CPUARMState
*env
= &cpu
->env
;
2457 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2463 #ifndef CONFIG_USER_ONLY
2464 #include "hw/core/sysemu-cpu-ops.h"
2466 static const struct SysemuCPUOps arm_sysemu_ops
= {
2467 .get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
,
2468 .asidx_from_attrs
= arm_asidx_from_attrs
,
2469 .write_elf32_note
= arm_cpu_write_elf32_note
,
2470 .write_elf64_note
= arm_cpu_write_elf64_note
,
2471 .virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
,
2472 .legacy_vmsd
= &vmstate_arm_cpu
,
2477 static const TCGCPUOps arm_tcg_ops
= {
2478 .initialize
= arm_translate_init
,
2479 .synchronize_from_tb
= arm_cpu_synchronize_from_tb
,
2480 .debug_excp_handler
= arm_debug_excp_handler
,
2481 .restore_state_to_opc
= arm_restore_state_to_opc
,
2483 #ifdef CONFIG_USER_ONLY
2484 .record_sigsegv
= arm_cpu_record_sigsegv
,
2485 .record_sigbus
= arm_cpu_record_sigbus
,
2487 .tlb_fill
= arm_cpu_tlb_fill
,
2488 .cpu_exec_interrupt
= arm_cpu_exec_interrupt
,
2489 .do_interrupt
= arm_cpu_do_interrupt
,
2490 .do_transaction_failed
= arm_cpu_do_transaction_failed
,
2491 .do_unaligned_access
= arm_cpu_do_unaligned_access
,
2492 .adjust_watchpoint_address
= arm_adjust_watchpoint_address
,
2493 .debug_check_watchpoint
= arm_debug_check_watchpoint
,
2494 .debug_check_breakpoint
= arm_debug_check_breakpoint
,
2495 #endif /* !CONFIG_USER_ONLY */
2497 #endif /* CONFIG_TCG */
2499 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2501 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2502 CPUClass
*cc
= CPU_CLASS(acc
);
2503 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2504 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
2506 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2507 &acc
->parent_realize
);
2509 device_class_set_props(dc
, arm_cpu_properties
);
2511 resettable_class_set_parent_phases(rc
, NULL
, arm_cpu_reset_hold
, NULL
,
2512 &acc
->parent_phases
);
2514 cc
->class_by_name
= arm_cpu_class_by_name
;
2515 cc
->has_work
= arm_cpu_has_work
;
2516 cc
->mmu_index
= arm_cpu_mmu_index
;
2517 cc
->dump_state
= arm_cpu_dump_state
;
2518 cc
->set_pc
= arm_cpu_set_pc
;
2519 cc
->get_pc
= arm_cpu_get_pc
;
2520 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2521 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2522 #ifndef CONFIG_USER_ONLY
2523 cc
->sysemu_ops
= &arm_sysemu_ops
;
2525 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2526 cc
->gdb_stop_before_watchpoint
= true;
2527 cc
->disas_set_info
= arm_disas_set_info
;
2530 cc
->tcg_ops
= &arm_tcg_ops
;
2531 #endif /* CONFIG_TCG */
2534 static void arm_cpu_instance_init(Object
*obj
)
2536 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2538 acc
->info
->initfn(obj
);
2539 arm_cpu_post_init(obj
);
2542 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2544 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2545 CPUClass
*cc
= CPU_CLASS(acc
);
2548 cc
->gdb_core_xml_file
= "arm-core.xml";
2551 void arm_cpu_register(const ARMCPUInfo
*info
)
2553 TypeInfo type_info
= {
2554 .parent
= TYPE_ARM_CPU
,
2555 .instance_init
= arm_cpu_instance_init
,
2556 .class_init
= info
->class_init
?: cpu_register_class_init
,
2557 .class_data
= (void *)info
,
2560 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2561 type_register(&type_info
);
2562 g_free((void *)type_info
.name
);
2565 static const TypeInfo arm_cpu_type_info
= {
2566 .name
= TYPE_ARM_CPU
,
2568 .instance_size
= sizeof(ARMCPU
),
2569 .instance_align
= __alignof__(ARMCPU
),
2570 .instance_init
= arm_cpu_initfn
,
2571 .instance_finalize
= arm_cpu_finalizefn
,
2573 .class_size
= sizeof(ARMCPUClass
),
2574 .class_init
= arm_cpu_class_init
,
2577 static void arm_cpu_register_types(void)
2579 type_register_static(&arm_cpu_type_info
);
2582 type_init(arm_cpu_register_types
)