target/arm/cpu-features.h

   1 /*
   2  * QEMU Arm CPU -- feature test functions
   3  *
   4  *  Copyright (c) 2023 Linaro Ltd
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef TARGET_ARM_FEATURES_H
  21 #define TARGET_ARM_FEATURES_H
  22
  23 #include "hw/registerfields.h"
  24
  25 /*
  26  * Naming convention for isar_feature functions:
  27  * Functions which test 32-bit ID registers should have _aa32_ in
  28  * their name. Functions which test 64-bit ID registers should have
  29  * _aa64_ in their name. These must only be used in code where we
  30  * know for certain that the CPU has AArch32 or AArch64 respectively
  31  * or where the correct answer for a CPU which doesn't implement that
  32  * CPU state is "false" (eg when generating A32 or A64 code, if adding
  33  * system registers that are specific to that CPU state, for "should
  34  * we let this system register bit be set" tests where the 32-bit
  35  * flavour of the register doesn't have the bit, and so on).
  36  * Functions which simply ask "does this feature exist at all" have
  37  * _any_ in their name, and always return the logical OR of the _aa64_
  38  * and the _aa32_ function.
  39  */
  40
  41 /*
  42  * 32-bit feature tests via id registers.
  43  */
  44 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
  45 {
  46     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
  47 }
  48
  49 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
  50 {
  51     return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
  52 }
  53
  54 static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
  55 {
  56     /* (M-profile) low-overhead loops and branch future */
  57     return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
  58 }
  59
  60 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
  61 {
  62     return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
  63 }
  64
  65 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
  66 {
  67     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
  68 }
  69
  70 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
  71 {
  72     return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
  73 }
  74
  75 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
  76 {
  77     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
  78 }
  79
  80 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
  81 {
  82     return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
  83 }
  84
  85 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
  86 {
  87     return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
  88 }
  89
  90 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
  91 {
  92     return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
  93 }
  94
  95 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
  96 {
  97     return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
  98 }
  99
 100 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
 101 {
 102     return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
 103 }
 104
 105 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
 106 {
 107     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
 108 }
 109
 110 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
 111 {
 112     return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
 113 }
 114
 115 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
 116 {
 117     return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
 118 }
 119
 120 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
 121 {
 122     return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
 123 }
 124
 125 static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
 126 {
 127     return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
 128 }
 129
 130 static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
 131 {
 132     return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
 133 }
 134
 135 static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
 136 {
 137     return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
 138 }
 139
 140 static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
 141 {
 142     return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
 143 }
 144
 145 static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
 146 {
 147     /*
 148      * Return true if M-profile state handling insns
 149      * (VSCCLRM, CLRM, FPCTX access insns) are implemented
 150      */
 151     return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
 152 }
 153
 154 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 155 {
 156     /* Sadly this is encoded differently for A-profile and M-profile */
 157     if (isar_feature_aa32_mprofile(id)) {
 158         return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
 159     } else {
 160         return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
 161     }
 162 }
 163
 164 static inline bool isar_feature_aa32_mve(const ARMISARegisters *id)
 165 {
 166     /*
 167      * Return true if MVE is supported (either integer or floating point).
 168      * We must check for M-profile as the MVFR1 field means something
 169      * else for A-profile.
 170      */
 171     return isar_feature_aa32_mprofile(id) &&
 172         FIELD_EX32(id->mvfr1, MVFR1, MVE) > 0;
 173 }
 174
 175 static inline bool isar_feature_aa32_mve_fp(const ARMISARegisters *id)
 176 {
 177     /*
 178      * Return true if MVE is supported (either integer or floating point).
 179      * We must check for M-profile as the MVFR1 field means something
 180      * else for A-profile.
 181      */
 182     return isar_feature_aa32_mprofile(id) &&
 183         FIELD_EX32(id->mvfr1, MVFR1, MVE) >= 2;
 184 }
 185
 186 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
 187 {
 188     /*
 189      * Return true if either VFP or SIMD is implemented.
 190      * In this case, a minimum of VFP w/ D0-D15.
 191      */
 192     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
 193 }
 194
 195 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
 196 {
 197     /* Return true if D16-D31 are implemented */
 198     return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
 199 }
 200
 201 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
 202 {
 203     return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
 204 }
 205
 206 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
 207 {
 208     /* Return true if CPU supports single precision floating point, VFPv2 */
 209     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
 210 }
 211
 212 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
 213 {
 214     /* Return true if CPU supports single precision floating point, VFPv3 */
 215     return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
 216 }
 217
 218 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
 219 {
 220     /* Return true if CPU supports double precision floating point, VFPv2 */
 221     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
 222 }
 223
 224 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
 225 {
 226     /* Return true if CPU supports double precision floating point, VFPv3 */
 227     return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
 228 }
 229
 230 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
 231 {
 232     return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
 233 }
 234
 235 /*
 236  * We always set the FP and SIMD FP16 fields to indicate identical
 237  * levels of support (assuming SIMD is implemented at all), so
 238  * we only need one set of accessors.
 239  */
 240 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
 241 {
 242     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
 243 }
 244
 245 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
 246 {
 247     return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
 248 }
 249
 250 /*
 251  * Note that this ID register field covers both VFP and Neon FMAC,
 252  * so should usually be tested in combination with some other
 253  * check that confirms the presence of whichever of VFP or Neon is
 254  * relevant, to avoid accidentally enabling a Neon feature on
 255  * a VFP-no-Neon core or vice-versa.
 256  */
 257 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
 258 {
 259     return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
 260 }
 261
 262 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
 263 {
 264     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
 265 }
 266
 267 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
 268 {
 269     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
 270 }
 271
 272 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
 273 {
 274     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
 275 }
 276
 277 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
 278 {
 279     return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
 280 }
 281
 282 static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
 283 {
 284     return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
 285 }
 286
 287 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
 288 {
 289     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
 290 }
 291
 292 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
 293 {
 294     return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
 295 }
 296
 297 static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
 298 {
 299     /* 0xf means "non-standard IMPDEF PMU" */
 300     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
 301         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
 302 }
 303
 304 static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
 305 {
 306     /* 0xf means "non-standard IMPDEF PMU" */
 307     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
 308         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
 309 }
 310
 311 static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
 312 {
 313     /* 0xf means "non-standard IMPDEF PMU" */
 314     return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
 315         FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
 316 }
 317
 318 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
 319 {
 320     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
 321 }
 322
 323 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
 324 {
 325     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
 326 }
 327
 328 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
 329 {
 330     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
 331 }
 332
 333 static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
 334 {
 335     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
 336 }
 337
 338 static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
 339 {
 340     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
 341 }
 342
 343 static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
 344 {
 345     return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
 346 }
 347
 348 static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
 349 {
 350     return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
 351 }
 352
 353 static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
 354 {
 355     return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
 356 }
 357
 358 static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
 359 {
 360     return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
 361 }
 362
 363 static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
 364 {
 365     return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
 366 }
 367
 368 static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
 369 {
 370     return FIELD_EX32(id->dbgdevid, DBGDEVID, DOUBLELOCK) > 0;
 371 }
 372
 373 /*
 374  * 64-bit feature tests via id registers.
 375  */
 376 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
 377 {
 378     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
 379 }
 380
 381 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
 382 {
 383     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
 384 }
 385
 386 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
 387 {
 388     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
 389 }
 390
 391 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
 392 {
 393     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
 394 }
 395
 396 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
 397 {
 398     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
 399 }
 400
 401 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
 402 {
 403     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
 404 }
 405
 406 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
 407 {
 408     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
 409 }
 410
 411 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
 412 {
 413     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
 414 }
 415
 416 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
 417 {
 418     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
 419 }
 420
 421 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
 422 {
 423     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
 424 }
 425
 426 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
 427 {
 428     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
 429 }
 430
 431 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
 432 {
 433     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
 434 }
 435
 436 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
 437 {
 438     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
 439 }
 440
 441 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
 442 {
 443     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
 444 }
 445
 446 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
 447 {
 448     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
 449 }
 450
 451 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
 452 {
 453     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
 454 }
 455
 456 static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
 457 {
 458     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
 459 }
 460
 461 static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
 462 {
 463     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
 464 }
 465
 466 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
 467 {
 468     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
 469 }
 470
 471 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
 472 {
 473     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
 474 }
 475
 476 /*
 477  * These are the values from APA/API/APA3.
 478  * In general these must be compared '>=', per the normal Arm ARM
 479  * treatment of fields in ID registers.
 480  */
 481 typedef enum {
 482     PauthFeat_None         = 0,
 483     PauthFeat_1            = 1,
 484     PauthFeat_EPAC         = 2,
 485     PauthFeat_2            = 3,
 486     PauthFeat_FPAC         = 4,
 487     PauthFeat_FPACCOMBINED = 5,
 488 } ARMPauthFeature;
 489
 490 static inline ARMPauthFeature
 491 isar_feature_pauth_feature(const ARMISARegisters *id)
 492 {
 493     /*
 494      * Architecturally, only one of {APA,API,APA3} may be active (non-zero)
 495      * and the other two must be zero.  Thus we may avoid conditionals.
 496      */
 497     return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
 498             FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
 499             FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
 500 }
 501
 502 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
 503 {
 504     /*
 505      * Return true if any form of pauth is enabled, as this
 506      * predicate controls migration of the 128-bit keys.
 507      */
 508     return isar_feature_pauth_feature(id) != PauthFeat_None;
 509 }
 510
 511 static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
 512 {
 513     /*
 514      * Return true if pauth is enabled with the architected QARMA5 algorithm.
 515      * QEMU will always enable or disable both APA and GPA.
 516      */
 517     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
 518 }
 519
 520 static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
 521 {
 522     /*
 523      * Return true if pauth is enabled with the architected QARMA3 algorithm.
 524      * QEMU will always enable or disable both APA3 and GPA3.
 525      */
 526     return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
 527 }
 528
 529 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
 530 {
 531     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
 532 }
 533
 534 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
 535 {
 536     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
 537 }
 538
 539 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
 540 {
 541     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
 542 }
 543
 544 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
 545 {
 546     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
 547 }
 548
 549 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
 550 {
 551     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
 552 }
 553
 554 static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
 555 {
 556     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
 557 }
 558
 559 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
 560 {
 561     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
 562 }
 563
 564 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
 565 {
 566     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
 567 }
 568
 569 static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
 570 {
 571     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
 572 }
 573
 574 static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
 575 {
 576     return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
 577 }
 578
 579 static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
 580 {
 581     return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
 582 }
 583
 584 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
 585 {
 586     /* We always set the AdvSIMD and FP fields identically.  */
 587     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
 588 }
 589
 590 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
 591 {
 592     /* We always set the AdvSIMD and FP fields identically wrt FP16.  */
 593     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
 594 }
 595
 596 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
 597 {
 598     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
 599 }
 600
 601 static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
 602 {
 603     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
 604 }
 605
 606 static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
 607 {
 608     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
 609 }
 610
 611 static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
 612 {
 613     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
 614 }
 615
 616 static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
 617 {
 618     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
 619 }
 620
 621 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
 622 {
 623     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
 624 }
 625
 626 static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
 627 {
 628     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
 629 }
 630
 631 static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
 632 {
 633     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
 634 }
 635
 636 static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
 637 {
 638     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
 639 }
 640
 641 static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
 642 {
 643     int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
 644     if (key >= 2) {
 645         return true;      /* FEAT_CSV2_2 */
 646     }
 647     if (key == 1) {
 648         key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
 649         return key >= 2;  /* FEAT_CSV2_1p2 */
 650     }
 651     return false;
 652 }
 653
 654 static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
 655 {
 656     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
 657 }
 658
 659 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
 660 {
 661     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
 662 }
 663
 664 static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
 665 {
 666     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
 667 }
 668
 669 static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
 670 {
 671     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
 672 }
 673
 674 static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id)
 675 {
 676     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 3;
 677 }
 678
 679 static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
 680 {
 681     return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
 682 }
 683
 684 static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
 685 {
 686     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
 687 }
 688
 689 static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
 690 {
 691     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
 692     return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
 693 }
 694
 695 static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
 696 {
 697     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
 698 }
 699
 700 static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
 701 {
 702     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
 703     return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
 704 }
 705
 706 static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
 707 {
 708     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
 709 }
 710
 711 static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
 712 {
 713     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
 714 }
 715
 716 static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
 717 {
 718     return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
 719 }
 720
 721 static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
 722 {
 723     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
 724     return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
 725 }
 726
 727 static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
 728 {
 729     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
 730     return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
 731 }
 732
 733 static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
 734 {
 735     unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
 736     return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
 737 }
 738
 739 static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
 740 {
 741     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
 742 }
 743
 744 static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
 745 {
 746     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
 747 }
 748
 749 static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
 750 {
 751     return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
 752 }
 753
 754 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
 755 {
 756     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
 757 }
 758
 759 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
 760 {
 761     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
 762 }
 763
 764 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
 765 {
 766     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
 767 }
 768
 769 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
 770 {
 771     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
 772 }
 773
 774 static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
 775 {
 776     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
 777 }
 778
 779 static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
 780 {
 781     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
 782 }
 783
 784 static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
 785 {
 786     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
 787 }
 788
 789 static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
 790 {
 791     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
 792 }
 793
 794 static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
 795 {
 796     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
 797 }
 798
 799 static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
 800 {
 801     return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
 802 }
 803
 804 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
 805 {
 806     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
 807 }
 808
 809 static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
 810 {
 811     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
 812 }
 813
 814 static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
 815 {
 816     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
 817 }
 818
 819 static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
 820 {
 821     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
 822 }
 823
 824 static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
 825 {
 826     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
 827 }
 828
 829 static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
 830 {
 831     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
 832 }
 833
 834 static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
 835 {
 836     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
 837 }
 838
 839 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
 840 {
 841     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
 842 }
 843
 844 static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
 845 {
 846     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
 847 }
 848
 849 static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
 850 {
 851     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
 852 }
 853
 854 static inline bool isar_feature_aa64_nv(const ARMISARegisters *id)
 855 {
 856     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0;
 857 }
 858
 859 static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
 860 {
 861     return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >= 2;
 862 }
 863
 864 static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
 865 {
 866     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
 867         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
 868 }
 869
 870 static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
 871 {
 872     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
 873         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
 874 }
 875
 876 static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
 877 {
 878     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
 879         FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
 880 }
 881
 882 static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
 883 {
 884     return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
 885 }
 886
 887 static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
 888 {
 889     return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
 890 }
 891
 892 static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
 893 {
 894     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
 895 }
 896
 897 static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
 898 {
 899     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
 900 }
 901
 902 static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
 903 {
 904     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
 905 }
 906
 907 static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
 908 {
 909     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
 910 }
 911
 912 static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
 913 {
 914     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
 915 }
 916
 917 static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
 918 {
 919     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
 920 }
 921
 922 static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
 923 {
 924     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
 925 }
 926
 927 static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
 928 {
 929     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
 930 }
 931
 932 static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
 933 {
 934     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
 935 }
 936
 937 static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
 938 {
 939     return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
 940 }
 941
 942 static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
 943 {
 944     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
 945 }
 946
 947 static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
 948 {
 949     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
 950 }
 951
 952 static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
 953 {
 954     return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
 955 }
 956
 957 /*
 958  * Feature tests for "does this exist in either 32-bit or 64-bit?"
 959  */
 960 static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
 961 {
 962     return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
 963 }
 964
 965 static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
 966 {
 967     return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
 968 }
 969
 970 static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id)
 971 {
 972     return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id);
 973 }
 974
 975 static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id)
 976 {
 977     return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id);
 978 }
 979
 980 static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id)
 981 {
 982     return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id);
 983 }
 984
 985 static inline bool isar_feature_any_ccidx(const ARMISARegisters *id)
 986 {
 987     return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id);
 988 }
 989
 990 static inline bool isar_feature_any_tts2uxn(const ARMISARegisters *id)
 991 {
 992     return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id);
 993 }
 994
 995 static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id)
 996 {
 997     return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(id);
 998 }
 999
1000 static inline bool isar_feature_any_ras(const ARMISARegisters *id)
1001 {
1002     return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id);
1003 }
1004
1005 static inline bool isar_feature_any_half_evt(const ARMISARegisters *id)
1006 {
1007     return isar_feature_aa64_half_evt(id) || isar_feature_aa32_half_evt(id);
1008 }
1009
1010 static inline bool isar_feature_any_evt(const ARMISARegisters *id)
1011 {
1012     return isar_feature_aa64_evt(id) || isar_feature_aa32_evt(id);
1013 }
1014
1015 /*
1016  * Forward to the above feature tests given an ARMCPU pointer.
1017  */
1018 #define cpu_isar_feature(name, cpu) \
1019     ({ ARMCPU *cpu_ = (cpu); isar_feature_##name(&cpu_->isar); })
1020
1021 #endif