2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "hw/qdev-properties.h"
18 #include "monitor/monitor.h"
19 #include "hw/ppc/xive.h"
20 #include "hw/ppc/xive_regs.h"
23 * XIVE Thread Interrupt Management context
27 * Convert a priority number to an Interrupt Pending Buffer (IPB)
28 * register, which indicates a pending interrupt at the priority
29 * corresponding to the bit number
31 static uint8_t priority_to_ipb(uint8_t priority
)
33 return priority
> XIVE_PRIORITY_MAX
?
34 0 : 1 << (XIVE_PRIORITY_MAX
- priority
);
38 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
39 * Interrupt Priority Register (PIPR), which contains the priority of
40 * the most favored pending notification.
42 static uint8_t ipb_to_pipr(uint8_t ibp
)
44 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
47 static void ipb_update(uint8_t *regs
, uint8_t priority
)
49 regs
[TM_IPB
] |= priority_to_ipb(priority
);
50 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
53 static uint8_t exception_mask(uint8_t ring
)
61 g_assert_not_reached();
65 static qemu_irq
xive_tctx_output(XiveTCTX
*tctx
, uint8_t ring
)
69 return 0; /* Not supported */
71 return tctx
->os_output
;
74 return tctx
->hv_output
;
80 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
82 uint8_t *regs
= &tctx
->regs
[ring
];
83 uint8_t nsr
= regs
[TM_NSR
];
84 uint8_t mask
= exception_mask(ring
);
86 qemu_irq_lower(xive_tctx_output(tctx
, ring
));
88 if (regs
[TM_NSR
] & mask
) {
89 uint8_t cppr
= regs
[TM_PIPR
];
93 /* Reset the pending buffer bit */
94 regs
[TM_IPB
] &= ~priority_to_ipb(cppr
);
95 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
97 /* Drop Exception bit */
98 regs
[TM_NSR
] &= ~mask
;
101 return (nsr
<< 8) | regs
[TM_CPPR
];
104 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
106 uint8_t *regs
= &tctx
->regs
[ring
];
108 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
111 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
114 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
117 g_assert_not_reached();
119 qemu_irq_raise(xive_tctx_output(tctx
, ring
));
123 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
125 if (cppr
> XIVE_PRIORITY_MAX
) {
129 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
131 /* CPPR has changed, check if we need to raise a pending exception */
132 xive_tctx_notify(tctx
, ring
);
136 * XIVE Thread Interrupt Management Area (TIMA)
139 static void xive_tm_set_hv_cppr(XiveTCTX
*tctx
, hwaddr offset
,
140 uint64_t value
, unsigned size
)
142 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
145 static uint64_t xive_tm_ack_hv_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
147 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
150 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX
*tctx
, hwaddr offset
,
155 ret
= tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
] & TM_QW2W2_POOL_CAM
;
156 tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
] &= ~TM_QW2W2_POOL_CAM
;
160 static void xive_tm_vt_push(XiveTCTX
*tctx
, hwaddr offset
,
161 uint64_t value
, unsigned size
)
163 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
166 static uint64_t xive_tm_vt_poll(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
168 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
172 * Define an access map for each page of the TIMA that we will use in
173 * the memory region ops to filter values when doing loads and stores
174 * of raw registers values
176 * Registers accessibility bits :
184 static const uint8_t xive_tm_hw_view
[] = {
185 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
186 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
187 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
188 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
191 static const uint8_t xive_tm_hv_view
[] = {
192 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
193 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
194 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
195 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
198 static const uint8_t xive_tm_os_view
[] = {
199 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
200 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
201 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
205 static const uint8_t xive_tm_user_view
[] = {
206 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
207 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
209 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
213 * Overall TIMA access map for the thread interrupt management context
216 static const uint8_t *xive_tm_views
[] = {
217 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
218 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
219 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
220 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
224 * Computes a register access mask for a given offset in the TIMA
226 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
228 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
229 uint8_t reg_offset
= offset
& 0x3F;
230 uint8_t reg_mask
= write
? 0x1 : 0x2;
234 for (i
= 0; i
< size
; i
++) {
235 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
236 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
243 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
246 uint8_t ring_offset
= offset
& 0x30;
247 uint8_t reg_offset
= offset
& 0x3F;
248 uint64_t mask
= xive_tm_mask(offset
, size
, true);
252 * Only 4 or 8 bytes stores are allowed and the User ring is
255 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
256 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
257 HWADDR_PRIx
"\n", offset
);
262 * Use the register offset for the raw values and filter out
265 for (i
= 0; i
< size
; i
++) {
266 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
268 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
274 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
276 uint8_t ring_offset
= offset
& 0x30;
277 uint8_t reg_offset
= offset
& 0x3F;
278 uint64_t mask
= xive_tm_mask(offset
, size
, false);
283 * Only 4 or 8 bytes loads are allowed and the User ring is
286 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
287 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
288 HWADDR_PRIx
"\n", offset
);
292 /* Use the register offset for the raw values */
294 for (i
= 0; i
< size
; i
++) {
295 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
298 /* filter out reserved values */
303 * The TM context is mapped twice within each page. Stores and loads
304 * to the first mapping below 2K write and read the specified values
305 * without modification. The second mapping above 2K performs specific
306 * state changes (side effects) in addition to setting/returning the
307 * interrupt management area context of the processor thread.
309 static uint64_t xive_tm_ack_os_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
311 return xive_tctx_accept(tctx
, TM_QW1_OS
);
314 static void xive_tm_set_os_cppr(XiveTCTX
*tctx
, hwaddr offset
,
315 uint64_t value
, unsigned size
)
317 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
321 * Adjust the IPB to allow a CPU to process event queues of other
322 * priorities during one physical interrupt cycle.
324 static void xive_tm_set_os_pending(XiveTCTX
*tctx
, hwaddr offset
,
325 uint64_t value
, unsigned size
)
327 ipb_update(&tctx
->regs
[TM_QW1_OS
], value
& 0xff);
328 xive_tctx_notify(tctx
, TM_QW1_OS
);
332 * Define a mapping of "special" operations depending on the TIMA page
333 * offset and the size of the operation.
335 typedef struct XiveTmOp
{
339 void (*write_handler
)(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
341 uint64_t (*read_handler
)(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
);
344 static const XiveTmOp xive_tm_operations
[] = {
346 * MMIOs below 2K : raw values and special operations without side
349 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
350 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
351 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
352 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
354 /* MMIOs above 2K : special operations with side effects */
355 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
356 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
357 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
358 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
359 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
362 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
364 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
365 uint32_t op_offset
= offset
& 0xFFF;
368 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
369 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
371 /* Accesses done from a more privileged TIMA page is allowed */
372 if (xto
->page_offset
>= page_offset
&&
373 xto
->op_offset
== op_offset
&&
375 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
385 void xive_tctx_tm_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
391 * TODO: check V bit in Q[0-3]W2
395 * First, check for special operations in the 2K region
397 if (offset
& 0x800) {
398 xto
= xive_tm_find_op(offset
, size
, true);
400 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA"
401 "@%"HWADDR_PRIx
"\n", offset
);
403 xto
->write_handler(tctx
, offset
, value
, size
);
409 * Then, for special operations in the region below 2K.
411 xto
= xive_tm_find_op(offset
, size
, true);
413 xto
->write_handler(tctx
, offset
, value
, size
);
418 * Finish with raw access to the register values
420 xive_tm_raw_write(tctx
, offset
, value
, size
);
423 uint64_t xive_tctx_tm_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
428 * TODO: check V bit in Q[0-3]W2
432 * First, check for special operations in the 2K region
434 if (offset
& 0x800) {
435 xto
= xive_tm_find_op(offset
, size
, false);
437 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
438 "@%"HWADDR_PRIx
"\n", offset
);
441 return xto
->read_handler(tctx
, offset
, size
);
445 * Then, for special operations in the region below 2K.
447 xto
= xive_tm_find_op(offset
, size
, false);
449 return xto
->read_handler(tctx
, offset
, size
);
453 * Finish with raw access to the register values
455 return xive_tm_raw_read(tctx
, offset
, size
);
458 static void xive_tm_write(void *opaque
, hwaddr offset
,
459 uint64_t value
, unsigned size
)
461 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
463 xive_tctx_tm_write(tctx
, offset
, value
, size
);
466 static uint64_t xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
468 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
470 return xive_tctx_tm_read(tctx
, offset
, size
);
473 const MemoryRegionOps xive_tm_ops
= {
474 .read
= xive_tm_read
,
475 .write
= xive_tm_write
,
476 .endianness
= DEVICE_BIG_ENDIAN
,
478 .min_access_size
= 1,
479 .max_access_size
= 8,
482 .min_access_size
= 1,
483 .max_access_size
= 8,
487 static inline uint32_t xive_tctx_word2(uint8_t *ring
)
489 return *((uint32_t *) &ring
[TM_WORD2
]);
492 static char *xive_tctx_ring_print(uint8_t *ring
)
494 uint32_t w2
= xive_tctx_word2(ring
);
496 return g_strdup_printf("%02x %02x %02x %02x %02x "
497 "%02x %02x %02x %08x",
498 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
499 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
503 static const char * const xive_tctx_ring_names
[] = {
504 "USER", "OS", "POOL", "PHYS",
507 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
509 int cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
512 if (kvm_irqchip_in_kernel()) {
513 Error
*local_err
= NULL
;
515 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
517 error_report_err(local_err
);
522 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
525 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
526 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
527 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
528 xive_tctx_ring_names
[i
], s
);
533 static void xive_tctx_reset(void *dev
)
535 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
537 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
539 /* Set some defaults */
540 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
541 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
542 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
545 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
548 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
549 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
550 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
551 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
554 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
556 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
560 Error
*local_err
= NULL
;
562 obj
= object_property_get_link(OBJECT(dev
), "cpu", &local_err
);
564 error_propagate(errp
, local_err
);
565 error_prepend(errp
, "required link 'cpu' not found: ");
569 cpu
= POWERPC_CPU(obj
);
573 switch (PPC_INPUT(env
)) {
574 case PPC_FLAGS_INPUT_POWER9
:
575 tctx
->hv_output
= env
->irq_inputs
[POWER9_INPUT_HINT
];
576 tctx
->os_output
= env
->irq_inputs
[POWER9_INPUT_INT
];
580 error_setg(errp
, "XIVE interrupt controller does not support "
581 "this CPU bus model");
585 /* Connect the presenter to the VCPU (required for CPU hotplug) */
586 if (kvm_irqchip_in_kernel()) {
587 kvmppc_xive_cpu_connect(tctx
, &local_err
);
589 error_propagate(errp
, local_err
);
594 qemu_register_reset(xive_tctx_reset
, dev
);
597 static void xive_tctx_unrealize(DeviceState
*dev
, Error
**errp
)
599 qemu_unregister_reset(xive_tctx_reset
, dev
);
602 static int vmstate_xive_tctx_pre_save(void *opaque
)
604 Error
*local_err
= NULL
;
606 if (kvm_irqchip_in_kernel()) {
607 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque
), &local_err
);
609 error_report_err(local_err
);
617 static const VMStateDescription vmstate_xive_tctx
= {
618 .name
= TYPE_XIVE_TCTX
,
620 .minimum_version_id
= 1,
621 .pre_save
= vmstate_xive_tctx_pre_save
,
622 .post_load
= NULL
, /* handled by the sPAPRxive model */
623 .fields
= (VMStateField
[]) {
624 VMSTATE_BUFFER(regs
, XiveTCTX
),
625 VMSTATE_END_OF_LIST()
629 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
631 DeviceClass
*dc
= DEVICE_CLASS(klass
);
633 dc
->desc
= "XIVE Interrupt Thread Context";
634 dc
->realize
= xive_tctx_realize
;
635 dc
->unrealize
= xive_tctx_unrealize
;
636 dc
->vmsd
= &vmstate_xive_tctx
;
639 static const TypeInfo xive_tctx_info
= {
640 .name
= TYPE_XIVE_TCTX
,
641 .parent
= TYPE_DEVICE
,
642 .instance_size
= sizeof(XiveTCTX
),
643 .class_init
= xive_tctx_class_init
,
646 Object
*xive_tctx_create(Object
*cpu
, XiveRouter
*xrtr
, Error
**errp
)
648 Error
*local_err
= NULL
;
651 obj
= object_new(TYPE_XIVE_TCTX
);
652 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
, &error_abort
);
654 object_property_add_const_link(obj
, "cpu", cpu
, &error_abort
);
655 object_property_set_bool(obj
, true, "realized", &local_err
);
663 object_unparent(obj
);
664 error_propagate(errp
, local_err
);
672 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
674 uint8_t old_pq
= *pq
& 0x3;
682 static bool xive_esb_trigger(uint8_t *pq
)
684 uint8_t old_pq
= *pq
& 0x3;
688 xive_esb_set(pq
, XIVE_ESB_PENDING
);
690 case XIVE_ESB_PENDING
:
691 case XIVE_ESB_QUEUED
:
692 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
695 xive_esb_set(pq
, XIVE_ESB_OFF
);
698 g_assert_not_reached();
702 static bool xive_esb_eoi(uint8_t *pq
)
704 uint8_t old_pq
= *pq
& 0x3;
708 case XIVE_ESB_PENDING
:
709 xive_esb_set(pq
, XIVE_ESB_RESET
);
711 case XIVE_ESB_QUEUED
:
712 xive_esb_set(pq
, XIVE_ESB_PENDING
);
715 xive_esb_set(pq
, XIVE_ESB_OFF
);
718 g_assert_not_reached();
723 * XIVE Interrupt Source (or IVSE)
726 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
728 assert(srcno
< xsrc
->nr_irqs
);
730 return xsrc
->status
[srcno
] & 0x3;
733 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
735 assert(srcno
< xsrc
->nr_irqs
);
737 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
741 * Returns whether the event notification should be forwarded.
743 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
745 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
747 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
751 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
759 * Returns whether the event notification should be forwarded.
761 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
765 assert(srcno
< xsrc
->nr_irqs
);
767 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
769 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
770 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
771 qemu_log_mask(LOG_GUEST_ERROR
,
772 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
779 * Returns whether the event notification should be forwarded.
781 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
785 assert(srcno
< xsrc
->nr_irqs
);
787 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
790 * LSI sources do not set the Q bit but they can still be
791 * asserted, in which case we should forward a new event
794 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
795 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
796 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
803 * Forward the source event notification to the Router
805 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
807 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
810 xnc
->notify(xsrc
->xive
, srcno
);
815 * In a two pages ESB MMIO setting, even page is the trigger page, odd
816 * page is for management
818 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
820 return !((addr
>> shift
) & 1);
823 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
825 return xive_source_esb_has_2page(xsrc
) &&
826 addr_is_even(addr
, xsrc
->esb_shift
- 1);
831 * Trigger page Management/EOI page
833 * ESB MMIO setting 2 pages 1 or 2 pages
835 * 0x000 .. 0x3FF -1 EOI and return 0|1
836 * 0x400 .. 0x7FF -1 EOI and return 0|1
837 * 0x800 .. 0xBFF -1 return PQ
838 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
839 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
840 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
841 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
843 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
845 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
846 uint32_t offset
= addr
& 0xFFF;
847 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
850 /* In a two pages ESB MMIO setting, trigger page should not be read */
851 if (xive_source_is_trigger_page(xsrc
, addr
)) {
852 qemu_log_mask(LOG_GUEST_ERROR
,
853 "XIVE: invalid load on IRQ %d trigger page at "
854 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
859 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
860 ret
= xive_source_esb_eoi(xsrc
, srcno
);
862 /* Forward the source event notification for routing */
864 xive_source_notify(xsrc
, srcno
);
868 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
869 ret
= xive_source_esb_get(xsrc
, srcno
);
872 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
873 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
874 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
875 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
876 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
879 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
888 * Trigger page Management/EOI page
890 * ESB MMIO setting 2 pages 1 or 2 pages
892 * 0x000 .. 0x3FF Trigger Trigger
893 * 0x400 .. 0x7FF Trigger EOI
894 * 0x800 .. 0xBFF Trigger undefined
895 * 0xC00 .. 0xCFF Trigger PQ=00
896 * 0xD00 .. 0xDFF Trigger PQ=01
897 * 0xE00 .. 0xDFF Trigger PQ=10
898 * 0xF00 .. 0xDFF Trigger PQ=11
900 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
901 uint64_t value
, unsigned size
)
903 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
904 uint32_t offset
= addr
& 0xFFF;
905 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
908 /* In a two pages ESB MMIO setting, trigger page only triggers */
909 if (xive_source_is_trigger_page(xsrc
, addr
)) {
910 notify
= xive_source_esb_trigger(xsrc
, srcno
);
916 notify
= xive_source_esb_trigger(xsrc
, srcno
);
919 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
920 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
921 qemu_log_mask(LOG_GUEST_ERROR
,
922 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
926 notify
= xive_source_esb_eoi(xsrc
, srcno
);
929 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
930 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
931 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
932 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
933 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
937 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
943 /* Forward the source event notification for routing */
945 xive_source_notify(xsrc
, srcno
);
949 static const MemoryRegionOps xive_source_esb_ops
= {
950 .read
= xive_source_esb_read
,
951 .write
= xive_source_esb_write
,
952 .endianness
= DEVICE_BIG_ENDIAN
,
954 .min_access_size
= 8,
955 .max_access_size
= 8,
958 .min_access_size
= 8,
959 .max_access_size
= 8,
963 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
965 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
968 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
970 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
972 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
976 notify
= xive_source_esb_trigger(xsrc
, srcno
);
980 /* Forward the source event notification for routing */
982 xive_source_notify(xsrc
, srcno
);
986 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
990 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
991 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
993 if (pq
== XIVE_ESB_OFF
) {
997 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
998 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
999 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1000 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1001 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
1005 static void xive_source_reset(void *dev
)
1007 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1009 /* Do not clear the LSI bitmap */
1011 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
1012 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
1015 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1017 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1019 Error
*local_err
= NULL
;
1021 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1023 error_propagate(errp
, local_err
);
1024 error_prepend(errp
, "required link 'xive' not found: ");
1028 xsrc
->xive
= XIVE_NOTIFIER(obj
);
1030 if (!xsrc
->nr_irqs
) {
1031 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1035 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1036 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1037 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1038 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1039 error_setg(errp
, "Invalid ESB shift setting");
1043 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1044 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1046 if (!kvm_irqchip_in_kernel()) {
1047 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1048 &xive_source_esb_ops
, xsrc
, "xive.esb",
1049 (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
);
1052 qemu_register_reset(xive_source_reset
, dev
);
1055 static const VMStateDescription vmstate_xive_source
= {
1056 .name
= TYPE_XIVE_SOURCE
,
1058 .minimum_version_id
= 1,
1059 .fields
= (VMStateField
[]) {
1060 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1061 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1062 VMSTATE_END_OF_LIST()
1067 * The default XIVE interrupt source setting for the ESB MMIOs is two
1068 * 64k pages without Store EOI, to be in sync with KVM.
1070 static Property xive_source_properties
[] = {
1071 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1072 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1073 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1074 DEFINE_PROP_END_OF_LIST(),
1077 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1079 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1081 dc
->desc
= "XIVE Interrupt Source";
1082 dc
->props
= xive_source_properties
;
1083 dc
->realize
= xive_source_realize
;
1084 dc
->vmsd
= &vmstate_xive_source
;
1087 static const TypeInfo xive_source_info
= {
1088 .name
= TYPE_XIVE_SOURCE
,
1089 .parent
= TYPE_DEVICE
,
1090 .instance_size
= sizeof(XiveSource
),
1091 .class_init
= xive_source_class_init
,
1098 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1100 uint64_t qaddr_base
= xive_end_qaddr(end
);
1101 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1102 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1103 uint32_t qentries
= 1 << (qsize
+ 10);
1107 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1109 monitor_printf(mon
, " [ ");
1110 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1111 for (i
= 0; i
< width
; i
++) {
1112 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1113 uint32_t qdata
= -1;
1115 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
1117 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1118 HWADDR_PRIx
"\n", qaddr
);
1121 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1122 be32_to_cpu(qdata
));
1123 qindex
= (qindex
+ 1) & (qentries
- 1);
1127 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1129 uint64_t qaddr_base
= xive_end_qaddr(end
);
1130 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1131 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1132 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1133 uint32_t qentries
= 1 << (qsize
+ 10);
1135 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1136 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1138 if (!xive_end_is_valid(end
)) {
1142 monitor_printf(mon
, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64
1143 "% 6d/%5d ^%d", end_idx
,
1144 xive_end_is_valid(end
) ? 'v' : '-',
1145 xive_end_is_enqueue(end
) ? 'q' : '-',
1146 xive_end_is_notify(end
) ? 'n' : '-',
1147 xive_end_is_backlog(end
) ? 'b' : '-',
1148 xive_end_is_escalate(end
) ? 'e' : '-',
1149 priority
, nvt
, qaddr_base
, qindex
, qentries
, qgen
);
1151 xive_end_queue_pic_print_info(end
, 6, mon
);
1152 monitor_printf(mon
, "]\n");
1155 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1157 uint64_t qaddr_base
= xive_end_qaddr(end
);
1158 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1159 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1160 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1162 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1163 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1164 uint32_t qentries
= 1 << (qsize
+ 10);
1166 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
1167 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1168 HWADDR_PRIx
"\n", qaddr
);
1172 qindex
= (qindex
+ 1) & (qentries
- 1);
1175 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1177 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1181 * XIVE Router (aka. Virtualization Controller or IVRE)
1184 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1187 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1189 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1192 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1195 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1197 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1200 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1201 XiveEND
*end
, uint8_t word_number
)
1203 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1205 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1208 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1211 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1213 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1216 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1217 XiveNVT
*nvt
, uint8_t word_number
)
1219 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1221 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1224 XiveTCTX
*xive_router_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
1226 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1228 return xrc
->get_tctx(xrtr
, cs
);
1232 * Encode the HW CAM line in the block group mode format :
1234 * chip << 19 | 0000000 0 0001 thread (7Bit)
1236 static uint32_t xive_tctx_hw_cam_line(XiveTCTX
*tctx
)
1238 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1239 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1241 return xive_nvt_cam_line((pir
>> 8) & 0xf, 1 << 7 | (pir
& 0x7f));
1245 * The thread context register words are in big-endian format.
1247 static int xive_presenter_tctx_match(XiveTCTX
*tctx
, uint8_t format
,
1248 uint8_t nvt_blk
, uint32_t nvt_idx
,
1249 bool cam_ignore
, uint32_t logic_serv
)
1251 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1252 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1253 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1254 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1255 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1258 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1259 * identifier are ignored in the "CAM" match.
1263 if (cam_ignore
== true) {
1265 * F=0 & i=1: Logical server notification (bits ignored at
1266 * the end of the NVT identifier)
1268 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1273 /* F=0 & i=0: Specific NVT notification */
1276 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1277 cam
== xive_tctx_hw_cam_line(tctx
)) {
1278 return TM_QW3_HV_PHYS
;
1282 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1283 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1284 return TM_QW2_HV_POOL
;
1288 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1289 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1293 /* F=1 : User level Event-Based Branch (EBB) notification */
1296 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1297 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1298 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1299 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1306 typedef struct XiveTCTXMatch
{
1311 static bool xive_presenter_match(XiveRouter
*xrtr
, uint8_t format
,
1312 uint8_t nvt_blk
, uint32_t nvt_idx
,
1313 bool cam_ignore
, uint8_t priority
,
1314 uint32_t logic_serv
, XiveTCTXMatch
*match
)
1319 * TODO (PowerNV): handle chip_id overwrite of block field for
1320 * hardwired CAM compares
1324 XiveTCTX
*tctx
= xive_router_get_tctx(xrtr
, cs
);
1328 * HW checks that the CPU is enabled in the Physical Thread
1329 * Enable Register (PTER).
1333 * Check the thread context CAM lines and record matches. We
1334 * will handle CPU exception delivery later
1336 ring
= xive_presenter_tctx_match(tctx
, format
, nvt_blk
, nvt_idx
,
1337 cam_ignore
, logic_serv
);
1339 * Save the context and follow on to catch duplicates, that we
1340 * don't support yet.
1344 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
1345 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
1355 qemu_log_mask(LOG_UNIMP
, "XIVE: NVT %x/%x is not dispatched\n",
1364 * This is our simple Xive Presenter Engine model. It is merged in the
1365 * Router as it does not require an extra object.
1367 * It receives notification requests sent by the IVRE to find one
1368 * matching NVT (or more) dispatched on the processor threads. In case
1369 * of a single NVT notification, the process is abreviated and the
1370 * thread is signaled if a match is found. In case of a logical server
1371 * notification (bits ignored at the end of the NVT identifier), the
1372 * IVPE and IVRE select a winning thread using different filters. This
1373 * involves 2 or 3 exchanges on the PowerBus that the model does not
1376 * The parameters represent what is sent on the PowerBus
1378 static void xive_presenter_notify(XiveRouter
*xrtr
, uint8_t format
,
1379 uint8_t nvt_blk
, uint32_t nvt_idx
,
1380 bool cam_ignore
, uint8_t priority
,
1381 uint32_t logic_serv
)
1384 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1387 /* NVT cache lookup */
1388 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1389 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1394 if (!xive_nvt_is_valid(&nvt
)) {
1395 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1400 found
= xive_presenter_match(xrtr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1401 priority
, logic_serv
, &match
);
1403 ipb_update(&match
.tctx
->regs
[match
.ring
], priority
);
1404 xive_tctx_notify(match
.tctx
, match
.ring
);
1408 /* Record the IPB in the associated NVT structure */
1409 ipb_update((uint8_t *) &nvt
.w4
, priority
);
1410 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1413 * If no matching NVT is dispatched on a HW thread :
1414 * - update the NVT structure if backlog is activated
1415 * - escalate (ESe PQ bits and EAS in w4-5) if escalation is
1421 * An END trigger can come from an event trigger (IPI or HW) or from
1422 * another chip. We don't model the PowerBus but the END trigger
1423 * message has the same parameters than in the function below.
1425 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1426 uint32_t end_idx
, uint32_t end_data
)
1432 /* END cache lookup */
1433 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1434 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1439 if (!xive_end_is_valid(&end
)) {
1440 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1445 if (xive_end_is_enqueue(&end
)) {
1446 xive_end_enqueue(&end
, end_data
);
1447 /* Enqueuing event data modifies the EQ toggle and index */
1448 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1452 * The W7 format depends on the F bit in W6. It defines the type
1453 * of the notification :
1455 * F=0 : single or multiple NVT notification
1456 * F=1 : User level Event-Based Branch (EBB) notification, no
1459 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1460 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1462 /* The END is masked */
1463 if (format
== 0 && priority
== 0xff) {
1468 * Check the END ESn (Event State Buffer for notification) for
1469 * even futher coalescing in the Router
1471 if (!xive_end_is_notify(&end
)) {
1472 uint8_t pq
= xive_get_field32(END_W1_ESn
, end
.w1
);
1473 bool notify
= xive_esb_trigger(&pq
);
1475 if (pq
!= xive_get_field32(END_W1_ESn
, end
.w1
)) {
1476 end
.w1
= xive_set_field32(END_W1_ESn
, end
.w1
, pq
);
1477 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1480 /* ESn[Q]=1 : end of notification */
1487 * Follows IVPE notification
1489 xive_presenter_notify(xrtr
, format
,
1490 xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
),
1491 xive_get_field32(END_W6_NVT_INDEX
, end
.w6
),
1492 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1494 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1496 /* TODO: Auto EOI. */
1499 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
1501 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1502 uint8_t eas_blk
= XIVE_SRCNO_BLOCK(lisn
);
1503 uint32_t eas_idx
= XIVE_SRCNO_INDEX(lisn
);
1506 /* EAS cache lookup */
1507 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1508 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1513 * The IVRE checks the State Bit Cache at this point. We skip the
1514 * SBC lookup because the state bits of the sources are modeled
1515 * internally in QEMU.
1518 if (!xive_eas_is_valid(&eas
)) {
1519 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1523 if (xive_eas_is_masked(&eas
)) {
1524 /* Notification completed */
1529 * The event trigger becomes an END trigger
1531 xive_router_end_notify(xrtr
,
1532 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1533 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1534 xive_get_field64(EAS_END_DATA
, eas
.w
));
1537 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1539 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1540 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1542 dc
->desc
= "XIVE Router Engine";
1543 xnc
->notify
= xive_router_notify
;
1546 static const TypeInfo xive_router_info
= {
1547 .name
= TYPE_XIVE_ROUTER
,
1548 .parent
= TYPE_SYS_BUS_DEVICE
,
1550 .class_size
= sizeof(XiveRouterClass
),
1551 .class_init
= xive_router_class_init
,
1552 .interfaces
= (InterfaceInfo
[]) {
1553 { TYPE_XIVE_NOTIFIER
},
1558 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1560 if (!xive_eas_is_valid(eas
)) {
1564 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1565 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1566 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1567 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1568 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1572 * END ESB MMIO loads
1574 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1576 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1577 uint32_t offset
= addr
& 0xFFF;
1581 uint32_t end_esmask
;
1585 end_blk
= xsrc
->block_id
;
1586 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1588 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1589 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1594 if (!xive_end_is_valid(&end
)) {
1595 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1600 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1601 pq
= xive_get_field32(end_esmask
, end
.w1
);
1604 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1605 ret
= xive_esb_eoi(&pq
);
1607 /* Forward the source event notification for routing ?? */
1610 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1614 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1615 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1616 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1617 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1618 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1621 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1626 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1627 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1628 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1635 * END ESB MMIO stores are invalid
1637 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1638 uint64_t value
, unsigned size
)
1640 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1641 HWADDR_PRIx
"\n", addr
);
1644 static const MemoryRegionOps xive_end_source_ops
= {
1645 .read
= xive_end_source_read
,
1646 .write
= xive_end_source_write
,
1647 .endianness
= DEVICE_BIG_ENDIAN
,
1649 .min_access_size
= 8,
1650 .max_access_size
= 8,
1653 .min_access_size
= 8,
1654 .max_access_size
= 8,
1658 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1660 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1662 Error
*local_err
= NULL
;
1664 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1666 error_propagate(errp
, local_err
);
1667 error_prepend(errp
, "required link 'xive' not found: ");
1671 xsrc
->xrtr
= XIVE_ROUTER(obj
);
1673 if (!xsrc
->nr_ends
) {
1674 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1678 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1679 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1680 error_setg(errp
, "Invalid ESB shift setting");
1685 * Each END is assigned an even/odd pair of MMIO pages, the even page
1686 * manages the ESn field while the odd page manages the ESe field.
1688 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1689 &xive_end_source_ops
, xsrc
, "xive.end",
1690 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1693 static Property xive_end_source_properties
[] = {
1694 DEFINE_PROP_UINT8("block-id", XiveENDSource
, block_id
, 0),
1695 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1696 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1697 DEFINE_PROP_END_OF_LIST(),
1700 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1702 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1704 dc
->desc
= "XIVE END Source";
1705 dc
->props
= xive_end_source_properties
;
1706 dc
->realize
= xive_end_source_realize
;
1709 static const TypeInfo xive_end_source_info
= {
1710 .name
= TYPE_XIVE_END_SOURCE
,
1711 .parent
= TYPE_DEVICE
,
1712 .instance_size
= sizeof(XiveENDSource
),
1713 .class_init
= xive_end_source_class_init
,
1719 static const TypeInfo xive_notifier_info
= {
1720 .name
= TYPE_XIVE_NOTIFIER
,
1721 .parent
= TYPE_INTERFACE
,
1722 .class_size
= sizeof(XiveNotifierClass
),
1725 static void xive_register_types(void)
1727 type_register_static(&xive_source_info
);
1728 type_register_static(&xive_notifier_info
);
1729 type_register_static(&xive_router_info
);
1730 type_register_static(&xive_end_source_info
);
1731 type_register_static(&xive_tctx_info
);
1734 type_init(xive_register_types
)