include/hw/ppc/pnv_lpc.h

   1 /*
   2  * QEMU PowerPC PowerNV LPC controller
   3  *
   4  * Copyright (c) 2016, IBM Corporation.
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef _PPC_PNV_LPC_H
  20 #define _PPC_PNV_LPC_H
  21
  22 #include "hw/ppc/pnv_psi.h"
  23
  24 #define TYPE_PNV_LPC "pnv-lpc"
  25 #define PNV_LPC(obj) \
  26      OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV_LPC)
  27 #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
  28 #define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC)
  29
  30 typedef struct PnvLpcController {
  31     DeviceState parent;
  32
  33     uint64_t eccb_stat_reg;
  34     uint32_t eccb_data_reg;
  35
  36     /* OPB bus */
  37     MemoryRegion opb_mr;
  38     AddressSpace opb_as;
  39
  40     /* ISA IO and Memory space */
  41     MemoryRegion isa_io;
  42     MemoryRegion isa_mem;
  43     MemoryRegion isa_fw;
  44
  45     /* Windows from OPB to ISA (aliases) */
  46     MemoryRegion opb_isa_io;
  47     MemoryRegion opb_isa_mem;
  48     MemoryRegion opb_isa_fw;
  49
  50     /* Registers */
  51     MemoryRegion lpc_hc_regs;
  52     MemoryRegion opb_master_regs;
  53
  54     /* OPB Master LS registers */
  55     uint32_t opb_irq_stat;
  56     uint32_t opb_irq_mask;
  57     uint32_t opb_irq_pol;
  58     uint32_t opb_irq_input;
  59
  60     /* LPC HC registers */
  61     uint32_t lpc_hc_fw_seg_idsel;
  62     uint32_t lpc_hc_fw_rd_acc_size;
  63     uint32_t lpc_hc_irqser_ctrl;
  64     uint32_t lpc_hc_irqmask;
  65     uint32_t lpc_hc_irqstat;
  66     uint32_t lpc_hc_error_addr;
  67
  68     /* XSCOM registers */
  69     MemoryRegion xscom_regs;
  70
  71     /* PSI to generate interrupts */
  72     PnvPsi *psi;
  73 } PnvLpcController;
  74
  75 #define PNV_LPC_CLASS(klass) \
  76      OBJECT_CLASS_CHECK(PnvLpcClass, (klass), TYPE_PNV_LPC)
  77 #define PNV_LPC_GET_CLASS(obj) \
  78      OBJECT_GET_CLASS(PnvLpcClass, (obj), TYPE_PNV_LPC)
  79
  80 typedef struct PnvLpcClass {
  81     DeviceClass parent_class;
  82
  83     int psi_irq;
  84
  85     DeviceRealize parent_realize;
  86 } PnvLpcClass;
  87
  88 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
  89
  90 #endif /* _PPC_PNV_LPC_H */