1 #include "qemu/osdep.h"
5 #include "exec/gdbstub.h"
6 #include "exec/helper-proto.h"
7 #include "qemu/host-utils.h"
8 #include "sysemu/arch_init.h"
9 #include "sysemu/sysemu.h"
10 #include "qemu/bitops.h"
11 #include "qemu/crc32c.h"
12 #include "exec/exec-all.h"
13 #include "exec/cpu_ldst.h"
15 #include <zlib.h> /* For crc32 */
16 #include "exec/semihost.h"
17 #include "sysemu/kvm.h"
19 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
21 #ifndef CONFIG_USER_ONLY
22 /* Cacheability and shareability attributes for a memory access */
23 typedef struct ARMCacheAttrs
{
24 unsigned int attrs
:8; /* as in the MAIR register encoding */
25 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
28 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
29 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
30 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
31 target_ulong
*page_size
,
32 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
34 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
35 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
36 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
37 target_ulong
*page_size_ptr
,
38 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
);
40 /* Security attributes for an address, as returned by v8m_security_lookup. */
41 typedef struct V8M_SAttributes
{
50 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
51 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
52 V8M_SAttributes
*sattrs
);
54 /* Definitions for the PMCCNTR and PMCR registers */
60 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
64 /* VFP data registers are always little-endian. */
65 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
67 stq_le_p(buf
, *aa32_vfp_dreg(env
, reg
));
70 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
71 /* Aliases for Q regs. */
74 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
76 stq_le_p(buf
+ 8, q
[1]);
80 switch (reg
- nregs
) {
81 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
82 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
83 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
88 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
92 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
94 *aa32_vfp_dreg(env
, reg
) = ldq_le_p(buf
);
97 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
100 uint64_t *q
= aa32_vfp_qreg(env
, reg
- 32);
101 q
[0] = ldq_le_p(buf
);
102 q
[1] = ldq_le_p(buf
+ 8);
106 switch (reg
- nregs
) {
107 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
108 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
109 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
114 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
118 /* 128 bit FP register */
120 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
122 stq_le_p(buf
+ 8, q
[1]);
127 stl_p(buf
, vfp_get_fpsr(env
));
131 stl_p(buf
, vfp_get_fpcr(env
));
138 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
142 /* 128 bit FP register */
144 uint64_t *q
= aa64_vfp_qreg(env
, reg
);
145 q
[0] = ldq_le_p(buf
);
146 q
[1] = ldq_le_p(buf
+ 8);
151 vfp_set_fpsr(env
, ldl_p(buf
));
155 vfp_set_fpcr(env
, ldl_p(buf
));
162 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
164 assert(ri
->fieldoffset
);
165 if (cpreg_field_is_64bit(ri
)) {
166 return CPREG_FIELD64(env
, ri
);
168 return CPREG_FIELD32(env
, ri
);
172 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
175 assert(ri
->fieldoffset
);
176 if (cpreg_field_is_64bit(ri
)) {
177 CPREG_FIELD64(env
, ri
) = value
;
179 CPREG_FIELD32(env
, ri
) = value
;
183 static void *raw_ptr(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
185 return (char *)env
+ ri
->fieldoffset
;
188 uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
190 /* Raw read of a coprocessor register (as needed for migration, etc). */
191 if (ri
->type
& ARM_CP_CONST
) {
192 return ri
->resetvalue
;
193 } else if (ri
->raw_readfn
) {
194 return ri
->raw_readfn(env
, ri
);
195 } else if (ri
->readfn
) {
196 return ri
->readfn(env
, ri
);
198 return raw_read(env
, ri
);
202 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
205 /* Raw write of a coprocessor register (as needed for migration, etc).
206 * Note that constant registers are treated as write-ignored; the
207 * caller should check for success by whether a readback gives the
210 if (ri
->type
& ARM_CP_CONST
) {
212 } else if (ri
->raw_writefn
) {
213 ri
->raw_writefn(env
, ri
, v
);
214 } else if (ri
->writefn
) {
215 ri
->writefn(env
, ri
, v
);
217 raw_write(env
, ri
, v
);
221 static bool raw_accessors_invalid(const ARMCPRegInfo
*ri
)
223 /* Return true if the regdef would cause an assertion if you called
224 * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
225 * program bug for it not to have the NO_RAW flag).
226 * NB that returning false here doesn't necessarily mean that calling
227 * read/write_raw_cp_reg() is safe, because we can't distinguish "has
228 * read/write access functions which are safe for raw use" from "has
229 * read/write access functions which have side effects but has forgotten
230 * to provide raw access functions".
231 * The tests here line up with the conditions in read/write_raw_cp_reg()
232 * and assertions in raw_read()/raw_write().
234 if ((ri
->type
& ARM_CP_CONST
) ||
236 ((ri
->raw_writefn
|| ri
->writefn
) && (ri
->raw_readfn
|| ri
->readfn
))) {
242 bool write_cpustate_to_list(ARMCPU
*cpu
)
244 /* Write the coprocessor state from cpu->env to the (index,value) list. */
248 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
249 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
250 const ARMCPRegInfo
*ri
;
252 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
257 if (ri
->type
& ARM_CP_NO_RAW
) {
260 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
265 bool write_list_to_cpustate(ARMCPU
*cpu
)
270 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
271 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
272 uint64_t v
= cpu
->cpreg_values
[i
];
273 const ARMCPRegInfo
*ri
;
275 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
280 if (ri
->type
& ARM_CP_NO_RAW
) {
283 /* Write value and confirm it reads back as written
284 * (to catch read-only registers and partially read-only
285 * registers where the incoming migration value doesn't match)
287 write_raw_cp_reg(&cpu
->env
, ri
, v
);
288 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
295 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
297 ARMCPU
*cpu
= opaque
;
299 const ARMCPRegInfo
*ri
;
301 regidx
= *(uint32_t *)key
;
302 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
304 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
305 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
306 /* The value array need not be initialized at this point */
307 cpu
->cpreg_array_len
++;
311 static void count_cpreg(gpointer key
, gpointer opaque
)
313 ARMCPU
*cpu
= opaque
;
315 const ARMCPRegInfo
*ri
;
317 regidx
= *(uint32_t *)key
;
318 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
320 if (!(ri
->type
& (ARM_CP_NO_RAW
|ARM_CP_ALIAS
))) {
321 cpu
->cpreg_array_len
++;
325 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
327 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
328 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
339 void init_cpreg_list(ARMCPU
*cpu
)
341 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
342 * Note that we require cpreg_tuples[] to be sorted by key ID.
347 keys
= g_hash_table_get_keys(cpu
->cp_regs
);
348 keys
= g_list_sort(keys
, cpreg_key_compare
);
350 cpu
->cpreg_array_len
= 0;
352 g_list_foreach(keys
, count_cpreg
, cpu
);
354 arraylen
= cpu
->cpreg_array_len
;
355 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
356 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
357 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
358 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
359 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
360 cpu
->cpreg_array_len
= 0;
362 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
364 assert(cpu
->cpreg_array_len
== arraylen
);
370 * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
371 * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
373 * access_el3_aa32ns: Used to check AArch32 register views.
374 * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
376 static CPAccessResult
access_el3_aa32ns(CPUARMState
*env
,
377 const ARMCPRegInfo
*ri
,
380 bool secure
= arm_is_secure_below_el3(env
);
382 assert(!arm_el_is_aa64(env
, 3));
384 return CP_ACCESS_TRAP_UNCATEGORIZED
;
389 static CPAccessResult
access_el3_aa32ns_aa64any(CPUARMState
*env
,
390 const ARMCPRegInfo
*ri
,
393 if (!arm_el_is_aa64(env
, 3)) {
394 return access_el3_aa32ns(env
, ri
, isread
);
399 /* Some secure-only AArch32 registers trap to EL3 if used from
400 * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
401 * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
402 * We assume that the .access field is set to PL1_RW.
404 static CPAccessResult
access_trap_aa32s_el1(CPUARMState
*env
,
405 const ARMCPRegInfo
*ri
,
408 if (arm_current_el(env
) == 3) {
411 if (arm_is_secure_below_el3(env
)) {
412 return CP_ACCESS_TRAP_EL3
;
414 /* This will be EL1 NS and EL2 NS, which just UNDEF */
415 return CP_ACCESS_TRAP_UNCATEGORIZED
;
418 /* Check for traps to "powerdown debug" registers, which are controlled
421 static CPAccessResult
access_tdosa(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
424 int el
= arm_current_el(env
);
426 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDOSA
)
427 && !arm_is_secure_below_el3(env
)) {
428 return CP_ACCESS_TRAP_EL2
;
430 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDOSA
)) {
431 return CP_ACCESS_TRAP_EL3
;
436 /* Check for traps to "debug ROM" registers, which are controlled
437 * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
439 static CPAccessResult
access_tdra(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
442 int el
= arm_current_el(env
);
444 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDRA
)
445 && !arm_is_secure_below_el3(env
)) {
446 return CP_ACCESS_TRAP_EL2
;
448 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
449 return CP_ACCESS_TRAP_EL3
;
454 /* Check for traps to general debug registers, which are controlled
455 * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
457 static CPAccessResult
access_tda(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
460 int el
= arm_current_el(env
);
462 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TDA
)
463 && !arm_is_secure_below_el3(env
)) {
464 return CP_ACCESS_TRAP_EL2
;
466 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TDA
)) {
467 return CP_ACCESS_TRAP_EL3
;
472 /* Check for traps to performance monitor registers, which are controlled
473 * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
475 static CPAccessResult
access_tpm(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
478 int el
= arm_current_el(env
);
480 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
481 && !arm_is_secure_below_el3(env
)) {
482 return CP_ACCESS_TRAP_EL2
;
484 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
485 return CP_ACCESS_TRAP_EL3
;
490 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
492 ARMCPU
*cpu
= arm_env_get_cpu(env
);
494 raw_write(env
, ri
, value
);
495 tlb_flush(CPU(cpu
)); /* Flush TLB as domain not tracked in TLB */
498 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
500 ARMCPU
*cpu
= arm_env_get_cpu(env
);
502 if (raw_read(env
, ri
) != value
) {
503 /* Unlike real hardware the qemu TLB uses virtual addresses,
504 * not modified virtual addresses, so this causes a TLB flush.
507 raw_write(env
, ri
, value
);
511 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
514 ARMCPU
*cpu
= arm_env_get_cpu(env
);
516 if (raw_read(env
, ri
) != value
&& !arm_feature(env
, ARM_FEATURE_PMSA
)
517 && !extended_addresses_enabled(env
)) {
518 /* For VMSA (when not using the LPAE long descriptor page table
519 * format) this register includes the ASID, so do a TLB flush.
520 * For PMSA it is purely a process ID and no action is needed.
524 raw_write(env
, ri
, value
);
527 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
530 /* Invalidate all (TLBIALL) */
531 ARMCPU
*cpu
= arm_env_get_cpu(env
);
536 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
539 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
540 ARMCPU
*cpu
= arm_env_get_cpu(env
);
542 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
545 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
548 /* Invalidate by ASID (TLBIASID) */
549 ARMCPU
*cpu
= arm_env_get_cpu(env
);
554 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
557 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
558 ARMCPU
*cpu
= arm_env_get_cpu(env
);
560 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
563 /* IS variants of TLB operations must affect all cores */
564 static void tlbiall_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
567 CPUState
*cs
= ENV_GET_CPU(env
);
569 tlb_flush_all_cpus_synced(cs
);
572 static void tlbiasid_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
575 CPUState
*cs
= ENV_GET_CPU(env
);
577 tlb_flush_all_cpus_synced(cs
);
580 static void tlbimva_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
583 CPUState
*cs
= ENV_GET_CPU(env
);
585 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
588 static void tlbimvaa_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
591 CPUState
*cs
= ENV_GET_CPU(env
);
593 tlb_flush_page_all_cpus_synced(cs
, value
& TARGET_PAGE_MASK
);
596 static void tlbiall_nsnh_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
599 CPUState
*cs
= ENV_GET_CPU(env
);
601 tlb_flush_by_mmuidx(cs
,
602 ARMMMUIdxBit_S12NSE1
|
603 ARMMMUIdxBit_S12NSE0
|
607 static void tlbiall_nsnh_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
610 CPUState
*cs
= ENV_GET_CPU(env
);
612 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
613 ARMMMUIdxBit_S12NSE1
|
614 ARMMMUIdxBit_S12NSE0
|
618 static void tlbiipas2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
621 /* Invalidate by IPA. This has to invalidate any structures that
622 * contain only stage 2 translation information, but does not need
623 * to apply to structures that contain combined stage 1 and stage 2
624 * translation information.
625 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
627 CPUState
*cs
= ENV_GET_CPU(env
);
630 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
634 pageaddr
= sextract64(value
<< 12, 0, 40);
636 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
639 static void tlbiipas2_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
642 CPUState
*cs
= ENV_GET_CPU(env
);
645 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
649 pageaddr
= sextract64(value
<< 12, 0, 40);
651 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
655 static void tlbiall_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
658 CPUState
*cs
= ENV_GET_CPU(env
);
660 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
663 static void tlbiall_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
666 CPUState
*cs
= ENV_GET_CPU(env
);
668 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
671 static void tlbimva_hyp_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
674 CPUState
*cs
= ENV_GET_CPU(env
);
675 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
677 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
680 static void tlbimva_hyp_is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
683 CPUState
*cs
= ENV_GET_CPU(env
);
684 uint64_t pageaddr
= value
& ~MAKE_64BIT_MASK(0, 12);
686 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
690 static const ARMCPRegInfo cp_reginfo
[] = {
691 /* Define the secure and non-secure FCSE identifier CP registers
692 * separately because there is no secure bank in V8 (no _EL3). This allows
693 * the secure register to be properly reset and migrated. There is also no
694 * v8 EL1 version of the register so the non-secure instance stands alone.
696 { .name
= "FCSEIDR(NS)",
697 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
698 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
699 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_ns
),
700 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
701 { .name
= "FCSEIDR(S)",
702 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 0,
703 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
704 .fieldoffset
= offsetof(CPUARMState
, cp15
.fcseidr_s
),
705 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
706 /* Define the secure and non-secure context identifier CP registers
707 * separately because there is no secure bank in V8 (no _EL3). This allows
708 * the secure register to be properly reset and migrated. In the
709 * non-secure case, the 32-bit register will have reset and migration
710 * disabled during registration as it is handled by the 64-bit instance.
712 { .name
= "CONTEXTIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
713 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
714 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_NS
,
715 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el
[1]),
716 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
717 { .name
= "CONTEXTIDR(S)", .state
= ARM_CP_STATE_AA32
,
718 .cp
= 15, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
719 .access
= PL1_RW
, .secure
= ARM_CP_SECSTATE_S
,
720 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_s
),
721 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
725 static const ARMCPRegInfo not_v8_cp_reginfo
[] = {
726 /* NB: Some of these registers exist in v8 but with more precise
727 * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
729 /* MMU Domain access control / MPU write buffer control */
731 .cp
= 15, .opc1
= CP_ANY
, .crn
= 3, .crm
= CP_ANY
, .opc2
= CP_ANY
,
732 .access
= PL1_RW
, .resetvalue
= 0,
733 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
734 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
735 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
736 /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
737 * For v6 and v5, these mappings are overly broad.
739 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 0,
740 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
741 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 1,
742 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
743 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 4,
744 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
745 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= 8,
746 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
747 /* Cache maintenance ops; some of this space may be overridden later. */
748 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
749 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
750 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
754 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
755 /* Not all pre-v6 cores implemented this WFI, so this is slightly
758 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
759 .access
= PL1_W
, .type
= ARM_CP_WFI
},
763 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
764 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
765 * is UNPREDICTABLE; we choose to NOP as most implementations do).
767 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
768 .access
= PL1_W
, .type
= ARM_CP_WFI
},
769 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
770 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
771 * OMAPCP will override this space.
773 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
774 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
776 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
777 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
779 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
780 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
781 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
783 /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
784 * implementing it as RAZ means the "debug architecture version" bits
785 * will read as a reserved value, which should cause Linux to not try
786 * to use the debug hardware.
788 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
789 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
790 /* MMU TLB control. Note that the wildcarding means we cover not just
791 * the unified TLB ops but also the dside/iside/inner-shareable variants.
793 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
794 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
795 .type
= ARM_CP_NO_RAW
},
796 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
797 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
798 .type
= ARM_CP_NO_RAW
},
799 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
800 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
801 .type
= ARM_CP_NO_RAW
},
802 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
803 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
804 .type
= ARM_CP_NO_RAW
},
805 { .name
= "PRRR", .cp
= 15, .crn
= 10, .crm
= 2,
806 .opc1
= 0, .opc2
= 0, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
807 { .name
= "NMRR", .cp
= 15, .crn
= 10, .crm
= 2,
808 .opc1
= 0, .opc2
= 1, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
812 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
817 /* In ARMv8 most bits of CPACR_EL1 are RES0. */
818 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
819 /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
820 * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
821 * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
823 if (arm_feature(env
, ARM_FEATURE_VFP
)) {
824 /* VFP coprocessor: cp10 & cp11 [23:20] */
825 mask
|= (1 << 31) | (1 << 30) | (0xf << 20);
827 if (!arm_feature(env
, ARM_FEATURE_NEON
)) {
828 /* ASEDIS [31] bit is RAO/WI */
832 /* VFPv3 and upwards with NEON implement 32 double precision
833 * registers (D0-D31).
835 if (!arm_feature(env
, ARM_FEATURE_NEON
) ||
836 !arm_feature(env
, ARM_FEATURE_VFP3
)) {
837 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
843 env
->cp15
.cpacr_el1
= value
;
846 static CPAccessResult
cpacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
849 if (arm_feature(env
, ARM_FEATURE_V8
)) {
850 /* Check if CPACR accesses are to be trapped to EL2 */
851 if (arm_current_el(env
) == 1 &&
852 (env
->cp15
.cptr_el
[2] & CPTR_TCPAC
) && !arm_is_secure(env
)) {
853 return CP_ACCESS_TRAP_EL2
;
854 /* Check if CPACR accesses are to be trapped to EL3 */
855 } else if (arm_current_el(env
) < 3 &&
856 (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
857 return CP_ACCESS_TRAP_EL3
;
864 static CPAccessResult
cptr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
867 /* Check if CPTR accesses are set to trap to EL3 */
868 if (arm_current_el(env
) == 2 && (env
->cp15
.cptr_el
[3] & CPTR_TCPAC
)) {
869 return CP_ACCESS_TRAP_EL3
;
875 static const ARMCPRegInfo v6_cp_reginfo
[] = {
876 /* prefetch by MVA in v6, NOP in v7 */
877 { .name
= "MVA_prefetch",
878 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
879 .access
= PL1_W
, .type
= ARM_CP_NOP
},
880 /* We need to break the TB after ISB to execute self-modifying code
881 * correctly and also to take any pending interrupts immediately.
882 * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
884 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
885 .access
= PL0_W
, .type
= ARM_CP_NO_RAW
, .writefn
= arm_cp_write_ignore
},
886 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
887 .access
= PL0_W
, .type
= ARM_CP_NOP
},
888 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
889 .access
= PL0_W
, .type
= ARM_CP_NOP
},
890 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
892 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ifar_s
),
893 offsetof(CPUARMState
, cp15
.ifar_ns
) },
895 /* Watchpoint Fault Address Register : should actually only be present
896 * for 1136, 1176, 11MPCore.
898 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
899 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
900 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
901 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2, .accessfn
= cpacr_access
,
902 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.cpacr_el1
),
903 .resetvalue
= 0, .writefn
= cpacr_write
},
907 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
910 /* Performance monitor registers user accessibility is controlled
911 * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
912 * trapping to EL2 or EL3 for other accesses.
914 int el
= arm_current_el(env
);
916 if (el
== 0 && !(env
->cp15
.c9_pmuserenr
& 1)) {
917 return CP_ACCESS_TRAP
;
919 if (el
< 2 && (env
->cp15
.mdcr_el2
& MDCR_TPM
)
920 && !arm_is_secure_below_el3(env
)) {
921 return CP_ACCESS_TRAP_EL2
;
923 if (el
< 3 && (env
->cp15
.mdcr_el3
& MDCR_TPM
)) {
924 return CP_ACCESS_TRAP_EL3
;
930 static CPAccessResult
pmreg_access_xevcntr(CPUARMState
*env
,
931 const ARMCPRegInfo
*ri
,
934 /* ER: event counter read trap control */
935 if (arm_feature(env
, ARM_FEATURE_V8
)
936 && arm_current_el(env
) == 0
937 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0
942 return pmreg_access(env
, ri
, isread
);
945 static CPAccessResult
pmreg_access_swinc(CPUARMState
*env
,
946 const ARMCPRegInfo
*ri
,
949 /* SW: software increment write trap control */
950 if (arm_feature(env
, ARM_FEATURE_V8
)
951 && arm_current_el(env
) == 0
952 && (env
->cp15
.c9_pmuserenr
& (1 << 1)) != 0
957 return pmreg_access(env
, ri
, isread
);
960 #ifndef CONFIG_USER_ONLY
962 static CPAccessResult
pmreg_access_selr(CPUARMState
*env
,
963 const ARMCPRegInfo
*ri
,
966 /* ER: event counter read trap control */
967 if (arm_feature(env
, ARM_FEATURE_V8
)
968 && arm_current_el(env
) == 0
969 && (env
->cp15
.c9_pmuserenr
& (1 << 3)) != 0) {
973 return pmreg_access(env
, ri
, isread
);
976 static CPAccessResult
pmreg_access_ccntr(CPUARMState
*env
,
977 const ARMCPRegInfo
*ri
,
980 /* CR: cycle counter read trap control */
981 if (arm_feature(env
, ARM_FEATURE_V8
)
982 && arm_current_el(env
) == 0
983 && (env
->cp15
.c9_pmuserenr
& (1 << 2)) != 0
988 return pmreg_access(env
, ri
, isread
);
991 static inline bool arm_ccnt_enabled(CPUARMState
*env
)
993 /* This does not support checking PMCCFILTR_EL0 register */
995 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
1002 void pmccntr_sync(CPUARMState
*env
)
1004 uint64_t temp_ticks
;
1006 temp_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1007 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1009 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1010 /* Increment once every 64 processor clock cycles */
1014 if (arm_ccnt_enabled(env
)) {
1015 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
1019 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1024 if (value
& PMCRC
) {
1025 /* The counter has been reset */
1026 env
->cp15
.c15_ccnt
= 0;
1029 /* only the DP, X, D and E bits are writable */
1030 env
->cp15
.c9_pmcr
&= ~0x39;
1031 env
->cp15
.c9_pmcr
|= (value
& 0x39);
1036 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1038 uint64_t total_ticks
;
1040 if (!arm_ccnt_enabled(env
)) {
1041 /* Counter is disabled, do not change value */
1042 return env
->cp15
.c15_ccnt
;
1045 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1046 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1048 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1049 /* Increment once every 64 processor clock cycles */
1052 return total_ticks
- env
->cp15
.c15_ccnt
;
1055 static void pmselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1058 /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and
1059 * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the
1060 * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are
1063 env
->cp15
.c9_pmselr
= value
& 0x1f;
1066 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1069 uint64_t total_ticks
;
1071 if (!arm_ccnt_enabled(env
)) {
1072 /* Counter is disabled, set the absolute value */
1073 env
->cp15
.c15_ccnt
= value
;
1077 total_ticks
= muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
1078 ARM_CPU_FREQ
, NANOSECONDS_PER_SECOND
);
1080 if (env
->cp15
.c9_pmcr
& PMCRD
) {
1081 /* Increment once every 64 processor clock cycles */
1084 env
->cp15
.c15_ccnt
= total_ticks
- value
;
1087 static void pmccntr_write32(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1090 uint64_t cur_val
= pmccntr_read(env
, NULL
);
1092 pmccntr_write(env
, ri
, deposit64(cur_val
, 0, 32, value
));
1095 #else /* CONFIG_USER_ONLY */
1097 void pmccntr_sync(CPUARMState
*env
)
1103 static void pmccfiltr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1107 env
->cp15
.pmccfiltr_el0
= value
& 0x7E000000;
1111 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1115 env
->cp15
.c9_pmcnten
|= value
;
1118 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1122 env
->cp15
.c9_pmcnten
&= ~value
;
1125 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1128 env
->cp15
.c9_pmovsr
&= ~value
;
1131 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1134 /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
1135 * PMSELR value is equal to or greater than the number of implemented
1136 * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
1138 if (env
->cp15
.c9_pmselr
== 0x1f) {
1139 pmccfiltr_write(env
, ri
, value
);
1143 static uint64_t pmxevtyper_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1145 /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
1146 * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
1148 if (env
->cp15
.c9_pmselr
== 0x1f) {
1149 return env
->cp15
.pmccfiltr_el0
;
1155 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1158 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1159 env
->cp15
.c9_pmuserenr
= value
& 0xf;
1161 env
->cp15
.c9_pmuserenr
= value
& 1;
1165 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1168 /* We have no event counters so only the C bit can be changed */
1170 env
->cp15
.c9_pminten
|= value
;
1173 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1177 env
->cp15
.c9_pminten
&= ~value
;
1180 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1183 /* Note that even though the AArch64 view of this register has bits
1184 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
1185 * architectural requirements for bits which are RES0 only in some
1186 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
1187 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
1189 raw_write(env
, ri
, value
& ~0x1FULL
);
1192 static void scr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1194 /* We only mask off bits that are RES0 both for AArch64 and AArch32.
1195 * For bits that vary between AArch32/64, code needs to check the
1196 * current execution mode before directly using the feature bit.
1198 uint32_t valid_mask
= SCR_AARCH64_MASK
| SCR_AARCH32_MASK
;
1200 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1201 valid_mask
&= ~SCR_HCE
;
1203 /* On ARMv7, SMD (or SCD as it is called in v7) is only
1204 * supported if EL2 exists. The bit is UNK/SBZP when
1205 * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
1206 * when EL2 is unavailable.
1207 * On ARMv8, this bit is always available.
1209 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1210 !arm_feature(env
, ARM_FEATURE_V8
)) {
1211 valid_mask
&= ~SCR_SMD
;
1215 /* Clear all-context RES0 bits. */
1216 value
&= valid_mask
;
1217 raw_write(env
, ri
, value
);
1220 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1222 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1224 /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1227 uint32_t index
= A32_BANKED_REG_GET(env
, csselr
,
1228 ri
->secure
& ARM_CP_SECSTATE_S
);
1230 return cpu
->ccsidr
[index
];
1233 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1236 raw_write(env
, ri
, value
& 0xf);
1239 static uint64_t isr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1241 CPUState
*cs
= ENV_GET_CPU(env
);
1244 if (cs
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1247 if (cs
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1250 /* External aborts are not possible in QEMU so A bit is always clear */
1254 static const ARMCPRegInfo v7_cp_reginfo
[] = {
1255 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1256 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
1257 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1258 /* Performance monitors are implementation defined in v7,
1259 * but with an ARM recommended set of registers, which we
1260 * follow (although we don't actually implement any counters)
1262 * Performance registers fall into three categories:
1263 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1264 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1265 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1266 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1267 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1269 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
1270 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1271 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1272 .writefn
= pmcntenset_write
,
1273 .accessfn
= pmreg_access
,
1274 .raw_writefn
= raw_write
},
1275 { .name
= "PMCNTENSET_EL0", .state
= ARM_CP_STATE_AA64
,
1276 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 1,
1277 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1278 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
), .resetvalue
= 0,
1279 .writefn
= pmcntenset_write
, .raw_writefn
= raw_write
},
1280 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
1282 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcnten
),
1283 .accessfn
= pmreg_access
,
1284 .writefn
= pmcntenclr_write
,
1285 .type
= ARM_CP_ALIAS
},
1286 { .name
= "PMCNTENCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1287 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 2,
1288 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1289 .type
= ARM_CP_ALIAS
,
1290 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
1291 .writefn
= pmcntenclr_write
},
1292 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
1293 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1294 .accessfn
= pmreg_access
,
1295 .writefn
= pmovsr_write
,
1296 .raw_writefn
= raw_write
},
1297 { .name
= "PMOVSCLR_EL0", .state
= ARM_CP_STATE_AA64
,
1298 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 3,
1299 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1300 .type
= ARM_CP_ALIAS
,
1301 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
1302 .writefn
= pmovsr_write
,
1303 .raw_writefn
= raw_write
},
1304 /* Unimplemented so WI. */
1305 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
1306 .access
= PL0_W
, .accessfn
= pmreg_access_swinc
, .type
= ARM_CP_NOP
},
1307 #ifndef CONFIG_USER_ONLY
1308 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
1309 .access
= PL0_RW
, .type
= ARM_CP_ALIAS
,
1310 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmselr
),
1311 .accessfn
= pmreg_access_selr
, .writefn
= pmselr_write
,
1312 .raw_writefn
= raw_write
},
1313 { .name
= "PMSELR_EL0", .state
= ARM_CP_STATE_AA64
,
1314 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 5,
1315 .access
= PL0_RW
, .accessfn
= pmreg_access_selr
,
1316 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmselr
),
1317 .writefn
= pmselr_write
, .raw_writefn
= raw_write
, },
1318 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
1319 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
1320 .readfn
= pmccntr_read
, .writefn
= pmccntr_write32
,
1321 .accessfn
= pmreg_access_ccntr
},
1322 { .name
= "PMCCNTR_EL0", .state
= ARM_CP_STATE_AA64
,
1323 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 0,
1324 .access
= PL0_RW
, .accessfn
= pmreg_access_ccntr
,
1326 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
, },
1328 { .name
= "PMCCFILTR_EL0", .state
= ARM_CP_STATE_AA64
,
1329 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 15, .opc2
= 7,
1330 .writefn
= pmccfiltr_write
,
1331 .access
= PL0_RW
, .accessfn
= pmreg_access
,
1333 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmccfiltr_el0
),
1335 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
1336 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1337 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1338 { .name
= "PMXEVTYPER_EL0", .state
= ARM_CP_STATE_AA64
,
1339 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 13, .opc2
= 1,
1340 .access
= PL0_RW
, .type
= ARM_CP_NO_RAW
, .accessfn
= pmreg_access
,
1341 .writefn
= pmxevtyper_write
, .readfn
= pmxevtyper_read
},
1342 /* Unimplemented, RAZ/WI. */
1343 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
1344 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
1345 .accessfn
= pmreg_access_xevcntr
},
1346 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
1347 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
,
1348 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1350 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1351 { .name
= "PMUSERENR_EL0", .state
= ARM_CP_STATE_AA64
,
1352 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 14, .opc2
= 0,
1353 .access
= PL0_R
| PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1354 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
1356 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
1357 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
1358 .access
= PL1_RW
, .accessfn
= access_tpm
,
1359 .type
= ARM_CP_ALIAS
,
1360 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pminten
),
1362 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
1363 { .name
= "PMINTENSET_EL1", .state
= ARM_CP_STATE_AA64
,
1364 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 1,
1365 .access
= PL1_RW
, .accessfn
= access_tpm
,
1367 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1368 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
,
1369 .resetvalue
= 0x0 },
1370 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
1371 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1372 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1373 .writefn
= pmintenclr_write
, },
1374 { .name
= "PMINTENCLR_EL1", .state
= ARM_CP_STATE_AA64
,
1375 .opc0
= 3, .opc1
= 0, .crn
= 9, .crm
= 14, .opc2
= 2,
1376 .access
= PL1_RW
, .accessfn
= access_tpm
, .type
= ARM_CP_ALIAS
,
1377 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
1378 .writefn
= pmintenclr_write
},
1379 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
1380 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
1381 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_RAW
},
1382 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
1383 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
1384 .access
= PL1_RW
, .writefn
= csselr_write
, .resetvalue
= 0,
1385 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.csselr_s
),
1386 offsetof(CPUARMState
, cp15
.csselr_ns
) } },
1387 /* Auxiliary ID register: this actually has an IMPDEF value but for now
1388 * just RAZ for all cores:
1390 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
1391 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
1392 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1393 /* Auxiliary fault status registers: these also are IMPDEF, and we
1394 * choose to RAZ/WI for all cores.
1396 { .name
= "AFSR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1397 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 0,
1398 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1399 { .name
= "AFSR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1400 .opc0
= 3, .opc1
= 0, .crn
= 5, .crm
= 1, .opc2
= 1,
1401 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1402 /* MAIR can just read-as-written because we don't implement caches
1403 * and so don't need to care about memory attributes.
1405 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
1406 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
1407 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[1]),
1409 { .name
= "MAIR_EL3", .state
= ARM_CP_STATE_AA64
,
1410 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 2, .opc2
= 0,
1411 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[3]),
1413 /* For non-long-descriptor page tables these are PRRR and NMRR;
1414 * regardless they still act as reads-as-written for QEMU.
1416 /* MAIR0/1 are defined separately from their 64-bit counterpart which
1417 * allows them to assign the correct fieldoffset based on the endianness
1418 * handled in the field definitions.
1420 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
,
1421 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
1422 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair0_s
),
1423 offsetof(CPUARMState
, cp15
.mair0_ns
) },
1424 .resetfn
= arm_cp_reset_ignore
},
1425 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
,
1426 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
1427 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.mair1_s
),
1428 offsetof(CPUARMState
, cp15
.mair1_ns
) },
1429 .resetfn
= arm_cp_reset_ignore
},
1430 { .name
= "ISR_EL1", .state
= ARM_CP_STATE_BOTH
,
1431 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 1, .opc2
= 0,
1432 .type
= ARM_CP_NO_RAW
, .access
= PL1_R
, .readfn
= isr_read
},
1433 /* 32 bit ITLB invalidates */
1434 { .name
= "ITLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 0,
1435 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1436 { .name
= "ITLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 1,
1437 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1438 { .name
= "ITLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 5, .opc2
= 2,
1439 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1440 /* 32 bit DTLB invalidates */
1441 { .name
= "DTLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 0,
1442 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1443 { .name
= "DTLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 1,
1444 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1445 { .name
= "DTLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 6, .opc2
= 2,
1446 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1447 /* 32 bit TLB invalidates */
1448 { .name
= "TLBIALL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1449 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_write
},
1450 { .name
= "TLBIMVA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1451 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
1452 { .name
= "TLBIASID", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1453 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiasid_write
},
1454 { .name
= "TLBIMVAA", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1455 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
1459 static const ARMCPRegInfo v7mp_cp_reginfo
[] = {
1460 /* 32 bit TLB invalidates, Inner Shareable */
1461 { .name
= "TLBIALLIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1462 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbiall_is_write
},
1463 { .name
= "TLBIMVAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1464 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
1465 { .name
= "TLBIASIDIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1466 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1467 .writefn
= tlbiasid_is_write
},
1468 { .name
= "TLBIMVAAIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1469 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
1470 .writefn
= tlbimvaa_is_write
},
1474 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1481 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1484 if (arm_current_el(env
) == 0 && (env
->teecr
& 1)) {
1485 return CP_ACCESS_TRAP
;
1487 return CP_ACCESS_OK
;
1490 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
1491 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
1492 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
1494 .writefn
= teecr_write
},
1495 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
1496 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
1497 .accessfn
= teehbr_access
, .resetvalue
= 0 },
1501 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
1502 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
1503 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
1505 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[0]), .resetvalue
= 0 },
1506 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
1508 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrurw_s
),
1509 offsetoflow32(CPUARMState
, cp15
.tpidrurw_ns
) },
1510 .resetfn
= arm_cp_reset_ignore
},
1511 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
1512 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
1513 .access
= PL0_R
|PL1_W
,
1514 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el
[0]),
1516 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
1517 .access
= PL0_R
|PL1_W
,
1518 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidruro_s
),
1519 offsetoflow32(CPUARMState
, cp15
.tpidruro_ns
) },
1520 .resetfn
= arm_cp_reset_ignore
},
1521 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_AA64
,
1522 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
1524 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[1]), .resetvalue
= 0 },
1525 { .name
= "TPIDRPRW", .opc1
= 0, .cp
= 15, .crn
= 13, .crm
= 0, .opc2
= 4,
1527 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tpidrprw_s
),
1528 offsetoflow32(CPUARMState
, cp15
.tpidrprw_ns
) },
1533 #ifndef CONFIG_USER_ONLY
1535 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1538 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1539 * Writable only at the highest implemented exception level.
1541 int el
= arm_current_el(env
);
1545 if (!extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
1546 return CP_ACCESS_TRAP
;
1550 if (!isread
&& ri
->state
== ARM_CP_STATE_AA32
&&
1551 arm_is_secure_below_el3(env
)) {
1552 /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1553 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1561 if (!isread
&& el
< arm_highest_el(env
)) {
1562 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1565 return CP_ACCESS_OK
;
1568 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
,
1571 unsigned int cur_el
= arm_current_el(env
);
1572 bool secure
= arm_is_secure(env
);
1574 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1576 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
1577 return CP_ACCESS_TRAP
;
1580 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1581 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1582 !extract32(env
->cp15
.cnthctl_el2
, 0, 1)) {
1583 return CP_ACCESS_TRAP_EL2
;
1585 return CP_ACCESS_OK
;
1588 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
,
1591 unsigned int cur_el
= arm_current_el(env
);
1592 bool secure
= arm_is_secure(env
);
1594 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1595 * EL0[PV]TEN is zero.
1598 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
1599 return CP_ACCESS_TRAP
;
1602 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
1603 timeridx
== GTIMER_PHYS
&& !secure
&& cur_el
< 2 &&
1604 !extract32(env
->cp15
.cnthctl_el2
, 1, 1)) {
1605 return CP_ACCESS_TRAP_EL2
;
1607 return CP_ACCESS_OK
;
1610 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
1611 const ARMCPRegInfo
*ri
,
1614 return gt_counter_access(env
, GTIMER_PHYS
, isread
);
1617 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
1618 const ARMCPRegInfo
*ri
,
1621 return gt_counter_access(env
, GTIMER_VIRT
, isread
);
1624 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1627 return gt_timer_access(env
, GTIMER_PHYS
, isread
);
1630 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1633 return gt_timer_access(env
, GTIMER_VIRT
, isread
);
1636 static CPAccessResult
gt_stimer_access(CPUARMState
*env
,
1637 const ARMCPRegInfo
*ri
,
1640 /* The AArch64 register view of the secure physical timer is
1641 * always accessible from EL3, and configurably accessible from
1644 switch (arm_current_el(env
)) {
1646 if (!arm_is_secure(env
)) {
1647 return CP_ACCESS_TRAP
;
1649 if (!(env
->cp15
.scr_el3
& SCR_ST
)) {
1650 return CP_ACCESS_TRAP_EL3
;
1652 return CP_ACCESS_OK
;
1655 return CP_ACCESS_TRAP
;
1657 return CP_ACCESS_OK
;
1659 g_assert_not_reached();
1663 static uint64_t gt_get_countervalue(CPUARMState
*env
)
1665 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
1668 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
1670 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
1673 /* Timer enabled: calculate and set current ISTATUS, irq, and
1674 * reset timer to when ISTATUS next has to change
1676 uint64_t offset
= timeridx
== GTIMER_VIRT
?
1677 cpu
->env
.cp15
.cntvoff_el2
: 0;
1678 uint64_t count
= gt_get_countervalue(&cpu
->env
);
1679 /* Note that this must be unsigned 64 bit arithmetic: */
1680 int istatus
= count
- offset
>= gt
->cval
;
1684 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
1686 irqstate
= (istatus
&& !(gt
->ctl
& 2));
1687 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1690 /* Next transition is when count rolls back over to zero */
1691 nexttick
= UINT64_MAX
;
1693 /* Next transition is when we hit cval */
1694 nexttick
= gt
->cval
+ offset
;
1696 /* Note that the desired next expiry time might be beyond the
1697 * signed-64-bit range of a QEMUTimer -- in this case we just
1698 * set the timer for as far in the future as possible. When the
1699 * timer expires we will reset the timer for any remaining period.
1701 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
1702 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
1704 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
1705 trace_arm_gt_recalc(timeridx
, irqstate
, nexttick
);
1707 /* Timer disabled: ISTATUS and timer output always clear */
1709 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
1710 timer_del(cpu
->gt_timer
[timeridx
]);
1711 trace_arm_gt_recalc_disabled(timeridx
);
1715 static void gt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1718 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1720 timer_del(cpu
->gt_timer
[timeridx
]);
1723 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1725 return gt_get_countervalue(env
);
1728 static uint64_t gt_virt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1730 return gt_get_countervalue(env
) - env
->cp15
.cntvoff_el2
;
1733 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1737 trace_arm_gt_cval_write(timeridx
, value
);
1738 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
1739 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1742 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1745 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1747 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
1748 (gt_get_countervalue(env
) - offset
));
1751 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1755 uint64_t offset
= timeridx
== GTIMER_VIRT
? env
->cp15
.cntvoff_el2
: 0;
1757 trace_arm_gt_tval_write(timeridx
, value
);
1758 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) - offset
+
1759 sextract64(value
, 0, 32);
1760 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
1763 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1767 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1768 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
1770 trace_arm_gt_ctl_write(timeridx
, value
);
1771 env
->cp15
.c14_timer
[timeridx
].ctl
= deposit64(oldval
, 0, 2, value
);
1772 if ((oldval
^ value
) & 1) {
1773 /* Enable toggled */
1774 gt_recalc_timer(cpu
, timeridx
);
1775 } else if ((oldval
^ value
) & 2) {
1776 /* IMASK toggled: don't need to recalculate,
1777 * just set the interrupt line based on ISTATUS
1779 int irqstate
= (oldval
& 4) && !(value
& 2);
1781 trace_arm_gt_imask_toggle(timeridx
, irqstate
);
1782 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], irqstate
);
1786 static void gt_phys_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1788 gt_timer_reset(env
, ri
, GTIMER_PHYS
);
1791 static void gt_phys_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1794 gt_cval_write(env
, ri
, GTIMER_PHYS
, value
);
1797 static uint64_t gt_phys_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1799 return gt_tval_read(env
, ri
, GTIMER_PHYS
);
1802 static void gt_phys_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1805 gt_tval_write(env
, ri
, GTIMER_PHYS
, value
);
1808 static void gt_phys_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1811 gt_ctl_write(env
, ri
, GTIMER_PHYS
, value
);
1814 static void gt_virt_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1816 gt_timer_reset(env
, ri
, GTIMER_VIRT
);
1819 static void gt_virt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1822 gt_cval_write(env
, ri
, GTIMER_VIRT
, value
);
1825 static uint64_t gt_virt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1827 return gt_tval_read(env
, ri
, GTIMER_VIRT
);
1830 static void gt_virt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1833 gt_tval_write(env
, ri
, GTIMER_VIRT
, value
);
1836 static void gt_virt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1839 gt_ctl_write(env
, ri
, GTIMER_VIRT
, value
);
1842 static void gt_cntvoff_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1845 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1847 trace_arm_gt_cntvoff_write(value
);
1848 raw_write(env
, ri
, value
);
1849 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1852 static void gt_hyp_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1854 gt_timer_reset(env
, ri
, GTIMER_HYP
);
1857 static void gt_hyp_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1860 gt_cval_write(env
, ri
, GTIMER_HYP
, value
);
1863 static uint64_t gt_hyp_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1865 return gt_tval_read(env
, ri
, GTIMER_HYP
);
1868 static void gt_hyp_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1871 gt_tval_write(env
, ri
, GTIMER_HYP
, value
);
1874 static void gt_hyp_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1877 gt_ctl_write(env
, ri
, GTIMER_HYP
, value
);
1880 static void gt_sec_timer_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1882 gt_timer_reset(env
, ri
, GTIMER_SEC
);
1885 static void gt_sec_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1888 gt_cval_write(env
, ri
, GTIMER_SEC
, value
);
1891 static uint64_t gt_sec_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1893 return gt_tval_read(env
, ri
, GTIMER_SEC
);
1896 static void gt_sec_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1899 gt_tval_write(env
, ri
, GTIMER_SEC
, value
);
1902 static void gt_sec_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1905 gt_ctl_write(env
, ri
, GTIMER_SEC
, value
);
1908 void arm_gt_ptimer_cb(void *opaque
)
1910 ARMCPU
*cpu
= opaque
;
1912 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1915 void arm_gt_vtimer_cb(void *opaque
)
1917 ARMCPU
*cpu
= opaque
;
1919 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1922 void arm_gt_htimer_cb(void *opaque
)
1924 ARMCPU
*cpu
= opaque
;
1926 gt_recalc_timer(cpu
, GTIMER_HYP
);
1929 void arm_gt_stimer_cb(void *opaque
)
1931 ARMCPU
*cpu
= opaque
;
1933 gt_recalc_timer(cpu
, GTIMER_SEC
);
1936 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1937 /* Note that CNTFRQ is purely reads-as-written for the benefit
1938 * of software; writing it doesn't actually change the timer frequency.
1939 * Our reset value matches the fixed frequency we implement the timer at.
1941 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1942 .type
= ARM_CP_ALIAS
,
1943 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1944 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1946 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1947 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1948 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1949 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1950 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1952 /* overall control: mostly access permissions */
1953 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1954 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1956 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1959 /* per-timer control */
1960 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1961 .secure
= ARM_CP_SECSTATE_NS
,
1962 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1963 .accessfn
= gt_ptimer_access
,
1964 .fieldoffset
= offsetoflow32(CPUARMState
,
1965 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1966 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1968 { .name
= "CNTP_CTL(S)",
1969 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1970 .secure
= ARM_CP_SECSTATE_S
,
1971 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1972 .accessfn
= gt_ptimer_access
,
1973 .fieldoffset
= offsetoflow32(CPUARMState
,
1974 cp15
.c14_timer
[GTIMER_SEC
].ctl
),
1975 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
1977 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1978 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1979 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1980 .accessfn
= gt_ptimer_access
,
1981 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1983 .writefn
= gt_phys_ctl_write
, .raw_writefn
= raw_write
,
1985 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1986 .type
= ARM_CP_IO
| ARM_CP_ALIAS
, .access
= PL1_RW
| PL0_R
,
1987 .accessfn
= gt_vtimer_access
,
1988 .fieldoffset
= offsetoflow32(CPUARMState
,
1989 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1990 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
1992 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1993 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1994 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1995 .accessfn
= gt_vtimer_access
,
1996 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1998 .writefn
= gt_virt_ctl_write
, .raw_writefn
= raw_write
,
2000 /* TimerValue views: a 32 bit downcounting view of the underlying state */
2001 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2002 .secure
= ARM_CP_SECSTATE_NS
,
2003 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2004 .accessfn
= gt_ptimer_access
,
2005 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2007 { .name
= "CNTP_TVAL(S)",
2008 .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
2009 .secure
= ARM_CP_SECSTATE_S
,
2010 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2011 .accessfn
= gt_ptimer_access
,
2012 .readfn
= gt_sec_tval_read
, .writefn
= gt_sec_tval_write
,
2014 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2015 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
2016 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2017 .accessfn
= gt_ptimer_access
, .resetfn
= gt_phys_timer_reset
,
2018 .readfn
= gt_phys_tval_read
, .writefn
= gt_phys_tval_write
,
2020 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
2021 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2022 .accessfn
= gt_vtimer_access
,
2023 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2025 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2026 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
2027 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
2028 .accessfn
= gt_vtimer_access
, .resetfn
= gt_virt_timer_reset
,
2029 .readfn
= gt_virt_tval_read
, .writefn
= gt_virt_tval_write
,
2031 /* The counter itself */
2032 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
2033 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2034 .accessfn
= gt_pct_access
,
2035 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2037 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
2038 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
2039 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2040 .accessfn
= gt_pct_access
, .readfn
= gt_cnt_read
,
2042 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
2043 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_RAW
| ARM_CP_IO
,
2044 .accessfn
= gt_vct_access
,
2045 .readfn
= gt_virt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
2047 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
2048 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
2049 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
| ARM_CP_IO
,
2050 .accessfn
= gt_vct_access
, .readfn
= gt_virt_cnt_read
,
2052 /* Comparison value, indicating when the timer goes off */
2053 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
2054 .secure
= ARM_CP_SECSTATE_NS
,
2055 .access
= PL1_RW
| PL0_R
,
2056 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2057 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2058 .accessfn
= gt_ptimer_access
,
2059 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2061 { .name
= "CNTP_CVAL(S)", .cp
= 15, .crm
= 14, .opc1
= 2,
2062 .secure
= ARM_CP_SECSTATE_S
,
2063 .access
= PL1_RW
| PL0_R
,
2064 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2065 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2066 .accessfn
= gt_ptimer_access
,
2067 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2069 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2070 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
2071 .access
= PL1_RW
| PL0_R
,
2073 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
2074 .resetvalue
= 0, .accessfn
= gt_ptimer_access
,
2075 .writefn
= gt_phys_cval_write
, .raw_writefn
= raw_write
,
2077 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
2078 .access
= PL1_RW
| PL0_R
,
2079 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_ALIAS
,
2080 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2081 .accessfn
= gt_vtimer_access
,
2082 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2084 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
2085 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
2086 .access
= PL1_RW
| PL0_R
,
2088 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
2089 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
2090 .writefn
= gt_virt_cval_write
, .raw_writefn
= raw_write
,
2092 /* Secure timer -- this is actually restricted to only EL3
2093 * and configurably Secure-EL1 via the accessfn.
2095 { .name
= "CNTPS_TVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2096 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 0,
2097 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL1_RW
,
2098 .accessfn
= gt_stimer_access
,
2099 .readfn
= gt_sec_tval_read
,
2100 .writefn
= gt_sec_tval_write
,
2101 .resetfn
= gt_sec_timer_reset
,
2103 { .name
= "CNTPS_CTL_EL1", .state
= ARM_CP_STATE_AA64
,
2104 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 1,
2105 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2106 .accessfn
= gt_stimer_access
,
2107 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].ctl
),
2109 .writefn
= gt_sec_ctl_write
, .raw_writefn
= raw_write
,
2111 { .name
= "CNTPS_CVAL_EL1", .state
= ARM_CP_STATE_AA64
,
2112 .opc0
= 3, .opc1
= 7, .crn
= 14, .crm
= 2, .opc2
= 2,
2113 .type
= ARM_CP_IO
, .access
= PL1_RW
,
2114 .accessfn
= gt_stimer_access
,
2115 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_SEC
].cval
),
2116 .writefn
= gt_sec_cval_write
, .raw_writefn
= raw_write
,
2122 /* In user-mode none of the generic timer registers are accessible,
2123 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
2124 * so instead just don't register any of them.
2126 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
2132 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2134 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2135 raw_write(env
, ri
, value
);
2136 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
2137 raw_write(env
, ri
, value
& 0xfffff6ff);
2139 raw_write(env
, ri
, value
& 0xfffff1ff);
2143 #ifndef CONFIG_USER_ONLY
2144 /* get_phys_addr() isn't present for user-mode-only targets */
2146 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2150 /* The ATS12NSO* operations must trap to EL3 if executed in
2151 * Secure EL1 (which can only happen if EL3 is AArch64).
2152 * They are simply UNDEF if executed from NS EL1.
2153 * They function normally from EL2 or EL3.
2155 if (arm_current_el(env
) == 1) {
2156 if (arm_is_secure_below_el3(env
)) {
2157 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3
;
2159 return CP_ACCESS_TRAP_UNCATEGORIZED
;
2162 return CP_ACCESS_OK
;
2165 static uint64_t do_ats_write(CPUARMState
*env
, uint64_t value
,
2166 MMUAccessType access_type
, ARMMMUIdx mmu_idx
)
2169 target_ulong page_size
;
2173 bool format64
= false;
2174 MemTxAttrs attrs
= {};
2175 ARMMMUFaultInfo fi
= {};
2176 ARMCacheAttrs cacheattrs
= {};
2178 ret
= get_phys_addr(env
, value
, access_type
, mmu_idx
, &phys_addr
, &attrs
,
2179 &prot
, &page_size
, &fi
, &cacheattrs
);
2183 } else if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2186 * * TTBCR.EAE determines whether the result is returned using the
2187 * 32-bit or the 64-bit PAR format
2188 * * Instructions executed in Hyp mode always use the 64bit format
2190 * ATS1S2NSOxx uses the 64bit format if any of the following is true:
2191 * * The Non-secure TTBCR.EAE bit is set to 1
2192 * * The implementation includes EL2, and the value of HCR.VM is 1
2194 * ATS1Hx always uses the 64bit format (not supported yet).
2196 format64
= arm_s1_regime_using_lpae_format(env
, mmu_idx
);
2198 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
2199 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
2200 format64
|= env
->cp15
.hcr_el2
& HCR_VM
;
2202 format64
|= arm_current_el(env
) == 2;
2208 /* Create a 64-bit PAR */
2209 par64
= (1 << 11); /* LPAE bit always set */
2211 par64
|= phys_addr
& ~0xfffULL
;
2212 if (!attrs
.secure
) {
2213 par64
|= (1 << 9); /* NS */
2215 par64
|= (uint64_t)cacheattrs
.attrs
<< 56; /* ATTR */
2216 par64
|= cacheattrs
.shareability
<< 7; /* SH */
2218 uint32_t fsr
= arm_fi_to_lfsc(&fi
);
2221 par64
|= (fsr
& 0x3f) << 1; /* FS */
2222 /* Note that S2WLK and FSTAGE are always zero, because we don't
2223 * implement virtualization and therefore there can't be a stage 2
2228 /* fsr is a DFSR/IFSR value for the short descriptor
2229 * translation table format (with WnR always clear).
2230 * Convert it to a 32-bit PAR.
2233 /* We do not set any attribute bits in the PAR */
2234 if (page_size
== (1 << 24)
2235 && arm_feature(env
, ARM_FEATURE_V7
)) {
2236 par64
= (phys_addr
& 0xff000000) | (1 << 1);
2238 par64
= phys_addr
& 0xfffff000;
2240 if (!attrs
.secure
) {
2241 par64
|= (1 << 9); /* NS */
2244 uint32_t fsr
= arm_fi_to_sfsc(&fi
);
2246 par64
= ((fsr
& (1 << 10)) >> 5) | ((fsr
& (1 << 12)) >> 6) |
2247 ((fsr
& 0xf) << 1) | 1;
2253 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
2255 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2258 int el
= arm_current_el(env
);
2259 bool secure
= arm_is_secure_below_el3(env
);
2261 switch (ri
->opc2
& 6) {
2263 /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2266 mmu_idx
= ARMMMUIdx_S1E3
;
2269 mmu_idx
= ARMMMUIdx_S1NSE1
;
2272 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2275 g_assert_not_reached();
2279 /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2282 mmu_idx
= ARMMMUIdx_S1SE0
;
2285 mmu_idx
= ARMMMUIdx_S1NSE0
;
2288 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2291 g_assert_not_reached();
2295 /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2296 mmu_idx
= ARMMMUIdx_S12NSE1
;
2299 /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2300 mmu_idx
= ARMMMUIdx_S12NSE0
;
2303 g_assert_not_reached();
2306 par64
= do_ats_write(env
, value
, access_type
, mmu_idx
);
2308 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2311 static void ats1h_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2314 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2317 par64
= do_ats_write(env
, value
, access_type
, ARMMMUIdx_S2NS
);
2319 A32_BANKED_CURRENT_REG_SET(env
, par
, par64
);
2322 static CPAccessResult
at_s1e2_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2325 if (arm_current_el(env
) == 3 && !(env
->cp15
.scr_el3
& SCR_NS
)) {
2326 return CP_ACCESS_TRAP
;
2328 return CP_ACCESS_OK
;
2331 static void ats_write64(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2334 MMUAccessType access_type
= ri
->opc2
& 1 ? MMU_DATA_STORE
: MMU_DATA_LOAD
;
2336 int secure
= arm_is_secure_below_el3(env
);
2338 switch (ri
->opc2
& 6) {
2341 case 0: /* AT S1E1R, AT S1E1W */
2342 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S1NSE1
;
2344 case 4: /* AT S1E2R, AT S1E2W */
2345 mmu_idx
= ARMMMUIdx_S1E2
;
2347 case 6: /* AT S1E3R, AT S1E3W */
2348 mmu_idx
= ARMMMUIdx_S1E3
;
2351 g_assert_not_reached();
2354 case 2: /* AT S1E0R, AT S1E0W */
2355 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S1NSE0
;
2357 case 4: /* AT S12E1R, AT S12E1W */
2358 mmu_idx
= secure
? ARMMMUIdx_S1SE1
: ARMMMUIdx_S12NSE1
;
2360 case 6: /* AT S12E0R, AT S12E0W */
2361 mmu_idx
= secure
? ARMMMUIdx_S1SE0
: ARMMMUIdx_S12NSE0
;
2364 g_assert_not_reached();
2367 env
->cp15
.par_el
[1] = do_ats_write(env
, value
, access_type
, mmu_idx
);
2371 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
2372 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
2373 .access
= PL1_RW
, .resetvalue
= 0,
2374 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.par_s
),
2375 offsetoflow32(CPUARMState
, cp15
.par_ns
) },
2376 .writefn
= par_write
},
2377 #ifndef CONFIG_USER_ONLY
2378 /* This underdecoding is safe because the reginfo is NO_RAW. */
2379 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
2380 .access
= PL1_W
, .accessfn
= ats_access
,
2381 .writefn
= ats_write
, .type
= ARM_CP_NO_RAW
},
2386 /* Return basic MPU access permission bits. */
2387 static uint32_t simple_mpu_ap_bits(uint32_t val
)
2394 for (i
= 0; i
< 16; i
+= 2) {
2395 ret
|= (val
>> i
) & mask
;
2401 /* Pad basic MPU access permission bits to extended format. */
2402 static uint32_t extended_mpu_ap_bits(uint32_t val
)
2409 for (i
= 0; i
< 16; i
+= 2) {
2410 ret
|= (val
& mask
) << i
;
2416 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2419 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
2422 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2424 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
2427 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2430 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
2433 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2435 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
2438 static uint64_t pmsav7_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2440 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2446 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2450 static void pmsav7_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2453 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2454 uint32_t *u32p
= *(uint32_t **)raw_ptr(env
, ri
);
2460 u32p
+= env
->pmsav7
.rnr
[M_REG_NS
];
2461 tlb_flush(CPU(cpu
)); /* Mappings may have changed - purge! */
2465 static void pmsav7_rgnr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2468 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2469 uint32_t nrgs
= cpu
->pmsav7_dregion
;
2471 if (value
>= nrgs
) {
2472 qemu_log_mask(LOG_GUEST_ERROR
,
2473 "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2474 " > %" PRIu32
"\n", (uint32_t)value
, nrgs
);
2478 raw_write(env
, ri
, value
);
2481 static const ARMCPRegInfo pmsav7_cp_reginfo
[] = {
2482 /* Reset for all these registers is handled in arm_cpu_reset(),
2483 * because the PMSAv7 is also used by M-profile CPUs, which do
2484 * not register cpregs but still need the state to be reset.
2486 { .name
= "DRBAR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 0,
2487 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2488 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drbar
),
2489 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2490 .resetfn
= arm_cp_reset_ignore
},
2491 { .name
= "DRSR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 2,
2492 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2493 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.drsr
),
2494 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2495 .resetfn
= arm_cp_reset_ignore
},
2496 { .name
= "DRACR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 1, .opc2
= 4,
2497 .access
= PL1_RW
, .type
= ARM_CP_NO_RAW
,
2498 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.dracr
),
2499 .readfn
= pmsav7_read
, .writefn
= pmsav7_write
,
2500 .resetfn
= arm_cp_reset_ignore
},
2501 { .name
= "RGNR", .cp
= 15, .crn
= 6, .opc1
= 0, .crm
= 2, .opc2
= 0,
2503 .fieldoffset
= offsetof(CPUARMState
, pmsav7
.rnr
[M_REG_NS
]),
2504 .writefn
= pmsav7_rgnr_write
,
2505 .resetfn
= arm_cp_reset_ignore
},
2509 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
2510 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2511 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2512 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2513 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
2514 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2515 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2516 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2517 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
2518 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
2520 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
2522 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
2524 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
2526 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
2528 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
2529 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
2531 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
2532 /* Protection region base and size registers */
2533 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
2534 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2535 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
2536 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
2537 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2538 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
2539 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
2540 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2541 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
2542 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
2543 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2544 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
2545 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
2546 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2547 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
2548 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
2549 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2550 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
2551 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
2552 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2553 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
2554 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
2555 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
2556 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
2560 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2563 TCR
*tcr
= raw_ptr(env
, ri
);
2564 int maskshift
= extract32(value
, 0, 3);
2566 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
2567 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& TTBCR_EAE
)) {
2568 /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2569 * using Long-desciptor translation table format */
2570 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
2571 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
2572 /* In an implementation that includes the Security Extensions
2573 * TTBCR has additional fields PD0 [4] and PD1 [5] for
2574 * Short-descriptor translation table format.
2576 value
&= TTBCR_PD1
| TTBCR_PD0
| TTBCR_N
;
2582 /* Update the masks corresponding to the TCR bank being written
2583 * Note that we always calculate mask and base_mask, but
2584 * they are only used for short-descriptor tables (ie if EAE is 0);
2585 * for long-descriptor tables the TCR fields are used differently
2586 * and the mask and base_mask values are meaningless.
2588 tcr
->raw_tcr
= value
;
2589 tcr
->mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
2590 tcr
->base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
2593 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2596 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2598 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2599 /* With LPAE the TTBCR could result in a change of ASID
2600 * via the TTBCR.A1 bit, so do a TLB flush.
2602 tlb_flush(CPU(cpu
));
2604 vmsa_ttbcr_raw_write(env
, ri
, value
);
2607 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2609 TCR
*tcr
= raw_ptr(env
, ri
);
2611 /* Reset both the TCR as well as the masks corresponding to the bank of
2612 * the TCR being reset.
2616 tcr
->base_mask
= 0xffffc000u
;
2619 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2622 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2623 TCR
*tcr
= raw_ptr(env
, ri
);
2625 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2626 tlb_flush(CPU(cpu
));
2627 tcr
->raw_tcr
= value
;
2630 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2633 /* 64 bit accesses to the TTBRs can change the ASID and so we
2634 * must flush the TLB.
2636 if (cpreg_field_is_64bit(ri
)) {
2637 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2639 tlb_flush(CPU(cpu
));
2641 raw_write(env
, ri
, value
);
2644 static void vttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2647 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2648 CPUState
*cs
= CPU(cpu
);
2650 /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
2651 if (raw_read(env
, ri
) != value
) {
2652 tlb_flush_by_mmuidx(cs
,
2653 ARMMMUIdxBit_S12NSE1
|
2654 ARMMMUIdxBit_S12NSE0
|
2656 raw_write(env
, ri
, value
);
2660 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo
[] = {
2661 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
2662 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
,
2663 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dfsr_s
),
2664 offsetoflow32(CPUARMState
, cp15
.dfsr_ns
) }, },
2665 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
2666 .access
= PL1_RW
, .resetvalue
= 0,
2667 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.ifsr_s
),
2668 offsetoflow32(CPUARMState
, cp15
.ifsr_ns
) } },
2669 { .name
= "DFAR", .cp
= 15, .opc1
= 0, .crn
= 6, .crm
= 0, .opc2
= 0,
2670 .access
= PL1_RW
, .resetvalue
= 0,
2671 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.dfar_s
),
2672 offsetof(CPUARMState
, cp15
.dfar_ns
) } },
2673 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_AA64
,
2674 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
2675 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[1]),
2680 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
2681 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
2682 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
2684 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[1]), .resetvalue
= 0, },
2685 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
2686 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 0,
2687 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2688 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2689 offsetof(CPUARMState
, cp15
.ttbr0_ns
) } },
2690 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
2691 .opc0
= 3, .opc1
= 0, .crn
= 2, .crm
= 0, .opc2
= 1,
2692 .access
= PL1_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
2693 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2694 offsetof(CPUARMState
, cp15
.ttbr1_ns
) } },
2695 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
2696 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2697 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
2698 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
2699 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[1]) },
2700 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
2701 .access
= PL1_RW
, .type
= ARM_CP_ALIAS
, .writefn
= vmsa_ttbcr_write
,
2702 .raw_writefn
= vmsa_ttbcr_raw_write
,
2703 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.tcr_el
[3]),
2704 offsetoflow32(CPUARMState
, cp15
.tcr_el
[1])} },
2708 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2711 env
->cp15
.c15_ticonfig
= value
& 0xe7;
2712 /* The OS_TYPE bit in this register changes the reported CPUID! */
2713 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
2714 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
2717 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2720 env
->cp15
.c15_threadid
= value
& 0xffff;
2723 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2726 /* Wait-for-interrupt (deprecated) */
2727 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
2730 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2733 /* On OMAP there are registers indicating the max/min index of dcache lines
2734 * containing a dirty line; cache flush operations have to reset these.
2736 env
->cp15
.c15_i_max
= 0x000;
2737 env
->cp15
.c15_i_min
= 0xff0;
2740 static const ARMCPRegInfo omap_cp_reginfo
[] = {
2741 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
2742 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
2743 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el
[1]),
2745 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2746 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2747 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2749 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
2750 .writefn
= omap_ticonfig_write
},
2751 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
2753 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
2754 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
2755 .access
= PL1_RW
, .resetvalue
= 0xff0,
2756 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
2757 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
2759 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
2760 .writefn
= omap_threadid_write
},
2761 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
2762 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2763 .type
= ARM_CP_NO_RAW
,
2764 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
2765 /* TODO: Peripheral port remap register:
2766 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2767 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2770 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
2771 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
2772 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
,
2773 .writefn
= omap_cachemaint_write
},
2774 { .name
= "C9", .cp
= 15, .crn
= 9,
2775 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
2776 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
2780 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2783 env
->cp15
.c15_cpar
= value
& 0x3fff;
2786 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
2787 { .name
= "XSCALE_CPAR",
2788 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
2789 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
2790 .writefn
= xscale_cpar_write
, },
2791 { .name
= "XSCALE_AUXCR",
2792 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
2793 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
2795 /* XScale specific cache-lockdown: since we have no cache we NOP these
2796 * and hope the guest does not really rely on cache behaviour.
2798 { .name
= "XSCALE_LOCK_ICACHE_LINE",
2799 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2800 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2801 { .name
= "XSCALE_UNLOCK_ICACHE",
2802 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2803 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2804 { .name
= "XSCALE_DCACHE_LOCK",
2805 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 0,
2806 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
2807 { .name
= "XSCALE_UNLOCK_DCACHE",
2808 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 2, .opc2
= 1,
2809 .access
= PL1_W
, .type
= ARM_CP_NOP
},
2813 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
2814 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2815 * implementation of this implementation-defined space.
2816 * Ideally this should eventually disappear in favour of actually
2817 * implementing the correct behaviour for all cores.
2819 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
2820 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2822 .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
| ARM_CP_OVERRIDE
,
2827 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
2828 /* Cache status: RAZ because we have no cache so it's always clean */
2829 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
2830 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2835 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
2836 /* We never have a a block transfer operation in progress */
2837 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
2838 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2840 /* The cache ops themselves: these all NOP for QEMU */
2841 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
2842 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2843 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
2844 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2845 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
2846 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2847 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
2848 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2849 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
2850 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2851 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
2852 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
2856 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
2857 /* The cache test-and-clean instructions always return (1 << 30)
2858 * to indicate that there are no dirty cache lines.
2860 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
2861 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2862 .resetvalue
= (1 << 30) },
2863 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
2864 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_RAW
,
2865 .resetvalue
= (1 << 30) },
2869 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
2870 /* Ignore ReadBuffer accesses */
2871 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
2872 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
2873 .access
= PL1_RW
, .resetvalue
= 0,
2874 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_RAW
},
2878 static uint64_t midr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2880 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2881 unsigned int cur_el
= arm_current_el(env
);
2882 bool secure
= arm_is_secure(env
);
2884 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2885 return env
->cp15
.vpidr_el2
;
2887 return raw_read(env
, ri
);
2890 static uint64_t mpidr_read_val(CPUARMState
*env
)
2892 ARMCPU
*cpu
= ARM_CPU(arm_env_get_cpu(env
));
2893 uint64_t mpidr
= cpu
->mp_affinity
;
2895 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
2896 mpidr
|= (1U << 31);
2897 /* Cores which are uniprocessor (non-coherent)
2898 * but still implement the MP extensions set
2899 * bit 30. (For instance, Cortex-R5).
2901 if (cpu
->mp_is_up
) {
2902 mpidr
|= (1u << 30);
2908 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2910 unsigned int cur_el
= arm_current_el(env
);
2911 bool secure
= arm_is_secure(env
);
2913 if (arm_feature(env
, ARM_FEATURE_EL2
) && !secure
&& cur_el
== 1) {
2914 return env
->cp15
.vmpidr_el2
;
2916 return mpidr_read_val(env
);
2919 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
2920 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
2921 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
2922 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_RAW
},
2926 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
2928 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
2929 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
2930 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2932 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2933 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
2934 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2936 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
2937 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .resetvalue
= 0,
2938 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.par_s
),
2939 offsetof(CPUARMState
, cp15
.par_ns
)} },
2940 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
2941 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2942 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr0_s
),
2943 offsetof(CPUARMState
, cp15
.ttbr0_ns
) },
2944 .writefn
= vmsa_ttbr_write
, },
2945 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
2946 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
2947 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.ttbr1_s
),
2948 offsetof(CPUARMState
, cp15
.ttbr1_ns
) },
2949 .writefn
= vmsa_ttbr_write
, },
2953 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2955 return vfp_get_fpcr(env
);
2958 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2961 vfp_set_fpcr(env
, value
);
2964 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2966 return vfp_get_fpsr(env
);
2969 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2972 vfp_set_fpsr(env
, value
);
2975 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2978 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
2979 return CP_ACCESS_TRAP
;
2981 return CP_ACCESS_OK
;
2984 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2987 env
->daif
= value
& PSTATE_DAIF
;
2990 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
2991 const ARMCPRegInfo
*ri
,
2994 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2995 * SCTLR_EL1.UCI is set.
2997 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCI
)) {
2998 return CP_ACCESS_TRAP
;
3000 return CP_ACCESS_OK
;
3003 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
3004 * Page D4-1736 (DDI0487A.b)
3007 static void tlbi_aa64_vmalle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3010 CPUState
*cs
= ENV_GET_CPU(env
);
3012 if (arm_is_secure_below_el3(env
)) {
3013 tlb_flush_by_mmuidx(cs
,
3014 ARMMMUIdxBit_S1SE1
|
3015 ARMMMUIdxBit_S1SE0
);
3017 tlb_flush_by_mmuidx(cs
,
3018 ARMMMUIdxBit_S12NSE1
|
3019 ARMMMUIdxBit_S12NSE0
);
3023 static void tlbi_aa64_vmalle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3026 CPUState
*cs
= ENV_GET_CPU(env
);
3027 bool sec
= arm_is_secure_below_el3(env
);
3030 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3031 ARMMMUIdxBit_S1SE1
|
3032 ARMMMUIdxBit_S1SE0
);
3034 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3035 ARMMMUIdxBit_S12NSE1
|
3036 ARMMMUIdxBit_S12NSE0
);
3040 static void tlbi_aa64_alle1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3043 /* Note that the 'ALL' scope must invalidate both stage 1 and
3044 * stage 2 translations, whereas most other scopes only invalidate
3045 * stage 1 translations.
3047 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3048 CPUState
*cs
= CPU(cpu
);
3050 if (arm_is_secure_below_el3(env
)) {
3051 tlb_flush_by_mmuidx(cs
,
3052 ARMMMUIdxBit_S1SE1
|
3053 ARMMMUIdxBit_S1SE0
);
3055 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
3056 tlb_flush_by_mmuidx(cs
,
3057 ARMMMUIdxBit_S12NSE1
|
3058 ARMMMUIdxBit_S12NSE0
|
3061 tlb_flush_by_mmuidx(cs
,
3062 ARMMMUIdxBit_S12NSE1
|
3063 ARMMMUIdxBit_S12NSE0
);
3068 static void tlbi_aa64_alle2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3071 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3072 CPUState
*cs
= CPU(cpu
);
3074 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E2
);
3077 static void tlbi_aa64_alle3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3080 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3081 CPUState
*cs
= CPU(cpu
);
3083 tlb_flush_by_mmuidx(cs
, ARMMMUIdxBit_S1E3
);
3086 static void tlbi_aa64_alle1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3089 /* Note that the 'ALL' scope must invalidate both stage 1 and
3090 * stage 2 translations, whereas most other scopes only invalidate
3091 * stage 1 translations.
3093 CPUState
*cs
= ENV_GET_CPU(env
);
3094 bool sec
= arm_is_secure_below_el3(env
);
3095 bool has_el2
= arm_feature(env
, ARM_FEATURE_EL2
);
3098 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3099 ARMMMUIdxBit_S1SE1
|
3100 ARMMMUIdxBit_S1SE0
);
3101 } else if (has_el2
) {
3102 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3103 ARMMMUIdxBit_S12NSE1
|
3104 ARMMMUIdxBit_S12NSE0
|
3107 tlb_flush_by_mmuidx_all_cpus_synced(cs
,
3108 ARMMMUIdxBit_S12NSE1
|
3109 ARMMMUIdxBit_S12NSE0
);
3113 static void tlbi_aa64_alle2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3116 CPUState
*cs
= ENV_GET_CPU(env
);
3118 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E2
);
3121 static void tlbi_aa64_alle3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3124 CPUState
*cs
= ENV_GET_CPU(env
);
3126 tlb_flush_by_mmuidx_all_cpus_synced(cs
, ARMMMUIdxBit_S1E3
);
3129 static void tlbi_aa64_vae1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3132 /* Invalidate by VA, EL1&0 (AArch64 version).
3133 * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
3134 * since we don't support flush-for-specific-ASID-only or
3135 * flush-last-level-only.
3137 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3138 CPUState
*cs
= CPU(cpu
);
3139 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3141 if (arm_is_secure_below_el3(env
)) {
3142 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3143 ARMMMUIdxBit_S1SE1
|
3144 ARMMMUIdxBit_S1SE0
);
3146 tlb_flush_page_by_mmuidx(cs
, pageaddr
,
3147 ARMMMUIdxBit_S12NSE1
|
3148 ARMMMUIdxBit_S12NSE0
);
3152 static void tlbi_aa64_vae2_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3155 /* Invalidate by VA, EL2
3156 * Currently handles both VAE2 and VALE2, since we don't support
3157 * flush-last-level-only.
3159 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3160 CPUState
*cs
= CPU(cpu
);
3161 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3163 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E2
);
3166 static void tlbi_aa64_vae3_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3169 /* Invalidate by VA, EL3
3170 * Currently handles both VAE3 and VALE3, since we don't support
3171 * flush-last-level-only.
3173 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3174 CPUState
*cs
= CPU(cpu
);
3175 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3177 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S1E3
);
3180 static void tlbi_aa64_vae1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3183 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3184 CPUState
*cs
= CPU(cpu
);
3185 bool sec
= arm_is_secure_below_el3(env
);
3186 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3189 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3190 ARMMMUIdxBit_S1SE1
|
3191 ARMMMUIdxBit_S1SE0
);
3193 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3194 ARMMMUIdxBit_S12NSE1
|
3195 ARMMMUIdxBit_S12NSE0
);
3199 static void tlbi_aa64_vae2is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3202 CPUState
*cs
= ENV_GET_CPU(env
);
3203 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3205 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3209 static void tlbi_aa64_vae3is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3212 CPUState
*cs
= ENV_GET_CPU(env
);
3213 uint64_t pageaddr
= sextract64(value
<< 12, 0, 56);
3215 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3219 static void tlbi_aa64_ipas2e1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3222 /* Invalidate by IPA. This has to invalidate any structures that
3223 * contain only stage 2 translation information, but does not need
3224 * to apply to structures that contain combined stage 1 and stage 2
3225 * translation information.
3226 * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
3228 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3229 CPUState
*cs
= CPU(cpu
);
3232 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3236 pageaddr
= sextract64(value
<< 12, 0, 48);
3238 tlb_flush_page_by_mmuidx(cs
, pageaddr
, ARMMMUIdxBit_S2NS
);
3241 static void tlbi_aa64_ipas2e1is_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3244 CPUState
*cs
= ENV_GET_CPU(env
);
3247 if (!arm_feature(env
, ARM_FEATURE_EL2
) || !(env
->cp15
.scr_el3
& SCR_NS
)) {
3251 pageaddr
= sextract64(value
<< 12, 0, 48);
3253 tlb_flush_page_by_mmuidx_all_cpus_synced(cs
, pageaddr
,
3257 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3260 /* We don't implement EL2, so the only control on DC ZVA is the
3261 * bit in the SCTLR which can prohibit access for EL0.
3263 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_DZE
)) {
3264 return CP_ACCESS_TRAP
;
3266 return CP_ACCESS_OK
;
3269 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3271 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3272 int dzp_bit
= 1 << 4;
3274 /* DZP indicates whether DC ZVA access is allowed */
3275 if (aa64_zva_access(env
, NULL
, false) == CP_ACCESS_OK
) {
3278 return cpu
->dcz_blocksize
| dzp_bit
;
3281 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3284 if (!(env
->pstate
& PSTATE_SP
)) {
3285 /* Access to SP_EL0 is undefined if it's being used as
3286 * the stack pointer.
3288 return CP_ACCESS_TRAP_UNCATEGORIZED
;
3290 return CP_ACCESS_OK
;
3293 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
3295 return env
->pstate
& PSTATE_SP
;
3298 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
3300 update_spsel(env
, val
);
3303 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3306 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3308 if (raw_read(env
, ri
) == value
) {
3309 /* Skip the TLB flush if nothing actually changed; Linux likes
3310 * to do a lot of pointless SCTLR writes.
3315 if (arm_feature(env
, ARM_FEATURE_PMSA
) && !cpu
->has_mpu
) {
3316 /* M bit is RAZ/WI for PMSA with no MPU implemented */
3320 raw_write(env
, ri
, value
);
3321 /* ??? Lots of these bits are not implemented. */
3322 /* This may enable/disable the MMU, so do a TLB flush. */
3323 tlb_flush(CPU(cpu
));
3326 static CPAccessResult
fpexc32_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3329 if ((env
->cp15
.cptr_el
[2] & CPTR_TFP
) && arm_current_el(env
) == 2) {
3330 return CP_ACCESS_TRAP_FP_EL2
;
3332 if (env
->cp15
.cptr_el
[3] & CPTR_TFP
) {
3333 return CP_ACCESS_TRAP_FP_EL3
;
3335 return CP_ACCESS_OK
;
3338 static void sdcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
3341 env
->cp15
.mdcr_el3
= value
& SDCR_VALID_MASK
;
3344 static const ARMCPRegInfo v8_cp_reginfo
[] = {
3345 /* Minimal set of EL0-visible registers. This will need to be expanded
3346 * significantly for system emulation of AArch64 CPUs.
3348 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
3349 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
3350 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
3351 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
3352 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
3353 .type
= ARM_CP_NO_RAW
,
3354 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
3355 .fieldoffset
= offsetof(CPUARMState
, daif
),
3356 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
3357 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
3358 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
3359 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
3360 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
3361 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
3362 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
3363 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
3364 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
3365 .access
= PL0_R
, .type
= ARM_CP_NO_RAW
,
3366 .readfn
= aa64_dczid_read
},
3367 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
3368 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
3369 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
3370 #ifndef CONFIG_USER_ONLY
3371 /* Avoid overhead of an access check that always passes in user-mode */
3372 .accessfn
= aa64_zva_access
,
3375 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
3376 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
3377 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
3378 /* Cache ops: all NOPs since we don't emulate caches */
3379 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
3380 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3381 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3382 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
3383 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3384 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3385 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
3386 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
3387 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3388 .accessfn
= aa64_cacheop_access
},
3389 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
3390 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3391 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3392 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
3393 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3394 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3395 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
3396 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
3397 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3398 .accessfn
= aa64_cacheop_access
},
3399 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
3400 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3401 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3402 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
3403 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
3404 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3405 .accessfn
= aa64_cacheop_access
},
3406 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
3407 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
3408 .access
= PL0_W
, .type
= ARM_CP_NOP
,
3409 .accessfn
= aa64_cacheop_access
},
3410 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
3411 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3412 .access
= PL1_W
, .type
= ARM_CP_NOP
},
3413 /* TLBI operations */
3414 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
3415 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
3416 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3417 .writefn
= tlbi_aa64_vmalle1is_write
},
3418 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
3419 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
3420 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3421 .writefn
= tlbi_aa64_vae1is_write
},
3422 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
3423 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
3424 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3425 .writefn
= tlbi_aa64_vmalle1is_write
},
3426 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
3427 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
3428 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3429 .writefn
= tlbi_aa64_vae1is_write
},
3430 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
3431 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3432 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3433 .writefn
= tlbi_aa64_vae1is_write
},
3434 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
3435 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3436 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3437 .writefn
= tlbi_aa64_vae1is_write
},
3438 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
3439 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
3440 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3441 .writefn
= tlbi_aa64_vmalle1_write
},
3442 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
3443 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
3444 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3445 .writefn
= tlbi_aa64_vae1_write
},
3446 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
3447 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
3448 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3449 .writefn
= tlbi_aa64_vmalle1_write
},
3450 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
3451 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
3452 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3453 .writefn
= tlbi_aa64_vae1_write
},
3454 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
3455 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3456 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3457 .writefn
= tlbi_aa64_vae1_write
},
3458 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
3459 .opc0
= 1, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3460 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
3461 .writefn
= tlbi_aa64_vae1_write
},
3462 { .name
= "TLBI_IPAS2E1IS", .state
= ARM_CP_STATE_AA64
,
3463 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3464 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3465 .writefn
= tlbi_aa64_ipas2e1is_write
},
3466 { .name
= "TLBI_IPAS2LE1IS", .state
= ARM_CP_STATE_AA64
,
3467 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3468 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3469 .writefn
= tlbi_aa64_ipas2e1is_write
},
3470 { .name
= "TLBI_ALLE1IS", .state
= ARM_CP_STATE_AA64
,
3471 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3472 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3473 .writefn
= tlbi_aa64_alle1is_write
},
3474 { .name
= "TLBI_VMALLS12E1IS", .state
= ARM_CP_STATE_AA64
,
3475 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 6,
3476 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3477 .writefn
= tlbi_aa64_alle1is_write
},
3478 { .name
= "TLBI_IPAS2E1", .state
= ARM_CP_STATE_AA64
,
3479 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3480 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3481 .writefn
= tlbi_aa64_ipas2e1_write
},
3482 { .name
= "TLBI_IPAS2LE1", .state
= ARM_CP_STATE_AA64
,
3483 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3484 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3485 .writefn
= tlbi_aa64_ipas2e1_write
},
3486 { .name
= "TLBI_ALLE1", .state
= ARM_CP_STATE_AA64
,
3487 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3488 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3489 .writefn
= tlbi_aa64_alle1_write
},
3490 { .name
= "TLBI_VMALLS12E1", .state
= ARM_CP_STATE_AA64
,
3491 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 6,
3492 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3493 .writefn
= tlbi_aa64_alle1is_write
},
3494 #ifndef CONFIG_USER_ONLY
3495 /* 64 bit address translation operations */
3496 { .name
= "AT_S1E1R", .state
= ARM_CP_STATE_AA64
,
3497 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 0,
3498 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3499 { .name
= "AT_S1E1W", .state
= ARM_CP_STATE_AA64
,
3500 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 1,
3501 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3502 { .name
= "AT_S1E0R", .state
= ARM_CP_STATE_AA64
,
3503 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 2,
3504 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3505 { .name
= "AT_S1E0W", .state
= ARM_CP_STATE_AA64
,
3506 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 8, .opc2
= 3,
3507 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3508 { .name
= "AT_S12E1R", .state
= ARM_CP_STATE_AA64
,
3509 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 4,
3510 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3511 { .name
= "AT_S12E1W", .state
= ARM_CP_STATE_AA64
,
3512 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 5,
3513 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3514 { .name
= "AT_S12E0R", .state
= ARM_CP_STATE_AA64
,
3515 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 6,
3516 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3517 { .name
= "AT_S12E0W", .state
= ARM_CP_STATE_AA64
,
3518 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 7,
3519 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3520 /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3521 { .name
= "AT_S1E3R", .state
= ARM_CP_STATE_AA64
,
3522 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 0,
3523 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3524 { .name
= "AT_S1E3W", .state
= ARM_CP_STATE_AA64
,
3525 .opc0
= 1, .opc1
= 6, .crn
= 7, .crm
= 8, .opc2
= 1,
3526 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3527 { .name
= "PAR_EL1", .state
= ARM_CP_STATE_AA64
,
3528 .type
= ARM_CP_ALIAS
,
3529 .opc0
= 3, .opc1
= 0, .crn
= 7, .crm
= 4, .opc2
= 0,
3530 .access
= PL1_RW
, .resetvalue
= 0,
3531 .fieldoffset
= offsetof(CPUARMState
, cp15
.par_el
[1]),
3532 .writefn
= par_write
},
3534 /* TLB invalidate last level of translation table walk */
3535 { .name
= "TLBIMVALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
3536 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_is_write
},
3537 { .name
= "TLBIMVAALIS", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
3538 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
,
3539 .writefn
= tlbimvaa_is_write
},
3540 { .name
= "TLBIMVAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
3541 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimva_write
},
3542 { .name
= "TLBIMVAAL", .cp
= 15, .opc1
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
3543 .type
= ARM_CP_NO_RAW
, .access
= PL1_W
, .writefn
= tlbimvaa_write
},
3544 { .name
= "TLBIMVALH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3545 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3546 .writefn
= tlbimva_hyp_write
},
3547 { .name
= "TLBIMVALHIS",
3548 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3549 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3550 .writefn
= tlbimva_hyp_is_write
},
3551 { .name
= "TLBIIPAS2",
3552 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 1,
3553 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3554 .writefn
= tlbiipas2_write
},
3555 { .name
= "TLBIIPAS2IS",
3556 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 1,
3557 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3558 .writefn
= tlbiipas2_is_write
},
3559 { .name
= "TLBIIPAS2L",
3560 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 4, .opc2
= 5,
3561 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3562 .writefn
= tlbiipas2_write
},
3563 { .name
= "TLBIIPAS2LIS",
3564 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 0, .opc2
= 5,
3565 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3566 .writefn
= tlbiipas2_is_write
},
3567 /* 32 bit cache operations */
3568 { .name
= "ICIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
3569 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3570 { .name
= "BPIALLUIS", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 6,
3571 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3572 { .name
= "ICIALLU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
3573 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3574 { .name
= "ICIMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 1,
3575 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3576 { .name
= "BPIALL", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 6,
3577 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3578 { .name
= "BPIMVA", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 7,
3579 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3580 { .name
= "DCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
3581 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3582 { .name
= "DCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
3583 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3584 { .name
= "DCCMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 1,
3585 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3586 { .name
= "DCCSW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
3587 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3588 { .name
= "DCCMVAU", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 11, .opc2
= 1,
3589 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3590 { .name
= "DCCIMVAC", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 1,
3591 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3592 { .name
= "DCCISW", .cp
= 15, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
3593 .type
= ARM_CP_NOP
, .access
= PL1_W
},
3594 /* MMU Domain access control / MPU write buffer control */
3595 { .name
= "DACR", .cp
= 15, .opc1
= 0, .crn
= 3, .crm
= 0, .opc2
= 0,
3596 .access
= PL1_RW
, .resetvalue
= 0,
3597 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3598 .bank_fieldoffsets
= { offsetoflow32(CPUARMState
, cp15
.dacr_s
),
3599 offsetoflow32(CPUARMState
, cp15
.dacr_ns
) } },
3600 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
3601 .type
= ARM_CP_ALIAS
,
3602 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
3604 .fieldoffset
= offsetof(CPUARMState
, elr_el
[1]) },
3605 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
3606 .type
= ARM_CP_ALIAS
,
3607 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
3609 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_SVC
]) },
3610 /* We rely on the access checks not allowing the guest to write to the
3611 * state field when SPSel indicates that it's being used as the stack
3614 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
3615 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
3616 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
3617 .type
= ARM_CP_ALIAS
,
3618 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
3619 { .name
= "SP_EL1", .state
= ARM_CP_STATE_AA64
,
3620 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 1, .opc2
= 0,
3621 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3622 .fieldoffset
= offsetof(CPUARMState
, sp_el
[1]) },
3623 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
3624 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
3625 .type
= ARM_CP_NO_RAW
,
3626 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
3627 { .name
= "FPEXC32_EL2", .state
= ARM_CP_STATE_AA64
,
3628 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 3, .opc2
= 0,
3629 .type
= ARM_CP_ALIAS
,
3630 .fieldoffset
= offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPEXC
]),
3631 .access
= PL2_RW
, .accessfn
= fpexc32_access
},
3632 { .name
= "DACR32_EL2", .state
= ARM_CP_STATE_AA64
,
3633 .opc0
= 3, .opc1
= 4, .crn
= 3, .crm
= 0, .opc2
= 0,
3634 .access
= PL2_RW
, .resetvalue
= 0,
3635 .writefn
= dacr_write
, .raw_writefn
= raw_write
,
3636 .fieldoffset
= offsetof(CPUARMState
, cp15
.dacr32_el2
) },
3637 { .name
= "IFSR32_EL2", .state
= ARM_CP_STATE_AA64
,
3638 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 0, .opc2
= 1,
3639 .access
= PL2_RW
, .resetvalue
= 0,
3640 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr32_el2
) },
3641 { .name
= "SPSR_IRQ", .state
= ARM_CP_STATE_AA64
,
3642 .type
= ARM_CP_ALIAS
,
3643 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 0,
3645 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_IRQ
]) },
3646 { .name
= "SPSR_ABT", .state
= ARM_CP_STATE_AA64
,
3647 .type
= ARM_CP_ALIAS
,
3648 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 1,
3650 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_ABT
]) },
3651 { .name
= "SPSR_UND", .state
= ARM_CP_STATE_AA64
,
3652 .type
= ARM_CP_ALIAS
,
3653 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 2,
3655 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_UND
]) },
3656 { .name
= "SPSR_FIQ", .state
= ARM_CP_STATE_AA64
,
3657 .type
= ARM_CP_ALIAS
,
3658 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 3, .opc2
= 3,
3660 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_FIQ
]) },
3661 { .name
= "MDCR_EL3", .state
= ARM_CP_STATE_AA64
,
3662 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 3, .opc2
= 1,
3664 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el3
) },
3665 { .name
= "SDCR", .type
= ARM_CP_ALIAS
,
3666 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 1,
3667 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
3668 .writefn
= sdcr_write
,
3669 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mdcr_el3
) },
3673 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
3674 static const ARMCPRegInfo el3_no_el2_cp_reginfo
[] = {
3675 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3676 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3678 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3679 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3680 .type
= ARM_CP_NO_RAW
,
3681 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3683 .readfn
= arm_cp_read_zero
, .writefn
= arm_cp_write_ignore
},
3684 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3685 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3686 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3687 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3688 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3689 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3691 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3692 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3693 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3694 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3695 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3696 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3698 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3699 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3700 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3702 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3703 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3704 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3706 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3707 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3708 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3710 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3711 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3712 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3713 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3714 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3715 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3716 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3717 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3718 .cp
= 15, .opc1
= 6, .crm
= 2,
3719 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3720 .type
= ARM_CP_CONST
| ARM_CP_64BIT
, .resetvalue
= 0 },
3721 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3722 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3723 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3724 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3725 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3726 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3727 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3728 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3729 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3730 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3731 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3732 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3733 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3734 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3736 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3737 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3738 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3739 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3740 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3741 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3742 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3743 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3745 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3746 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3747 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3748 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3749 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_CONST
,
3751 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
3752 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
3753 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3754 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3755 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
3756 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3757 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3758 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
3759 .access
= PL2_RW
, .accessfn
= access_tda
,
3760 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3761 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_BOTH
,
3762 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
3763 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
3764 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3765 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3766 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
3767 .access
= PL2_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
3771 static void hcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
3773 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3774 uint64_t valid_mask
= HCR_MASK
;
3776 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
3777 valid_mask
&= ~HCR_HCD
;
3778 } else if (cpu
->psci_conduit
!= QEMU_PSCI_CONDUIT_SMC
) {
3779 /* Architecturally HCR.TSC is RES0 if EL3 is not implemented.
3780 * However, if we're using the SMC PSCI conduit then QEMU is
3781 * effectively acting like EL3 firmware and so the guest at
3782 * EL2 should retain the ability to prevent EL1 from being
3783 * able to make SMC calls into the ersatz firmware, so in
3784 * that case HCR.TSC should be read/write.
3786 valid_mask
&= ~HCR_TSC
;
3789 /* Clear RES0 bits. */
3790 value
&= valid_mask
;
3792 /* These bits change the MMU setup:
3793 * HCR_VM enables stage 2 translation
3794 * HCR_PTW forbids certain page-table setups
3795 * HCR_DC Disables stage1 and enables stage2 translation
3797 if ((raw_read(env
, ri
) ^ value
) & (HCR_VM
| HCR_PTW
| HCR_DC
)) {
3798 tlb_flush(CPU(cpu
));
3800 raw_write(env
, ri
, value
);
3803 static const ARMCPRegInfo el2_cp_reginfo
[] = {
3804 { .name
= "HCR_EL2", .state
= ARM_CP_STATE_AA64
,
3805 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 0,
3806 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.hcr_el2
),
3807 .writefn
= hcr_write
},
3808 { .name
= "ELR_EL2", .state
= ARM_CP_STATE_AA64
,
3809 .type
= ARM_CP_ALIAS
,
3810 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 1,
3812 .fieldoffset
= offsetof(CPUARMState
, elr_el
[2]) },
3813 { .name
= "ESR_EL2", .state
= ARM_CP_STATE_AA64
,
3814 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 2, .opc2
= 0,
3815 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[2]) },
3816 { .name
= "FAR_EL2", .state
= ARM_CP_STATE_AA64
,
3817 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 0,
3818 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[2]) },
3819 { .name
= "SPSR_EL2", .state
= ARM_CP_STATE_AA64
,
3820 .type
= ARM_CP_ALIAS
,
3821 .opc0
= 3, .opc1
= 4, .crn
= 4, .crm
= 0, .opc2
= 0,
3823 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_HYP
]) },
3824 { .name
= "VBAR_EL2", .state
= ARM_CP_STATE_AA64
,
3825 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 0,
3826 .access
= PL2_RW
, .writefn
= vbar_write
,
3827 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[2]),
3829 { .name
= "SP_EL2", .state
= ARM_CP_STATE_AA64
,
3830 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 1, .opc2
= 0,
3831 .access
= PL3_RW
, .type
= ARM_CP_ALIAS
,
3832 .fieldoffset
= offsetof(CPUARMState
, sp_el
[2]) },
3833 { .name
= "CPTR_EL2", .state
= ARM_CP_STATE_BOTH
,
3834 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 2,
3835 .access
= PL2_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
3836 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[2]) },
3837 { .name
= "MAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3838 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 0,
3839 .access
= PL2_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el
[2]),
3841 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3842 .opc1
= 4, .crn
= 10, .crm
= 2, .opc2
= 1,
3843 .access
= PL2_RW
, .type
= ARM_CP_ALIAS
,
3844 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el
[2]) },
3845 { .name
= "AMAIR_EL2", .state
= ARM_CP_STATE_BOTH
,
3846 .opc0
= 3, .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 0,
3847 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3849 /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3850 { .name
= "HMAIR1", .state
= ARM_CP_STATE_AA32
,
3851 .opc1
= 4, .crn
= 10, .crm
= 3, .opc2
= 1,
3852 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3854 { .name
= "AFSR0_EL2", .state
= ARM_CP_STATE_BOTH
,
3855 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 0,
3856 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3858 { .name
= "AFSR1_EL2", .state
= ARM_CP_STATE_BOTH
,
3859 .opc0
= 3, .opc1
= 4, .crn
= 5, .crm
= 1, .opc2
= 1,
3860 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
3862 { .name
= "TCR_EL2", .state
= ARM_CP_STATE_BOTH
,
3863 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 2,
3865 /* no .writefn needed as this can't cause an ASID change;
3866 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3868 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[2]) },
3869 { .name
= "VTCR", .state
= ARM_CP_STATE_AA32
,
3870 .cp
= 15, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3871 .type
= ARM_CP_ALIAS
,
3872 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3873 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3874 { .name
= "VTCR_EL2", .state
= ARM_CP_STATE_AA64
,
3875 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 2,
3877 /* no .writefn needed as this can't cause an ASID change;
3878 * no .raw_writefn or .resetfn needed as we never use mask/base_mask
3880 .fieldoffset
= offsetof(CPUARMState
, cp15
.vtcr_el2
) },
3881 { .name
= "VTTBR", .state
= ARM_CP_STATE_AA32
,
3882 .cp
= 15, .opc1
= 6, .crm
= 2,
3883 .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3884 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
3885 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
),
3886 .writefn
= vttbr_write
},
3887 { .name
= "VTTBR_EL2", .state
= ARM_CP_STATE_AA64
,
3888 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 1, .opc2
= 0,
3889 .access
= PL2_RW
, .writefn
= vttbr_write
,
3890 .fieldoffset
= offsetof(CPUARMState
, cp15
.vttbr_el2
) },
3891 { .name
= "SCTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
3892 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 0,
3893 .access
= PL2_RW
, .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
3894 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[2]) },
3895 { .name
= "TPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
3896 .opc0
= 3, .opc1
= 4, .crn
= 13, .crm
= 0, .opc2
= 2,
3897 .access
= PL2_RW
, .resetvalue
= 0,
3898 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[2]) },
3899 { .name
= "TTBR0_EL2", .state
= ARM_CP_STATE_AA64
,
3900 .opc0
= 3, .opc1
= 4, .crn
= 2, .crm
= 0, .opc2
= 0,
3901 .access
= PL2_RW
, .resetvalue
= 0,
3902 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3903 { .name
= "HTTBR", .cp
= 15, .opc1
= 4, .crm
= 2,
3904 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
,
3905 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[2]) },
3906 { .name
= "TLBIALLNSNH",
3907 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 4,
3908 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3909 .writefn
= tlbiall_nsnh_write
},
3910 { .name
= "TLBIALLNSNHIS",
3911 .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 4,
3912 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3913 .writefn
= tlbiall_nsnh_is_write
},
3914 { .name
= "TLBIALLH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3915 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3916 .writefn
= tlbiall_hyp_write
},
3917 { .name
= "TLBIALLHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3918 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3919 .writefn
= tlbiall_hyp_is_write
},
3920 { .name
= "TLBIMVAH", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3921 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3922 .writefn
= tlbimva_hyp_write
},
3923 { .name
= "TLBIMVAHIS", .cp
= 15, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3924 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3925 .writefn
= tlbimva_hyp_is_write
},
3926 { .name
= "TLBI_ALLE2", .state
= ARM_CP_STATE_AA64
,
3927 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 0,
3928 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3929 .writefn
= tlbi_aa64_alle2_write
},
3930 { .name
= "TLBI_VAE2", .state
= ARM_CP_STATE_AA64
,
3931 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 1,
3932 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3933 .writefn
= tlbi_aa64_vae2_write
},
3934 { .name
= "TLBI_VALE2", .state
= ARM_CP_STATE_AA64
,
3935 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 7, .opc2
= 5,
3936 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3937 .writefn
= tlbi_aa64_vae2_write
},
3938 { .name
= "TLBI_ALLE2IS", .state
= ARM_CP_STATE_AA64
,
3939 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 0,
3940 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3941 .writefn
= tlbi_aa64_alle2is_write
},
3942 { .name
= "TLBI_VAE2IS", .state
= ARM_CP_STATE_AA64
,
3943 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 1,
3944 .type
= ARM_CP_NO_RAW
, .access
= PL2_W
,
3945 .writefn
= tlbi_aa64_vae2is_write
},
3946 { .name
= "TLBI_VALE2IS", .state
= ARM_CP_STATE_AA64
,
3947 .opc0
= 1, .opc1
= 4, .crn
= 8, .crm
= 3, .opc2
= 5,
3948 .access
= PL2_W
, .type
= ARM_CP_NO_RAW
,
3949 .writefn
= tlbi_aa64_vae2is_write
},
3950 #ifndef CONFIG_USER_ONLY
3951 /* Unlike the other EL2-related AT operations, these must
3952 * UNDEF from EL3 if EL2 is not implemented, which is why we
3953 * define them here rather than with the rest of the AT ops.
3955 { .name
= "AT_S1E2R", .state
= ARM_CP_STATE_AA64
,
3956 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3957 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3958 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3959 { .name
= "AT_S1E2W", .state
= ARM_CP_STATE_AA64
,
3960 .opc0
= 1, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3961 .access
= PL2_W
, .accessfn
= at_s1e2_access
,
3962 .type
= ARM_CP_NO_RAW
, .writefn
= ats_write64
},
3963 /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3964 * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3965 * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3966 * to behave as if SCR.NS was 1.
3968 { .name
= "ATS1HR", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 0,
3970 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3971 { .name
= "ATS1HW", .cp
= 15, .opc1
= 4, .crn
= 7, .crm
= 8, .opc2
= 1,
3973 .writefn
= ats1h_write
, .type
= ARM_CP_NO_RAW
},
3974 { .name
= "CNTHCTL_EL2", .state
= ARM_CP_STATE_BOTH
,
3975 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 1, .opc2
= 0,
3976 /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3977 * reset values as IMPDEF. We choose to reset to 3 to comply with
3978 * both ARMv7 and ARMv8.
3980 .access
= PL2_RW
, .resetvalue
= 3,
3981 .fieldoffset
= offsetof(CPUARMState
, cp15
.cnthctl_el2
) },
3982 { .name
= "CNTVOFF_EL2", .state
= ARM_CP_STATE_AA64
,
3983 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 0, .opc2
= 3,
3984 .access
= PL2_RW
, .type
= ARM_CP_IO
, .resetvalue
= 0,
3985 .writefn
= gt_cntvoff_write
,
3986 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3987 { .name
= "CNTVOFF", .cp
= 15, .opc1
= 4, .crm
= 14,
3988 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_ALIAS
| ARM_CP_IO
,
3989 .writefn
= gt_cntvoff_write
,
3990 .fieldoffset
= offsetof(CPUARMState
, cp15
.cntvoff_el2
) },
3991 { .name
= "CNTHP_CVAL_EL2", .state
= ARM_CP_STATE_AA64
,
3992 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 2,
3993 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3994 .type
= ARM_CP_IO
, .access
= PL2_RW
,
3995 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
3996 { .name
= "CNTHP_CVAL", .cp
= 15, .opc1
= 6, .crm
= 14,
3997 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].cval
),
3998 .access
= PL2_RW
, .type
= ARM_CP_64BIT
| ARM_CP_IO
,
3999 .writefn
= gt_hyp_cval_write
, .raw_writefn
= raw_write
},
4000 { .name
= "CNTHP_TVAL_EL2", .state
= ARM_CP_STATE_BOTH
,
4001 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 0,
4002 .type
= ARM_CP_NO_RAW
| ARM_CP_IO
, .access
= PL2_RW
,
4003 .resetfn
= gt_hyp_timer_reset
,
4004 .readfn
= gt_hyp_tval_read
, .writefn
= gt_hyp_tval_write
},
4005 { .name
= "CNTHP_CTL_EL2", .state
= ARM_CP_STATE_BOTH
,
4007 .opc0
= 3, .opc1
= 4, .crn
= 14, .crm
= 2, .opc2
= 1,
4009 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_HYP
].ctl
),
4011 .writefn
= gt_hyp_ctl_write
, .raw_writefn
= raw_write
},
4013 /* The only field of MDCR_EL2 that has a defined architectural reset value
4014 * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
4015 * don't impelment any PMU event counters, so using zero as a reset
4016 * value for MDCR_EL2 is okay
4018 { .name
= "MDCR_EL2", .state
= ARM_CP_STATE_BOTH
,
4019 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 1,
4020 .access
= PL2_RW
, .resetvalue
= 0,
4021 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdcr_el2
), },
4022 { .name
= "HPFAR", .state
= ARM_CP_STATE_AA32
,
4023 .cp
= 15, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4024 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4025 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4026 { .name
= "HPFAR_EL2", .state
= ARM_CP_STATE_AA64
,
4027 .opc0
= 3, .opc1
= 4, .crn
= 6, .crm
= 0, .opc2
= 4,
4029 .fieldoffset
= offsetof(CPUARMState
, cp15
.hpfar_el2
) },
4030 { .name
= "HSTR_EL2", .state
= ARM_CP_STATE_BOTH
,
4031 .cp
= 15, .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 1, .opc2
= 3,
4033 .fieldoffset
= offsetof(CPUARMState
, cp15
.hstr_el2
) },
4037 static CPAccessResult
nsacr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4040 /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
4041 * At Secure EL1 it traps to EL3.
4043 if (arm_current_el(env
) == 3) {
4044 return CP_ACCESS_OK
;
4046 if (arm_is_secure_below_el3(env
)) {
4047 return CP_ACCESS_TRAP_EL3
;
4049 /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
4051 return CP_ACCESS_OK
;
4053 return CP_ACCESS_TRAP_UNCATEGORIZED
;
4056 static const ARMCPRegInfo el3_cp_reginfo
[] = {
4057 { .name
= "SCR_EL3", .state
= ARM_CP_STATE_AA64
,
4058 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 0,
4059 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.scr_el3
),
4060 .resetvalue
= 0, .writefn
= scr_write
},
4061 { .name
= "SCR", .type
= ARM_CP_ALIAS
,
4062 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 0,
4063 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4064 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.scr_el3
),
4065 .writefn
= scr_write
},
4066 { .name
= "SDER32_EL3", .state
= ARM_CP_STATE_AA64
,
4067 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 1,
4068 .access
= PL3_RW
, .resetvalue
= 0,
4069 .fieldoffset
= offsetof(CPUARMState
, cp15
.sder
) },
4071 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 1,
4072 .access
= PL3_RW
, .resetvalue
= 0,
4073 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.sder
) },
4074 { .name
= "MVBAR", .cp
= 15, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4075 .access
= PL1_RW
, .accessfn
= access_trap_aa32s_el1
,
4076 .writefn
= vbar_write
, .resetvalue
= 0,
4077 .fieldoffset
= offsetof(CPUARMState
, cp15
.mvbar
) },
4078 { .name
= "TTBR0_EL3", .state
= ARM_CP_STATE_AA64
,
4079 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 0,
4080 .access
= PL3_RW
, .writefn
= vmsa_ttbr_write
, .resetvalue
= 0,
4081 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el
[3]) },
4082 { .name
= "TCR_EL3", .state
= ARM_CP_STATE_AA64
,
4083 .opc0
= 3, .opc1
= 6, .crn
= 2, .crm
= 0, .opc2
= 2,
4085 /* no .writefn needed as this can't cause an ASID change;
4086 * we must provide a .raw_writefn and .resetfn because we handle
4087 * reset and migration for the AArch32 TTBCR(S), which might be
4088 * using mask and base_mask.
4090 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= vmsa_ttbcr_raw_write
,
4091 .fieldoffset
= offsetof(CPUARMState
, cp15
.tcr_el
[3]) },
4092 { .name
= "ELR_EL3", .state
= ARM_CP_STATE_AA64
,
4093 .type
= ARM_CP_ALIAS
,
4094 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 1,
4096 .fieldoffset
= offsetof(CPUARMState
, elr_el
[3]) },
4097 { .name
= "ESR_EL3", .state
= ARM_CP_STATE_AA64
,
4098 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 2, .opc2
= 0,
4099 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el
[3]) },
4100 { .name
= "FAR_EL3", .state
= ARM_CP_STATE_AA64
,
4101 .opc0
= 3, .opc1
= 6, .crn
= 6, .crm
= 0, .opc2
= 0,
4102 .access
= PL3_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el
[3]) },
4103 { .name
= "SPSR_EL3", .state
= ARM_CP_STATE_AA64
,
4104 .type
= ARM_CP_ALIAS
,
4105 .opc0
= 3, .opc1
= 6, .crn
= 4, .crm
= 0, .opc2
= 0,
4107 .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[BANK_MON
]) },
4108 { .name
= "VBAR_EL3", .state
= ARM_CP_STATE_AA64
,
4109 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 0,
4110 .access
= PL3_RW
, .writefn
= vbar_write
,
4111 .fieldoffset
= offsetof(CPUARMState
, cp15
.vbar_el
[3]),
4113 { .name
= "CPTR_EL3", .state
= ARM_CP_STATE_AA64
,
4114 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 1, .opc2
= 2,
4115 .access
= PL3_RW
, .accessfn
= cptr_access
, .resetvalue
= 0,
4116 .fieldoffset
= offsetof(CPUARMState
, cp15
.cptr_el
[3]) },
4117 { .name
= "TPIDR_EL3", .state
= ARM_CP_STATE_AA64
,
4118 .opc0
= 3, .opc1
= 6, .crn
= 13, .crm
= 0, .opc2
= 2,
4119 .access
= PL3_RW
, .resetvalue
= 0,
4120 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el
[3]) },
4121 { .name
= "AMAIR_EL3", .state
= ARM_CP_STATE_AA64
,
4122 .opc0
= 3, .opc1
= 6, .crn
= 10, .crm
= 3, .opc2
= 0,
4123 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4125 { .name
= "AFSR0_EL3", .state
= ARM_CP_STATE_BOTH
,
4126 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 0,
4127 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4129 { .name
= "AFSR1_EL3", .state
= ARM_CP_STATE_BOTH
,
4130 .opc0
= 3, .opc1
= 6, .crn
= 5, .crm
= 1, .opc2
= 1,
4131 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
4133 { .name
= "TLBI_ALLE3IS", .state
= ARM_CP_STATE_AA64
,
4134 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 0,
4135 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4136 .writefn
= tlbi_aa64_alle3is_write
},
4137 { .name
= "TLBI_VAE3IS", .state
= ARM_CP_STATE_AA64
,
4138 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 1,
4139 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4140 .writefn
= tlbi_aa64_vae3is_write
},
4141 { .name
= "TLBI_VALE3IS", .state
= ARM_CP_STATE_AA64
,
4142 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 3, .opc2
= 5,
4143 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4144 .writefn
= tlbi_aa64_vae3is_write
},
4145 { .name
= "TLBI_ALLE3", .state
= ARM_CP_STATE_AA64
,
4146 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 0,
4147 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4148 .writefn
= tlbi_aa64_alle3_write
},
4149 { .name
= "TLBI_VAE3", .state
= ARM_CP_STATE_AA64
,
4150 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 1,
4151 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4152 .writefn
= tlbi_aa64_vae3_write
},
4153 { .name
= "TLBI_VALE3", .state
= ARM_CP_STATE_AA64
,
4154 .opc0
= 1, .opc1
= 6, .crn
= 8, .crm
= 7, .opc2
= 5,
4155 .access
= PL3_W
, .type
= ARM_CP_NO_RAW
,
4156 .writefn
= tlbi_aa64_vae3_write
},
4160 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4163 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
4164 * but the AArch32 CTR has its own reginfo struct)
4166 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UCT
)) {
4167 return CP_ACCESS_TRAP
;
4169 return CP_ACCESS_OK
;
4172 static void oslar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4175 /* Writes to OSLAR_EL1 may update the OS lock status, which can be
4176 * read via a bit in OSLSR_EL1.
4180 if (ri
->state
== ARM_CP_STATE_AA32
) {
4181 oslock
= (value
== 0xC5ACCE55);
4186 env
->cp15
.oslsr_el1
= deposit32(env
->cp15
.oslsr_el1
, 1, 1, oslock
);
4189 static const ARMCPRegInfo debug_cp_reginfo
[] = {
4190 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
4191 * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
4192 * unlike DBGDRAR it is never accessible from EL0.
4193 * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
4196 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
4197 .access
= PL0_R
, .accessfn
= access_tdra
,
4198 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4199 { .name
= "MDRAR_EL1", .state
= ARM_CP_STATE_AA64
,
4200 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
4201 .access
= PL1_R
, .accessfn
= access_tdra
,
4202 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4203 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
4204 .access
= PL0_R
, .accessfn
= access_tdra
,
4205 .type
= ARM_CP_CONST
, .resetvalue
= 0 },
4206 /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
4207 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_BOTH
,
4208 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4209 .access
= PL1_RW
, .accessfn
= access_tda
,
4210 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
),
4212 /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
4213 * We don't implement the configurable EL0 access.
4215 { .name
= "MDCCSR_EL0", .state
= ARM_CP_STATE_BOTH
,
4216 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4217 .type
= ARM_CP_ALIAS
,
4218 .access
= PL1_R
, .accessfn
= access_tda
,
4219 .fieldoffset
= offsetof(CPUARMState
, cp15
.mdscr_el1
), },
4220 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_BOTH
,
4221 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
4222 .access
= PL1_W
, .type
= ARM_CP_NO_RAW
,
4223 .accessfn
= access_tdosa
,
4224 .writefn
= oslar_write
},
4225 { .name
= "OSLSR_EL1", .state
= ARM_CP_STATE_BOTH
,
4226 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 4,
4227 .access
= PL1_R
, .resetvalue
= 10,
4228 .accessfn
= access_tdosa
,
4229 .fieldoffset
= offsetof(CPUARMState
, cp15
.oslsr_el1
) },
4230 /* Dummy OSDLR_EL1: 32-bit Linux will read this */
4231 { .name
= "OSDLR_EL1", .state
= ARM_CP_STATE_BOTH
,
4232 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 3, .opc2
= 4,
4233 .access
= PL1_RW
, .accessfn
= access_tdosa
,
4234 .type
= ARM_CP_NOP
},
4235 /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
4236 * implement vector catch debug events yet.
4239 .cp
= 14, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4240 .access
= PL1_RW
, .accessfn
= access_tda
,
4241 .type
= ARM_CP_NOP
},
4242 /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
4243 * to save and restore a 32-bit guest's DBGVCR)
4245 { .name
= "DBGVCR32_EL2", .state
= ARM_CP_STATE_AA64
,
4246 .opc0
= 2, .opc1
= 4, .crn
= 0, .crm
= 7, .opc2
= 0,
4247 .access
= PL2_RW
, .accessfn
= access_tda
,
4248 .type
= ARM_CP_NOP
},
4249 /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
4250 * Channel but Linux may try to access this register. The 32-bit
4251 * alias is DBGDCCINT.
4253 { .name
= "MDCCINT_EL1", .state
= ARM_CP_STATE_BOTH
,
4254 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4255 .access
= PL1_RW
, .accessfn
= access_tda
,
4256 .type
= ARM_CP_NOP
},
4260 static const ARMCPRegInfo debug_lpae_cp_reginfo
[] = {
4261 /* 64 bit access versions of the (dummy) debug registers */
4262 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
4263 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4264 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
4265 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
4269 void hw_watchpoint_update(ARMCPU
*cpu
, int n
)
4271 CPUARMState
*env
= &cpu
->env
;
4273 vaddr wvr
= env
->cp15
.dbgwvr
[n
];
4274 uint64_t wcr
= env
->cp15
.dbgwcr
[n
];
4276 int flags
= BP_CPU
| BP_STOP_BEFORE_ACCESS
;
4278 if (env
->cpu_watchpoint
[n
]) {
4279 cpu_watchpoint_remove_by_ref(CPU(cpu
), env
->cpu_watchpoint
[n
]);
4280 env
->cpu_watchpoint
[n
] = NULL
;
4283 if (!extract64(wcr
, 0, 1)) {
4284 /* E bit clear : watchpoint disabled */
4288 switch (extract64(wcr
, 3, 2)) {
4290 /* LSC 00 is reserved and must behave as if the wp is disabled */
4293 flags
|= BP_MEM_READ
;
4296 flags
|= BP_MEM_WRITE
;
4299 flags
|= BP_MEM_ACCESS
;
4303 /* Attempts to use both MASK and BAS fields simultaneously are
4304 * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
4305 * thus generating a watchpoint for every byte in the masked region.
4307 mask
= extract64(wcr
, 24, 4);
4308 if (mask
== 1 || mask
== 2) {
4309 /* Reserved values of MASK; we must act as if the mask value was
4310 * some non-reserved value, or as if the watchpoint were disabled.
4311 * We choose the latter.
4315 /* Watchpoint covers an aligned area up to 2GB in size */
4317 /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
4318 * whether the watchpoint fires when the unmasked bits match; we opt
4319 * to generate the exceptions.
4323 /* Watchpoint covers bytes defined by the byte address select bits */
4324 int bas
= extract64(wcr
, 5, 8);
4328 /* This must act as if the watchpoint is disabled */
4332 if (extract64(wvr
, 2, 1)) {
4333 /* Deprecated case of an only 4-aligned address. BAS[7:4] are
4334 * ignored, and BAS[3:0] define which bytes to watch.
4338 /* The BAS bits are supposed to be programmed to indicate a contiguous
4339 * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
4340 * we fire for each byte in the word/doubleword addressed by the WVR.
4341 * We choose to ignore any non-zero bits after the first range of 1s.
4343 basstart
= ctz32(bas
);
4344 len
= cto32(bas
>> basstart
);
4348 cpu_watchpoint_insert(CPU(cpu
), wvr
, len
, flags
,
4349 &env
->cpu_watchpoint
[n
]);
4352 void hw_watchpoint_update_all(ARMCPU
*cpu
)
4355 CPUARMState
*env
= &cpu
->env
;
4357 /* Completely clear out existing QEMU watchpoints and our array, to
4358 * avoid possible stale entries following migration load.
4360 cpu_watchpoint_remove_all(CPU(cpu
), BP_CPU
);
4361 memset(env
->cpu_watchpoint
, 0, sizeof(env
->cpu_watchpoint
));
4363 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_watchpoint
); i
++) {
4364 hw_watchpoint_update(cpu
, i
);
4368 static void dbgwvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4371 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4374 /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4375 * register reads and behaves as if values written are sign extended.
4376 * Bits [1:0] are RES0.
4378 value
= sextract64(value
, 0, 49) & ~3ULL;
4380 raw_write(env
, ri
, value
);
4381 hw_watchpoint_update(cpu
, i
);
4384 static void dbgwcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4387 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4390 raw_write(env
, ri
, value
);
4391 hw_watchpoint_update(cpu
, i
);
4394 void hw_breakpoint_update(ARMCPU
*cpu
, int n
)
4396 CPUARMState
*env
= &cpu
->env
;
4397 uint64_t bvr
= env
->cp15
.dbgbvr
[n
];
4398 uint64_t bcr
= env
->cp15
.dbgbcr
[n
];
4403 if (env
->cpu_breakpoint
[n
]) {
4404 cpu_breakpoint_remove_by_ref(CPU(cpu
), env
->cpu_breakpoint
[n
]);
4405 env
->cpu_breakpoint
[n
] = NULL
;
4408 if (!extract64(bcr
, 0, 1)) {
4409 /* E bit clear : watchpoint disabled */
4413 bt
= extract64(bcr
, 20, 4);
4416 case 4: /* unlinked address mismatch (reserved if AArch64) */
4417 case 5: /* linked address mismatch (reserved if AArch64) */
4418 qemu_log_mask(LOG_UNIMP
,
4419 "arm: address mismatch breakpoint types not implemented");
4421 case 0: /* unlinked address match */
4422 case 1: /* linked address match */
4424 /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4425 * we behave as if the register was sign extended. Bits [1:0] are
4426 * RES0. The BAS field is used to allow setting breakpoints on 16
4427 * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4428 * a bp will fire if the addresses covered by the bp and the addresses
4429 * covered by the insn overlap but the insn doesn't start at the
4430 * start of the bp address range. We choose to require the insn and
4431 * the bp to have the same address. The constraints on writing to
4432 * BAS enforced in dbgbcr_write mean we have only four cases:
4433 * 0b0000 => no breakpoint
4434 * 0b0011 => breakpoint on addr
4435 * 0b1100 => breakpoint on addr + 2
4436 * 0b1111 => breakpoint on addr
4437 * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4439 int bas
= extract64(bcr
, 5, 4);
4440 addr
= sextract64(bvr
, 0, 49) & ~3ULL;
4449 case 2: /* unlinked context ID match */
4450 case 8: /* unlinked VMID match (reserved if no EL2) */
4451 case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4452 qemu_log_mask(LOG_UNIMP
,
4453 "arm: unlinked context breakpoint types not implemented");
4455 case 9: /* linked VMID match (reserved if no EL2) */
4456 case 11: /* linked context ID and VMID match (reserved if no EL2) */
4457 case 3: /* linked context ID match */
4459 /* We must generate no events for Linked context matches (unless
4460 * they are linked to by some other bp/wp, which is handled in
4461 * updates for the linking bp/wp). We choose to also generate no events
4462 * for reserved values.
4467 cpu_breakpoint_insert(CPU(cpu
), addr
, flags
, &env
->cpu_breakpoint
[n
]);
4470 void hw_breakpoint_update_all(ARMCPU
*cpu
)
4473 CPUARMState
*env
= &cpu
->env
;
4475 /* Completely clear out existing QEMU breakpoints and our array, to
4476 * avoid possible stale entries following migration load.
4478 cpu_breakpoint_remove_all(CPU(cpu
), BP_CPU
);
4479 memset(env
->cpu_breakpoint
, 0, sizeof(env
->cpu_breakpoint
));
4481 for (i
= 0; i
< ARRAY_SIZE(cpu
->env
.cpu_breakpoint
); i
++) {
4482 hw_breakpoint_update(cpu
, i
);
4486 static void dbgbvr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4489 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4492 raw_write(env
, ri
, value
);
4493 hw_breakpoint_update(cpu
, i
);
4496 static void dbgbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
4499 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4502 /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4505 value
= deposit64(value
, 6, 1, extract64(value
, 5, 1));
4506 value
= deposit64(value
, 8, 1, extract64(value
, 7, 1));
4508 raw_write(env
, ri
, value
);
4509 hw_breakpoint_update(cpu
, i
);
4512 static void define_debug_regs(ARMCPU
*cpu
)
4514 /* Define v7 and v8 architectural debug registers.
4515 * These are just dummy implementations for now.
4518 int wrps
, brps
, ctx_cmps
;
4519 ARMCPRegInfo dbgdidr
= {
4520 .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
4521 .access
= PL0_R
, .accessfn
= access_tda
,
4522 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->dbgdidr
,
4525 /* Note that all these register fields hold "number of Xs minus 1". */
4526 brps
= extract32(cpu
->dbgdidr
, 24, 4);
4527 wrps
= extract32(cpu
->dbgdidr
, 28, 4);
4528 ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
4530 assert(ctx_cmps
<= brps
);
4532 /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4533 * of the debug registers such as number of breakpoints;
4534 * check that if they both exist then they agree.
4536 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
4537 assert(extract32(cpu
->id_aa64dfr0
, 12, 4) == brps
);
4538 assert(extract32(cpu
->id_aa64dfr0
, 20, 4) == wrps
);
4539 assert(extract32(cpu
->id_aa64dfr0
, 28, 4) == ctx_cmps
);
4542 define_one_arm_cp_reg(cpu
, &dbgdidr
);
4543 define_arm_cp_regs(cpu
, debug_cp_reginfo
);
4545 if (arm_feature(&cpu
->env
, ARM_FEATURE_LPAE
)) {
4546 define_arm_cp_regs(cpu
, debug_lpae_cp_reginfo
);
4549 for (i
= 0; i
< brps
+ 1; i
++) {
4550 ARMCPRegInfo dbgregs
[] = {
4551 { .name
= "DBGBVR", .state
= ARM_CP_STATE_BOTH
,
4552 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
4553 .access
= PL1_RW
, .accessfn
= access_tda
,
4554 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]),
4555 .writefn
= dbgbvr_write
, .raw_writefn
= raw_write
4557 { .name
= "DBGBCR", .state
= ARM_CP_STATE_BOTH
,
4558 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
4559 .access
= PL1_RW
, .accessfn
= access_tda
,
4560 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]),
4561 .writefn
= dbgbcr_write
, .raw_writefn
= raw_write
4565 define_arm_cp_regs(cpu
, dbgregs
);
4568 for (i
= 0; i
< wrps
+ 1; i
++) {
4569 ARMCPRegInfo dbgregs
[] = {
4570 { .name
= "DBGWVR", .state
= ARM_CP_STATE_BOTH
,
4571 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
4572 .access
= PL1_RW
, .accessfn
= access_tda
,
4573 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]),
4574 .writefn
= dbgwvr_write
, .raw_writefn
= raw_write
4576 { .name
= "DBGWCR", .state
= ARM_CP_STATE_BOTH
,
4577 .cp
= 14, .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
4578 .access
= PL1_RW
, .accessfn
= access_tda
,
4579 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]),
4580 .writefn
= dbgwcr_write
, .raw_writefn
= raw_write
4584 define_arm_cp_regs(cpu
, dbgregs
);
4588 /* We don't know until after realize whether there's a GICv3
4589 * attached, and that is what registers the gicv3 sysregs.
4590 * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_EL1
4593 static uint64_t id_pfr1_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4595 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4596 uint64_t pfr1
= cpu
->id_pfr1
;
4598 if (env
->gicv3state
) {
4604 static uint64_t id_aa64pfr0_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
4606 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4607 uint64_t pfr0
= cpu
->id_aa64pfr0
;
4609 if (env
->gicv3state
) {
4615 void register_cp_regs_for_features(ARMCPU
*cpu
)
4617 /* Register all the coprocessor registers based on feature bits */
4618 CPUARMState
*env
= &cpu
->env
;
4619 if (arm_feature(env
, ARM_FEATURE_M
)) {
4620 /* M profile has no coprocessor registers */
4624 define_arm_cp_regs(cpu
, cp_reginfo
);
4625 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
4626 /* Must go early as it is full of wildcards that may be
4627 * overridden by later definitions.
4629 define_arm_cp_regs(cpu
, not_v8_cp_reginfo
);
4632 if (arm_feature(env
, ARM_FEATURE_V6
)) {
4633 /* The ID registers all have impdef reset values */
4634 ARMCPRegInfo v6_idregs
[] = {
4635 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
4636 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
4637 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4638 .resetvalue
= cpu
->id_pfr0
},
4639 /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
4640 * the value of the GIC field until after we define these regs.
4642 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
4643 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
4644 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4645 .readfn
= id_pfr1_read
,
4646 .writefn
= arm_cp_write_ignore
},
4647 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
4648 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
4649 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4650 .resetvalue
= cpu
->id_dfr0
},
4651 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
4652 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
4653 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4654 .resetvalue
= cpu
->id_afr0
},
4655 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
4656 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
4657 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4658 .resetvalue
= cpu
->id_mmfr0
},
4659 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
4660 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
4661 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4662 .resetvalue
= cpu
->id_mmfr1
},
4663 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
4664 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
4665 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4666 .resetvalue
= cpu
->id_mmfr2
},
4667 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
4668 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
4669 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4670 .resetvalue
= cpu
->id_mmfr3
},
4671 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
4672 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
4673 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4674 .resetvalue
= cpu
->id_isar0
},
4675 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
4676 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
4677 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4678 .resetvalue
= cpu
->id_isar1
},
4679 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
4680 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
4681 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4682 .resetvalue
= cpu
->id_isar2
},
4683 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
4684 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
4685 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4686 .resetvalue
= cpu
->id_isar3
},
4687 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
4688 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
4689 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4690 .resetvalue
= cpu
->id_isar4
},
4691 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
4692 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
4693 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4694 .resetvalue
= cpu
->id_isar5
},
4695 { .name
= "ID_MMFR4", .state
= ARM_CP_STATE_BOTH
,
4696 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 6,
4697 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4698 .resetvalue
= cpu
->id_mmfr4
},
4699 /* 7 is as yet unallocated and must RAZ */
4700 { .name
= "ID_ISAR7_RESERVED", .state
= ARM_CP_STATE_BOTH
,
4701 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 7,
4702 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4706 define_arm_cp_regs(cpu
, v6_idregs
);
4707 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
4709 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
4711 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
4712 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
4714 if (arm_feature(env
, ARM_FEATURE_V7MP
) &&
4715 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
4716 define_arm_cp_regs(cpu
, v7mp_cp_reginfo
);
4718 if (arm_feature(env
, ARM_FEATURE_V7
)) {
4719 /* v7 performance monitor control register: same implementor
4720 * field as main ID register, and we implement only the cycle
4723 #ifndef CONFIG_USER_ONLY
4724 ARMCPRegInfo pmcr
= {
4725 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
4727 .type
= ARM_CP_IO
| ARM_CP_ALIAS
,
4728 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c9_pmcr
),
4729 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
4730 .raw_writefn
= raw_write
,
4732 ARMCPRegInfo pmcr64
= {
4733 .name
= "PMCR_EL0", .state
= ARM_CP_STATE_AA64
,
4734 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 0,
4735 .access
= PL0_RW
, .accessfn
= pmreg_access
,
4737 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
4738 .resetvalue
= cpu
->midr
& 0xff000000,
4739 .writefn
= pmcr_write
, .raw_writefn
= raw_write
,
4741 define_one_arm_cp_reg(cpu
, &pmcr
);
4742 define_one_arm_cp_reg(cpu
, &pmcr64
);
4744 ARMCPRegInfo clidr
= {
4745 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
4746 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
4747 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
4749 define_one_arm_cp_reg(cpu
, &clidr
);
4750 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
4751 define_debug_regs(cpu
);
4753 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
4755 if (arm_feature(env
, ARM_FEATURE_V8
)) {
4756 /* AArch64 ID registers, which all have impdef reset values.
4757 * Note that within the ID register ranges the unused slots
4758 * must all RAZ, not UNDEF; future architecture versions may
4759 * define new registers here.
4761 ARMCPRegInfo v8_idregs
[] = {
4762 /* ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST because we don't
4763 * know the right value for the GIC field until after we
4764 * define these regs.
4766 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4767 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
4768 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
,
4769 .readfn
= id_aa64pfr0_read
,
4770 .writefn
= arm_cp_write_ignore
},
4771 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4772 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
4773 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4774 .resetvalue
= cpu
->id_aa64pfr1
},
4775 { .name
= "ID_AA64PFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4776 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 2,
4777 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4779 { .name
= "ID_AA64PFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4780 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 3,
4781 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4783 { .name
= "ID_AA64PFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4784 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 4,
4785 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4787 { .name
= "ID_AA64PFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4788 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 5,
4789 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4791 { .name
= "ID_AA64PFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4792 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 6,
4793 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4795 { .name
= "ID_AA64PFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4796 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 7,
4797 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4799 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4800 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
4801 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4802 .resetvalue
= cpu
->id_aa64dfr0
},
4803 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4804 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
4805 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4806 .resetvalue
= cpu
->id_aa64dfr1
},
4807 { .name
= "ID_AA64DFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4808 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 2,
4809 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4811 { .name
= "ID_AA64DFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4812 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 3,
4813 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4815 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4816 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
4817 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4818 .resetvalue
= cpu
->id_aa64afr0
},
4819 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4820 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
4821 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4822 .resetvalue
= cpu
->id_aa64afr1
},
4823 { .name
= "ID_AA64AFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4824 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 6,
4825 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4827 { .name
= "ID_AA64AFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4828 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 7,
4829 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4831 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
4832 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
4833 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4834 .resetvalue
= cpu
->id_aa64isar0
},
4835 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
4836 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
4837 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4838 .resetvalue
= cpu
->id_aa64isar1
},
4839 { .name
= "ID_AA64ISAR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4840 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 2,
4841 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4843 { .name
= "ID_AA64ISAR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4844 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 3,
4845 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4847 { .name
= "ID_AA64ISAR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4848 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 4,
4849 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4851 { .name
= "ID_AA64ISAR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4852 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 5,
4853 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4855 { .name
= "ID_AA64ISAR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4856 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 6,
4857 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4859 { .name
= "ID_AA64ISAR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4860 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 7,
4861 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4863 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4864 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
4865 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4866 .resetvalue
= cpu
->id_aa64mmfr0
},
4867 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4868 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
4869 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4870 .resetvalue
= cpu
->id_aa64mmfr1
},
4871 { .name
= "ID_AA64MMFR2_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4872 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 2,
4873 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4875 { .name
= "ID_AA64MMFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4876 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 3,
4877 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4879 { .name
= "ID_AA64MMFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4880 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 4,
4881 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4883 { .name
= "ID_AA64MMFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4884 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 5,
4885 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4887 { .name
= "ID_AA64MMFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4888 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 6,
4889 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4891 { .name
= "ID_AA64MMFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4892 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 7,
4893 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4895 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
4896 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
4897 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4898 .resetvalue
= cpu
->mvfr0
},
4899 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
4900 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
4901 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4902 .resetvalue
= cpu
->mvfr1
},
4903 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
4904 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
4905 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4906 .resetvalue
= cpu
->mvfr2
},
4907 { .name
= "MVFR3_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4908 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 3,
4909 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4911 { .name
= "MVFR4_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4912 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 4,
4913 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4915 { .name
= "MVFR5_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4916 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 5,
4917 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4919 { .name
= "MVFR6_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4920 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 6,
4921 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4923 { .name
= "MVFR7_EL1_RESERVED", .state
= ARM_CP_STATE_AA64
,
4924 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 7,
4925 .access
= PL1_R
, .type
= ARM_CP_CONST
,
4927 { .name
= "PMCEID0", .state
= ARM_CP_STATE_AA32
,
4928 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 6,
4929 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4930 .resetvalue
= cpu
->pmceid0
},
4931 { .name
= "PMCEID0_EL0", .state
= ARM_CP_STATE_AA64
,
4932 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 6,
4933 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4934 .resetvalue
= cpu
->pmceid0
},
4935 { .name
= "PMCEID1", .state
= ARM_CP_STATE_AA32
,
4936 .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 12, .opc2
= 7,
4937 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4938 .resetvalue
= cpu
->pmceid1
},
4939 { .name
= "PMCEID1_EL0", .state
= ARM_CP_STATE_AA64
,
4940 .opc0
= 3, .opc1
= 3, .crn
= 9, .crm
= 12, .opc2
= 7,
4941 .access
= PL0_R
, .accessfn
= pmreg_access
, .type
= ARM_CP_CONST
,
4942 .resetvalue
= cpu
->pmceid1
},
4945 /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4946 if (!arm_feature(env
, ARM_FEATURE_EL3
) &&
4947 !arm_feature(env
, ARM_FEATURE_EL2
)) {
4948 ARMCPRegInfo rvbar
= {
4949 .name
= "RVBAR_EL1", .state
= ARM_CP_STATE_AA64
,
4950 .opc0
= 3, .opc1
= 0, .crn
= 12, .crm
= 0, .opc2
= 1,
4951 .type
= ARM_CP_CONST
, .access
= PL1_R
, .resetvalue
= cpu
->rvbar
4953 define_one_arm_cp_reg(cpu
, &rvbar
);
4955 define_arm_cp_regs(cpu
, v8_idregs
);
4956 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
4958 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
4959 uint64_t vmpidr_def
= mpidr_read_val(env
);
4960 ARMCPRegInfo vpidr_regs
[] = {
4961 { .name
= "VPIDR", .state
= ARM_CP_STATE_AA32
,
4962 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4963 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4964 .resetvalue
= cpu
->midr
,
4965 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4966 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4967 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
4968 .access
= PL2_RW
, .resetvalue
= cpu
->midr
,
4969 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
4970 { .name
= "VMPIDR", .state
= ARM_CP_STATE_AA32
,
4971 .cp
= 15, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4972 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns
,
4973 .resetvalue
= vmpidr_def
,
4974 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4975 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_AA64
,
4976 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
4978 .resetvalue
= vmpidr_def
,
4979 .fieldoffset
= offsetof(CPUARMState
, cp15
.vmpidr_el2
) },
4982 define_arm_cp_regs(cpu
, vpidr_regs
);
4983 define_arm_cp_regs(cpu
, el2_cp_reginfo
);
4984 /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4985 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
4986 ARMCPRegInfo rvbar
= {
4987 .name
= "RVBAR_EL2", .state
= ARM_CP_STATE_AA64
,
4988 .opc0
= 3, .opc1
= 4, .crn
= 12, .crm
= 0, .opc2
= 1,
4989 .type
= ARM_CP_CONST
, .access
= PL2_R
, .resetvalue
= cpu
->rvbar
4991 define_one_arm_cp_reg(cpu
, &rvbar
);
4994 /* If EL2 is missing but higher ELs are enabled, we need to
4995 * register the no_el2 reginfos.
4997 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
4998 /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4999 * of MIDR_EL1 and MPIDR_EL1.
5001 ARMCPRegInfo vpidr_regs
[] = {
5002 { .name
= "VPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5003 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 0,
5004 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5005 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->midr
,
5006 .fieldoffset
= offsetof(CPUARMState
, cp15
.vpidr_el2
) },
5007 { .name
= "VMPIDR_EL2", .state
= ARM_CP_STATE_BOTH
,
5008 .opc0
= 3, .opc1
= 4, .crn
= 0, .crm
= 0, .opc2
= 5,
5009 .access
= PL2_RW
, .accessfn
= access_el3_aa32ns_aa64any
,
5010 .type
= ARM_CP_NO_RAW
,
5011 .writefn
= arm_cp_write_ignore
, .readfn
= mpidr_read
},
5014 define_arm_cp_regs(cpu
, vpidr_regs
);
5015 define_arm_cp_regs(cpu
, el3_no_el2_cp_reginfo
);
5018 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5019 define_arm_cp_regs(cpu
, el3_cp_reginfo
);
5020 ARMCPRegInfo el3_regs
[] = {
5021 { .name
= "RVBAR_EL3", .state
= ARM_CP_STATE_AA64
,
5022 .opc0
= 3, .opc1
= 6, .crn
= 12, .crm
= 0, .opc2
= 1,
5023 .type
= ARM_CP_CONST
, .access
= PL3_R
, .resetvalue
= cpu
->rvbar
},
5024 { .name
= "SCTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5025 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 0,
5027 .raw_writefn
= raw_write
, .writefn
= sctlr_write
,
5028 .fieldoffset
= offsetof(CPUARMState
, cp15
.sctlr_el
[3]),
5029 .resetvalue
= cpu
->reset_sctlr
},
5033 define_arm_cp_regs(cpu
, el3_regs
);
5035 /* The behaviour of NSACR is sufficiently various that we don't
5036 * try to describe it in a single reginfo:
5037 * if EL3 is 64 bit, then trap to EL3 from S EL1,
5038 * reads as constant 0xc00 from NS EL1 and NS EL2
5039 * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
5040 * if v7 without EL3, register doesn't exist
5041 * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
5043 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
5044 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5045 ARMCPRegInfo nsacr
= {
5046 .name
= "NSACR", .type
= ARM_CP_CONST
,
5047 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5048 .access
= PL1_RW
, .accessfn
= nsacr_access
,
5051 define_one_arm_cp_reg(cpu
, &nsacr
);
5053 ARMCPRegInfo nsacr
= {
5055 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5056 .access
= PL3_RW
| PL1_R
,
5058 .fieldoffset
= offsetof(CPUARMState
, cp15
.nsacr
)
5060 define_one_arm_cp_reg(cpu
, &nsacr
);
5063 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5064 ARMCPRegInfo nsacr
= {
5065 .name
= "NSACR", .type
= ARM_CP_CONST
,
5066 .cp
= 15, .opc1
= 0, .crn
= 1, .crm
= 1, .opc2
= 2,
5070 define_one_arm_cp_reg(cpu
, &nsacr
);
5074 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
5075 if (arm_feature(env
, ARM_FEATURE_V6
)) {
5076 /* PMSAv6 not implemented */
5077 assert(arm_feature(env
, ARM_FEATURE_V7
));
5078 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5079 define_arm_cp_regs(cpu
, pmsav7_cp_reginfo
);
5081 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
5084 define_arm_cp_regs(cpu
, vmsa_pmsa_cp_reginfo
);
5085 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
5087 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
5088 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
5090 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
5091 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
5093 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
5094 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
5096 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
5097 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
5099 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
5100 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
5102 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
5103 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
5105 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
5106 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
5108 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5109 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
5111 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5112 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
5114 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
5115 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
5117 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
5118 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
5120 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
5121 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
5122 * be read-only (ie write causes UNDEF exception).
5125 ARMCPRegInfo id_pre_v8_midr_cp_reginfo
[] = {
5126 /* Pre-v8 MIDR space.
5127 * Note that the MIDR isn't a simple constant register because
5128 * of the TI925 behaviour where writes to another register can
5129 * cause the MIDR value to change.
5131 * Unimplemented registers in the c15 0 0 0 space default to
5132 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
5133 * and friends override accordingly.
5136 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
5137 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
5138 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
5139 .readfn
= midr_read
,
5140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5141 .type
= ARM_CP_OVERRIDE
},
5142 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
5144 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
5145 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5147 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
5148 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5150 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
5151 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5153 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
5154 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5156 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
5157 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5160 ARMCPRegInfo id_v8_midr_cp_reginfo
[] = {
5161 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5162 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 0,
5163 .access
= PL1_R
, .type
= ARM_CP_NO_RAW
, .resetvalue
= cpu
->midr
,
5164 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
5165 .readfn
= midr_read
},
5166 /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
5167 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5168 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5169 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5170 { .name
= "MIDR", .type
= ARM_CP_ALIAS
| ARM_CP_CONST
,
5171 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 7,
5172 .access
= PL1_R
, .resetvalue
= cpu
->midr
},
5173 { .name
= "REVIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
5174 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 0, .opc2
= 6,
5175 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->revidr
},
5178 ARMCPRegInfo id_cp_reginfo
[] = {
5179 /* These are common to v8 and pre-v8 */
5181 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
5182 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5183 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
5184 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
5185 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
5186 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
5187 /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
5189 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
5190 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
5193 /* TLBTR is specific to VMSA */
5194 ARMCPRegInfo id_tlbtr_reginfo
= {
5196 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
5197 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
5199 /* MPUIR is specific to PMSA V6+ */
5200 ARMCPRegInfo id_mpuir_reginfo
= {
5202 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 4,
5203 .access
= PL1_R
, .type
= ARM_CP_CONST
,
5204 .resetvalue
= cpu
->pmsav7_dregion
<< 8
5206 ARMCPRegInfo crn0_wi_reginfo
= {
5207 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
5208 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
5209 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
5211 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
5212 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
5214 /* Register the blanket "writes ignored" value first to cover the
5215 * whole space. Then update the specific ID registers to allow write
5216 * access, so that they ignore writes rather than causing them to
5219 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
5220 for (r
= id_pre_v8_midr_cp_reginfo
;
5221 r
->type
!= ARM_CP_SENTINEL
; r
++) {
5224 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5227 id_tlbtr_reginfo
.access
= PL1_RW
;
5228 id_tlbtr_reginfo
.access
= PL1_RW
;
5230 if (arm_feature(env
, ARM_FEATURE_V8
)) {
5231 define_arm_cp_regs(cpu
, id_v8_midr_cp_reginfo
);
5233 define_arm_cp_regs(cpu
, id_pre_v8_midr_cp_reginfo
);
5235 define_arm_cp_regs(cpu
, id_cp_reginfo
);
5236 if (!arm_feature(env
, ARM_FEATURE_PMSA
)) {
5237 define_one_arm_cp_reg(cpu
, &id_tlbtr_reginfo
);
5238 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
5239 define_one_arm_cp_reg(cpu
, &id_mpuir_reginfo
);
5243 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
5244 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
5247 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
5248 ARMCPRegInfo auxcr_reginfo
[] = {
5249 { .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
5250 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
5251 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
5252 .resetvalue
= cpu
->reset_auxcr
},
5253 { .name
= "ACTLR_EL2", .state
= ARM_CP_STATE_BOTH
,
5254 .opc0
= 3, .opc1
= 4, .crn
= 1, .crm
= 0, .opc2
= 1,
5255 .access
= PL2_RW
, .type
= ARM_CP_CONST
,
5257 { .name
= "ACTLR_EL3", .state
= ARM_CP_STATE_AA64
,
5258 .opc0
= 3, .opc1
= 6, .crn
= 1, .crm
= 0, .opc2
= 1,
5259 .access
= PL3_RW
, .type
= ARM_CP_CONST
,
5263 define_arm_cp_regs(cpu
, auxcr_reginfo
);
5266 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
5267 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5268 /* 32 bit view is [31:18] 0...0 [43:32]. */
5269 uint32_t cbar32
= (extract64(cpu
->reset_cbar
, 18, 14) << 18)
5270 | extract64(cpu
->reset_cbar
, 32, 12);
5271 ARMCPRegInfo cbar_reginfo
[] = {
5273 .type
= ARM_CP_CONST
,
5274 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5275 .access
= PL1_R
, .resetvalue
= cpu
->reset_cbar
},
5276 { .name
= "CBAR_EL1", .state
= ARM_CP_STATE_AA64
,
5277 .type
= ARM_CP_CONST
,
5278 .opc0
= 3, .opc1
= 1, .crn
= 15, .crm
= 3, .opc2
= 0,
5279 .access
= PL1_R
, .resetvalue
= cbar32
},
5282 /* We don't implement a r/w 64 bit CBAR currently */
5283 assert(arm_feature(env
, ARM_FEATURE_CBAR_RO
));
5284 define_arm_cp_regs(cpu
, cbar_reginfo
);
5286 ARMCPRegInfo cbar
= {
5288 .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
5289 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
5290 .fieldoffset
= offsetof(CPUARMState
,
5291 cp15
.c15_config_base_address
)
5293 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
5294 cbar
.access
= PL1_R
;
5295 cbar
.fieldoffset
= 0;
5296 cbar
.type
= ARM_CP_CONST
;
5298 define_one_arm_cp_reg(cpu
, &cbar
);
5302 if (arm_feature(env
, ARM_FEATURE_VBAR
)) {
5303 ARMCPRegInfo vbar_cp_reginfo
[] = {
5304 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
5305 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
5306 .access
= PL1_RW
, .writefn
= vbar_write
,
5307 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.vbar_s
),
5308 offsetof(CPUARMState
, cp15
.vbar_ns
) },
5312 define_arm_cp_regs(cpu
, vbar_cp_reginfo
);
5315 /* Generic registers whose values depend on the implementation */
5317 ARMCPRegInfo sctlr
= {
5318 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
5319 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 0,
5321 .bank_fieldoffsets
= { offsetof(CPUARMState
, cp15
.sctlr_s
),
5322 offsetof(CPUARMState
, cp15
.sctlr_ns
) },
5323 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
5324 .raw_writefn
= raw_write
,
5326 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
5327 /* Normally we would always end the TB on an SCTLR write, but Linux
5328 * arch/arm/mach-pxa/sleep.S expects two instructions following
5329 * an MMU enable to execute from cache. Imitate this behaviour.
5331 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
5333 define_one_arm_cp_reg(cpu
, &sctlr
);
5337 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
5339 CPUState
*cs
= CPU(cpu
);
5340 CPUARMState
*env
= &cpu
->env
;
5342 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
5343 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
5344 aarch64_fpu_gdb_set_reg
,
5345 34, "aarch64-fpu.xml", 0);
5346 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
5347 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5348 51, "arm-neon.xml", 0);
5349 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
5350 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5351 35, "arm-vfp3.xml", 0);
5352 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
5353 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
5354 19, "arm-vfp.xml", 0);
5358 /* Sort alphabetically by type name, except for "any". */
5359 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5361 ObjectClass
*class_a
= (ObjectClass
*)a
;
5362 ObjectClass
*class_b
= (ObjectClass
*)b
;
5363 const char *name_a
, *name_b
;
5365 name_a
= object_class_get_name(class_a
);
5366 name_b
= object_class_get_name(class_b
);
5367 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
5369 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
5372 return strcmp(name_a
, name_b
);
5376 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
5378 ObjectClass
*oc
= data
;
5379 CPUListState
*s
= user_data
;
5380 const char *typename
;
5383 typename
= object_class_get_name(oc
);
5384 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5385 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
5390 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
5394 .cpu_fprintf
= cpu_fprintf
,
5398 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5399 list
= g_slist_sort(list
, arm_cpu_list_compare
);
5400 (*cpu_fprintf
)(f
, "Available CPUs:\n");
5401 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
5404 /* The 'host' CPU type is dynamically registered only if KVM is
5405 * enabled, so we have to special-case it here:
5407 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
5411 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
5413 ObjectClass
*oc
= data
;
5414 CpuDefinitionInfoList
**cpu_list
= user_data
;
5415 CpuDefinitionInfoList
*entry
;
5416 CpuDefinitionInfo
*info
;
5417 const char *typename
;
5419 typename
= object_class_get_name(oc
);
5420 info
= g_malloc0(sizeof(*info
));
5421 info
->name
= g_strndup(typename
,
5422 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
5423 info
->q_typename
= g_strdup(typename
);
5425 entry
= g_malloc0(sizeof(*entry
));
5426 entry
->value
= info
;
5427 entry
->next
= *cpu_list
;
5431 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
5433 CpuDefinitionInfoList
*cpu_list
= NULL
;
5436 list
= object_class_get_list(TYPE_ARM_CPU
, false);
5437 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
5443 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
5444 void *opaque
, int state
, int secstate
,
5445 int crm
, int opc1
, int opc2
)
5447 /* Private utility function for define_one_arm_cp_reg_with_opaque():
5448 * add a single reginfo struct to the hash table.
5450 uint32_t *key
= g_new(uint32_t, 1);
5451 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
5452 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
5453 int ns
= (secstate
& ARM_CP_SECSTATE_NS
) ? 1 : 0;
5455 /* Reset the secure state to the specific incoming state. This is
5456 * necessary as the register may have been defined with both states.
5458 r2
->secure
= secstate
;
5460 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5461 /* Register is banked (using both entries in array).
5462 * Overwriting fieldoffset as the array is only used to define
5463 * banked registers but later only fieldoffset is used.
5465 r2
->fieldoffset
= r
->bank_fieldoffsets
[ns
];
5468 if (state
== ARM_CP_STATE_AA32
) {
5469 if (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1]) {
5470 /* If the register is banked then we don't need to migrate or
5471 * reset the 32-bit instance in certain cases:
5473 * 1) If the register has both 32-bit and 64-bit instances then we
5474 * can count on the 64-bit instance taking care of the
5476 * 2) If ARMv8 is enabled then we can count on a 64-bit version
5477 * taking care of the secure bank. This requires that separate
5478 * 32 and 64-bit definitions are provided.
5480 if ((r
->state
== ARM_CP_STATE_BOTH
&& ns
) ||
5481 (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) && !ns
)) {
5482 r2
->type
|= ARM_CP_ALIAS
;
5484 } else if ((secstate
!= r
->secure
) && !ns
) {
5485 /* The register is not banked so we only want to allow migration of
5486 * the non-secure instance.
5488 r2
->type
|= ARM_CP_ALIAS
;
5491 if (r
->state
== ARM_CP_STATE_BOTH
) {
5492 /* We assume it is a cp15 register if the .cp field is left unset.
5498 #ifdef HOST_WORDS_BIGENDIAN
5499 if (r2
->fieldoffset
) {
5500 r2
->fieldoffset
+= sizeof(uint32_t);
5505 if (state
== ARM_CP_STATE_AA64
) {
5506 /* To allow abbreviation of ARMCPRegInfo
5507 * definitions, we treat cp == 0 as equivalent to
5508 * the value for "standard guest-visible sysreg".
5509 * STATE_BOTH definitions are also always "standard
5510 * sysreg" in their AArch64 view (the .cp value may
5511 * be non-zero for the benefit of the AArch32 view).
5513 if (r
->cp
== 0 || r
->state
== ARM_CP_STATE_BOTH
) {
5514 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
5516 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
5517 r2
->opc0
, opc1
, opc2
);
5519 *key
= ENCODE_CP_REG(r2
->cp
, is64
, ns
, r2
->crn
, crm
, opc1
, opc2
);
5522 r2
->opaque
= opaque
;
5524 /* reginfo passed to helpers is correct for the actual access,
5525 * and is never ARM_CP_STATE_BOTH:
5528 /* Make sure reginfo passed to helpers for wildcarded regs
5529 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5534 /* By convention, for wildcarded registers only the first
5535 * entry is used for migration; the others are marked as
5536 * ALIAS so we don't try to transfer the register
5537 * multiple times. Special registers (ie NOP/WFI) are
5538 * never migratable and not even raw-accessible.
5540 if ((r
->type
& ARM_CP_SPECIAL
)) {
5541 r2
->type
|= ARM_CP_NO_RAW
;
5543 if (((r
->crm
== CP_ANY
) && crm
!= 0) ||
5544 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
5545 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
5546 r2
->type
|= ARM_CP_ALIAS
;
5549 /* Check that raw accesses are either forbidden or handled. Note that
5550 * we can't assert this earlier because the setup of fieldoffset for
5551 * banked registers has to be done first.
5553 if (!(r2
->type
& ARM_CP_NO_RAW
)) {
5554 assert(!raw_accessors_invalid(r2
));
5557 /* Overriding of an existing definition must be explicitly
5560 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
5561 ARMCPRegInfo
*oldreg
;
5562 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
5563 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
5564 fprintf(stderr
, "Register redefined: cp=%d %d bit "
5565 "crn=%d crm=%d opc1=%d opc2=%d, "
5566 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
5567 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
5568 oldreg
->name
, r2
->name
);
5569 g_assert_not_reached();
5572 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
5576 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
5577 const ARMCPRegInfo
*r
, void *opaque
)
5579 /* Define implementations of coprocessor registers.
5580 * We store these in a hashtable because typically
5581 * there are less than 150 registers in a space which
5582 * is 16*16*16*8*8 = 262144 in size.
5583 * Wildcarding is supported for the crm, opc1 and opc2 fields.
5584 * If a register is defined twice then the second definition is
5585 * used, so this can be used to define some generic registers and
5586 * then override them with implementation specific variations.
5587 * At least one of the original and the second definition should
5588 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5589 * against accidental use.
5591 * The state field defines whether the register is to be
5592 * visible in the AArch32 or AArch64 execution state. If the
5593 * state is set to ARM_CP_STATE_BOTH then we synthesise a
5594 * reginfo structure for the AArch32 view, which sees the lower
5595 * 32 bits of the 64 bit register.
5597 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5598 * be wildcarded. AArch64 registers are always considered to be 64
5599 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5600 * the register, if any.
5602 int crm
, opc1
, opc2
, state
;
5603 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
5604 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
5605 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
5606 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
5607 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
5608 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
5609 /* 64 bit registers have only CRm and Opc1 fields */
5610 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
5611 /* op0 only exists in the AArch64 encodings */
5612 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
5613 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5614 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
5615 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5616 * encodes a minimum access level for the register. We roll this
5617 * runtime check into our general permission check code, so check
5618 * here that the reginfo's specified permissions are strict enough
5619 * to encompass the generic architectural permission check.
5621 if (r
->state
!= ARM_CP_STATE_AA32
) {
5624 case 0: case 1: case 2:
5637 /* unallocated encoding, so not possible */
5645 /* min_EL EL1, secure mode only (we don't check the latter) */
5649 /* broken reginfo with out-of-range opc1 */
5653 /* assert our permissions are not too lax (stricter is fine) */
5654 assert((r
->access
& ~mask
) == 0);
5657 /* Check that the register definition has enough info to handle
5658 * reads and writes if they are permitted.
5660 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
5661 if (r
->access
& PL3_R
) {
5662 assert((r
->fieldoffset
||
5663 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5666 if (r
->access
& PL3_W
) {
5667 assert((r
->fieldoffset
||
5668 (r
->bank_fieldoffsets
[0] && r
->bank_fieldoffsets
[1])) ||
5672 /* Bad type field probably means missing sentinel at end of reg list */
5673 assert(cptype_valid(r
->type
));
5674 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
5675 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
5676 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
5677 for (state
= ARM_CP_STATE_AA32
;
5678 state
<= ARM_CP_STATE_AA64
; state
++) {
5679 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
5682 if (state
== ARM_CP_STATE_AA32
) {
5683 /* Under AArch32 CP registers can be common
5684 * (same for secure and non-secure world) or banked.
5686 switch (r
->secure
) {
5687 case ARM_CP_SECSTATE_S
:
5688 case ARM_CP_SECSTATE_NS
:
5689 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5690 r
->secure
, crm
, opc1
, opc2
);
5693 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5696 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5702 /* AArch64 registers get mapped to non-secure instance
5704 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
5714 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
5715 const ARMCPRegInfo
*regs
, void *opaque
)
5717 /* Define a whole list of registers */
5718 const ARMCPRegInfo
*r
;
5719 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
5720 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
5724 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
5726 return g_hash_table_lookup(cpregs
, &encoded_cp
);
5729 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
5732 /* Helper coprocessor write function for write-ignore registers */
5735 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
5737 /* Helper coprocessor write function for read-as-zero registers */
5741 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
5743 /* Helper coprocessor reset function for do-nothing-on-reset registers */
5746 static int bad_mode_switch(CPUARMState
*env
, int mode
, CPSRWriteType write_type
)
5748 /* Return true if it is not valid for us to switch to
5749 * this CPU mode (ie all the UNPREDICTABLE cases in
5750 * the ARM ARM CPSRWriteByInstr pseudocode).
5753 /* Changes to or from Hyp via MSR and CPS are illegal. */
5754 if (write_type
== CPSRWriteByInstr
&&
5755 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_HYP
||
5756 mode
== ARM_CPU_MODE_HYP
)) {
5761 case ARM_CPU_MODE_USR
:
5763 case ARM_CPU_MODE_SYS
:
5764 case ARM_CPU_MODE_SVC
:
5765 case ARM_CPU_MODE_ABT
:
5766 case ARM_CPU_MODE_UND
:
5767 case ARM_CPU_MODE_IRQ
:
5768 case ARM_CPU_MODE_FIQ
:
5769 /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5770 * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5772 /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5773 * and CPS are treated as illegal mode changes.
5775 if (write_type
== CPSRWriteByInstr
&&
5776 (env
->cp15
.hcr_el2
& HCR_TGE
) &&
5777 (env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
&&
5778 !arm_is_secure_below_el3(env
)) {
5782 case ARM_CPU_MODE_HYP
:
5783 return !arm_feature(env
, ARM_FEATURE_EL2
)
5784 || arm_current_el(env
) < 2 || arm_is_secure(env
);
5785 case ARM_CPU_MODE_MON
:
5786 return arm_current_el(env
) < 3;
5792 uint32_t cpsr_read(CPUARMState
*env
)
5795 ZF
= (env
->ZF
== 0);
5796 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
5797 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
5798 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
5799 | ((env
->condexec_bits
& 0xfc) << 8)
5800 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
5803 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
,
5804 CPSRWriteType write_type
)
5806 uint32_t changed_daif
;
5808 if (mask
& CPSR_NZCV
) {
5809 env
->ZF
= (~val
) & CPSR_Z
;
5811 env
->CF
= (val
>> 29) & 1;
5812 env
->VF
= (val
<< 3) & 0x80000000;
5815 env
->QF
= ((val
& CPSR_Q
) != 0);
5817 env
->thumb
= ((val
& CPSR_T
) != 0);
5818 if (mask
& CPSR_IT_0_1
) {
5819 env
->condexec_bits
&= ~3;
5820 env
->condexec_bits
|= (val
>> 25) & 3;
5822 if (mask
& CPSR_IT_2_7
) {
5823 env
->condexec_bits
&= 3;
5824 env
->condexec_bits
|= (val
>> 8) & 0xfc;
5826 if (mask
& CPSR_GE
) {
5827 env
->GE
= (val
>> 16) & 0xf;
5830 /* In a V7 implementation that includes the security extensions but does
5831 * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5832 * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5833 * bits respectively.
5835 * In a V8 implementation, it is permitted for privileged software to
5836 * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5838 if (write_type
!= CPSRWriteRaw
&& !arm_feature(env
, ARM_FEATURE_V8
) &&
5839 arm_feature(env
, ARM_FEATURE_EL3
) &&
5840 !arm_feature(env
, ARM_FEATURE_EL2
) &&
5841 !arm_is_secure(env
)) {
5843 changed_daif
= (env
->daif
^ val
) & mask
;
5845 if (changed_daif
& CPSR_A
) {
5846 /* Check to see if we are allowed to change the masking of async
5847 * abort exceptions from a non-secure state.
5849 if (!(env
->cp15
.scr_el3
& SCR_AW
)) {
5850 qemu_log_mask(LOG_GUEST_ERROR
,
5851 "Ignoring attempt to switch CPSR_A flag from "
5852 "non-secure world with SCR.AW bit clear\n");
5857 if (changed_daif
& CPSR_F
) {
5858 /* Check to see if we are allowed to change the masking of FIQ
5859 * exceptions from a non-secure state.
5861 if (!(env
->cp15
.scr_el3
& SCR_FW
)) {
5862 qemu_log_mask(LOG_GUEST_ERROR
,
5863 "Ignoring attempt to switch CPSR_F flag from "
5864 "non-secure world with SCR.FW bit clear\n");
5868 /* Check whether non-maskable FIQ (NMFI) support is enabled.
5869 * If this bit is set software is not allowed to mask
5870 * FIQs, but is allowed to set CPSR_F to 0.
5872 if ((A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_NMFI
) &&
5874 qemu_log_mask(LOG_GUEST_ERROR
,
5875 "Ignoring attempt to enable CPSR_F flag "
5876 "(non-maskable FIQ [NMFI] support enabled)\n");
5882 env
->daif
&= ~(CPSR_AIF
& mask
);
5883 env
->daif
|= val
& CPSR_AIF
& mask
;
5885 if (write_type
!= CPSRWriteRaw
&&
5886 ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
)) {
5887 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
) {
5888 /* Note that we can only get here in USR mode if this is a
5889 * gdb stub write; for this case we follow the architectural
5890 * behaviour for guest writes in USR mode of ignoring an attempt
5891 * to switch mode. (Those are caught by translate.c for writes
5892 * triggered by guest instructions.)
5895 } else if (bad_mode_switch(env
, val
& CPSR_M
, write_type
)) {
5896 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5897 * v7, and has defined behaviour in v8:
5898 * + leave CPSR.M untouched
5899 * + allow changes to the other CPSR fields
5901 * For user changes via the GDB stub, we don't set PSTATE.IL,
5902 * as this would be unnecessarily harsh for a user error.
5905 if (write_type
!= CPSRWriteByGDBStub
&&
5906 arm_feature(env
, ARM_FEATURE_V8
)) {
5911 switch_mode(env
, val
& CPSR_M
);
5914 mask
&= ~CACHED_CPSR_BITS
;
5915 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
5918 /* Sign/zero extend */
5919 uint32_t HELPER(sxtb16
)(uint32_t x
)
5922 res
= (uint16_t)(int8_t)x
;
5923 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
5927 uint32_t HELPER(uxtb16
)(uint32_t x
)
5930 res
= (uint16_t)(uint8_t)x
;
5931 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
5935 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
5939 if (num
== INT_MIN
&& den
== -1)
5944 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
5951 uint32_t HELPER(rbit
)(uint32_t x
)
5956 #if defined(CONFIG_USER_ONLY)
5958 /* These should probably raise undefined insn exceptions. */
5959 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
5961 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5963 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
5966 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
5968 ARMCPU
*cpu
= arm_env_get_cpu(env
);
5970 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
5974 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
5976 /* translate.c should never generate calls here in user-only mode */
5977 g_assert_not_reached();
5980 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
5982 /* translate.c should never generate calls here in user-only mode */
5983 g_assert_not_reached();
5986 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
5988 /* The TT instructions can be used by unprivileged code, but in
5989 * user-only emulation we don't have the MPU.
5990 * Luckily since we know we are NonSecure unprivileged (and that in
5991 * turn means that the A flag wasn't specified), all the bits in the
5992 * register must be zero:
5993 * IREGION: 0 because IRVALID is 0
5994 * IRVALID: 0 because NS
5996 * NSRW: 0 because NS
5998 * RW: 0 because unpriv and A flag not set
5999 * R: 0 because unpriv and A flag not set
6000 * SRVALID: 0 because NS
6001 * MRVALID: 0 because unpriv and A flag not set
6002 * SREGION: 0 becaus SRVALID is 0
6003 * MREGION: 0 because MRVALID is 0
6008 void switch_mode(CPUARMState
*env
, int mode
)
6010 ARMCPU
*cpu
= arm_env_get_cpu(env
);
6012 if (mode
!= ARM_CPU_MODE_USR
) {
6013 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
6017 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6018 uint32_t cur_el
, bool secure
)
6023 void aarch64_sync_64_to_32(CPUARMState
*env
)
6025 g_assert_not_reached();
6030 void switch_mode(CPUARMState
*env
, int mode
)
6035 old_mode
= env
->uncached_cpsr
& CPSR_M
;
6036 if (mode
== old_mode
)
6039 if (old_mode
== ARM_CPU_MODE_FIQ
) {
6040 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6041 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
6042 } else if (mode
== ARM_CPU_MODE_FIQ
) {
6043 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
6044 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
6047 i
= bank_number(old_mode
);
6048 env
->banked_r13
[i
] = env
->regs
[13];
6049 env
->banked_r14
[i
] = env
->regs
[14];
6050 env
->banked_spsr
[i
] = env
->spsr
;
6052 i
= bank_number(mode
);
6053 env
->regs
[13] = env
->banked_r13
[i
];
6054 env
->regs
[14] = env
->banked_r14
[i
];
6055 env
->spsr
= env
->banked_spsr
[i
];
6058 /* Physical Interrupt Target EL Lookup Table
6060 * [ From ARM ARM section G1.13.4 (Table G1-15) ]
6062 * The below multi-dimensional table is used for looking up the target
6063 * exception level given numerous condition criteria. Specifically, the
6064 * target EL is based on SCR and HCR routing controls as well as the
6065 * currently executing EL and secure state.
6068 * target_el_table[2][2][2][2][2][4]
6069 * | | | | | +--- Current EL
6070 * | | | | +------ Non-secure(0)/Secure(1)
6071 * | | | +--------- HCR mask override
6072 * | | +------------ SCR exec state control
6073 * | +--------------- SCR mask override
6074 * +------------------ 32-bit(0)/64-bit(1) EL3
6076 * The table values are as such:
6080 * The ARM ARM target EL table includes entries indicating that an "exception
6081 * is not taken". The two cases where this is applicable are:
6082 * 1) An exception is taken from EL3 but the SCR does not have the exception
6084 * 2) An exception is taken from EL2 but the HCR does not have the exception
6086 * In these two cases, the below table contain a target of EL1. This value is
6087 * returned as it is expected that the consumer of the table data will check
6088 * for "target EL >= current EL" to ensure the exception is not taken.
6092 * BIT IRQ IMO Non-secure Secure
6093 * EL3 FIQ RW FMO EL0 EL1 EL2 EL3 EL0 EL1 EL2 EL3
6095 static const int8_t target_el_table
[2][2][2][2][2][4] = {
6096 {{{{/* 0 0 0 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6097 {/* 0 0 0 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},
6098 {{/* 0 0 1 0 */{ 1, 1, 2, -1 },{ 3, -1, -1, 3 },},
6099 {/* 0 0 1 1 */{ 2, 2, 2, -1 },{ 3, -1, -1, 3 },},},},
6100 {{{/* 0 1 0 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6101 {/* 0 1 0 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},
6102 {{/* 0 1 1 0 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},
6103 {/* 0 1 1 1 */{ 3, 3, 3, -1 },{ 3, -1, -1, 3 },},},},},
6104 {{{{/* 1 0 0 0 */{ 1, 1, 2, -1 },{ 1, 1, -1, 1 },},
6105 {/* 1 0 0 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},
6106 {{/* 1 0 1 0 */{ 1, 1, 1, -1 },{ 1, 1, -1, 1 },},
6107 {/* 1 0 1 1 */{ 2, 2, 2, -1 },{ 1, 1, -1, 1 },},},},
6108 {{{/* 1 1 0 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6109 {/* 1 1 0 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},
6110 {{/* 1 1 1 0 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},
6111 {/* 1 1 1 1 */{ 3, 3, 3, -1 },{ 3, 3, -1, 3 },},},},},
6115 * Determine the target EL for physical exceptions
6117 uint32_t arm_phys_excp_target_el(CPUState
*cs
, uint32_t excp_idx
,
6118 uint32_t cur_el
, bool secure
)
6120 CPUARMState
*env
= cs
->env_ptr
;
6125 /* Is the highest EL AArch64? */
6126 int is64
= arm_feature(env
, ARM_FEATURE_AARCH64
);
6128 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
6129 rw
= ((env
->cp15
.scr_el3
& SCR_RW
) == SCR_RW
);
6131 /* Either EL2 is the highest EL (and so the EL2 register width
6132 * is given by is64); or there is no EL2 or EL3, in which case
6133 * the value of 'rw' does not affect the table lookup anyway.
6140 scr
= ((env
->cp15
.scr_el3
& SCR_IRQ
) == SCR_IRQ
);
6141 hcr
= ((env
->cp15
.hcr_el2
& HCR_IMO
) == HCR_IMO
);
6144 scr
= ((env
->cp15
.scr_el3
& SCR_FIQ
) == SCR_FIQ
);
6145 hcr
= ((env
->cp15
.hcr_el2
& HCR_FMO
) == HCR_FMO
);
6148 scr
= ((env
->cp15
.scr_el3
& SCR_EA
) == SCR_EA
);
6149 hcr
= ((env
->cp15
.hcr_el2
& HCR_AMO
) == HCR_AMO
);
6153 /* If HCR.TGE is set then HCR is treated as being 1 */
6154 hcr
|= ((env
->cp15
.hcr_el2
& HCR_TGE
) == HCR_TGE
);
6156 /* Perform a table-lookup for the target EL given the current state */
6157 target_el
= target_el_table
[is64
][scr
][rw
][hcr
][secure
][cur_el
];
6159 assert(target_el
> 0);
6164 static void v7m_push(CPUARMState
*env
, uint32_t val
)
6166 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
6169 stl_phys(cs
->as
, env
->regs
[13], val
);
6172 /* Return true if we're using the process stack pointer (not the MSP) */
6173 static bool v7m_using_psp(CPUARMState
*env
)
6175 /* Handler mode always uses the main stack; for thread mode
6176 * the CONTROL.SPSEL bit determines the answer.
6177 * Note that in v7M it is not possible to be in Handler mode with
6178 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
6180 return !arm_v7m_is_handler_mode(env
) &&
6181 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
6184 /* Write to v7M CONTROL.SPSEL bit for the specified security bank.
6185 * This may change the current stack pointer between Main and Process
6186 * stack pointers if it is done for the CONTROL register for the current
6189 static void write_v7m_control_spsel_for_secstate(CPUARMState
*env
,
6193 bool old_is_psp
= v7m_using_psp(env
);
6195 env
->v7m
.control
[secstate
] =
6196 deposit32(env
->v7m
.control
[secstate
],
6197 R_V7M_CONTROL_SPSEL_SHIFT
,
6198 R_V7M_CONTROL_SPSEL_LENGTH
, new_spsel
);
6200 if (secstate
== env
->v7m
.secure
) {
6201 bool new_is_psp
= v7m_using_psp(env
);
6204 if (old_is_psp
!= new_is_psp
) {
6205 tmp
= env
->v7m
.other_sp
;
6206 env
->v7m
.other_sp
= env
->regs
[13];
6207 env
->regs
[13] = tmp
;
6212 /* Write to v7M CONTROL.SPSEL bit. This may change the current
6213 * stack pointer between Main and Process stack pointers.
6215 static void write_v7m_control_spsel(CPUARMState
*env
, bool new_spsel
)
6217 write_v7m_control_spsel_for_secstate(env
, new_spsel
, env
->v7m
.secure
);
6220 void write_v7m_exception(CPUARMState
*env
, uint32_t new_exc
)
6222 /* Write a new value to v7m.exception, thus transitioning into or out
6223 * of Handler mode; this may result in a change of active stack pointer.
6225 bool new_is_psp
, old_is_psp
= v7m_using_psp(env
);
6228 env
->v7m
.exception
= new_exc
;
6230 new_is_psp
= v7m_using_psp(env
);
6232 if (old_is_psp
!= new_is_psp
) {
6233 tmp
= env
->v7m
.other_sp
;
6234 env
->v7m
.other_sp
= env
->regs
[13];
6235 env
->regs
[13] = tmp
;
6239 /* Switch M profile security state between NS and S */
6240 static void switch_v7m_security_state(CPUARMState
*env
, bool new_secstate
)
6242 uint32_t new_ss_msp
, new_ss_psp
;
6244 if (env
->v7m
.secure
== new_secstate
) {
6248 /* All the banked state is accessed by looking at env->v7m.secure
6249 * except for the stack pointer; rearrange the SP appropriately.
6251 new_ss_msp
= env
->v7m
.other_ss_msp
;
6252 new_ss_psp
= env
->v7m
.other_ss_psp
;
6254 if (v7m_using_psp(env
)) {
6255 env
->v7m
.other_ss_psp
= env
->regs
[13];
6256 env
->v7m
.other_ss_msp
= env
->v7m
.other_sp
;
6258 env
->v7m
.other_ss_msp
= env
->regs
[13];
6259 env
->v7m
.other_ss_psp
= env
->v7m
.other_sp
;
6262 env
->v7m
.secure
= new_secstate
;
6264 if (v7m_using_psp(env
)) {
6265 env
->regs
[13] = new_ss_psp
;
6266 env
->v7m
.other_sp
= new_ss_msp
;
6268 env
->regs
[13] = new_ss_msp
;
6269 env
->v7m
.other_sp
= new_ss_psp
;
6273 void HELPER(v7m_bxns
)(CPUARMState
*env
, uint32_t dest
)
6276 * - if the return value is a magic value, do exception return (like BX)
6277 * - otherwise bit 0 of the return value is the target security state
6281 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6282 /* Covers FNC_RETURN and EXC_RETURN magic */
6283 min_magic
= FNC_RETURN_MIN_MAGIC
;
6285 /* EXC_RETURN magic only */
6286 min_magic
= EXC_RETURN_MIN_MAGIC
;
6289 if (dest
>= min_magic
) {
6290 /* This is an exception return magic value; put it where
6291 * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT.
6292 * Note that if we ever add gen_ss_advance() singlestep support to
6293 * M profile this should count as an "instruction execution complete"
6294 * event (compare gen_bx_excret_final_code()).
6296 env
->regs
[15] = dest
& ~1;
6297 env
->thumb
= dest
& 1;
6298 HELPER(exception_internal
)(env
, EXCP_EXCEPTION_EXIT
);
6302 /* translate.c should have made BXNS UNDEF unless we're secure */
6303 assert(env
->v7m
.secure
);
6305 switch_v7m_security_state(env
, dest
& 1);
6307 env
->regs
[15] = dest
& ~1;
6310 void HELPER(v7m_blxns
)(CPUARMState
*env
, uint32_t dest
)
6312 /* Handle v7M BLXNS:
6313 * - bit 0 of the destination address is the target security state
6316 /* At this point regs[15] is the address just after the BLXNS */
6317 uint32_t nextinst
= env
->regs
[15] | 1;
6318 uint32_t sp
= env
->regs
[13] - 8;
6321 /* translate.c will have made BLXNS UNDEF unless we're secure */
6322 assert(env
->v7m
.secure
);
6325 /* target is Secure, so this is just a normal BLX,
6326 * except that the low bit doesn't indicate Thumb/not.
6328 env
->regs
[14] = nextinst
;
6330 env
->regs
[15] = dest
& ~1;
6334 /* Target is non-secure: first push a stack frame */
6335 if (!QEMU_IS_ALIGNED(sp
, 8)) {
6336 qemu_log_mask(LOG_GUEST_ERROR
,
6337 "BLXNS with misaligned SP is UNPREDICTABLE\n");
6340 saved_psr
= env
->v7m
.exception
;
6341 if (env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SFPA_MASK
) {
6342 saved_psr
|= XPSR_SFPA
;
6345 /* Note that these stores can throw exceptions on MPU faults */
6346 cpu_stl_data(env
, sp
, nextinst
);
6347 cpu_stl_data(env
, sp
+ 4, saved_psr
);
6350 env
->regs
[14] = 0xfeffffff;
6351 if (arm_v7m_is_handler_mode(env
)) {
6352 /* Write a dummy value to IPSR, to avoid leaking the current secure
6353 * exception number to non-secure code. This is guaranteed not
6354 * to cause write_v7m_exception() to actually change stacks.
6356 write_v7m_exception(env
, 1);
6358 switch_v7m_security_state(env
, 0);
6360 env
->regs
[15] = dest
;
6363 static uint32_t *get_v7m_sp_ptr(CPUARMState
*env
, bool secure
, bool threadmode
,
6366 /* Return a pointer to the location where we currently store the
6367 * stack pointer for the requested security state and thread mode.
6368 * This pointer will become invalid if the CPU state is updated
6369 * such that the stack pointers are switched around (eg changing
6370 * the SPSEL control bit).
6371 * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().
6372 * Unlike that pseudocode, we require the caller to pass us in the
6373 * SPSEL control bit value; this is because we also use this
6374 * function in handling of pushing of the callee-saves registers
6375 * part of the v8M stack frame (pseudocode PushCalleeStack()),
6376 * and in the tailchain codepath the SPSEL bit comes from the exception
6377 * return magic LR value from the previous exception. The pseudocode
6378 * opencodes the stack-selection in PushCalleeStack(), but we prefer
6379 * to make this utility function generic enough to do the job.
6381 bool want_psp
= threadmode
&& spsel
;
6383 if (secure
== env
->v7m
.secure
) {
6384 if (want_psp
== v7m_using_psp(env
)) {
6385 return &env
->regs
[13];
6387 return &env
->v7m
.other_sp
;
6391 return &env
->v7m
.other_ss_psp
;
6393 return &env
->v7m
.other_ss_msp
;
6398 static uint32_t arm_v7m_load_vector(ARMCPU
*cpu
, bool targets_secure
)
6400 CPUState
*cs
= CPU(cpu
);
6401 CPUARMState
*env
= &cpu
->env
;
6403 hwaddr vec
= env
->v7m
.vecbase
[targets_secure
] + env
->v7m
.exception
* 4;
6406 addr
= address_space_ldl(cs
->as
, vec
,
6407 MEMTXATTRS_UNSPECIFIED
, &result
);
6408 if (result
!= MEMTX_OK
) {
6409 /* Architecturally this should cause a HardFault setting HSFR.VECTTBL,
6410 * which would then be immediately followed by our failing to load
6411 * the entry vector for that HardFault, which is a Lockup case.
6412 * Since we don't model Lockup, we just report this guest error
6415 cpu_abort(cs
, "Failed to read from %s exception vector table "
6416 "entry %08x\n", targets_secure
? "secure" : "nonsecure",
6422 static void v7m_push_callee_stack(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
)
6424 /* For v8M, push the callee-saves register part of the stack frame.
6425 * Compare the v8M pseudocode PushCalleeStack().
6426 * In the tailchaining case this may not be the current stack.
6428 CPUARMState
*env
= &cpu
->env
;
6429 CPUState
*cs
= CPU(cpu
);
6430 uint32_t *frame_sp_p
;
6434 frame_sp_p
= get_v7m_sp_ptr(env
, true,
6435 lr
& R_V7M_EXCRET_MODE_MASK
,
6436 lr
& R_V7M_EXCRET_SPSEL_MASK
);
6438 frame_sp_p
= &env
->regs
[13];
6441 frameptr
= *frame_sp_p
- 0x28;
6443 stl_phys(cs
->as
, frameptr
, 0xfefa125b);
6444 stl_phys(cs
->as
, frameptr
+ 0x8, env
->regs
[4]);
6445 stl_phys(cs
->as
, frameptr
+ 0xc, env
->regs
[5]);
6446 stl_phys(cs
->as
, frameptr
+ 0x10, env
->regs
[6]);
6447 stl_phys(cs
->as
, frameptr
+ 0x14, env
->regs
[7]);
6448 stl_phys(cs
->as
, frameptr
+ 0x18, env
->regs
[8]);
6449 stl_phys(cs
->as
, frameptr
+ 0x1c, env
->regs
[9]);
6450 stl_phys(cs
->as
, frameptr
+ 0x20, env
->regs
[10]);
6451 stl_phys(cs
->as
, frameptr
+ 0x24, env
->regs
[11]);
6453 *frame_sp_p
= frameptr
;
6456 static void v7m_exception_taken(ARMCPU
*cpu
, uint32_t lr
, bool dotailchain
)
6458 /* Do the "take the exception" parts of exception entry,
6459 * but not the pushing of state to the stack. This is
6460 * similar to the pseudocode ExceptionTaken() function.
6462 CPUARMState
*env
= &cpu
->env
;
6464 bool targets_secure
;
6466 targets_secure
= armv7m_nvic_acknowledge_irq(env
->nvic
);
6468 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6469 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6470 (lr
& R_V7M_EXCRET_S_MASK
)) {
6471 /* The background code (the owner of the registers in the
6472 * exception frame) is Secure. This means it may either already
6473 * have or now needs to push callee-saves registers.
6475 if (targets_secure
) {
6476 if (dotailchain
&& !(lr
& R_V7M_EXCRET_ES_MASK
)) {
6477 /* We took an exception from Secure to NonSecure
6478 * (which means the callee-saved registers got stacked)
6479 * and are now tailchaining to a Secure exception.
6480 * Clear DCRS so eventual return from this Secure
6481 * exception unstacks the callee-saved registers.
6483 lr
&= ~R_V7M_EXCRET_DCRS_MASK
;
6486 /* We're going to a non-secure exception; push the
6487 * callee-saves registers to the stack now, if they're
6488 * not already saved.
6490 if (lr
& R_V7M_EXCRET_DCRS_MASK
&&
6491 !(dotailchain
&& (lr
& R_V7M_EXCRET_ES_MASK
))) {
6492 v7m_push_callee_stack(cpu
, lr
, dotailchain
);
6494 lr
|= R_V7M_EXCRET_DCRS_MASK
;
6498 lr
&= ~R_V7M_EXCRET_ES_MASK
;
6499 if (targets_secure
|| !arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6500 lr
|= R_V7M_EXCRET_ES_MASK
;
6502 lr
&= ~R_V7M_EXCRET_SPSEL_MASK
;
6503 if (env
->v7m
.control
[targets_secure
] & R_V7M_CONTROL_SPSEL_MASK
) {
6504 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
6507 /* Clear registers if necessary to prevent non-secure exception
6508 * code being able to see register values from secure code.
6509 * Where register values become architecturally UNKNOWN we leave
6510 * them with their previous values.
6512 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6513 if (!targets_secure
) {
6514 /* Always clear the caller-saved registers (they have been
6515 * pushed to the stack earlier in v7m_push_stack()).
6516 * Clear callee-saved registers if the background code is
6517 * Secure (in which case these regs were saved in
6518 * v7m_push_callee_stack()).
6522 for (i
= 0; i
< 13; i
++) {
6523 /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
6524 if (i
< 4 || i
> 11 || (lr
& R_V7M_EXCRET_S_MASK
)) {
6529 xpsr_write(env
, 0, XPSR_NZCV
| XPSR_Q
| XPSR_GE
| XPSR_IT
);
6534 /* Switch to target security state -- must do this before writing SPSEL */
6535 switch_v7m_security_state(env
, targets_secure
);
6536 write_v7m_control_spsel(env
, 0);
6537 arm_clear_exclusive(env
);
6539 env
->condexec_bits
= 0;
6541 addr
= arm_v7m_load_vector(cpu
, targets_secure
);
6542 env
->regs
[15] = addr
& 0xfffffffe;
6543 env
->thumb
= addr
& 1;
6546 static void v7m_push_stack(ARMCPU
*cpu
)
6548 /* Do the "set up stack frame" part of exception entry,
6549 * similar to pseudocode PushStack().
6551 CPUARMState
*env
= &cpu
->env
;
6552 uint32_t xpsr
= xpsr_read(env
);
6554 /* Align stack pointer if the guest wants that */
6555 if ((env
->regs
[13] & 4) &&
6556 (env
->v7m
.ccr
[env
->v7m
.secure
] & R_V7M_CCR_STKALIGN_MASK
)) {
6558 xpsr
|= XPSR_SPREALIGN
;
6560 /* Switch to the handler mode. */
6561 v7m_push(env
, xpsr
);
6562 v7m_push(env
, env
->regs
[15]);
6563 v7m_push(env
, env
->regs
[14]);
6564 v7m_push(env
, env
->regs
[12]);
6565 v7m_push(env
, env
->regs
[3]);
6566 v7m_push(env
, env
->regs
[2]);
6567 v7m_push(env
, env
->regs
[1]);
6568 v7m_push(env
, env
->regs
[0]);
6571 static void do_v7m_exception_exit(ARMCPU
*cpu
)
6573 CPUARMState
*env
= &cpu
->env
;
6574 CPUState
*cs
= CPU(cpu
);
6577 bool ufault
= false;
6578 bool sfault
= false;
6579 bool return_to_sp_process
;
6580 bool return_to_handler
;
6581 bool rettobase
= false;
6582 bool exc_secure
= false;
6583 bool return_to_secure
;
6585 /* If we're not in Handler mode then jumps to magic exception-exit
6586 * addresses don't have magic behaviour. However for the v8M
6587 * security extensions the magic secure-function-return has to
6588 * work in thread mode too, so to avoid doing an extra check in
6589 * the generated code we allow exception-exit magic to also cause the
6590 * internal exception and bring us here in thread mode. Correct code
6591 * will never try to do this (the following insn fetch will always
6592 * fault) so we the overhead of having taken an unnecessary exception
6595 if (!arm_v7m_is_handler_mode(env
)) {
6599 /* In the spec pseudocode ExceptionReturn() is called directly
6600 * from BXWritePC() and gets the full target PC value including
6601 * bit zero. In QEMU's implementation we treat it as a normal
6602 * jump-to-register (which is then caught later on), and so split
6603 * the target value up between env->regs[15] and env->thumb in
6604 * gen_bx(). Reconstitute it.
6606 excret
= env
->regs
[15];
6611 qemu_log_mask(CPU_LOG_INT
, "Exception return: magic PC %" PRIx32
6612 " previous exception %d\n",
6613 excret
, env
->v7m
.exception
);
6615 if ((excret
& R_V7M_EXCRET_RES1_MASK
) != R_V7M_EXCRET_RES1_MASK
) {
6616 qemu_log_mask(LOG_GUEST_ERROR
, "M profile: zero high bits in exception "
6617 "exit PC value 0x%" PRIx32
" are UNPREDICTABLE\n",
6621 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6622 /* EXC_RETURN.ES validation check (R_SMFL). We must do this before
6623 * we pick which FAULTMASK to clear.
6625 if (!env
->v7m
.secure
&&
6626 ((excret
& R_V7M_EXCRET_ES_MASK
) ||
6627 !(excret
& R_V7M_EXCRET_DCRS_MASK
))) {
6629 /* For all other purposes, treat ES as 0 (R_HXSR) */
6630 excret
&= ~R_V7M_EXCRET_ES_MASK
;
6634 if (env
->v7m
.exception
!= ARMV7M_EXCP_NMI
) {
6635 /* Auto-clear FAULTMASK on return from other than NMI.
6636 * If the security extension is implemented then this only
6637 * happens if the raw execution priority is >= 0; the
6638 * value of the ES bit in the exception return value indicates
6639 * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)
6641 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6642 exc_secure
= excret
& R_V7M_EXCRET_ES_MASK
;
6643 if (armv7m_nvic_raw_execution_priority(env
->nvic
) >= 0) {
6644 env
->v7m
.faultmask
[exc_secure
] = 0;
6647 env
->v7m
.faultmask
[M_REG_NS
] = 0;
6651 switch (armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
,
6654 /* attempt to exit an exception that isn't active */
6658 /* still an irq active now */
6661 /* we returned to base exception level, no nesting.
6662 * (In the pseudocode this is written using "NestedActivation != 1"
6663 * where we have 'rettobase == false'.)
6668 g_assert_not_reached();
6671 return_to_handler
= !(excret
& R_V7M_EXCRET_MODE_MASK
);
6672 return_to_sp_process
= excret
& R_V7M_EXCRET_SPSEL_MASK
;
6673 return_to_secure
= arm_feature(env
, ARM_FEATURE_M_SECURITY
) &&
6674 (excret
& R_V7M_EXCRET_S_MASK
);
6676 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6677 if (!arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
6678 /* UNPREDICTABLE if S == 1 or DCRS == 0 or ES == 1 (R_XLCP);
6679 * we choose to take the UsageFault.
6681 if ((excret
& R_V7M_EXCRET_S_MASK
) ||
6682 (excret
& R_V7M_EXCRET_ES_MASK
) ||
6683 !(excret
& R_V7M_EXCRET_DCRS_MASK
)) {
6687 if (excret
& R_V7M_EXCRET_RES0_MASK
) {
6691 /* For v7M we only recognize certain combinations of the low bits */
6692 switch (excret
& 0xf) {
6693 case 1: /* Return to Handler */
6695 case 13: /* Return to Thread using Process stack */
6696 case 9: /* Return to Thread using Main stack */
6697 /* We only need to check NONBASETHRDENA for v7M, because in
6698 * v8M this bit does not exist (it is RES1).
6701 !(env
->v7m
.ccr
[env
->v7m
.secure
] &
6702 R_V7M_CCR_NONBASETHRDENA_MASK
)) {
6712 env
->v7m
.sfsr
|= R_V7M_SFSR_INVER_MASK
;
6713 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
6714 v7m_exception_taken(cpu
, excret
, true);
6715 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
6716 "stackframe: failed EXC_RETURN.ES validity check\n");
6721 /* Bad exception return: instead of popping the exception
6722 * stack, directly take a usage fault on the current stack.
6724 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6725 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
6726 v7m_exception_taken(cpu
, excret
, true);
6727 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
6728 "stackframe: failed exception return integrity check\n");
6732 /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in
6733 * Handler mode (and will be until we write the new XPSR.Interrupt
6734 * field) this does not switch around the current stack pointer.
6736 write_v7m_control_spsel_for_secstate(env
, return_to_sp_process
, exc_secure
);
6738 switch_v7m_security_state(env
, return_to_secure
);
6741 /* The stack pointer we should be reading the exception frame from
6742 * depends on bits in the magic exception return type value (and
6743 * for v8M isn't necessarily the stack pointer we will eventually
6744 * end up resuming execution with). Get a pointer to the location
6745 * in the CPU state struct where the SP we need is currently being
6746 * stored; we will use and modify it in place.
6747 * We use this limited C variable scope so we don't accidentally
6748 * use 'frame_sp_p' after we do something that makes it invalid.
6750 uint32_t *frame_sp_p
= get_v7m_sp_ptr(env
,
6753 return_to_sp_process
);
6754 uint32_t frameptr
= *frame_sp_p
;
6756 if (!QEMU_IS_ALIGNED(frameptr
, 8) &&
6757 arm_feature(env
, ARM_FEATURE_V8
)) {
6758 qemu_log_mask(LOG_GUEST_ERROR
,
6759 "M profile exception return with non-8-aligned SP "
6760 "for destination state is UNPREDICTABLE\n");
6763 /* Do we need to pop callee-saved registers? */
6764 if (return_to_secure
&&
6765 ((excret
& R_V7M_EXCRET_ES_MASK
) == 0 ||
6766 (excret
& R_V7M_EXCRET_DCRS_MASK
) == 0)) {
6767 uint32_t expected_sig
= 0xfefa125b;
6768 uint32_t actual_sig
= ldl_phys(cs
->as
, frameptr
);
6770 if (expected_sig
!= actual_sig
) {
6771 /* Take a SecureFault on the current stack */
6772 env
->v7m
.sfsr
|= R_V7M_SFSR_INVIS_MASK
;
6773 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
6774 v7m_exception_taken(cpu
, excret
, true);
6775 qemu_log_mask(CPU_LOG_INT
, "...taking SecureFault on existing "
6776 "stackframe: failed exception return integrity "
6777 "signature check\n");
6781 env
->regs
[4] = ldl_phys(cs
->as
, frameptr
+ 0x8);
6782 env
->regs
[5] = ldl_phys(cs
->as
, frameptr
+ 0xc);
6783 env
->regs
[6] = ldl_phys(cs
->as
, frameptr
+ 0x10);
6784 env
->regs
[7] = ldl_phys(cs
->as
, frameptr
+ 0x14);
6785 env
->regs
[8] = ldl_phys(cs
->as
, frameptr
+ 0x18);
6786 env
->regs
[9] = ldl_phys(cs
->as
, frameptr
+ 0x1c);
6787 env
->regs
[10] = ldl_phys(cs
->as
, frameptr
+ 0x20);
6788 env
->regs
[11] = ldl_phys(cs
->as
, frameptr
+ 0x24);
6793 /* Pop registers. TODO: make these accesses use the correct
6794 * attributes and address space (S/NS, priv/unpriv) and handle
6795 * memory transaction failures.
6797 env
->regs
[0] = ldl_phys(cs
->as
, frameptr
);
6798 env
->regs
[1] = ldl_phys(cs
->as
, frameptr
+ 0x4);
6799 env
->regs
[2] = ldl_phys(cs
->as
, frameptr
+ 0x8);
6800 env
->regs
[3] = ldl_phys(cs
->as
, frameptr
+ 0xc);
6801 env
->regs
[12] = ldl_phys(cs
->as
, frameptr
+ 0x10);
6802 env
->regs
[14] = ldl_phys(cs
->as
, frameptr
+ 0x14);
6803 env
->regs
[15] = ldl_phys(cs
->as
, frameptr
+ 0x18);
6805 /* Returning from an exception with a PC with bit 0 set is defined
6806 * behaviour on v8M (bit 0 is ignored), but for v7M it was specified
6807 * to be UNPREDICTABLE. In practice actual v7M hardware seems to ignore
6808 * the lsbit, and there are several RTOSes out there which incorrectly
6809 * assume the r15 in the stack frame should be a Thumb-style "lsbit
6810 * indicates ARM/Thumb" value, so ignore the bit on v7M as well, but
6811 * complain about the badly behaved guest.
6813 if (env
->regs
[15] & 1) {
6814 env
->regs
[15] &= ~1U;
6815 if (!arm_feature(env
, ARM_FEATURE_V8
)) {
6816 qemu_log_mask(LOG_GUEST_ERROR
,
6817 "M profile return from interrupt with misaligned "
6818 "PC is UNPREDICTABLE on v7M\n");
6822 xpsr
= ldl_phys(cs
->as
, frameptr
+ 0x1c);
6824 if (arm_feature(env
, ARM_FEATURE_V8
)) {
6825 /* For v8M we have to check whether the xPSR exception field
6826 * matches the EXCRET value for return to handler/thread
6827 * before we commit to changing the SP and xPSR.
6829 bool will_be_handler
= (xpsr
& XPSR_EXCP
) != 0;
6830 if (return_to_handler
!= will_be_handler
) {
6831 /* Take an INVPC UsageFault on the current stack.
6832 * By this point we will have switched to the security state
6833 * for the background state, so this UsageFault will target
6836 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
6838 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6839 v7m_exception_taken(cpu
, excret
, true);
6840 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on existing "
6841 "stackframe: failed exception return integrity "
6847 /* Commit to consuming the stack frame */
6849 /* Undo stack alignment (the SPREALIGN bit indicates that the original
6850 * pre-exception SP was not 8-aligned and we added a padding word to
6851 * align it, so we undo this by ORing in the bit that increases it
6852 * from the current 8-aligned value to the 8-unaligned value. (Adding 4
6853 * would work too but a logical OR is how the pseudocode specifies it.)
6855 if (xpsr
& XPSR_SPREALIGN
) {
6858 *frame_sp_p
= frameptr
;
6860 /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
6861 xpsr_write(env
, xpsr
, ~XPSR_SPREALIGN
);
6863 /* The restored xPSR exception field will be zero if we're
6864 * resuming in Thread mode. If that doesn't match what the
6865 * exception return excret specified then this is a UsageFault.
6866 * v7M requires we make this check here; v8M did it earlier.
6868 if (return_to_handler
!= arm_v7m_is_handler_mode(env
)) {
6869 /* Take an INVPC UsageFault by pushing the stack again;
6870 * we know we're v7M so this is never a Secure UsageFault.
6872 assert(!arm_feature(env
, ARM_FEATURE_V8
));
6873 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, false);
6874 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6875 v7m_push_stack(cpu
);
6876 v7m_exception_taken(cpu
, excret
, false);
6877 qemu_log_mask(CPU_LOG_INT
, "...taking UsageFault on new stackframe: "
6878 "failed exception return integrity check\n");
6882 /* Otherwise, we have a successful exception exit. */
6883 arm_clear_exclusive(env
);
6884 qemu_log_mask(CPU_LOG_INT
, "...successful exception return\n");
6887 static bool do_v7m_function_return(ARMCPU
*cpu
)
6889 /* v8M security extensions magic function return.
6891 * (1) throw an exception (longjump)
6892 * (2) return true if we successfully handled the function return
6893 * (3) return false if we failed a consistency check and have
6894 * pended a UsageFault that needs to be taken now
6896 * At this point the magic return value is split between env->regs[15]
6897 * and env->thumb. We don't bother to reconstitute it because we don't
6898 * need it (all values are handled the same way).
6900 CPUARMState
*env
= &cpu
->env
;
6901 uint32_t newpc
, newpsr
, newpsr_exc
;
6903 qemu_log_mask(CPU_LOG_INT
, "...really v7M secure function return\n");
6906 bool threadmode
, spsel
;
6909 uint32_t *frame_sp_p
;
6912 /* Pull the return address and IPSR from the Secure stack */
6913 threadmode
= !arm_v7m_is_handler_mode(env
);
6914 spsel
= env
->v7m
.control
[M_REG_S
] & R_V7M_CONTROL_SPSEL_MASK
;
6916 frame_sp_p
= get_v7m_sp_ptr(env
, true, threadmode
, spsel
);
6917 frameptr
= *frame_sp_p
;
6919 /* These loads may throw an exception (for MPU faults). We want to
6920 * do them as secure, so work out what MMU index that is.
6922 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
6923 oi
= make_memop_idx(MO_LE
, arm_to_core_mmu_idx(mmu_idx
));
6924 newpc
= helper_le_ldul_mmu(env
, frameptr
, oi
, 0);
6925 newpsr
= helper_le_ldul_mmu(env
, frameptr
+ 4, oi
, 0);
6927 /* Consistency checks on new IPSR */
6928 newpsr_exc
= newpsr
& XPSR_EXCP
;
6929 if (!((env
->v7m
.exception
== 0 && newpsr_exc
== 0) ||
6930 (env
->v7m
.exception
== 1 && newpsr_exc
!= 0))) {
6931 /* Pend the fault and tell our caller to take it */
6932 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVPC_MASK
;
6933 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
,
6935 qemu_log_mask(CPU_LOG_INT
,
6936 "...taking INVPC UsageFault: "
6937 "IPSR consistency check failed\n");
6941 *frame_sp_p
= frameptr
+ 8;
6944 /* This invalidates frame_sp_p */
6945 switch_v7m_security_state(env
, true);
6946 env
->v7m
.exception
= newpsr_exc
;
6947 env
->v7m
.control
[M_REG_S
] &= ~R_V7M_CONTROL_SFPA_MASK
;
6948 if (newpsr
& XPSR_SFPA
) {
6949 env
->v7m
.control
[M_REG_S
] |= R_V7M_CONTROL_SFPA_MASK
;
6951 xpsr_write(env
, 0, XPSR_IT
);
6952 env
->thumb
= newpc
& 1;
6953 env
->regs
[15] = newpc
& ~1;
6955 qemu_log_mask(CPU_LOG_INT
, "...function return successful\n");
6959 static void arm_log_exception(int idx
)
6961 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
6962 const char *exc
= NULL
;
6963 static const char * const excnames
[] = {
6964 [EXCP_UDEF
] = "Undefined Instruction",
6966 [EXCP_PREFETCH_ABORT
] = "Prefetch Abort",
6967 [EXCP_DATA_ABORT
] = "Data Abort",
6970 [EXCP_BKPT
] = "Breakpoint",
6971 [EXCP_EXCEPTION_EXIT
] = "QEMU v7M exception exit",
6972 [EXCP_KERNEL_TRAP
] = "QEMU intercept of kernel commpage",
6973 [EXCP_HVC
] = "Hypervisor Call",
6974 [EXCP_HYP_TRAP
] = "Hypervisor Trap",
6975 [EXCP_SMC
] = "Secure Monitor Call",
6976 [EXCP_VIRQ
] = "Virtual IRQ",
6977 [EXCP_VFIQ
] = "Virtual FIQ",
6978 [EXCP_SEMIHOST
] = "Semihosting call",
6979 [EXCP_NOCP
] = "v7M NOCP UsageFault",
6980 [EXCP_INVSTATE
] = "v7M INVSTATE UsageFault",
6983 if (idx
>= 0 && idx
< ARRAY_SIZE(excnames
)) {
6984 exc
= excnames
[idx
];
6989 qemu_log_mask(CPU_LOG_INT
, "Taking exception %d [%s]\n", idx
, exc
);
6993 static bool v7m_read_half_insn(ARMCPU
*cpu
, ARMMMUIdx mmu_idx
,
6994 uint32_t addr
, uint16_t *insn
)
6996 /* Load a 16-bit portion of a v7M instruction, returning true on success,
6997 * or false on failure (in which case we will have pended the appropriate
6999 * We need to do the instruction fetch's MPU and SAU checks
7000 * like this because there is no MMU index that would allow
7001 * doing the load with a single function call. Instead we must
7002 * first check that the security attributes permit the load
7003 * and that they don't mismatch on the two halves of the instruction,
7004 * and then we do the load as a secure load (ie using the security
7005 * attributes of the address, not the CPU, as architecturally required).
7007 CPUState
*cs
= CPU(cpu
);
7008 CPUARMState
*env
= &cpu
->env
;
7009 V8M_SAttributes sattrs
= {};
7010 MemTxAttrs attrs
= {};
7011 ARMMMUFaultInfo fi
= {};
7013 target_ulong page_size
;
7017 v8m_security_lookup(env
, addr
, MMU_INST_FETCH
, mmu_idx
, &sattrs
);
7018 if (!sattrs
.nsc
|| sattrs
.ns
) {
7019 /* This must be the second half of the insn, and it straddles a
7020 * region boundary with the second half not being S&NSC.
7022 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7023 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7024 qemu_log_mask(CPU_LOG_INT
,
7025 "...really SecureFault with SFSR.INVEP\n");
7028 if (get_phys_addr(env
, addr
, MMU_INST_FETCH
, mmu_idx
,
7029 &physaddr
, &attrs
, &prot
, &page_size
, &fi
, NULL
)) {
7030 /* the MPU lookup failed */
7031 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7032 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
, env
->v7m
.secure
);
7033 qemu_log_mask(CPU_LOG_INT
, "...really MemManage with CFSR.IACCVIOL\n");
7036 *insn
= address_space_lduw_le(arm_addressspace(cs
, attrs
), physaddr
,
7038 if (txres
!= MEMTX_OK
) {
7039 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7040 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7041 qemu_log_mask(CPU_LOG_INT
, "...really BusFault with CFSR.IBUSERR\n");
7047 static bool v7m_handle_execute_nsc(ARMCPU
*cpu
)
7049 /* Check whether this attempt to execute code in a Secure & NS-Callable
7050 * memory region is for an SG instruction; if so, then emulate the
7051 * effect of the SG instruction and return true. Otherwise pend
7052 * the correct kind of exception and return false.
7054 CPUARMState
*env
= &cpu
->env
;
7058 /* We should never get here unless get_phys_addr_pmsav8() caused
7059 * an exception for NS executing in S&NSC memory.
7061 assert(!env
->v7m
.secure
);
7062 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7064 /* We want to do the MPU lookup as secure; work out what mmu_idx that is */
7065 mmu_idx
= arm_v7m_mmu_idx_for_secstate(env
, true);
7067 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15], &insn
)) {
7075 if (insn
!= 0xe97f) {
7076 /* Not an SG instruction first half (we choose the IMPDEF
7077 * early-SG-check option).
7082 if (!v7m_read_half_insn(cpu
, mmu_idx
, env
->regs
[15] + 2, &insn
)) {
7086 if (insn
!= 0xe97f) {
7087 /* Not an SG instruction second half (yes, both halves of the SG
7088 * insn have the same hex value)
7093 /* OK, we have confirmed that we really have an SG instruction.
7094 * We know we're NS in S memory so don't need to repeat those checks.
7096 qemu_log_mask(CPU_LOG_INT
, "...really an SG instruction at 0x%08" PRIx32
7097 ", executing it\n", env
->regs
[15]);
7098 env
->regs
[14] &= ~1;
7099 switch_v7m_security_state(env
, true);
7100 xpsr_write(env
, 0, XPSR_IT
);
7105 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7106 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7107 qemu_log_mask(CPU_LOG_INT
,
7108 "...really SecureFault with SFSR.INVEP\n");
7112 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
7114 ARMCPU
*cpu
= ARM_CPU(cs
);
7115 CPUARMState
*env
= &cpu
->env
;
7118 arm_log_exception(cs
->exception_index
);
7120 /* For exceptions we just mark as pending on the NVIC, and let that
7122 switch (cs
->exception_index
) {
7124 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7125 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_UNDEFINSTR_MASK
;
7128 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7129 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_NOCP_MASK
;
7132 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
, env
->v7m
.secure
);
7133 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_INVSTATE_MASK
;
7136 /* The PC already points to the next instruction. */
7137 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
, env
->v7m
.secure
);
7139 case EXCP_PREFETCH_ABORT
:
7140 case EXCP_DATA_ABORT
:
7141 /* Note that for M profile we don't have a guest facing FSR, but
7142 * the env->exception.fsr will be populated by the code that
7143 * raises the fault, in the A profile short-descriptor format.
7145 switch (env
->exception
.fsr
& 0xf) {
7146 case M_FAKE_FSR_NSC_EXEC
:
7147 /* Exception generated when we try to execute code at an address
7148 * which is marked as Secure & Non-Secure Callable and the CPU
7149 * is in the Non-Secure state. The only instruction which can
7150 * be executed like this is SG (and that only if both halves of
7151 * the SG instruction have the same security attributes.)
7152 * Everything else must generate an INVEP SecureFault, so we
7153 * emulate the SG instruction here.
7155 if (v7m_handle_execute_nsc(cpu
)) {
7159 case M_FAKE_FSR_SFAULT
:
7160 /* Various flavours of SecureFault for attempts to execute or
7161 * access data in the wrong security state.
7163 switch (cs
->exception_index
) {
7164 case EXCP_PREFETCH_ABORT
:
7165 if (env
->v7m
.secure
) {
7166 env
->v7m
.sfsr
|= R_V7M_SFSR_INVTRAN_MASK
;
7167 qemu_log_mask(CPU_LOG_INT
,
7168 "...really SecureFault with SFSR.INVTRAN\n");
7170 env
->v7m
.sfsr
|= R_V7M_SFSR_INVEP_MASK
;
7171 qemu_log_mask(CPU_LOG_INT
,
7172 "...really SecureFault with SFSR.INVEP\n");
7175 case EXCP_DATA_ABORT
:
7176 /* This must be an NS access to S memory */
7177 env
->v7m
.sfsr
|= R_V7M_SFSR_AUVIOL_MASK
;
7178 qemu_log_mask(CPU_LOG_INT
,
7179 "...really SecureFault with SFSR.AUVIOL\n");
7182 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SECURE
, false);
7184 case 0x8: /* External Abort */
7185 switch (cs
->exception_index
) {
7186 case EXCP_PREFETCH_ABORT
:
7187 env
->v7m
.cfsr
[M_REG_NS
] |= R_V7M_CFSR_IBUSERR_MASK
;
7188 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IBUSERR\n");
7190 case EXCP_DATA_ABORT
:
7191 env
->v7m
.cfsr
[M_REG_NS
] |=
7192 (R_V7M_CFSR_PRECISERR_MASK
| R_V7M_CFSR_BFARVALID_MASK
);
7193 env
->v7m
.bfar
= env
->exception
.vaddress
;
7194 qemu_log_mask(CPU_LOG_INT
,
7195 "...with CFSR.PRECISERR and BFAR 0x%x\n",
7199 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_BUS
, false);
7202 /* All other FSR values are either MPU faults or "can't happen
7203 * for M profile" cases.
7205 switch (cs
->exception_index
) {
7206 case EXCP_PREFETCH_ABORT
:
7207 env
->v7m
.cfsr
[env
->v7m
.secure
] |= R_V7M_CFSR_IACCVIOL_MASK
;
7208 qemu_log_mask(CPU_LOG_INT
, "...with CFSR.IACCVIOL\n");
7210 case EXCP_DATA_ABORT
:
7211 env
->v7m
.cfsr
[env
->v7m
.secure
] |=
7212 (R_V7M_CFSR_DACCVIOL_MASK
| R_V7M_CFSR_MMARVALID_MASK
);
7213 env
->v7m
.mmfar
[env
->v7m
.secure
] = env
->exception
.vaddress
;
7214 qemu_log_mask(CPU_LOG_INT
,
7215 "...with CFSR.DACCVIOL and MMFAR 0x%x\n",
7216 env
->v7m
.mmfar
[env
->v7m
.secure
]);
7219 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
,
7225 if (semihosting_enabled()) {
7227 nr
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
)) & 0xff;
7230 qemu_log_mask(CPU_LOG_INT
,
7231 "...handling as semihosting call 0x%x\n",
7233 env
->regs
[0] = do_arm_semihosting(env
);
7237 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
, false);
7241 case EXCP_EXCEPTION_EXIT
:
7242 if (env
->regs
[15] < EXC_RETURN_MIN_MAGIC
) {
7243 /* Must be v8M security extension function return */
7244 assert(env
->regs
[15] >= FNC_RETURN_MIN_MAGIC
);
7245 assert(arm_feature(env
, ARM_FEATURE_M_SECURITY
));
7246 if (do_v7m_function_return(cpu
)) {
7250 do_v7m_exception_exit(cpu
);
7255 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7256 return; /* Never happens. Keep compiler happy. */
7259 if (arm_feature(env
, ARM_FEATURE_V8
)) {
7260 lr
= R_V7M_EXCRET_RES1_MASK
|
7261 R_V7M_EXCRET_DCRS_MASK
|
7262 R_V7M_EXCRET_FTYPE_MASK
;
7263 /* The S bit indicates whether we should return to Secure
7264 * or NonSecure (ie our current state).
7265 * The ES bit indicates whether we're taking this exception
7266 * to Secure or NonSecure (ie our target state). We set it
7267 * later, in v7m_exception_taken().
7268 * The SPSEL bit is also set in v7m_exception_taken() for v8M.
7269 * This corresponds to the ARM ARM pseudocode for v8M setting
7270 * some LR bits in PushStack() and some in ExceptionTaken();
7271 * the distinction matters for the tailchain cases where we
7272 * can take an exception without pushing the stack.
7274 if (env
->v7m
.secure
) {
7275 lr
|= R_V7M_EXCRET_S_MASK
;
7278 lr
= R_V7M_EXCRET_RES1_MASK
|
7279 R_V7M_EXCRET_S_MASK
|
7280 R_V7M_EXCRET_DCRS_MASK
|
7281 R_V7M_EXCRET_FTYPE_MASK
|
7282 R_V7M_EXCRET_ES_MASK
;
7283 if (env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
) {
7284 lr
|= R_V7M_EXCRET_SPSEL_MASK
;
7287 if (!arm_v7m_is_handler_mode(env
)) {
7288 lr
|= R_V7M_EXCRET_MODE_MASK
;
7291 v7m_push_stack(cpu
);
7292 v7m_exception_taken(cpu
, lr
, false);
7293 qemu_log_mask(CPU_LOG_INT
, "... as %d\n", env
->v7m
.exception
);
7296 /* Function used to synchronize QEMU's AArch64 register set with AArch32
7297 * register set. This is necessary when switching between AArch32 and AArch64
7300 void aarch64_sync_32_to_64(CPUARMState
*env
)
7303 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7305 /* We can blanket copy R[0:7] to X[0:7] */
7306 for (i
= 0; i
< 8; i
++) {
7307 env
->xregs
[i
] = env
->regs
[i
];
7310 /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
7311 * Otherwise, they come from the banked user regs.
7313 if (mode
== ARM_CPU_MODE_FIQ
) {
7314 for (i
= 8; i
< 13; i
++) {
7315 env
->xregs
[i
] = env
->usr_regs
[i
- 8];
7318 for (i
= 8; i
< 13; i
++) {
7319 env
->xregs
[i
] = env
->regs
[i
];
7323 /* Registers x13-x23 are the various mode SP and FP registers. Registers
7324 * r13 and r14 are only copied if we are in that mode, otherwise we copy
7325 * from the mode banked register.
7327 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7328 env
->xregs
[13] = env
->regs
[13];
7329 env
->xregs
[14] = env
->regs
[14];
7331 env
->xregs
[13] = env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)];
7332 /* HYP is an exception in that it is copied from r14 */
7333 if (mode
== ARM_CPU_MODE_HYP
) {
7334 env
->xregs
[14] = env
->regs
[14];
7336 env
->xregs
[14] = env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)];
7340 if (mode
== ARM_CPU_MODE_HYP
) {
7341 env
->xregs
[15] = env
->regs
[13];
7343 env
->xregs
[15] = env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)];
7346 if (mode
== ARM_CPU_MODE_IRQ
) {
7347 env
->xregs
[16] = env
->regs
[14];
7348 env
->xregs
[17] = env
->regs
[13];
7350 env
->xregs
[16] = env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)];
7351 env
->xregs
[17] = env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)];
7354 if (mode
== ARM_CPU_MODE_SVC
) {
7355 env
->xregs
[18] = env
->regs
[14];
7356 env
->xregs
[19] = env
->regs
[13];
7358 env
->xregs
[18] = env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)];
7359 env
->xregs
[19] = env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)];
7362 if (mode
== ARM_CPU_MODE_ABT
) {
7363 env
->xregs
[20] = env
->regs
[14];
7364 env
->xregs
[21] = env
->regs
[13];
7366 env
->xregs
[20] = env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)];
7367 env
->xregs
[21] = env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)];
7370 if (mode
== ARM_CPU_MODE_UND
) {
7371 env
->xregs
[22] = env
->regs
[14];
7372 env
->xregs
[23] = env
->regs
[13];
7374 env
->xregs
[22] = env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)];
7375 env
->xregs
[23] = env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)];
7378 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7379 * mode, then we can copy from r8-r14. Otherwise, we copy from the
7380 * FIQ bank for r8-r14.
7382 if (mode
== ARM_CPU_MODE_FIQ
) {
7383 for (i
= 24; i
< 31; i
++) {
7384 env
->xregs
[i
] = env
->regs
[i
- 16]; /* X[24:30] <- R[8:14] */
7387 for (i
= 24; i
< 29; i
++) {
7388 env
->xregs
[i
] = env
->fiq_regs
[i
- 24];
7390 env
->xregs
[29] = env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)];
7391 env
->xregs
[30] = env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)];
7394 env
->pc
= env
->regs
[15];
7397 /* Function used to synchronize QEMU's AArch32 register set with AArch64
7398 * register set. This is necessary when switching between AArch32 and AArch64
7401 void aarch64_sync_64_to_32(CPUARMState
*env
)
7404 uint32_t mode
= env
->uncached_cpsr
& CPSR_M
;
7406 /* We can blanket copy X[0:7] to R[0:7] */
7407 for (i
= 0; i
< 8; i
++) {
7408 env
->regs
[i
] = env
->xregs
[i
];
7411 /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
7412 * Otherwise, we copy x8-x12 into the banked user regs.
7414 if (mode
== ARM_CPU_MODE_FIQ
) {
7415 for (i
= 8; i
< 13; i
++) {
7416 env
->usr_regs
[i
- 8] = env
->xregs
[i
];
7419 for (i
= 8; i
< 13; i
++) {
7420 env
->regs
[i
] = env
->xregs
[i
];
7424 /* Registers r13 & r14 depend on the current mode.
7425 * If we are in a given mode, we copy the corresponding x registers to r13
7426 * and r14. Otherwise, we copy the x register to the banked r13 and r14
7429 if (mode
== ARM_CPU_MODE_USR
|| mode
== ARM_CPU_MODE_SYS
) {
7430 env
->regs
[13] = env
->xregs
[13];
7431 env
->regs
[14] = env
->xregs
[14];
7433 env
->banked_r13
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[13];
7435 /* HYP is an exception in that it does not have its own banked r14 but
7436 * shares the USR r14
7438 if (mode
== ARM_CPU_MODE_HYP
) {
7439 env
->regs
[14] = env
->xregs
[14];
7441 env
->banked_r14
[bank_number(ARM_CPU_MODE_USR
)] = env
->xregs
[14];
7445 if (mode
== ARM_CPU_MODE_HYP
) {
7446 env
->regs
[13] = env
->xregs
[15];
7448 env
->banked_r13
[bank_number(ARM_CPU_MODE_HYP
)] = env
->xregs
[15];
7451 if (mode
== ARM_CPU_MODE_IRQ
) {
7452 env
->regs
[14] = env
->xregs
[16];
7453 env
->regs
[13] = env
->xregs
[17];
7455 env
->banked_r14
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[16];
7456 env
->banked_r13
[bank_number(ARM_CPU_MODE_IRQ
)] = env
->xregs
[17];
7459 if (mode
== ARM_CPU_MODE_SVC
) {
7460 env
->regs
[14] = env
->xregs
[18];
7461 env
->regs
[13] = env
->xregs
[19];
7463 env
->banked_r14
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[18];
7464 env
->banked_r13
[bank_number(ARM_CPU_MODE_SVC
)] = env
->xregs
[19];
7467 if (mode
== ARM_CPU_MODE_ABT
) {
7468 env
->regs
[14] = env
->xregs
[20];
7469 env
->regs
[13] = env
->xregs
[21];
7471 env
->banked_r14
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[20];
7472 env
->banked_r13
[bank_number(ARM_CPU_MODE_ABT
)] = env
->xregs
[21];
7475 if (mode
== ARM_CPU_MODE_UND
) {
7476 env
->regs
[14] = env
->xregs
[22];
7477 env
->regs
[13] = env
->xregs
[23];
7479 env
->banked_r14
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[22];
7480 env
->banked_r13
[bank_number(ARM_CPU_MODE_UND
)] = env
->xregs
[23];
7483 /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in FIQ
7484 * mode, then we can copy to r8-r14. Otherwise, we copy to the
7485 * FIQ bank for r8-r14.
7487 if (mode
== ARM_CPU_MODE_FIQ
) {
7488 for (i
= 24; i
< 31; i
++) {
7489 env
->regs
[i
- 16] = env
->xregs
[i
]; /* X[24:30] -> R[8:14] */
7492 for (i
= 24; i
< 29; i
++) {
7493 env
->fiq_regs
[i
- 24] = env
->xregs
[i
];
7495 env
->banked_r13
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[29];
7496 env
->banked_r14
[bank_number(ARM_CPU_MODE_FIQ
)] = env
->xregs
[30];
7499 env
->regs
[15] = env
->pc
;
7502 static void arm_cpu_do_interrupt_aarch32(CPUState
*cs
)
7504 ARMCPU
*cpu
= ARM_CPU(cs
);
7505 CPUARMState
*env
= &cpu
->env
;
7512 /* If this is a debug exception we must update the DBGDSCR.MOE bits */
7513 switch (env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
) {
7515 case EC_BREAKPOINT_SAME_EL
:
7519 case EC_WATCHPOINT_SAME_EL
:
7525 case EC_VECTORCATCH
:
7534 env
->cp15
.mdscr_el1
= deposit64(env
->cp15
.mdscr_el1
, 2, 4, moe
);
7537 /* TODO: Vectored interrupt controller. */
7538 switch (cs
->exception_index
) {
7540 new_mode
= ARM_CPU_MODE_UND
;
7549 new_mode
= ARM_CPU_MODE_SVC
;
7552 /* The PC already points to the next instruction. */
7556 env
->exception
.fsr
= 2;
7557 /* Fall through to prefetch abort. */
7558 case EXCP_PREFETCH_ABORT
:
7559 A32_BANKED_CURRENT_REG_SET(env
, ifsr
, env
->exception
.fsr
);
7560 A32_BANKED_CURRENT_REG_SET(env
, ifar
, env
->exception
.vaddress
);
7561 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
7562 env
->exception
.fsr
, (uint32_t)env
->exception
.vaddress
);
7563 new_mode
= ARM_CPU_MODE_ABT
;
7565 mask
= CPSR_A
| CPSR_I
;
7568 case EXCP_DATA_ABORT
:
7569 A32_BANKED_CURRENT_REG_SET(env
, dfsr
, env
->exception
.fsr
);
7570 A32_BANKED_CURRENT_REG_SET(env
, dfar
, env
->exception
.vaddress
);
7571 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
7573 (uint32_t)env
->exception
.vaddress
);
7574 new_mode
= ARM_CPU_MODE_ABT
;
7576 mask
= CPSR_A
| CPSR_I
;
7580 new_mode
= ARM_CPU_MODE_IRQ
;
7582 /* Disable IRQ and imprecise data aborts. */
7583 mask
= CPSR_A
| CPSR_I
;
7585 if (env
->cp15
.scr_el3
& SCR_IRQ
) {
7586 /* IRQ routed to monitor mode */
7587 new_mode
= ARM_CPU_MODE_MON
;
7592 new_mode
= ARM_CPU_MODE_FIQ
;
7594 /* Disable FIQ, IRQ and imprecise data aborts. */
7595 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7596 if (env
->cp15
.scr_el3
& SCR_FIQ
) {
7597 /* FIQ routed to monitor mode */
7598 new_mode
= ARM_CPU_MODE_MON
;
7603 new_mode
= ARM_CPU_MODE_IRQ
;
7605 /* Disable IRQ and imprecise data aborts. */
7606 mask
= CPSR_A
| CPSR_I
;
7610 new_mode
= ARM_CPU_MODE_FIQ
;
7612 /* Disable FIQ, IRQ and imprecise data aborts. */
7613 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7617 new_mode
= ARM_CPU_MODE_MON
;
7619 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
7623 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7624 return; /* Never happens. Keep compiler happy. */
7627 if (new_mode
== ARM_CPU_MODE_MON
) {
7628 addr
+= env
->cp15
.mvbar
;
7629 } else if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
7630 /* High vectors. When enabled, base address cannot be remapped. */
7633 /* ARM v7 architectures provide a vector base address register to remap
7634 * the interrupt vector table.
7635 * This register is only followed in non-monitor mode, and is banked.
7636 * Note: only bits 31:5 are valid.
7638 addr
+= A32_BANKED_CURRENT_REG_GET(env
, vbar
);
7641 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_MON
) {
7642 env
->cp15
.scr_el3
&= ~SCR_NS
;
7645 switch_mode (env
, new_mode
);
7646 /* For exceptions taken to AArch32 we must clear the SS bit in both
7647 * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
7649 env
->uncached_cpsr
&= ~PSTATE_SS
;
7650 env
->spsr
= cpsr_read(env
);
7651 /* Clear IT bits. */
7652 env
->condexec_bits
= 0;
7653 /* Switch to the new mode, and to the correct instruction set. */
7654 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
7655 /* Set new mode endianness */
7656 env
->uncached_cpsr
&= ~CPSR_E
;
7657 if (env
->cp15
.sctlr_el
[arm_current_el(env
)] & SCTLR_EE
) {
7658 env
->uncached_cpsr
|= CPSR_E
;
7661 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
7662 * and we should just guard the thumb mode on V4 */
7663 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
7664 env
->thumb
= (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_TE
) != 0;
7666 env
->regs
[14] = env
->regs
[15] + offset
;
7667 env
->regs
[15] = addr
;
7670 /* Handle exception entry to a target EL which is using AArch64 */
7671 static void arm_cpu_do_interrupt_aarch64(CPUState
*cs
)
7673 ARMCPU
*cpu
= ARM_CPU(cs
);
7674 CPUARMState
*env
= &cpu
->env
;
7675 unsigned int new_el
= env
->exception
.target_el
;
7676 target_ulong addr
= env
->cp15
.vbar_el
[new_el
];
7677 unsigned int new_mode
= aarch64_pstate_mode(new_el
, true);
7679 if (arm_current_el(env
) < new_el
) {
7680 /* Entry vector offset depends on whether the implemented EL
7681 * immediately lower than the target level is using AArch32 or AArch64
7687 is_aa64
= (env
->cp15
.scr_el3
& SCR_RW
) != 0;
7690 is_aa64
= (env
->cp15
.hcr_el2
& HCR_RW
) != 0;
7693 is_aa64
= is_a64(env
);
7696 g_assert_not_reached();
7704 } else if (pstate_read(env
) & PSTATE_SP
) {
7708 switch (cs
->exception_index
) {
7709 case EXCP_PREFETCH_ABORT
:
7710 case EXCP_DATA_ABORT
:
7711 env
->cp15
.far_el
[new_el
] = env
->exception
.vaddress
;
7712 qemu_log_mask(CPU_LOG_INT
, "...with FAR 0x%" PRIx64
"\n",
7713 env
->cp15
.far_el
[new_el
]);
7721 env
->cp15
.esr_el
[new_el
] = env
->exception
.syndrome
;
7732 qemu_log_mask(CPU_LOG_INT
,
7733 "...handling as semihosting call 0x%" PRIx64
"\n",
7735 env
->xregs
[0] = do_arm_semihosting(env
);
7738 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
7742 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = pstate_read(env
);
7743 aarch64_save_sp(env
, arm_current_el(env
));
7744 env
->elr_el
[new_el
] = env
->pc
;
7746 env
->banked_spsr
[aarch64_banked_spsr_index(new_el
)] = cpsr_read(env
);
7747 env
->elr_el
[new_el
] = env
->regs
[15];
7749 aarch64_sync_32_to_64(env
);
7751 env
->condexec_bits
= 0;
7753 qemu_log_mask(CPU_LOG_INT
, "...with ELR 0x%" PRIx64
"\n",
7754 env
->elr_el
[new_el
]);
7756 pstate_write(env
, PSTATE_DAIF
| new_mode
);
7758 aarch64_restore_sp(env
, new_el
);
7762 qemu_log_mask(CPU_LOG_INT
, "...to EL%d PC 0x%" PRIx64
" PSTATE 0x%x\n",
7763 new_el
, env
->pc
, pstate_read(env
));
7766 static inline bool check_for_semihosting(CPUState
*cs
)
7768 /* Check whether this exception is a semihosting call; if so
7769 * then handle it and return true; otherwise return false.
7771 ARMCPU
*cpu
= ARM_CPU(cs
);
7772 CPUARMState
*env
= &cpu
->env
;
7775 if (cs
->exception_index
== EXCP_SEMIHOST
) {
7776 /* This is always the 64-bit semihosting exception.
7777 * The "is this usermode" and "is semihosting enabled"
7778 * checks have been done at translate time.
7780 qemu_log_mask(CPU_LOG_INT
,
7781 "...handling as semihosting call 0x%" PRIx64
"\n",
7783 env
->xregs
[0] = do_arm_semihosting(env
);
7790 /* Only intercept calls from privileged modes, to provide some
7791 * semblance of security.
7793 if (cs
->exception_index
!= EXCP_SEMIHOST
&&
7794 (!semihosting_enabled() ||
7795 ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_USR
))) {
7799 switch (cs
->exception_index
) {
7801 /* This is always a semihosting call; the "is this usermode"
7802 * and "is semihosting enabled" checks have been done at
7807 /* Check for semihosting interrupt. */
7809 imm
= arm_lduw_code(env
, env
->regs
[15] - 2, arm_sctlr_b(env
))
7815 imm
= arm_ldl_code(env
, env
->regs
[15] - 4, arm_sctlr_b(env
))
7817 if (imm
== 0x123456) {
7823 /* See if this is a semihosting syscall. */
7825 imm
= arm_lduw_code(env
, env
->regs
[15], arm_sctlr_b(env
))
7837 qemu_log_mask(CPU_LOG_INT
,
7838 "...handling as semihosting call 0x%x\n",
7840 env
->regs
[0] = do_arm_semihosting(env
);
7845 /* Handle a CPU exception for A and R profile CPUs.
7846 * Do any appropriate logging, handle PSCI calls, and then hand off
7847 * to the AArch64-entry or AArch32-entry function depending on the
7848 * target exception level's register width.
7850 void arm_cpu_do_interrupt(CPUState
*cs
)
7852 ARMCPU
*cpu
= ARM_CPU(cs
);
7853 CPUARMState
*env
= &cpu
->env
;
7854 unsigned int new_el
= env
->exception
.target_el
;
7856 assert(!arm_feature(env
, ARM_FEATURE_M
));
7858 arm_log_exception(cs
->exception_index
);
7859 qemu_log_mask(CPU_LOG_INT
, "...from EL%d to EL%d\n", arm_current_el(env
),
7861 if (qemu_loglevel_mask(CPU_LOG_INT
)
7862 && !excp_is_internal(cs
->exception_index
)) {
7863 qemu_log_mask(CPU_LOG_INT
, "...with ESR 0x%x/0x%" PRIx32
"\n",
7864 env
->exception
.syndrome
>> ARM_EL_EC_SHIFT
,
7865 env
->exception
.syndrome
);
7868 if (arm_is_psci_call(cpu
, cs
->exception_index
)) {
7869 arm_handle_psci_call(cpu
);
7870 qemu_log_mask(CPU_LOG_INT
, "...handled as PSCI call\n");
7874 /* Semihosting semantics depend on the register width of the
7875 * code that caused the exception, not the target exception level,
7876 * so must be handled here.
7878 if (check_for_semihosting(cs
)) {
7882 assert(!excp_is_internal(cs
->exception_index
));
7883 if (arm_el_is_aa64(env
, new_el
)) {
7884 arm_cpu_do_interrupt_aarch64(cs
);
7886 arm_cpu_do_interrupt_aarch32(cs
);
7889 /* Hooks may change global state so BQL should be held, also the
7890 * BQL needs to be held for any modification of
7891 * cs->interrupt_request.
7893 g_assert(qemu_mutex_iothread_locked());
7895 arm_call_el_change_hook(cpu
);
7897 if (!kvm_enabled()) {
7898 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
7902 /* Return the exception level which controls this address translation regime */
7903 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7906 case ARMMMUIdx_S2NS
:
7907 case ARMMMUIdx_S1E2
:
7909 case ARMMMUIdx_S1E3
:
7911 case ARMMMUIdx_S1SE0
:
7912 return arm_el_is_aa64(env
, 3) ? 1 : 3;
7913 case ARMMMUIdx_S1SE1
:
7914 case ARMMMUIdx_S1NSE0
:
7915 case ARMMMUIdx_S1NSE1
:
7916 case ARMMMUIdx_MPrivNegPri
:
7917 case ARMMMUIdx_MUserNegPri
:
7918 case ARMMMUIdx_MPriv
:
7919 case ARMMMUIdx_MUser
:
7920 case ARMMMUIdx_MSPrivNegPri
:
7921 case ARMMMUIdx_MSUserNegPri
:
7922 case ARMMMUIdx_MSPriv
:
7923 case ARMMMUIdx_MSUser
:
7926 g_assert_not_reached();
7930 /* Return the SCTLR value which controls this address translation regime */
7931 static inline uint32_t regime_sctlr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7933 return env
->cp15
.sctlr_el
[regime_el(env
, mmu_idx
)];
7936 /* Return true if the specified stage of address translation is disabled */
7937 static inline bool regime_translation_disabled(CPUARMState
*env
,
7940 if (arm_feature(env
, ARM_FEATURE_M
)) {
7941 switch (env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)] &
7942 (R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
)) {
7943 case R_V7M_MPU_CTRL_ENABLE_MASK
:
7944 /* Enabled, but not for HardFault and NMI */
7945 return mmu_idx
& ARM_MMU_IDX_M_NEGPRI
;
7946 case R_V7M_MPU_CTRL_ENABLE_MASK
| R_V7M_MPU_CTRL_HFNMIENA_MASK
:
7947 /* Enabled for all cases */
7951 /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
7952 * we warned about that in armv7m_nvic.c when the guest set it.
7958 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7959 return (env
->cp15
.hcr_el2
& HCR_VM
) == 0;
7961 return (regime_sctlr(env
, mmu_idx
) & SCTLR_M
) == 0;
7964 static inline bool regime_translation_big_endian(CPUARMState
*env
,
7967 return (regime_sctlr(env
, mmu_idx
) & SCTLR_EE
) != 0;
7970 /* Return the TCR controlling this translation regime */
7971 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7973 if (mmu_idx
== ARMMMUIdx_S2NS
) {
7974 return &env
->cp15
.vtcr_el2
;
7976 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
7979 /* Convert a possible stage1+2 MMU index into the appropriate
7982 static inline ARMMMUIdx
stage_1_mmu_idx(ARMMMUIdx mmu_idx
)
7984 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
7985 mmu_idx
+= (ARMMMUIdx_S1NSE0
- ARMMMUIdx_S12NSE0
);
7990 /* Returns TBI0 value for current regime el */
7991 uint32_t arm_regime_tbi0(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
7996 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
7997 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
7999 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8001 tcr
= regime_tcr(env
, mmu_idx
);
8002 el
= regime_el(env
, mmu_idx
);
8005 return extract64(tcr
->raw_tcr
, 20, 1);
8007 return extract64(tcr
->raw_tcr
, 37, 1);
8011 /* Returns TBI1 value for current regime el */
8012 uint32_t arm_regime_tbi1(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8017 /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
8018 * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
8020 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8022 tcr
= regime_tcr(env
, mmu_idx
);
8023 el
= regime_el(env
, mmu_idx
);
8028 return extract64(tcr
->raw_tcr
, 38, 1);
8032 /* Return the TTBR associated with this translation regime */
8033 static inline uint64_t regime_ttbr(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8036 if (mmu_idx
== ARMMMUIdx_S2NS
) {
8037 return env
->cp15
.vttbr_el2
;
8040 return env
->cp15
.ttbr0_el
[regime_el(env
, mmu_idx
)];
8042 return env
->cp15
.ttbr1_el
[regime_el(env
, mmu_idx
)];
8046 /* Return true if the translation regime is using LPAE format page tables */
8047 static inline bool regime_using_lpae_format(CPUARMState
*env
,
8050 int el
= regime_el(env
, mmu_idx
);
8051 if (el
== 2 || arm_el_is_aa64(env
, el
)) {
8054 if (arm_feature(env
, ARM_FEATURE_LPAE
)
8055 && (regime_tcr(env
, mmu_idx
)->raw_tcr
& TTBCR_EAE
)) {
8061 /* Returns true if the stage 1 translation regime is using LPAE format page
8062 * tables. Used when raising alignment exceptions, whose FSR changes depending
8063 * on whether the long or short descriptor format is in use. */
8064 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8066 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
8068 return regime_using_lpae_format(env
, mmu_idx
);
8071 static inline bool regime_is_user(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
8074 case ARMMMUIdx_S1SE0
:
8075 case ARMMMUIdx_S1NSE0
:
8076 case ARMMMUIdx_MUser
:
8077 case ARMMMUIdx_MSUser
:
8078 case ARMMMUIdx_MUserNegPri
:
8079 case ARMMMUIdx_MSUserNegPri
:
8083 case ARMMMUIdx_S12NSE0
:
8084 case ARMMMUIdx_S12NSE1
:
8085 g_assert_not_reached();
8089 /* Translate section/page access permissions to page
8090 * R/W protection flags
8093 * @mmu_idx: MMU index indicating required translation regime
8094 * @ap: The 3-bit access permissions (AP[2:0])
8095 * @domain_prot: The 2-bit domain access permissions
8097 static inline int ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8098 int ap
, int domain_prot
)
8100 bool is_user
= regime_is_user(env
, mmu_idx
);
8102 if (domain_prot
== 3) {
8103 return PAGE_READ
| PAGE_WRITE
;
8108 if (arm_feature(env
, ARM_FEATURE_V7
)) {
8111 switch (regime_sctlr(env
, mmu_idx
) & (SCTLR_S
| SCTLR_R
)) {
8113 return is_user
? 0 : PAGE_READ
;
8120 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8125 return PAGE_READ
| PAGE_WRITE
;
8128 return PAGE_READ
| PAGE_WRITE
;
8129 case 4: /* Reserved. */
8132 return is_user
? 0 : PAGE_READ
;
8136 if (!arm_feature(env
, ARM_FEATURE_V6K
)) {
8141 g_assert_not_reached();
8145 /* Translate section/page access permissions to page
8146 * R/W protection flags.
8148 * @ap: The 2-bit simple AP (AP[2:1])
8149 * @is_user: TRUE if accessing from PL0
8151 static inline int simple_ap_to_rw_prot_is_user(int ap
, bool is_user
)
8155 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
8157 return PAGE_READ
| PAGE_WRITE
;
8159 return is_user
? 0 : PAGE_READ
;
8163 g_assert_not_reached();
8168 simple_ap_to_rw_prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, int ap
)
8170 return simple_ap_to_rw_prot_is_user(ap
, regime_is_user(env
, mmu_idx
));
8173 /* Translate S2 section/page access permissions to protection flags
8176 * @s2ap: The 2-bit stage2 access permissions (S2AP)
8177 * @xn: XN (execute-never) bit
8179 static int get_S2prot(CPUARMState
*env
, int s2ap
, int xn
)
8190 if (arm_el_is_aa64(env
, 2) || prot
& PAGE_READ
) {
8197 /* Translate section/page access permissions to protection flags
8200 * @mmu_idx: MMU index indicating required translation regime
8201 * @is_aa64: TRUE if AArch64
8202 * @ap: The 2-bit simple AP (AP[2:1])
8203 * @ns: NS (non-secure) bit
8204 * @xn: XN (execute-never) bit
8205 * @pxn: PXN (privileged execute-never) bit
8207 static int get_S1prot(CPUARMState
*env
, ARMMMUIdx mmu_idx
, bool is_aa64
,
8208 int ap
, int ns
, int xn
, int pxn
)
8210 bool is_user
= regime_is_user(env
, mmu_idx
);
8211 int prot_rw
, user_rw
;
8215 assert(mmu_idx
!= ARMMMUIdx_S2NS
);
8217 user_rw
= simple_ap_to_rw_prot_is_user(ap
, true);
8221 prot_rw
= simple_ap_to_rw_prot_is_user(ap
, false);
8224 if (ns
&& arm_is_secure(env
) && (env
->cp15
.scr_el3
& SCR_SIF
)) {
8228 /* TODO have_wxn should be replaced with
8229 * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
8230 * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
8231 * compatible processors have EL2, which is required for [U]WXN.
8233 have_wxn
= arm_feature(env
, ARM_FEATURE_LPAE
);
8236 wxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_WXN
;
8240 switch (regime_el(env
, mmu_idx
)) {
8243 xn
= pxn
|| (user_rw
& PAGE_WRITE
);
8250 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
8251 switch (regime_el(env
, mmu_idx
)) {
8255 xn
= xn
|| !(user_rw
& PAGE_READ
);
8259 uwxn
= regime_sctlr(env
, mmu_idx
) & SCTLR_UWXN
;
8261 xn
= xn
|| !(prot_rw
& PAGE_READ
) || pxn
||
8262 (uwxn
&& (user_rw
& PAGE_WRITE
));
8272 if (xn
|| (wxn
&& (prot_rw
& PAGE_WRITE
))) {
8275 return prot_rw
| PAGE_EXEC
;
8278 static bool get_level1_table_address(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8279 uint32_t *table
, uint32_t address
)
8281 /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
8282 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8284 if (address
& tcr
->mask
) {
8285 if (tcr
->raw_tcr
& TTBCR_PD1
) {
8286 /* Translation table walk disabled for TTBR1 */
8289 *table
= regime_ttbr(env
, mmu_idx
, 1) & 0xffffc000;
8291 if (tcr
->raw_tcr
& TTBCR_PD0
) {
8292 /* Translation table walk disabled for TTBR0 */
8295 *table
= regime_ttbr(env
, mmu_idx
, 0) & tcr
->base_mask
;
8297 *table
|= (address
>> 18) & 0x3ffc;
8301 /* Translate a S1 pagetable walk through S2 if needed. */
8302 static hwaddr
S1_ptw_translate(CPUARMState
*env
, ARMMMUIdx mmu_idx
,
8303 hwaddr addr
, MemTxAttrs txattrs
,
8304 ARMMMUFaultInfo
*fi
)
8306 if ((mmu_idx
== ARMMMUIdx_S1NSE0
|| mmu_idx
== ARMMMUIdx_S1NSE1
) &&
8307 !regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
8308 target_ulong s2size
;
8313 ret
= get_phys_addr_lpae(env
, addr
, 0, ARMMMUIdx_S2NS
, &s2pa
,
8314 &txattrs
, &s2prot
, &s2size
, fi
, NULL
);
8316 assert(fi
->type
!= ARMFault_None
);
8327 /* All loads done in the course of a page table walk go through here.
8328 * TODO: rather than ignoring errors from physical memory reads (which
8329 * are external aborts in ARM terminology) we should propagate this
8330 * error out so that we can turn it into a Data Abort if this walk
8331 * was being done for a CPU load/store or an address translation instruction
8332 * (but not if it was for a debug access).
8334 static uint32_t arm_ldl_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8335 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8337 ARMCPU
*cpu
= ARM_CPU(cs
);
8338 CPUARMState
*env
= &cpu
->env
;
8339 MemTxAttrs attrs
= {};
8340 MemTxResult result
= MEMTX_OK
;
8344 attrs
.secure
= is_secure
;
8345 as
= arm_addressspace(cs
, attrs
);
8346 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8350 if (regime_translation_big_endian(env
, mmu_idx
)) {
8351 data
= address_space_ldl_be(as
, addr
, attrs
, &result
);
8353 data
= address_space_ldl_le(as
, addr
, attrs
, &result
);
8355 if (result
== MEMTX_OK
) {
8358 fi
->type
= ARMFault_SyncExternalOnWalk
;
8359 fi
->ea
= arm_extabort_type(result
);
8363 static uint64_t arm_ldq_ptw(CPUState
*cs
, hwaddr addr
, bool is_secure
,
8364 ARMMMUIdx mmu_idx
, ARMMMUFaultInfo
*fi
)
8366 ARMCPU
*cpu
= ARM_CPU(cs
);
8367 CPUARMState
*env
= &cpu
->env
;
8368 MemTxAttrs attrs
= {};
8369 MemTxResult result
= MEMTX_OK
;
8373 attrs
.secure
= is_secure
;
8374 as
= arm_addressspace(cs
, attrs
);
8375 addr
= S1_ptw_translate(env
, mmu_idx
, addr
, attrs
, fi
);
8379 if (regime_translation_big_endian(env
, mmu_idx
)) {
8380 data
= address_space_ldq_be(as
, addr
, attrs
, &result
);
8382 data
= address_space_ldq_le(as
, addr
, attrs
, &result
);
8384 if (result
== MEMTX_OK
) {
8387 fi
->type
= ARMFault_SyncExternalOnWalk
;
8388 fi
->ea
= arm_extabort_type(result
);
8392 static bool get_phys_addr_v5(CPUARMState
*env
, uint32_t address
,
8393 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8394 hwaddr
*phys_ptr
, int *prot
,
8395 target_ulong
*page_size
,
8396 ARMMMUFaultInfo
*fi
)
8398 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8409 /* Pagetable walk. */
8410 /* Lookup l1 descriptor. */
8411 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8412 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8413 fi
->type
= ARMFault_Translation
;
8416 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8418 if (fi
->type
!= ARMFault_None
) {
8422 domain
= (desc
>> 5) & 0x0f;
8423 if (regime_el(env
, mmu_idx
) == 1) {
8424 dacr
= env
->cp15
.dacr_ns
;
8426 dacr
= env
->cp15
.dacr_s
;
8428 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8430 /* Section translation fault. */
8431 fi
->type
= ARMFault_Translation
;
8437 if (domain_prot
== 0 || domain_prot
== 2) {
8438 fi
->type
= ARMFault_Domain
;
8443 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8444 ap
= (desc
>> 10) & 3;
8445 *page_size
= 1024 * 1024;
8447 /* Lookup l2 entry. */
8449 /* Coarse pagetable. */
8450 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8452 /* Fine pagetable. */
8453 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
8455 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8457 if (fi
->type
!= ARMFault_None
) {
8461 case 0: /* Page translation fault. */
8462 fi
->type
= ARMFault_Translation
;
8464 case 1: /* 64k page. */
8465 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8466 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
8467 *page_size
= 0x10000;
8469 case 2: /* 4k page. */
8470 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8471 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
8472 *page_size
= 0x1000;
8474 case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
8476 /* ARMv6/XScale extended small page format */
8477 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
8478 || arm_feature(env
, ARM_FEATURE_V6
)) {
8479 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8480 *page_size
= 0x1000;
8482 /* UNPREDICTABLE in ARMv5; we choose to take a
8483 * page translation fault.
8485 fi
->type
= ARMFault_Translation
;
8489 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
8492 ap
= (desc
>> 4) & 3;
8495 /* Never happens, but compiler isn't smart enough to tell. */
8499 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
8500 *prot
|= *prot
? PAGE_EXEC
: 0;
8501 if (!(*prot
& (1 << access_type
))) {
8502 /* Access permission fault. */
8503 fi
->type
= ARMFault_Permission
;
8506 *phys_ptr
= phys_addr
;
8509 fi
->domain
= domain
;
8514 static bool get_phys_addr_v6(CPUARMState
*env
, uint32_t address
,
8515 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8516 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
8517 target_ulong
*page_size
, ARMMMUFaultInfo
*fi
)
8519 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
8533 /* Pagetable walk. */
8534 /* Lookup l1 descriptor. */
8535 if (!get_level1_table_address(env
, mmu_idx
, &table
, address
)) {
8536 /* Section translation fault if page walk is disabled by PD0 or PD1 */
8537 fi
->type
= ARMFault_Translation
;
8540 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8542 if (fi
->type
!= ARMFault_None
) {
8546 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
8547 /* Section translation fault, or attempt to use the encoding
8548 * which is Reserved on implementations without PXN.
8550 fi
->type
= ARMFault_Translation
;
8553 if ((type
== 1) || !(desc
& (1 << 18))) {
8554 /* Page or Section. */
8555 domain
= (desc
>> 5) & 0x0f;
8557 if (regime_el(env
, mmu_idx
) == 1) {
8558 dacr
= env
->cp15
.dacr_ns
;
8560 dacr
= env
->cp15
.dacr_s
;
8565 domain_prot
= (dacr
>> (domain
* 2)) & 3;
8566 if (domain_prot
== 0 || domain_prot
== 2) {
8567 /* Section or Page domain fault */
8568 fi
->type
= ARMFault_Domain
;
8572 if (desc
& (1 << 18)) {
8574 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
8575 phys_addr
|= (uint64_t)extract32(desc
, 20, 4) << 32;
8576 phys_addr
|= (uint64_t)extract32(desc
, 5, 4) << 36;
8577 *page_size
= 0x1000000;
8580 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
8581 *page_size
= 0x100000;
8583 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
8584 xn
= desc
& (1 << 4);
8586 ns
= extract32(desc
, 19, 1);
8588 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
8589 pxn
= (desc
>> 2) & 1;
8591 ns
= extract32(desc
, 3, 1);
8592 /* Lookup l2 entry. */
8593 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
8594 desc
= arm_ldl_ptw(cs
, table
, regime_is_secure(env
, mmu_idx
),
8596 if (fi
->type
!= ARMFault_None
) {
8599 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
8601 case 0: /* Page translation fault. */
8602 fi
->type
= ARMFault_Translation
;
8604 case 1: /* 64k page. */
8605 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
8606 xn
= desc
& (1 << 15);
8607 *page_size
= 0x10000;
8609 case 2: case 3: /* 4k page. */
8610 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
8612 *page_size
= 0x1000;
8615 /* Never happens, but compiler isn't smart enough to tell. */
8619 if (domain_prot
== 3) {
8620 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
8622 if (pxn
&& !regime_is_user(env
, mmu_idx
)) {
8625 if (xn
&& access_type
== MMU_INST_FETCH
) {
8626 fi
->type
= ARMFault_Permission
;
8630 if (arm_feature(env
, ARM_FEATURE_V6K
) &&
8631 (regime_sctlr(env
, mmu_idx
) & SCTLR_AFE
)) {
8632 /* The simplified model uses AP[0] as an access control bit. */
8633 if ((ap
& 1) == 0) {
8634 /* Access flag fault. */
8635 fi
->type
= ARMFault_AccessFlag
;
8638 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
>> 1);
8640 *prot
= ap_to_rw_prot(env
, mmu_idx
, ap
, domain_prot
);
8645 if (!(*prot
& (1 << access_type
))) {
8646 /* Access permission fault. */
8647 fi
->type
= ARMFault_Permission
;
8652 /* The NS bit will (as required by the architecture) have no effect if
8653 * the CPU doesn't support TZ or this is a non-secure translation
8654 * regime, because the attribute will already be non-secure.
8656 attrs
->secure
= false;
8658 *phys_ptr
= phys_addr
;
8661 fi
->domain
= domain
;
8667 * check_s2_mmu_setup
8669 * @is_aa64: True if the translation regime is in AArch64 state
8670 * @startlevel: Suggested starting level
8671 * @inputsize: Bitsize of IPAs
8672 * @stride: Page-table stride (See the ARM ARM)
8674 * Returns true if the suggested S2 translation parameters are OK and
8677 static bool check_s2_mmu_setup(ARMCPU
*cpu
, bool is_aa64
, int level
,
8678 int inputsize
, int stride
)
8680 const int grainsize
= stride
+ 3;
8683 /* Negative levels are never allowed. */
8688 startsizecheck
= inputsize
- ((3 - level
) * stride
+ grainsize
);
8689 if (startsizecheck
< 1 || startsizecheck
> stride
+ 4) {
8694 CPUARMState
*env
= &cpu
->env
;
8695 unsigned int pamax
= arm_pamax(cpu
);
8698 case 13: /* 64KB Pages. */
8699 if (level
== 0 || (level
== 1 && pamax
<= 42)) {
8703 case 11: /* 16KB Pages. */
8704 if (level
== 0 || (level
== 1 && pamax
<= 40)) {
8708 case 9: /* 4KB Pages. */
8709 if (level
== 0 && pamax
<= 42) {
8714 g_assert_not_reached();
8717 /* Inputsize checks. */
8718 if (inputsize
> pamax
&&
8719 (arm_el_is_aa64(env
, 1) || inputsize
> 40)) {
8720 /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. */
8724 /* AArch32 only supports 4KB pages. Assert on that. */
8725 assert(stride
== 9);
8734 /* Translate from the 4-bit stage 2 representation of
8735 * memory attributes (without cache-allocation hints) to
8736 * the 8-bit representation of the stage 1 MAIR registers
8737 * (which includes allocation hints).
8739 * ref: shared/translation/attrs/S2AttrDecode()
8740 * .../S2ConvertAttrsHints()
8742 static uint8_t convert_stage2_attrs(CPUARMState
*env
, uint8_t s2attrs
)
8744 uint8_t hiattr
= extract32(s2attrs
, 2, 2);
8745 uint8_t loattr
= extract32(s2attrs
, 0, 2);
8746 uint8_t hihint
= 0, lohint
= 0;
8748 if (hiattr
!= 0) { /* normal memory */
8749 if ((env
->cp15
.hcr_el2
& HCR_CD
) != 0) { /* cache disabled */
8750 hiattr
= loattr
= 1; /* non-cacheable */
8752 if (hiattr
!= 1) { /* Write-through or write-back */
8753 hihint
= 3; /* RW allocate */
8755 if (loattr
!= 1) { /* Write-through or write-back */
8756 lohint
= 3; /* RW allocate */
8761 return (hiattr
<< 6) | (hihint
<< 4) | (loattr
<< 2) | lohint
;
8764 static bool get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
8765 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
8766 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
, int *prot
,
8767 target_ulong
*page_size_ptr
,
8768 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
8770 ARMCPU
*cpu
= arm_env_get_cpu(env
);
8771 CPUState
*cs
= CPU(cpu
);
8772 /* Read an LPAE long-descriptor translation table. */
8773 ARMFaultType fault_type
= ARMFault_Translation
;
8780 hwaddr descaddr
, indexmask
, indexmask_grainsize
;
8781 uint32_t tableattrs
;
8782 target_ulong page_size
;
8788 TCR
*tcr
= regime_tcr(env
, mmu_idx
);
8789 int ap
, ns
, xn
, pxn
;
8790 uint32_t el
= regime_el(env
, mmu_idx
);
8791 bool ttbr1_valid
= true;
8792 uint64_t descaddrmask
;
8793 bool aarch64
= arm_el_is_aa64(env
, el
);
8796 * This code does not handle the different format TCR for VTCR_EL2.
8797 * This code also does not support shareability levels.
8798 * Attribute and permission bit handling should also be checked when adding
8799 * support for those page table walks.
8805 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8806 tbi
= extract64(tcr
->raw_tcr
, 20, 1);
8809 if (extract64(address
, 55, 1)) {
8810 tbi
= extract64(tcr
->raw_tcr
, 38, 1);
8812 tbi
= extract64(tcr
->raw_tcr
, 37, 1);
8817 /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
8821 ttbr1_valid
= false;
8826 /* There is no TTBR1 for EL2 */
8828 ttbr1_valid
= false;
8832 /* Determine whether this address is in the region controlled by
8833 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
8834 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
8835 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
8838 /* AArch64 translation. */
8839 t0sz
= extract32(tcr
->raw_tcr
, 0, 6);
8840 t0sz
= MIN(t0sz
, 39);
8841 t0sz
= MAX(t0sz
, 16);
8842 } else if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8843 /* AArch32 stage 1 translation. */
8844 t0sz
= extract32(tcr
->raw_tcr
, 0, 3);
8846 /* AArch32 stage 2 translation. */
8847 bool sext
= extract32(tcr
->raw_tcr
, 4, 1);
8848 bool sign
= extract32(tcr
->raw_tcr
, 3, 1);
8849 /* Address size is 40-bit for a stage 2 translation,
8850 * and t0sz can be negative (from -8 to 7),
8851 * so we need to adjust it to use the TTBR selecting logic below.
8854 t0sz
= sextract32(tcr
->raw_tcr
, 0, 4) + 8;
8856 /* If the sign-extend bit is not the same as t0sz[3], the result
8857 * is unpredictable. Flag this as a guest error. */
8859 qemu_log_mask(LOG_GUEST_ERROR
,
8860 "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
8863 t1sz
= extract32(tcr
->raw_tcr
, 16, 6);
8865 t1sz
= MIN(t1sz
, 39);
8866 t1sz
= MAX(t1sz
, 16);
8868 if (t0sz
&& !extract64(address
, addrsize
- t0sz
, t0sz
- tbi
)) {
8869 /* there is a ttbr0 region and we are in it (high bits all zero) */
8871 } else if (ttbr1_valid
&& t1sz
&&
8872 !extract64(~address
, addrsize
- t1sz
, t1sz
- tbi
)) {
8873 /* there is a ttbr1 region and we are in it (high bits all one) */
8876 /* ttbr0 region is "everything not in the ttbr1 region" */
8878 } else if (!t1sz
&& ttbr1_valid
) {
8879 /* ttbr1 region is "everything not in the ttbr0 region" */
8882 /* in the gap between the two regions, this is a Translation fault */
8883 fault_type
= ARMFault_Translation
;
8887 /* Note that QEMU ignores shareability and cacheability attributes,
8888 * so we don't need to do anything with the SH, ORGN, IRGN fields
8889 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
8890 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
8891 * implement any ASID-like capability so we can ignore it (instead
8892 * we will always flush the TLB any time the ASID is changed).
8894 if (ttbr_select
== 0) {
8895 ttbr
= regime_ttbr(env
, mmu_idx
, 0);
8897 epd
= extract32(tcr
->raw_tcr
, 7, 1);
8899 inputsize
= addrsize
- t0sz
;
8901 tg
= extract32(tcr
->raw_tcr
, 14, 2);
8902 if (tg
== 1) { /* 64KB pages */
8905 if (tg
== 2) { /* 16KB pages */
8909 /* We should only be here if TTBR1 is valid */
8910 assert(ttbr1_valid
);
8912 ttbr
= regime_ttbr(env
, mmu_idx
, 1);
8913 epd
= extract32(tcr
->raw_tcr
, 23, 1);
8914 inputsize
= addrsize
- t1sz
;
8916 tg
= extract32(tcr
->raw_tcr
, 30, 2);
8917 if (tg
== 3) { /* 64KB pages */
8920 if (tg
== 1) { /* 16KB pages */
8925 /* Here we should have set up all the parameters for the translation:
8926 * inputsize, ttbr, epd, stride, tbi
8930 /* Translation table walk disabled => Translation fault on TLB miss
8931 * Note: This is always 0 on 64-bit EL2 and EL3.
8936 if (mmu_idx
!= ARMMMUIdx_S2NS
) {
8937 /* The starting level depends on the virtual address size (which can
8938 * be up to 48 bits) and the translation granule size. It indicates
8939 * the number of strides (stride bits at a time) needed to
8940 * consume the bits of the input address. In the pseudocode this is:
8941 * level = 4 - RoundUp((inputsize - grainsize) / stride)
8942 * where their 'inputsize' is our 'inputsize', 'grainsize' is
8943 * our 'stride + 3' and 'stride' is our 'stride'.
8944 * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
8945 * = 4 - (inputsize - stride - 3 + stride - 1) / stride
8946 * = 4 - (inputsize - 4) / stride;
8948 level
= 4 - (inputsize
- 4) / stride
;
8950 /* For stage 2 translations the starting level is specified by the
8951 * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
8953 uint32_t sl0
= extract32(tcr
->raw_tcr
, 6, 2);
8954 uint32_t startlevel
;
8957 if (!aarch64
|| stride
== 9) {
8958 /* AArch32 or 4KB pages */
8959 startlevel
= 2 - sl0
;
8961 /* 16KB or 64KB pages */
8962 startlevel
= 3 - sl0
;
8965 /* Check that the starting level is valid. */
8966 ok
= check_s2_mmu_setup(cpu
, aarch64
, startlevel
,
8969 fault_type
= ARMFault_Translation
;
8975 indexmask_grainsize
= (1ULL << (stride
+ 3)) - 1;
8976 indexmask
= (1ULL << (inputsize
- (stride
* (4 - level
)))) - 1;
8978 /* Now we can extract the actual base address from the TTBR */
8979 descaddr
= extract64(ttbr
, 0, 48);
8980 descaddr
&= ~indexmask
;
8982 /* The address field in the descriptor goes up to bit 39 for ARMv7
8983 * but up to bit 47 for ARMv8, but we use the descaddrmask
8984 * up to bit 39 for AArch32, because we don't need other bits in that case
8985 * to construct next descriptor address (anyway they should be all zeroes).
8987 descaddrmask
= ((1ull << (aarch64
? 48 : 40)) - 1) &
8988 ~indexmask_grainsize
;
8990 /* Secure accesses start with the page table in secure memory and
8991 * can be downgraded to non-secure at any step. Non-secure accesses
8992 * remain non-secure. We implement this by just ORing in the NSTable/NS
8993 * bits at each step.
8995 tableattrs
= regime_is_secure(env
, mmu_idx
) ? 0 : (1 << 4);
8997 uint64_t descriptor
;
9000 descaddr
|= (address
>> (stride
* (4 - level
))) & indexmask
;
9002 nstable
= extract32(tableattrs
, 4, 1);
9003 descriptor
= arm_ldq_ptw(cs
, descaddr
, !nstable
, mmu_idx
, fi
);
9004 if (fi
->type
!= ARMFault_None
) {
9008 if (!(descriptor
& 1) ||
9009 (!(descriptor
& 2) && (level
== 3))) {
9010 /* Invalid, or the Reserved level 3 encoding */
9013 descaddr
= descriptor
& descaddrmask
;
9015 if ((descriptor
& 2) && (level
< 3)) {
9016 /* Table entry. The top five bits are attributes which may
9017 * propagate down through lower levels of the table (and
9018 * which are all arranged so that 0 means "no effect", so
9019 * we can gather them up by ORing in the bits at each level).
9021 tableattrs
|= extract64(descriptor
, 59, 5);
9023 indexmask
= indexmask_grainsize
;
9026 /* Block entry at level 1 or 2, or page entry at level 3.
9027 * These are basically the same thing, although the number
9028 * of bits we pull in from the vaddr varies.
9030 page_size
= (1ULL << ((stride
* (4 - level
)) + 3));
9031 descaddr
|= (address
& (page_size
- 1));
9032 /* Extract attributes from the descriptor */
9033 attrs
= extract64(descriptor
, 2, 10)
9034 | (extract64(descriptor
, 52, 12) << 10);
9036 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9037 /* Stage 2 table descriptors do not include any attribute fields */
9040 /* Merge in attributes from table descriptors */
9041 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
9042 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
9043 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
9044 * means "force PL1 access only", which means forcing AP[1] to 0.
9046 if (extract32(tableattrs
, 2, 1)) {
9049 attrs
|= nstable
<< 3; /* NS */
9052 /* Here descaddr is the final physical address, and attributes
9055 fault_type
= ARMFault_AccessFlag
;
9056 if ((attrs
& (1 << 8)) == 0) {
9061 ap
= extract32(attrs
, 4, 2);
9062 xn
= extract32(attrs
, 12, 1);
9064 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9066 *prot
= get_S2prot(env
, ap
, xn
);
9068 ns
= extract32(attrs
, 3, 1);
9069 pxn
= extract32(attrs
, 11, 1);
9070 *prot
= get_S1prot(env
, mmu_idx
, aarch64
, ap
, ns
, xn
, pxn
);
9073 fault_type
= ARMFault_Permission
;
9074 if (!(*prot
& (1 << access_type
))) {
9079 /* The NS bit will (as required by the architecture) have no effect if
9080 * the CPU doesn't support TZ or this is a non-secure translation
9081 * regime, because the attribute will already be non-secure.
9083 txattrs
->secure
= false;
9086 if (cacheattrs
!= NULL
) {
9087 if (mmu_idx
== ARMMMUIdx_S2NS
) {
9088 cacheattrs
->attrs
= convert_stage2_attrs(env
,
9089 extract32(attrs
, 0, 4));
9091 /* Index into MAIR registers for cache attributes */
9092 uint8_t attrindx
= extract32(attrs
, 0, 3);
9093 uint64_t mair
= env
->cp15
.mair_el
[regime_el(env
, mmu_idx
)];
9094 assert(attrindx
<= 7);
9095 cacheattrs
->attrs
= extract64(mair
, attrindx
* 8, 8);
9097 cacheattrs
->shareability
= extract32(attrs
, 6, 2);
9100 *phys_ptr
= descaddr
;
9101 *page_size_ptr
= page_size
;
9105 fi
->type
= fault_type
;
9107 /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
9108 fi
->stage2
= fi
->s1ptw
|| (mmu_idx
== ARMMMUIdx_S2NS
);
9112 static inline void get_phys_addr_pmsav7_default(CPUARMState
*env
,
9114 int32_t address
, int *prot
)
9116 if (!arm_feature(env
, ARM_FEATURE_M
)) {
9117 *prot
= PAGE_READ
| PAGE_WRITE
;
9119 case 0xF0000000 ... 0xFFFFFFFF:
9120 if (regime_sctlr(env
, mmu_idx
) & SCTLR_V
) {
9121 /* hivecs execing is ok */
9125 case 0x00000000 ... 0x7FFFFFFF:
9130 /* Default system address map for M profile cores.
9131 * The architecture specifies which regions are execute-never;
9132 * at the MPU level no other checks are defined.
9135 case 0x00000000 ... 0x1fffffff: /* ROM */
9136 case 0x20000000 ... 0x3fffffff: /* SRAM */
9137 case 0x60000000 ... 0x7fffffff: /* RAM */
9138 case 0x80000000 ... 0x9fffffff: /* RAM */
9139 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9141 case 0x40000000 ... 0x5fffffff: /* Peripheral */
9142 case 0xa0000000 ... 0xbfffffff: /* Device */
9143 case 0xc0000000 ... 0xdfffffff: /* Device */
9144 case 0xe0000000 ... 0xffffffff: /* System */
9145 *prot
= PAGE_READ
| PAGE_WRITE
;
9148 g_assert_not_reached();
9153 static bool pmsav7_use_background_region(ARMCPU
*cpu
,
9154 ARMMMUIdx mmu_idx
, bool is_user
)
9156 /* Return true if we should use the default memory map as a
9157 * "background" region if there are no hits against any MPU regions.
9159 CPUARMState
*env
= &cpu
->env
;
9165 if (arm_feature(env
, ARM_FEATURE_M
)) {
9166 return env
->v7m
.mpu_ctrl
[regime_is_secure(env
, mmu_idx
)]
9167 & R_V7M_MPU_CTRL_PRIVDEFENA_MASK
;
9169 return regime_sctlr(env
, mmu_idx
) & SCTLR_BR
;
9173 static inline bool m_is_ppb_region(CPUARMState
*env
, uint32_t address
)
9175 /* True if address is in the M profile PPB region 0xe0000000 - 0xe00fffff */
9176 return arm_feature(env
, ARM_FEATURE_M
) &&
9177 extract32(address
, 20, 12) == 0xe00;
9180 static inline bool m_is_system_region(CPUARMState
*env
, uint32_t address
)
9182 /* True if address is in the M profile system region
9183 * 0xe0000000 - 0xffffffff
9185 return arm_feature(env
, ARM_FEATURE_M
) && extract32(address
, 29, 3) == 0x7;
9188 static bool get_phys_addr_pmsav7(CPUARMState
*env
, uint32_t address
,
9189 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9190 hwaddr
*phys_ptr
, int *prot
,
9191 ARMMMUFaultInfo
*fi
)
9193 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9195 bool is_user
= regime_is_user(env
, mmu_idx
);
9197 *phys_ptr
= address
;
9200 if (regime_translation_disabled(env
, mmu_idx
) ||
9201 m_is_ppb_region(env
, address
)) {
9202 /* MPU disabled or M profile PPB access: use default memory map.
9203 * The other case which uses the default memory map in the
9204 * v7M ARM ARM pseudocode is exception vector reads from the vector
9205 * table. In QEMU those accesses are done in arm_v7m_load_vector(),
9206 * which always does a direct read using address_space_ldl(), rather
9207 * than going via this function, so we don't need to check that here.
9209 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9210 } else { /* MPU enabled */
9211 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9213 uint32_t base
= env
->pmsav7
.drbar
[n
];
9214 uint32_t rsize
= extract32(env
->pmsav7
.drsr
[n
], 1, 5);
9218 if (!(env
->pmsav7
.drsr
[n
] & 0x1)) {
9223 qemu_log_mask(LOG_GUEST_ERROR
,
9224 "DRSR[%d]: Rsize field cannot be 0\n", n
);
9228 rmask
= (1ull << rsize
) - 1;
9231 qemu_log_mask(LOG_GUEST_ERROR
,
9232 "DRBAR[%d]: 0x%" PRIx32
" misaligned "
9233 "to DRSR region size, mask = 0x%" PRIx32
"\n",
9238 if (address
< base
|| address
> base
+ rmask
) {
9242 /* Region matched */
9244 if (rsize
>= 8) { /* no subregions for regions < 256 bytes */
9246 uint32_t srdis_mask
;
9248 rsize
-= 3; /* sub region size (power of 2) */
9249 snd
= ((address
- base
) >> rsize
) & 0x7;
9250 srdis
= extract32(env
->pmsav7
.drsr
[n
], snd
+ 8, 1);
9252 srdis_mask
= srdis
? 0x3 : 0x0;
9253 for (i
= 2; i
<= 8 && rsize
< TARGET_PAGE_BITS
; i
*= 2) {
9254 /* This will check in groups of 2, 4 and then 8, whether
9255 * the subregion bits are consistent. rsize is incremented
9256 * back up to give the region size, considering consistent
9257 * adjacent subregions as one region. Stop testing if rsize
9258 * is already big enough for an entire QEMU page.
9260 int snd_rounded
= snd
& ~(i
- 1);
9261 uint32_t srdis_multi
= extract32(env
->pmsav7
.drsr
[n
],
9262 snd_rounded
+ 8, i
);
9263 if (srdis_mask
^ srdis_multi
) {
9266 srdis_mask
= (srdis_mask
<< i
) | srdis_mask
;
9270 if (rsize
< TARGET_PAGE_BITS
) {
9271 qemu_log_mask(LOG_UNIMP
,
9272 "DRSR[%d]: No support for MPU (sub)region "
9273 "alignment of %" PRIu32
" bits. Minimum is %d\n",
9274 n
, rsize
, TARGET_PAGE_BITS
);
9283 if (n
== -1) { /* no hits */
9284 if (!pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9285 /* background fault */
9286 fi
->type
= ARMFault_Background
;
9289 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9290 } else { /* a MPU hit! */
9291 uint32_t ap
= extract32(env
->pmsav7
.dracr
[n
], 8, 3);
9292 uint32_t xn
= extract32(env
->pmsav7
.dracr
[n
], 12, 1);
9294 if (m_is_system_region(env
, address
)) {
9295 /* System space is always execute never */
9299 if (is_user
) { /* User mode AP bit decoding */
9304 break; /* no access */
9306 *prot
|= PAGE_WRITE
;
9310 *prot
|= PAGE_READ
| PAGE_EXEC
;
9313 /* for v7M, same as 6; for R profile a reserved value */
9314 if (arm_feature(env
, ARM_FEATURE_M
)) {
9315 *prot
|= PAGE_READ
| PAGE_EXEC
;
9320 qemu_log_mask(LOG_GUEST_ERROR
,
9321 "DRACR[%d]: Bad value for AP bits: 0x%"
9322 PRIx32
"\n", n
, ap
);
9324 } else { /* Priv. mode AP bits decoding */
9327 break; /* no access */
9331 *prot
|= PAGE_WRITE
;
9335 *prot
|= PAGE_READ
| PAGE_EXEC
;
9338 /* for v7M, same as 6; for R profile a reserved value */
9339 if (arm_feature(env
, ARM_FEATURE_M
)) {
9340 *prot
|= PAGE_READ
| PAGE_EXEC
;
9345 qemu_log_mask(LOG_GUEST_ERROR
,
9346 "DRACR[%d]: Bad value for AP bits: 0x%"
9347 PRIx32
"\n", n
, ap
);
9353 *prot
&= ~PAGE_EXEC
;
9358 fi
->type
= ARMFault_Permission
;
9360 return !(*prot
& (1 << access_type
));
9363 static bool v8m_is_sau_exempt(CPUARMState
*env
,
9364 uint32_t address
, MMUAccessType access_type
)
9366 /* The architecture specifies that certain address ranges are
9367 * exempt from v8M SAU/IDAU checks.
9370 (access_type
== MMU_INST_FETCH
&& m_is_system_region(env
, address
)) ||
9371 (address
>= 0xe0000000 && address
<= 0xe0002fff) ||
9372 (address
>= 0xe000e000 && address
<= 0xe000efff) ||
9373 (address
>= 0xe002e000 && address
<= 0xe002efff) ||
9374 (address
>= 0xe0040000 && address
<= 0xe0041fff) ||
9375 (address
>= 0xe00ff000 && address
<= 0xe00fffff);
9378 static void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
9379 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9380 V8M_SAttributes
*sattrs
)
9382 /* Look up the security attributes for this address. Compare the
9383 * pseudocode SecurityCheck() function.
9384 * We assume the caller has zero-initialized *sattrs.
9386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9389 /* TODO: implement IDAU */
9391 if (access_type
== MMU_INST_FETCH
&& extract32(address
, 28, 4) == 0xf) {
9392 /* 0xf0000000..0xffffffff is always S for insn fetches */
9396 if (v8m_is_sau_exempt(env
, address
, access_type
)) {
9397 sattrs
->ns
= !regime_is_secure(env
, mmu_idx
);
9401 switch (env
->sau
.ctrl
& 3) {
9402 case 0: /* SAU.ENABLE == 0, SAU.ALLNS == 0 */
9404 case 2: /* SAU.ENABLE == 0, SAU.ALLNS == 1 */
9407 default: /* SAU.ENABLE == 1 */
9408 for (r
= 0; r
< cpu
->sau_sregion
; r
++) {
9409 if (env
->sau
.rlar
[r
] & 1) {
9410 uint32_t base
= env
->sau
.rbar
[r
] & ~0x1f;
9411 uint32_t limit
= env
->sau
.rlar
[r
] | 0x1f;
9413 if (base
<= address
&& limit
>= address
) {
9414 if (sattrs
->srvalid
) {
9415 /* If we hit in more than one region then we must report
9416 * as Secure, not NS-Callable, with no valid region
9420 sattrs
->nsc
= false;
9421 sattrs
->sregion
= 0;
9422 sattrs
->srvalid
= false;
9425 if (env
->sau
.rlar
[r
] & 2) {
9430 sattrs
->srvalid
= true;
9431 sattrs
->sregion
= r
;
9437 /* TODO when we support the IDAU then it may override the result here */
9442 static bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
9443 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9444 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
9445 int *prot
, ARMMMUFaultInfo
*fi
, uint32_t *mregion
)
9447 /* Perform a PMSAv8 MPU lookup (without also doing the SAU check
9448 * that a full phys-to-virt translation does).
9449 * mregion is (if not NULL) set to the region number which matched,
9450 * or -1 if no region number is returned (MPU off, address did not
9451 * hit a region, address hit in multiple regions).
9453 ARMCPU
*cpu
= arm_env_get_cpu(env
);
9454 bool is_user
= regime_is_user(env
, mmu_idx
);
9455 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
9457 int matchregion
= -1;
9460 *phys_ptr
= address
;
9466 /* Unlike the ARM ARM pseudocode, we don't need to check whether this
9467 * was an exception vector read from the vector table (which is always
9468 * done using the default system address map), because those accesses
9469 * are done in arm_v7m_load_vector(), which always does a direct
9470 * read using address_space_ldl(), rather than going via this function.
9472 if (regime_translation_disabled(env
, mmu_idx
)) { /* MPU disabled */
9474 } else if (m_is_ppb_region(env
, address
)) {
9476 } else if (pmsav7_use_background_region(cpu
, mmu_idx
, is_user
)) {
9479 for (n
= (int)cpu
->pmsav7_dregion
- 1; n
>= 0; n
--) {
9481 /* Note that the base address is bits [31:5] from the register
9482 * with bits [4:0] all zeroes, but the limit address is bits
9483 * [31:5] from the register with bits [4:0] all ones.
9485 uint32_t base
= env
->pmsav8
.rbar
[secure
][n
] & ~0x1f;
9486 uint32_t limit
= env
->pmsav8
.rlar
[secure
][n
] | 0x1f;
9488 if (!(env
->pmsav8
.rlar
[secure
][n
] & 0x1)) {
9489 /* Region disabled */
9493 if (address
< base
|| address
> limit
) {
9498 /* Multiple regions match -- always a failure (unlike
9499 * PMSAv7 where highest-numbered-region wins)
9501 fi
->type
= ARMFault_Permission
;
9509 if (base
& ~TARGET_PAGE_MASK
) {
9510 qemu_log_mask(LOG_UNIMP
,
9511 "MPU_RBAR[%d]: No support for MPU region base"
9512 "address of 0x%" PRIx32
". Minimum alignment is "
9514 n
, base
, TARGET_PAGE_BITS
);
9517 if ((limit
+ 1) & ~TARGET_PAGE_MASK
) {
9518 qemu_log_mask(LOG_UNIMP
,
9519 "MPU_RBAR[%d]: No support for MPU region limit"
9520 "address of 0x%" PRIx32
". Minimum alignment is "
9522 n
, limit
, TARGET_PAGE_BITS
);
9529 /* background fault */
9530 fi
->type
= ARMFault_Background
;
9534 if (matchregion
== -1) {
9535 /* hit using the background region */
9536 get_phys_addr_pmsav7_default(env
, mmu_idx
, address
, prot
);
9538 uint32_t ap
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 1, 2);
9539 uint32_t xn
= extract32(env
->pmsav8
.rbar
[secure
][matchregion
], 0, 1);
9541 if (m_is_system_region(env
, address
)) {
9542 /* System space is always execute never */
9546 *prot
= simple_ap_to_rw_prot(env
, mmu_idx
, ap
);
9550 /* We don't need to look the attribute up in the MAIR0/MAIR1
9551 * registers because that only tells us about cacheability.
9554 *mregion
= matchregion
;
9558 fi
->type
= ARMFault_Permission
;
9560 return !(*prot
& (1 << access_type
));
9564 static bool get_phys_addr_pmsav8(CPUARMState
*env
, uint32_t address
,
9565 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9566 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
9567 int *prot
, ARMMMUFaultInfo
*fi
)
9569 uint32_t secure
= regime_is_secure(env
, mmu_idx
);
9570 V8M_SAttributes sattrs
= {};
9572 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
9573 v8m_security_lookup(env
, address
, access_type
, mmu_idx
, &sattrs
);
9574 if (access_type
== MMU_INST_FETCH
) {
9575 /* Instruction fetches always use the MMU bank and the
9576 * transaction attribute determined by the fetch address,
9577 * regardless of CPU state. This is painful for QEMU
9578 * to handle, because it would mean we need to encode
9579 * into the mmu_idx not just the (user, negpri) information
9580 * for the current security state but also that for the
9581 * other security state, which would balloon the number
9582 * of mmu_idx values needed alarmingly.
9583 * Fortunately we can avoid this because it's not actually
9584 * possible to arbitrarily execute code from memory with
9585 * the wrong security attribute: it will always generate
9586 * an exception of some kind or another, apart from the
9587 * special case of an NS CPU executing an SG instruction
9588 * in S&NSC memory. So we always just fail the translation
9589 * here and sort things out in the exception handler
9590 * (including possibly emulating an SG instruction).
9592 if (sattrs
.ns
!= !secure
) {
9594 fi
->type
= ARMFault_QEMU_NSCExec
;
9596 fi
->type
= ARMFault_QEMU_SFault
;
9598 *phys_ptr
= address
;
9603 /* For data accesses we always use the MMU bank indicated
9604 * by the current CPU state, but the security attributes
9605 * might downgrade a secure access to nonsecure.
9608 txattrs
->secure
= false;
9609 } else if (!secure
) {
9610 /* NS access to S memory must fault.
9611 * Architecturally we should first check whether the
9612 * MPU information for this address indicates that we
9613 * are doing an unaligned access to Device memory, which
9614 * should generate a UsageFault instead. QEMU does not
9615 * currently check for that kind of unaligned access though.
9616 * If we added it we would need to do so as a special case
9617 * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
9619 fi
->type
= ARMFault_QEMU_SFault
;
9620 *phys_ptr
= address
;
9627 return pmsav8_mpu_lookup(env
, address
, access_type
, mmu_idx
, phys_ptr
,
9628 txattrs
, prot
, fi
, NULL
);
9631 static bool get_phys_addr_pmsav5(CPUARMState
*env
, uint32_t address
,
9632 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9633 hwaddr
*phys_ptr
, int *prot
,
9634 ARMMMUFaultInfo
*fi
)
9639 bool is_user
= regime_is_user(env
, mmu_idx
);
9641 if (regime_translation_disabled(env
, mmu_idx
)) {
9643 *phys_ptr
= address
;
9644 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9648 *phys_ptr
= address
;
9649 for (n
= 7; n
>= 0; n
--) {
9650 base
= env
->cp15
.c6_region
[n
];
9651 if ((base
& 1) == 0) {
9654 mask
= 1 << ((base
>> 1) & 0x1f);
9655 /* Keep this shift separate from the above to avoid an
9656 (undefined) << 32. */
9657 mask
= (mask
<< 1) - 1;
9658 if (((base
^ address
) & ~mask
) == 0) {
9663 fi
->type
= ARMFault_Background
;
9667 if (access_type
== MMU_INST_FETCH
) {
9668 mask
= env
->cp15
.pmsav5_insn_ap
;
9670 mask
= env
->cp15
.pmsav5_data_ap
;
9672 mask
= (mask
>> (n
* 4)) & 0xf;
9675 fi
->type
= ARMFault_Permission
;
9680 fi
->type
= ARMFault_Permission
;
9684 *prot
= PAGE_READ
| PAGE_WRITE
;
9689 *prot
|= PAGE_WRITE
;
9693 *prot
= PAGE_READ
| PAGE_WRITE
;
9697 fi
->type
= ARMFault_Permission
;
9707 /* Bad permission. */
9708 fi
->type
= ARMFault_Permission
;
9716 /* Combine either inner or outer cacheability attributes for normal
9717 * memory, according to table D4-42 and pseudocode procedure
9718 * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM).
9720 * NB: only stage 1 includes allocation hints (RW bits), leading to
9723 static uint8_t combine_cacheattr_nibble(uint8_t s1
, uint8_t s2
)
9725 if (s1
== 4 || s2
== 4) {
9726 /* non-cacheable has precedence */
9728 } else if (extract32(s1
, 2, 2) == 0 || extract32(s1
, 2, 2) == 2) {
9729 /* stage 1 write-through takes precedence */
9731 } else if (extract32(s2
, 2, 2) == 2) {
9732 /* stage 2 write-through takes precedence, but the allocation hint
9733 * is still taken from stage 1
9735 return (2 << 2) | extract32(s1
, 0, 2);
9736 } else { /* write-back */
9741 /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4
9742 * and CombineS1S2Desc()
9744 * @s1: Attributes from stage 1 walk
9745 * @s2: Attributes from stage 2 walk
9747 static ARMCacheAttrs
combine_cacheattrs(ARMCacheAttrs s1
, ARMCacheAttrs s2
)
9749 uint8_t s1lo
= extract32(s1
.attrs
, 0, 4), s2lo
= extract32(s2
.attrs
, 0, 4);
9750 uint8_t s1hi
= extract32(s1
.attrs
, 4, 4), s2hi
= extract32(s2
.attrs
, 4, 4);
9753 /* Combine shareability attributes (table D4-43) */
9754 if (s1
.shareability
== 2 || s2
.shareability
== 2) {
9755 /* if either are outer-shareable, the result is outer-shareable */
9756 ret
.shareability
= 2;
9757 } else if (s1
.shareability
== 3 || s2
.shareability
== 3) {
9758 /* if either are inner-shareable, the result is inner-shareable */
9759 ret
.shareability
= 3;
9761 /* both non-shareable */
9762 ret
.shareability
= 0;
9765 /* Combine memory type and cacheability attributes */
9766 if (s1hi
== 0 || s2hi
== 0) {
9767 /* Device has precedence over normal */
9768 if (s1lo
== 0 || s2lo
== 0) {
9769 /* nGnRnE has precedence over anything */
9771 } else if (s1lo
== 4 || s2lo
== 4) {
9772 /* non-Reordering has precedence over Reordering */
9773 ret
.attrs
= 4; /* nGnRE */
9774 } else if (s1lo
== 8 || s2lo
== 8) {
9775 /* non-Gathering has precedence over Gathering */
9776 ret
.attrs
= 8; /* nGRE */
9778 ret
.attrs
= 0xc; /* GRE */
9781 /* Any location for which the resultant memory type is any
9782 * type of Device memory is always treated as Outer Shareable.
9784 ret
.shareability
= 2;
9785 } else { /* Normal memory */
9786 /* Outer/inner cacheability combine independently */
9787 ret
.attrs
= combine_cacheattr_nibble(s1hi
, s2hi
) << 4
9788 | combine_cacheattr_nibble(s1lo
, s2lo
);
9790 if (ret
.attrs
== 0x44) {
9791 /* Any location for which the resultant memory type is Normal
9792 * Inner Non-cacheable, Outer Non-cacheable is always treated
9793 * as Outer Shareable.
9795 ret
.shareability
= 2;
9803 /* get_phys_addr - get the physical address for this virtual address
9805 * Find the physical address corresponding to the given virtual address,
9806 * by doing a translation table walk on MMU based systems or using the
9807 * MPU state on MPU based systems.
9809 * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
9810 * prot and page_size may not be filled in, and the populated fsr value provides
9811 * information on why the translation aborted, in the format of a
9812 * DFSR/IFSR fault register, with the following caveats:
9813 * * we honour the short vs long DFSR format differences.
9814 * * the WnR bit is never set (the caller must do this).
9815 * * for PSMAv5 based systems we don't bother to return a full FSR format
9819 * @address: virtual address to get physical address for
9820 * @access_type: 0 for read, 1 for write, 2 for execute
9821 * @mmu_idx: MMU index indicating required translation regime
9822 * @phys_ptr: set to the physical address corresponding to the virtual address
9823 * @attrs: set to the memory transaction attributes to use
9824 * @prot: set to the permissions for the page containing phys_ptr
9825 * @page_size: set to the size of the page containing phys_ptr
9826 * @fi: set to fault info if the translation fails
9827 * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
9829 static bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
9830 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
9831 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
9832 target_ulong
*page_size
,
9833 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
9835 if (mmu_idx
== ARMMMUIdx_S12NSE0
|| mmu_idx
== ARMMMUIdx_S12NSE1
) {
9836 /* Call ourselves recursively to do the stage 1 and then stage 2
9839 if (arm_feature(env
, ARM_FEATURE_EL2
)) {
9843 ARMCacheAttrs cacheattrs2
= {};
9845 ret
= get_phys_addr(env
, address
, access_type
,
9846 stage_1_mmu_idx(mmu_idx
), &ipa
, attrs
,
9847 prot
, page_size
, fi
, cacheattrs
);
9849 /* If S1 fails or S2 is disabled, return early. */
9850 if (ret
|| regime_translation_disabled(env
, ARMMMUIdx_S2NS
)) {
9855 /* S1 is done. Now do S2 translation. */
9856 ret
= get_phys_addr_lpae(env
, ipa
, access_type
, ARMMMUIdx_S2NS
,
9857 phys_ptr
, attrs
, &s2_prot
,
9859 cacheattrs
!= NULL
? &cacheattrs2
: NULL
);
9861 /* Combine the S1 and S2 perms. */
9864 /* Combine the S1 and S2 cache attributes, if needed */
9865 if (!ret
&& cacheattrs
!= NULL
) {
9866 *cacheattrs
= combine_cacheattrs(*cacheattrs
, cacheattrs2
);
9872 * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
9874 mmu_idx
= stage_1_mmu_idx(mmu_idx
);
9878 /* The page table entries may downgrade secure to non-secure, but
9879 * cannot upgrade an non-secure translation regime's attributes
9882 attrs
->secure
= regime_is_secure(env
, mmu_idx
);
9883 attrs
->user
= regime_is_user(env
, mmu_idx
);
9885 /* Fast Context Switch Extension. This doesn't exist at all in v8.
9886 * In v7 and earlier it affects all stage 1 translations.
9888 if (address
< 0x02000000 && mmu_idx
!= ARMMMUIdx_S2NS
9889 && !arm_feature(env
, ARM_FEATURE_V8
)) {
9890 if (regime_el(env
, mmu_idx
) == 3) {
9891 address
+= env
->cp15
.fcseidr_s
;
9893 address
+= env
->cp15
.fcseidr_ns
;
9897 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
9899 *page_size
= TARGET_PAGE_SIZE
;
9901 if (arm_feature(env
, ARM_FEATURE_V8
)) {
9903 ret
= get_phys_addr_pmsav8(env
, address
, access_type
, mmu_idx
,
9904 phys_ptr
, attrs
, prot
, fi
);
9905 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
9907 ret
= get_phys_addr_pmsav7(env
, address
, access_type
, mmu_idx
,
9908 phys_ptr
, prot
, fi
);
9911 ret
= get_phys_addr_pmsav5(env
, address
, access_type
, mmu_idx
,
9912 phys_ptr
, prot
, fi
);
9914 qemu_log_mask(CPU_LOG_MMU
, "PMSA MPU lookup for %s at 0x%08" PRIx32
9915 " mmu_idx %u -> %s (prot %c%c%c)\n",
9916 access_type
== MMU_DATA_LOAD
? "reading" :
9917 (access_type
== MMU_DATA_STORE
? "writing" : "execute"),
9918 (uint32_t)address
, mmu_idx
,
9919 ret
? "Miss" : "Hit",
9920 *prot
& PAGE_READ
? 'r' : '-',
9921 *prot
& PAGE_WRITE
? 'w' : '-',
9922 *prot
& PAGE_EXEC
? 'x' : '-');
9927 /* Definitely a real MMU, not an MPU */
9929 if (regime_translation_disabled(env
, mmu_idx
)) {
9931 *phys_ptr
= address
;
9932 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
9933 *page_size
= TARGET_PAGE_SIZE
;
9937 if (regime_using_lpae_format(env
, mmu_idx
)) {
9938 return get_phys_addr_lpae(env
, address
, access_type
, mmu_idx
,
9939 phys_ptr
, attrs
, prot
, page_size
,
9941 } else if (regime_sctlr(env
, mmu_idx
) & SCTLR_XP
) {
9942 return get_phys_addr_v6(env
, address
, access_type
, mmu_idx
,
9943 phys_ptr
, attrs
, prot
, page_size
, fi
);
9945 return get_phys_addr_v5(env
, address
, access_type
, mmu_idx
,
9946 phys_ptr
, prot
, page_size
, fi
);
9950 /* Walk the page table and (if the mapping exists) add the page
9951 * to the TLB. Return false on success, or true on failure. Populate
9952 * fsr with ARM DFSR/IFSR fault register format value on failure.
9954 bool arm_tlb_fill(CPUState
*cs
, vaddr address
,
9955 MMUAccessType access_type
, int mmu_idx
,
9956 ARMMMUFaultInfo
*fi
)
9958 ARMCPU
*cpu
= ARM_CPU(cs
);
9959 CPUARMState
*env
= &cpu
->env
;
9961 target_ulong page_size
;
9964 MemTxAttrs attrs
= {};
9966 ret
= get_phys_addr(env
, address
, access_type
,
9967 core_to_arm_mmu_idx(env
, mmu_idx
), &phys_addr
,
9968 &attrs
, &prot
, &page_size
, fi
, NULL
);
9970 /* Map a single [sub]page. */
9971 phys_addr
&= TARGET_PAGE_MASK
;
9972 address
&= TARGET_PAGE_MASK
;
9973 tlb_set_page_with_attrs(cs
, address
, phys_addr
, attrs
,
9974 prot
, mmu_idx
, page_size
);
9981 hwaddr
arm_cpu_get_phys_page_attrs_debug(CPUState
*cs
, vaddr addr
,
9984 ARMCPU
*cpu
= ARM_CPU(cs
);
9985 CPUARMState
*env
= &cpu
->env
;
9987 target_ulong page_size
;
9990 ARMMMUFaultInfo fi
= {};
9991 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
9993 *attrs
= (MemTxAttrs
) {};
9995 ret
= get_phys_addr(env
, addr
, 0, mmu_idx
, &phys_addr
,
9996 attrs
, &prot
, &page_size
, &fi
, NULL
);
10004 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
10007 unsigned el
= arm_current_el(env
);
10009 /* First handle registers which unprivileged can read */
10012 case 0 ... 7: /* xPSR sub-fields */
10014 if ((reg
& 1) && el
) {
10015 mask
|= XPSR_EXCP
; /* IPSR (unpriv. reads as zero) */
10018 mask
|= XPSR_NZCV
| XPSR_Q
; /* APSR */
10020 /* EPSR reads as zero */
10021 return xpsr_read(env
) & mask
;
10023 case 20: /* CONTROL */
10024 return env
->v7m
.control
[env
->v7m
.secure
];
10025 case 0x94: /* CONTROL_NS */
10026 /* We have to handle this here because unprivileged Secure code
10027 * can read the NS CONTROL register.
10029 if (!env
->v7m
.secure
) {
10032 return env
->v7m
.control
[M_REG_NS
];
10036 return 0; /* unprivileged reads others as zero */
10039 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10041 case 0x88: /* MSP_NS */
10042 if (!env
->v7m
.secure
) {
10045 return env
->v7m
.other_ss_msp
;
10046 case 0x89: /* PSP_NS */
10047 if (!env
->v7m
.secure
) {
10050 return env
->v7m
.other_ss_psp
;
10051 case 0x90: /* PRIMASK_NS */
10052 if (!env
->v7m
.secure
) {
10055 return env
->v7m
.primask
[M_REG_NS
];
10056 case 0x91: /* BASEPRI_NS */
10057 if (!env
->v7m
.secure
) {
10060 return env
->v7m
.basepri
[M_REG_NS
];
10061 case 0x93: /* FAULTMASK_NS */
10062 if (!env
->v7m
.secure
) {
10065 return env
->v7m
.faultmask
[M_REG_NS
];
10066 case 0x98: /* SP_NS */
10068 /* This gives the non-secure SP selected based on whether we're
10069 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10071 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10073 if (!env
->v7m
.secure
) {
10076 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10077 return env
->v7m
.other_ss_psp
;
10079 return env
->v7m
.other_ss_msp
;
10089 return v7m_using_psp(env
) ? env
->v7m
.other_sp
: env
->regs
[13];
10091 return v7m_using_psp(env
) ? env
->regs
[13] : env
->v7m
.other_sp
;
10092 case 16: /* PRIMASK */
10093 return env
->v7m
.primask
[env
->v7m
.secure
];
10094 case 17: /* BASEPRI */
10095 case 18: /* BASEPRI_MAX */
10096 return env
->v7m
.basepri
[env
->v7m
.secure
];
10097 case 19: /* FAULTMASK */
10098 return env
->v7m
.faultmask
[env
->v7m
.secure
];
10100 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to read unknown special"
10101 " register %d\n", reg
);
10106 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t maskreg
, uint32_t val
)
10108 /* We're passed bits [11..0] of the instruction; extract
10109 * SYSm and the mask bits.
10110 * Invalid combinations of SYSm and mask are UNPREDICTABLE;
10111 * we choose to treat them as if the mask bits were valid.
10112 * NB that the pseudocode 'mask' variable is bits [11..10],
10113 * whereas ours is [11..8].
10115 uint32_t mask
= extract32(maskreg
, 8, 4);
10116 uint32_t reg
= extract32(maskreg
, 0, 8);
10118 if (arm_current_el(env
) == 0 && reg
> 7) {
10119 /* only xPSR sub-fields may be written by unprivileged */
10123 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
10125 case 0x88: /* MSP_NS */
10126 if (!env
->v7m
.secure
) {
10129 env
->v7m
.other_ss_msp
= val
;
10131 case 0x89: /* PSP_NS */
10132 if (!env
->v7m
.secure
) {
10135 env
->v7m
.other_ss_psp
= val
;
10137 case 0x90: /* PRIMASK_NS */
10138 if (!env
->v7m
.secure
) {
10141 env
->v7m
.primask
[M_REG_NS
] = val
& 1;
10143 case 0x91: /* BASEPRI_NS */
10144 if (!env
->v7m
.secure
) {
10147 env
->v7m
.basepri
[M_REG_NS
] = val
& 0xff;
10149 case 0x93: /* FAULTMASK_NS */
10150 if (!env
->v7m
.secure
) {
10153 env
->v7m
.faultmask
[M_REG_NS
] = val
& 1;
10155 case 0x98: /* SP_NS */
10157 /* This gives the non-secure SP selected based on whether we're
10158 * currently in handler mode or not, using the NS CONTROL.SPSEL.
10160 bool spsel
= env
->v7m
.control
[M_REG_NS
] & R_V7M_CONTROL_SPSEL_MASK
;
10162 if (!env
->v7m
.secure
) {
10165 if (!arm_v7m_is_handler_mode(env
) && spsel
) {
10166 env
->v7m
.other_ss_psp
= val
;
10168 env
->v7m
.other_ss_msp
= val
;
10178 case 0 ... 7: /* xPSR sub-fields */
10179 /* only APSR is actually writable */
10181 uint32_t apsrmask
= 0;
10184 apsrmask
|= XPSR_NZCV
| XPSR_Q
;
10186 if ((mask
& 4) && arm_feature(env
, ARM_FEATURE_THUMB_DSP
)) {
10187 apsrmask
|= XPSR_GE
;
10189 xpsr_write(env
, val
, apsrmask
);
10193 if (v7m_using_psp(env
)) {
10194 env
->v7m
.other_sp
= val
;
10196 env
->regs
[13] = val
;
10200 if (v7m_using_psp(env
)) {
10201 env
->regs
[13] = val
;
10203 env
->v7m
.other_sp
= val
;
10206 case 16: /* PRIMASK */
10207 env
->v7m
.primask
[env
->v7m
.secure
] = val
& 1;
10209 case 17: /* BASEPRI */
10210 env
->v7m
.basepri
[env
->v7m
.secure
] = val
& 0xff;
10212 case 18: /* BASEPRI_MAX */
10214 if (val
!= 0 && (val
< env
->v7m
.basepri
[env
->v7m
.secure
]
10215 || env
->v7m
.basepri
[env
->v7m
.secure
] == 0)) {
10216 env
->v7m
.basepri
[env
->v7m
.secure
] = val
;
10219 case 19: /* FAULTMASK */
10220 env
->v7m
.faultmask
[env
->v7m
.secure
] = val
& 1;
10222 case 20: /* CONTROL */
10223 /* Writing to the SPSEL bit only has an effect if we are in
10224 * thread mode; other bits can be updated by any privileged code.
10225 * write_v7m_control_spsel() deals with updating the SPSEL bit in
10226 * env->v7m.control, so we only need update the others.
10227 * For v7M, we must just ignore explicit writes to SPSEL in handler
10228 * mode; for v8M the write is permitted but will have no effect.
10230 if (arm_feature(env
, ARM_FEATURE_V8
) ||
10231 !arm_v7m_is_handler_mode(env
)) {
10232 write_v7m_control_spsel(env
, (val
& R_V7M_CONTROL_SPSEL_MASK
) != 0);
10234 env
->v7m
.control
[env
->v7m
.secure
] &= ~R_V7M_CONTROL_NPRIV_MASK
;
10235 env
->v7m
.control
[env
->v7m
.secure
] |= val
& R_V7M_CONTROL_NPRIV_MASK
;
10238 qemu_log_mask(LOG_GUEST_ERROR
, "Attempt to write unknown special"
10239 " register %d\n", reg
);
10244 uint32_t HELPER(v7m_tt
)(CPUARMState
*env
, uint32_t addr
, uint32_t op
)
10246 /* Implement the TT instruction. op is bits [7:6] of the insn. */
10247 bool forceunpriv
= op
& 1;
10249 V8M_SAttributes sattrs
= {};
10251 bool r
, rw
, nsr
, nsrw
, mrvalid
;
10253 ARMMMUFaultInfo fi
= {};
10254 MemTxAttrs attrs
= {};
10259 bool targetsec
= env
->v7m
.secure
;
10261 /* Work out what the security state and privilege level we're
10262 * interested in is...
10265 targetsec
= !targetsec
;
10269 targetpriv
= false;
10271 targetpriv
= arm_v7m_is_handler_mode(env
) ||
10272 !(env
->v7m
.control
[targetsec
] & R_V7M_CONTROL_NPRIV_MASK
);
10275 /* ...and then figure out which MMU index this is */
10276 mmu_idx
= arm_v7m_mmu_idx_for_secstate_and_priv(env
, targetsec
, targetpriv
);
10278 /* We know that the MPU and SAU don't care about the access type
10279 * for our purposes beyond that we don't want to claim to be
10280 * an insn fetch, so we arbitrarily call this a read.
10283 /* MPU region info only available for privileged or if
10284 * inspecting the other MPU state.
10286 if (arm_current_el(env
) != 0 || alt
) {
10287 /* We can ignore the return value as prot is always set */
10288 pmsav8_mpu_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
,
10289 &phys_addr
, &attrs
, &prot
, &fi
, &mregion
);
10290 if (mregion
== -1) {
10296 r
= prot
& PAGE_READ
;
10297 rw
= prot
& PAGE_WRITE
;
10305 if (env
->v7m
.secure
) {
10306 v8m_security_lookup(env
, addr
, MMU_DATA_LOAD
, mmu_idx
, &sattrs
);
10307 nsr
= sattrs
.ns
&& r
;
10308 nsrw
= sattrs
.ns
&& rw
;
10315 tt_resp
= (sattrs
.iregion
<< 24) |
10316 (sattrs
.irvalid
<< 23) |
10317 ((!sattrs
.ns
) << 22) |
10322 (sattrs
.srvalid
<< 17) |
10324 (sattrs
.sregion
<< 8) |
10332 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
10334 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
10335 * Note that we do not implement the (architecturally mandated)
10336 * alignment fault for attempts to use this on Device memory
10337 * (which matches the usual QEMU behaviour of not implementing either
10338 * alignment faults or any memory attribute handling).
10341 ARMCPU
*cpu
= arm_env_get_cpu(env
);
10342 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
10343 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
10345 #ifndef CONFIG_USER_ONLY
10347 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
10348 * the block size so we might have to do more than one TLB lookup.
10349 * We know that in fact for any v8 CPU the page size is at least 4K
10350 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
10351 * 1K as an artefact of legacy v5 subpage support being present in the
10352 * same QEMU executable.
10354 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
10355 void *hostaddr
[maxidx
];
10357 unsigned mmu_idx
= cpu_mmu_index(env
, false);
10358 TCGMemOpIdx oi
= make_memop_idx(MO_UB
, mmu_idx
);
10360 for (try = 0; try < 2; try++) {
10362 for (i
= 0; i
< maxidx
; i
++) {
10363 hostaddr
[i
] = tlb_vaddr_to_host(env
,
10364 vaddr
+ TARGET_PAGE_SIZE
* i
,
10366 if (!hostaddr
[i
]) {
10371 /* If it's all in the TLB it's fair game for just writing to;
10372 * we know we don't need to update dirty status, etc.
10374 for (i
= 0; i
< maxidx
- 1; i
++) {
10375 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
10377 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
10380 /* OK, try a store and see if we can populate the tlb. This
10381 * might cause an exception if the memory isn't writable,
10382 * in which case we will longjmp out of here. We must for
10383 * this purpose use the actual register value passed to us
10384 * so that we get the fault address right.
10386 helper_ret_stb_mmu(env
, vaddr_in
, 0, oi
, GETPC());
10387 /* Now we can populate the other TLB entries, if any */
10388 for (i
= 0; i
< maxidx
; i
++) {
10389 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
10390 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
10391 helper_ret_stb_mmu(env
, va
, 0, oi
, GETPC());
10396 /* Slow path (probably attempt to do this to an I/O device or
10397 * similar, or clearing of a block of code we have translations
10398 * cached for). Just do a series of byte writes as the architecture
10399 * demands. It's not worth trying to use a cpu_physical_memory_map(),
10400 * memset(), unmap() sequence here because:
10401 * + we'd need to account for the blocksize being larger than a page
10402 * + the direct-RAM access case is almost always going to be dealt
10403 * with in the fastpath code above, so there's no speed benefit
10404 * + we would have to deal with the map returning NULL because the
10405 * bounce buffer was in use
10407 for (i
= 0; i
< blocklen
; i
++) {
10408 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, oi
, GETPC());
10412 memset(g2h(vaddr
), 0, blocklen
);
10416 /* Note that signed overflow is undefined in C. The following routines are
10417 careful to use unsigned types where modulo arithmetic is required.
10418 Failure to do so _will_ break on newer gcc. */
10420 /* Signed saturating arithmetic. */
10422 /* Perform 16-bit signed saturating addition. */
10423 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
10428 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
10437 /* Perform 8-bit signed saturating addition. */
10438 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
10443 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
10452 /* Perform 16-bit signed saturating subtraction. */
10453 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
10458 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
10467 /* Perform 8-bit signed saturating subtraction. */
10468 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
10473 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
10482 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
10483 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
10484 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
10485 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
10488 #include "op_addsub.h"
10490 /* Unsigned saturating arithmetic. */
10491 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
10500 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
10508 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
10517 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
10525 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
10526 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
10527 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
10528 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
10531 #include "op_addsub.h"
10533 /* Signed modulo arithmetic. */
10534 #define SARITH16(a, b, n, op) do { \
10536 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
10537 RESULT(sum, n, 16); \
10539 ge |= 3 << (n * 2); \
10542 #define SARITH8(a, b, n, op) do { \
10544 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
10545 RESULT(sum, n, 8); \
10551 #define ADD16(a, b, n) SARITH16(a, b, n, +)
10552 #define SUB16(a, b, n) SARITH16(a, b, n, -)
10553 #define ADD8(a, b, n) SARITH8(a, b, n, +)
10554 #define SUB8(a, b, n) SARITH8(a, b, n, -)
10558 #include "op_addsub.h"
10560 /* Unsigned modulo arithmetic. */
10561 #define ADD16(a, b, n) do { \
10563 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
10564 RESULT(sum, n, 16); \
10565 if ((sum >> 16) == 1) \
10566 ge |= 3 << (n * 2); \
10569 #define ADD8(a, b, n) do { \
10571 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
10572 RESULT(sum, n, 8); \
10573 if ((sum >> 8) == 1) \
10577 #define SUB16(a, b, n) do { \
10579 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
10580 RESULT(sum, n, 16); \
10581 if ((sum >> 16) == 0) \
10582 ge |= 3 << (n * 2); \
10585 #define SUB8(a, b, n) do { \
10587 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
10588 RESULT(sum, n, 8); \
10589 if ((sum >> 8) == 0) \
10596 #include "op_addsub.h"
10598 /* Halved signed arithmetic. */
10599 #define ADD16(a, b, n) \
10600 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
10601 #define SUB16(a, b, n) \
10602 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
10603 #define ADD8(a, b, n) \
10604 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
10605 #define SUB8(a, b, n) \
10606 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
10609 #include "op_addsub.h"
10611 /* Halved unsigned arithmetic. */
10612 #define ADD16(a, b, n) \
10613 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10614 #define SUB16(a, b, n) \
10615 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
10616 #define ADD8(a, b, n) \
10617 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10618 #define SUB8(a, b, n) \
10619 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
10622 #include "op_addsub.h"
10624 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
10632 /* Unsigned sum of absolute byte differences. */
10633 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
10636 sum
= do_usad(a
, b
);
10637 sum
+= do_usad(a
>> 8, b
>> 8);
10638 sum
+= do_usad(a
>> 16, b
>>16);
10639 sum
+= do_usad(a
>> 24, b
>> 24);
10643 /* For ARMv6 SEL instruction. */
10644 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
10656 mask
|= 0xff000000;
10657 return (a
& mask
) | (b
& ~mask
);
10660 /* VFP support. We follow the convention used for VFP instructions:
10661 Single precision routines have a "s" suffix, double precision a
10664 /* Convert host exception flags to vfp form. */
10665 static inline int vfp_exceptbits_from_host(int host_bits
)
10667 int target_bits
= 0;
10669 if (host_bits
& float_flag_invalid
)
10671 if (host_bits
& float_flag_divbyzero
)
10673 if (host_bits
& float_flag_overflow
)
10675 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
10677 if (host_bits
& float_flag_inexact
)
10678 target_bits
|= 0x10;
10679 if (host_bits
& float_flag_input_denormal
)
10680 target_bits
|= 0x80;
10681 return target_bits
;
10684 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
10689 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
10690 | (env
->vfp
.vec_len
<< 16)
10691 | (env
->vfp
.vec_stride
<< 20);
10692 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
10693 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
10694 fpscr
|= vfp_exceptbits_from_host(i
);
10698 uint32_t vfp_get_fpscr(CPUARMState
*env
)
10700 return HELPER(vfp_get_fpscr
)(env
);
10703 /* Convert vfp exception flags to target form. */
10704 static inline int vfp_exceptbits_to_host(int target_bits
)
10708 if (target_bits
& 1)
10709 host_bits
|= float_flag_invalid
;
10710 if (target_bits
& 2)
10711 host_bits
|= float_flag_divbyzero
;
10712 if (target_bits
& 4)
10713 host_bits
|= float_flag_overflow
;
10714 if (target_bits
& 8)
10715 host_bits
|= float_flag_underflow
;
10716 if (target_bits
& 0x10)
10717 host_bits
|= float_flag_inexact
;
10718 if (target_bits
& 0x80)
10719 host_bits
|= float_flag_input_denormal
;
10723 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
10728 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
10729 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
10730 env
->vfp
.vec_len
= (val
>> 16) & 7;
10731 env
->vfp
.vec_stride
= (val
>> 20) & 3;
10734 if (changed
& (3 << 22)) {
10735 i
= (val
>> 22) & 3;
10737 case FPROUNDING_TIEEVEN
:
10738 i
= float_round_nearest_even
;
10740 case FPROUNDING_POSINF
:
10741 i
= float_round_up
;
10743 case FPROUNDING_NEGINF
:
10744 i
= float_round_down
;
10746 case FPROUNDING_ZERO
:
10747 i
= float_round_to_zero
;
10750 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
10752 if (changed
& (1 << 24)) {
10753 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
10754 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
10756 if (changed
& (1 << 25))
10757 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
10759 i
= vfp_exceptbits_to_host(val
);
10760 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
10761 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
10764 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
10766 HELPER(vfp_set_fpscr
)(env
, val
);
10769 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
10771 #define VFP_BINOP(name) \
10772 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
10774 float_status *fpst = fpstp; \
10775 return float32_ ## name(a, b, fpst); \
10777 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
10779 float_status *fpst = fpstp; \
10780 return float64_ ## name(a, b, fpst); \
10792 float32
VFP_HELPER(neg
, s
)(float32 a
)
10794 return float32_chs(a
);
10797 float64
VFP_HELPER(neg
, d
)(float64 a
)
10799 return float64_chs(a
);
10802 float32
VFP_HELPER(abs
, s
)(float32 a
)
10804 return float32_abs(a
);
10807 float64
VFP_HELPER(abs
, d
)(float64 a
)
10809 return float64_abs(a
);
10812 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
10814 return float32_sqrt(a
, &env
->vfp
.fp_status
);
10817 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
10819 return float64_sqrt(a
, &env
->vfp
.fp_status
);
10822 /* XXX: check quiet/signaling case */
10823 #define DO_VFP_cmp(p, type) \
10824 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
10827 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
10828 case 0: flags = 0x6; break; \
10829 case -1: flags = 0x8; break; \
10830 case 1: flags = 0x2; break; \
10831 default: case 2: flags = 0x3; break; \
10833 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
10834 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
10836 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
10839 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
10840 case 0: flags = 0x6; break; \
10841 case -1: flags = 0x8; break; \
10842 case 1: flags = 0x2; break; \
10843 default: case 2: flags = 0x3; break; \
10845 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
10846 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
10848 DO_VFP_cmp(s
, float32
)
10849 DO_VFP_cmp(d
, float64
)
10852 /* Integer to float and float to integer conversions */
10854 #define CONV_ITOF(name, fsz, sign) \
10855 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
10857 float_status *fpst = fpstp; \
10858 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
10861 #define CONV_FTOI(name, fsz, sign, round) \
10862 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
10864 float_status *fpst = fpstp; \
10865 if (float##fsz##_is_any_nan(x)) { \
10866 float_raise(float_flag_invalid, fpst); \
10869 return float##fsz##_to_##sign##int32##round(x, fpst); \
10872 #define FLOAT_CONVS(name, p, fsz, sign) \
10873 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
10874 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
10875 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
10877 FLOAT_CONVS(si
, s
, 32, )
10878 FLOAT_CONVS(si
, d
, 64, )
10879 FLOAT_CONVS(ui
, s
, 32, u
)
10880 FLOAT_CONVS(ui
, d
, 64, u
)
10886 /* floating point conversion */
10887 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
10889 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
10890 /* ARM requires that S<->D conversion of any kind of NaN generates
10891 * a quiet NaN by forcing the most significant frac bit to 1.
10893 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
10896 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
10898 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
10899 /* ARM requires that S<->D conversion of any kind of NaN generates
10900 * a quiet NaN by forcing the most significant frac bit to 1.
10902 return float32_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
10905 /* VFP3 fixed point conversion. */
10906 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
10907 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
10910 float_status *fpst = fpstp; \
10912 tmp = itype##_to_##float##fsz(x, fpst); \
10913 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
10916 /* Notice that we want only input-denormal exception flags from the
10917 * scalbn operation: the other possible flags (overflow+inexact if
10918 * we overflow to infinity, output-denormal) aren't correct for the
10919 * complete scale-and-convert operation.
10921 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
10922 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
10926 float_status *fpst = fpstp; \
10927 int old_exc_flags = get_float_exception_flags(fpst); \
10929 if (float##fsz##_is_any_nan(x)) { \
10930 float_raise(float_flag_invalid, fpst); \
10933 tmp = float##fsz##_scalbn(x, shift, fpst); \
10934 old_exc_flags |= get_float_exception_flags(fpst) \
10935 & float_flag_input_denormal; \
10936 set_float_exception_flags(old_exc_flags, fpst); \
10937 return float##fsz##_to_##itype##round(tmp, fpst); \
10940 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
10941 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
10942 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
10943 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
10945 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
10946 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
10947 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
10949 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
10950 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
10951 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
10952 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
10953 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
10954 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
10955 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
10956 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
10957 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
10958 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
10959 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
10960 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
10961 #undef VFP_CONV_FIX
10962 #undef VFP_CONV_FIX_FLOAT
10963 #undef VFP_CONV_FLOAT_FIX_ROUND
10965 /* Set the current fp rounding mode and return the old one.
10966 * The argument is a softfloat float_round_ value.
10968 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
10970 float_status
*fp_status
= &env
->vfp
.fp_status
;
10972 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
10973 set_float_rounding_mode(rmode
, fp_status
);
10978 /* Set the current fp rounding mode in the standard fp status and return
10979 * the old one. This is for NEON instructions that need to change the
10980 * rounding mode but wish to use the standard FPSCR values for everything
10981 * else. Always set the rounding mode back to the correct value after
10983 * The argument is a softfloat float_round_ value.
10985 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
10987 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
10989 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
10990 set_float_rounding_mode(rmode
, fp_status
);
10995 /* Half precision conversions. */
10996 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
10998 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
10999 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
11001 return float32_maybe_silence_nan(r
, s
);
11006 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
11008 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11009 float16 r
= float32_to_float16(a
, ieee
, s
);
11011 r
= float16_maybe_silence_nan(r
, s
);
11013 return float16_val(r
);
11016 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
11018 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
11021 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
11023 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
11026 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
11028 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
11031 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
11033 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
11036 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
11038 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11039 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
11041 return float64_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
11046 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
11048 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
11049 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
11051 r
= float16_maybe_silence_nan(r
, &env
->vfp
.fp_status
);
11053 return float16_val(r
);
11056 #define float32_two make_float32(0x40000000)
11057 #define float32_three make_float32(0x40400000)
11058 #define float32_one_point_five make_float32(0x3fc00000)
11060 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11062 float_status
*s
= &env
->vfp
.standard_fp_status
;
11063 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11064 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11065 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11066 float_raise(float_flag_input_denormal
, s
);
11068 return float32_two
;
11070 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
11073 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
11075 float_status
*s
= &env
->vfp
.standard_fp_status
;
11077 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
11078 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
11079 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
11080 float_raise(float_flag_input_denormal
, s
);
11082 return float32_one_point_five
;
11084 product
= float32_mul(a
, b
, s
);
11085 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
11088 /* NEON helpers. */
11090 /* Constants 256 and 512 are used in some helpers; we avoid relying on
11091 * int->float conversions at run-time. */
11092 #define float64_256 make_float64(0x4070000000000000LL)
11093 #define float64_512 make_float64(0x4080000000000000LL)
11094 #define float32_maxnorm make_float32(0x7f7fffff)
11095 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
11097 /* Reciprocal functions
11099 * The algorithm that must be used to calculate the estimate
11100 * is specified by the ARM ARM, see FPRecipEstimate()
11103 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
11105 /* These calculations mustn't set any fp exception flags,
11106 * so we use a local copy of the fp_status.
11108 float_status dummy_status
= *real_fp_status
;
11109 float_status
*s
= &dummy_status
;
11110 /* q = (int)(a * 512.0) */
11111 float64 q
= float64_mul(float64_512
, a
, s
);
11112 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
11114 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
11115 q
= int64_to_float64(q_int
, s
);
11116 q
= float64_add(q
, float64_half
, s
);
11117 q
= float64_div(q
, float64_512
, s
);
11118 q
= float64_div(float64_one
, q
, s
);
11120 /* s = (int)(256.0 * r + 0.5) */
11121 q
= float64_mul(q
, float64_256
, s
);
11122 q
= float64_add(q
, float64_half
, s
);
11123 q_int
= float64_to_int64_round_to_zero(q
, s
);
11125 /* return (double)s / 256.0 */
11126 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
11129 /* Common wrapper to call recip_estimate */
11130 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
11132 uint64_t val64
= float64_val(num
);
11133 uint64_t frac
= extract64(val64
, 0, 52);
11134 int64_t exp
= extract64(val64
, 52, 11);
11136 float64 scaled
, estimate
;
11138 /* Generate the scaled number for the estimate function */
11140 if (extract64(frac
, 51, 1) == 0) {
11142 frac
= extract64(frac
, 0, 50) << 2;
11144 frac
= extract64(frac
, 0, 51) << 1;
11148 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
11149 scaled
= make_float64((0x3feULL
<< 52)
11150 | extract64(frac
, 44, 8) << 44);
11152 estimate
= recip_estimate(scaled
, fpst
);
11154 /* Build new result */
11155 val64
= float64_val(estimate
);
11156 sbit
= 0x8000000000000000ULL
& val64
;
11158 frac
= extract64(val64
, 0, 52);
11161 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
11162 } else if (exp
== -1) {
11163 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
11167 return make_float64(sbit
| (exp
<< 52) | frac
);
11170 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
11172 switch (fpst
->float_rounding_mode
) {
11173 case float_round_nearest_even
: /* Round to Nearest */
11175 case float_round_up
: /* Round to +Inf */
11177 case float_round_down
: /* Round to -Inf */
11179 case float_round_to_zero
: /* Round to Zero */
11183 g_assert_not_reached();
11186 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
11188 float_status
*fpst
= fpstp
;
11189 float32 f32
= float32_squash_input_denormal(input
, fpst
);
11190 uint32_t f32_val
= float32_val(f32
);
11191 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
11192 int32_t f32_exp
= extract32(f32_val
, 23, 8);
11193 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
11199 if (float32_is_any_nan(f32
)) {
11201 if (float32_is_signaling_nan(f32
, fpst
)) {
11202 float_raise(float_flag_invalid
, fpst
);
11203 nan
= float32_maybe_silence_nan(f32
, fpst
);
11205 if (fpst
->default_nan_mode
) {
11206 nan
= float32_default_nan(fpst
);
11209 } else if (float32_is_infinity(f32
)) {
11210 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
11211 } else if (float32_is_zero(f32
)) {
11212 float_raise(float_flag_divbyzero
, fpst
);
11213 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
11214 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
11215 /* Abs(value) < 2.0^-128 */
11216 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11217 if (round_to_inf(fpst
, f32_sbit
)) {
11218 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
11220 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
11222 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
11223 float_raise(float_flag_underflow
, fpst
);
11224 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
11228 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
11229 r64
= call_recip_estimate(f64
, 253, fpst
);
11230 r64_val
= float64_val(r64
);
11231 r64_exp
= extract64(r64_val
, 52, 11);
11232 r64_frac
= extract64(r64_val
, 0, 52);
11234 /* result = sign : result_exp<7:0> : fraction<51:29>; */
11235 return make_float32(f32_sbit
|
11236 (r64_exp
& 0xff) << 23 |
11237 extract64(r64_frac
, 29, 24));
11240 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
11242 float_status
*fpst
= fpstp
;
11243 float64 f64
= float64_squash_input_denormal(input
, fpst
);
11244 uint64_t f64_val
= float64_val(f64
);
11245 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
11246 int64_t f64_exp
= extract64(f64_val
, 52, 11);
11252 /* Deal with any special cases */
11253 if (float64_is_any_nan(f64
)) {
11255 if (float64_is_signaling_nan(f64
, fpst
)) {
11256 float_raise(float_flag_invalid
, fpst
);
11257 nan
= float64_maybe_silence_nan(f64
, fpst
);
11259 if (fpst
->default_nan_mode
) {
11260 nan
= float64_default_nan(fpst
);
11263 } else if (float64_is_infinity(f64
)) {
11264 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
11265 } else if (float64_is_zero(f64
)) {
11266 float_raise(float_flag_divbyzero
, fpst
);
11267 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11268 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
11269 /* Abs(value) < 2.0^-1024 */
11270 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
11271 if (round_to_inf(fpst
, f64_sbit
)) {
11272 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11274 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
11276 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
11277 float_raise(float_flag_underflow
, fpst
);
11278 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
11281 r64
= call_recip_estimate(f64
, 2045, fpst
);
11282 r64_val
= float64_val(r64
);
11283 r64_exp
= extract64(r64_val
, 52, 11);
11284 r64_frac
= extract64(r64_val
, 0, 52);
11286 /* result = sign : result_exp<10:0> : fraction<51:0> */
11287 return make_float64(f64_sbit
|
11288 ((r64_exp
& 0x7ff) << 52) |
11292 /* The algorithm that must be used to calculate the estimate
11293 * is specified by the ARM ARM.
11295 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
11297 /* These calculations mustn't set any fp exception flags,
11298 * so we use a local copy of the fp_status.
11300 float_status dummy_status
= *real_fp_status
;
11301 float_status
*s
= &dummy_status
;
11305 if (float64_lt(a
, float64_half
, s
)) {
11306 /* range 0.25 <= a < 0.5 */
11308 /* a in units of 1/512 rounded down */
11309 /* q0 = (int)(a * 512.0); */
11310 q
= float64_mul(float64_512
, a
, s
);
11311 q_int
= float64_to_int64_round_to_zero(q
, s
);
11313 /* reciprocal root r */
11314 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
11315 q
= int64_to_float64(q_int
, s
);
11316 q
= float64_add(q
, float64_half
, s
);
11317 q
= float64_div(q
, float64_512
, s
);
11318 q
= float64_sqrt(q
, s
);
11319 q
= float64_div(float64_one
, q
, s
);
11321 /* range 0.5 <= a < 1.0 */
11323 /* a in units of 1/256 rounded down */
11324 /* q1 = (int)(a * 256.0); */
11325 q
= float64_mul(float64_256
, a
, s
);
11326 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
11328 /* reciprocal root r */
11329 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
11330 q
= int64_to_float64(q_int
, s
);
11331 q
= float64_add(q
, float64_half
, s
);
11332 q
= float64_div(q
, float64_256
, s
);
11333 q
= float64_sqrt(q
, s
);
11334 q
= float64_div(float64_one
, q
, s
);
11336 /* r in units of 1/256 rounded to nearest */
11337 /* s = (int)(256.0 * r + 0.5); */
11339 q
= float64_mul(q
, float64_256
,s
);
11340 q
= float64_add(q
, float64_half
, s
);
11341 q_int
= float64_to_int64_round_to_zero(q
, s
);
11343 /* return (double)s / 256.0;*/
11344 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
11347 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
11349 float_status
*s
= fpstp
;
11350 float32 f32
= float32_squash_input_denormal(input
, s
);
11351 uint32_t val
= float32_val(f32
);
11352 uint32_t f32_sbit
= 0x80000000 & val
;
11353 int32_t f32_exp
= extract32(val
, 23, 8);
11354 uint32_t f32_frac
= extract32(val
, 0, 23);
11360 if (float32_is_any_nan(f32
)) {
11362 if (float32_is_signaling_nan(f32
, s
)) {
11363 float_raise(float_flag_invalid
, s
);
11364 nan
= float32_maybe_silence_nan(f32
, s
);
11366 if (s
->default_nan_mode
) {
11367 nan
= float32_default_nan(s
);
11370 } else if (float32_is_zero(f32
)) {
11371 float_raise(float_flag_divbyzero
, s
);
11372 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
11373 } else if (float32_is_neg(f32
)) {
11374 float_raise(float_flag_invalid
, s
);
11375 return float32_default_nan(s
);
11376 } else if (float32_is_infinity(f32
)) {
11377 return float32_zero
;
11380 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
11381 * preserving the parity of the exponent. */
11383 f64_frac
= ((uint64_t) f32_frac
) << 29;
11384 if (f32_exp
== 0) {
11385 while (extract64(f64_frac
, 51, 1) == 0) {
11386 f64_frac
= f64_frac
<< 1;
11387 f32_exp
= f32_exp
-1;
11389 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
11392 if (extract64(f32_exp
, 0, 1) == 0) {
11393 f64
= make_float64(((uint64_t) f32_sbit
) << 32
11397 f64
= make_float64(((uint64_t) f32_sbit
) << 32
11402 result_exp
= (380 - f32_exp
) / 2;
11404 f64
= recip_sqrt_estimate(f64
, s
);
11406 val64
= float64_val(f64
);
11408 val
= ((result_exp
& 0xff) << 23)
11409 | ((val64
>> 29) & 0x7fffff);
11410 return make_float32(val
);
11413 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
11415 float_status
*s
= fpstp
;
11416 float64 f64
= float64_squash_input_denormal(input
, s
);
11417 uint64_t val
= float64_val(f64
);
11418 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
11419 int64_t f64_exp
= extract64(val
, 52, 11);
11420 uint64_t f64_frac
= extract64(val
, 0, 52);
11421 int64_t result_exp
;
11422 uint64_t result_frac
;
11424 if (float64_is_any_nan(f64
)) {
11426 if (float64_is_signaling_nan(f64
, s
)) {
11427 float_raise(float_flag_invalid
, s
);
11428 nan
= float64_maybe_silence_nan(f64
, s
);
11430 if (s
->default_nan_mode
) {
11431 nan
= float64_default_nan(s
);
11434 } else if (float64_is_zero(f64
)) {
11435 float_raise(float_flag_divbyzero
, s
);
11436 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
11437 } else if (float64_is_neg(f64
)) {
11438 float_raise(float_flag_invalid
, s
);
11439 return float64_default_nan(s
);
11440 } else if (float64_is_infinity(f64
)) {
11441 return float64_zero
;
11444 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
11445 * preserving the parity of the exponent. */
11447 if (f64_exp
== 0) {
11448 while (extract64(f64_frac
, 51, 1) == 0) {
11449 f64_frac
= f64_frac
<< 1;
11450 f64_exp
= f64_exp
- 1;
11452 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
11455 if (extract64(f64_exp
, 0, 1) == 0) {
11456 f64
= make_float64(f64_sbit
11460 f64
= make_float64(f64_sbit
11465 result_exp
= (3068 - f64_exp
) / 2;
11467 f64
= recip_sqrt_estimate(f64
, s
);
11469 result_frac
= extract64(float64_val(f64
), 0, 52);
11471 return make_float64(f64_sbit
|
11472 ((result_exp
& 0x7ff) << 52) |
11476 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
11478 float_status
*s
= fpstp
;
11481 if ((a
& 0x80000000) == 0) {
11485 f64
= make_float64((0x3feULL
<< 52)
11486 | ((int64_t)(a
& 0x7fffffff) << 21));
11488 f64
= recip_estimate(f64
, s
);
11490 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
11493 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
11495 float_status
*fpst
= fpstp
;
11498 if ((a
& 0xc0000000) == 0) {
11502 if (a
& 0x80000000) {
11503 f64
= make_float64((0x3feULL
<< 52)
11504 | ((uint64_t)(a
& 0x7fffffff) << 21));
11505 } else { /* bits 31-30 == '01' */
11506 f64
= make_float64((0x3fdULL
<< 52)
11507 | ((uint64_t)(a
& 0x3fffffff) << 22));
11510 f64
= recip_sqrt_estimate(f64
, fpst
);
11512 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
11515 /* VFPv4 fused multiply-accumulate */
11516 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
11518 float_status
*fpst
= fpstp
;
11519 return float32_muladd(a
, b
, c
, 0, fpst
);
11522 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
11524 float_status
*fpst
= fpstp
;
11525 return float64_muladd(a
, b
, c
, 0, fpst
);
11528 /* ARMv8 round to integral */
11529 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
11531 return float32_round_to_int(x
, fp_status
);
11534 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
11536 return float64_round_to_int(x
, fp_status
);
11539 float32
HELPER(rints
)(float32 x
, void *fp_status
)
11541 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
11544 ret
= float32_round_to_int(x
, fp_status
);
11546 /* Suppress any inexact exceptions the conversion produced */
11547 if (!(old_flags
& float_flag_inexact
)) {
11548 new_flags
= get_float_exception_flags(fp_status
);
11549 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
11555 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
11557 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
11560 ret
= float64_round_to_int(x
, fp_status
);
11562 new_flags
= get_float_exception_flags(fp_status
);
11564 /* Suppress any inexact exceptions the conversion produced */
11565 if (!(old_flags
& float_flag_inexact
)) {
11566 new_flags
= get_float_exception_flags(fp_status
);
11567 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
11573 /* Convert ARM rounding mode to softfloat */
11574 int arm_rmode_to_sf(int rmode
)
11577 case FPROUNDING_TIEAWAY
:
11578 rmode
= float_round_ties_away
;
11580 case FPROUNDING_ODD
:
11581 /* FIXME: add support for TIEAWAY and ODD */
11582 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
11584 case FPROUNDING_TIEEVEN
:
11586 rmode
= float_round_nearest_even
;
11588 case FPROUNDING_POSINF
:
11589 rmode
= float_round_up
;
11591 case FPROUNDING_NEGINF
:
11592 rmode
= float_round_down
;
11594 case FPROUNDING_ZERO
:
11595 rmode
= float_round_to_zero
;
11602 * The upper bytes of val (above the number specified by 'bytes') must have
11603 * been zeroed out by the caller.
11605 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11609 stl_le_p(buf
, val
);
11611 /* zlib crc32 converts the accumulator and output to one's complement. */
11612 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
11615 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
11619 stl_le_p(buf
, val
);
11621 /* Linux crc32c converts the output to one's complement. */
11622 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;
11625 /* Return the exception level to which FP-disabled exceptions should
11626 * be taken, or 0 if FP is enabled.
11628 static inline int fp_exception_el(CPUARMState
*env
)
11630 #ifndef CONFIG_USER_ONLY
11632 int cur_el
= arm_current_el(env
);
11634 /* CPACR and the CPTR registers don't exist before v6, so FP is
11635 * always accessible
11637 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
11641 /* The CPACR controls traps to EL1, or PL1 if we're 32 bit:
11642 * 0, 2 : trap EL0 and EL1/PL1 accesses
11643 * 1 : trap only EL0 accesses
11644 * 3 : trap no accesses
11646 fpen
= extract32(env
->cp15
.cpacr_el1
, 20, 2);
11650 if (cur_el
== 0 || cur_el
== 1) {
11651 /* Trap to PL1, which might be EL1 or EL3 */
11652 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3)) {
11657 if (cur_el
== 3 && !is_a64(env
)) {
11658 /* Secure PL1 running at EL3 */
11671 /* For the CPTR registers we don't need to guard with an ARM_FEATURE
11672 * check because zero bits in the registers mean "don't trap".
11675 /* CPTR_EL2 : present in v7VE or v8 */
11676 if (cur_el
<= 2 && extract32(env
->cp15
.cptr_el
[2], 10, 1)
11677 && !arm_is_secure_below_el3(env
)) {
11678 /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
11682 /* CPTR_EL3 : present in v8 */
11683 if (extract32(env
->cp15
.cptr_el
[3], 10, 1)) {
11684 /* Trap all FP ops to EL3 */
11691 void cpu_get_tb_cpu_state(CPUARMState
*env
, target_ulong
*pc
,
11692 target_ulong
*cs_base
, uint32_t *pflags
)
11694 ARMMMUIdx mmu_idx
= core_to_arm_mmu_idx(env
, cpu_mmu_index(env
, false));
11699 flags
= ARM_TBFLAG_AARCH64_STATE_MASK
;
11700 /* Get control bits for tagged addresses */
11701 flags
|= (arm_regime_tbi0(env
, mmu_idx
) << ARM_TBFLAG_TBI0_SHIFT
);
11702 flags
|= (arm_regime_tbi1(env
, mmu_idx
) << ARM_TBFLAG_TBI1_SHIFT
);
11704 *pc
= env
->regs
[15];
11705 flags
= (env
->thumb
<< ARM_TBFLAG_THUMB_SHIFT
)
11706 | (env
->vfp
.vec_len
<< ARM_TBFLAG_VECLEN_SHIFT
)
11707 | (env
->vfp
.vec_stride
<< ARM_TBFLAG_VECSTRIDE_SHIFT
)
11708 | (env
->condexec_bits
<< ARM_TBFLAG_CONDEXEC_SHIFT
)
11709 | (arm_sctlr_b(env
) << ARM_TBFLAG_SCTLR_B_SHIFT
);
11710 if (!(access_secure_reg(env
))) {
11711 flags
|= ARM_TBFLAG_NS_MASK
;
11713 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30)
11714 || arm_el_is_aa64(env
, 1)) {
11715 flags
|= ARM_TBFLAG_VFPEN_MASK
;
11717 flags
|= (extract32(env
->cp15
.c15_cpar
, 0, 2)
11718 << ARM_TBFLAG_XSCALE_CPAR_SHIFT
);
11721 flags
|= (arm_to_core_mmu_idx(mmu_idx
) << ARM_TBFLAG_MMUIDX_SHIFT
);
11723 /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
11724 * states defined in the ARM ARM for software singlestep:
11725 * SS_ACTIVE PSTATE.SS State
11726 * 0 x Inactive (the TB flag for SS is always 0)
11727 * 1 0 Active-pending
11728 * 1 1 Active-not-pending
11730 if (arm_singlestep_active(env
)) {
11731 flags
|= ARM_TBFLAG_SS_ACTIVE_MASK
;
11733 if (env
->pstate
& PSTATE_SS
) {
11734 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
11737 if (env
->uncached_cpsr
& PSTATE_SS
) {
11738 flags
|= ARM_TBFLAG_PSTATE_SS_MASK
;
11742 if (arm_cpu_data_is_big_endian(env
)) {
11743 flags
|= ARM_TBFLAG_BE_DATA_MASK
;
11745 flags
|= fp_exception_el(env
) << ARM_TBFLAG_FPEXC_EL_SHIFT
;
11747 if (arm_v7m_is_handler_mode(env
)) {
11748 flags
|= ARM_TBFLAG_HANDLER_MASK
;