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target-ppc: Fix rlwimi, rlwinm, rlwnm again
[qemu/ar7.git] / target-ppc / translate.c
blob395b885f5b9eea31de0106c5f9c73b61d80e60c5
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/host-utils.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 #define CPU_SINGLE_STEP 0x1
37 #define CPU_BRANCH_STEP 0x2
38 #define GDBSTUB_SINGLE_STEP 0x4
39
40 /* Include definitions for instructions classes and implementations flags */
41 //#define PPC_DEBUG_DISAS
42 //#define DO_PPC_STATISTICS
43
44 #ifdef PPC_DEBUG_DISAS
45 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
46 #else
47 # define LOG_DISAS(...) do { } while (0)
48 #endif
49 /*****************************************************************************/
50 /* Code translation helpers */
51
52 /* global register indexes */
53 static TCGv_env cpu_env;
54 static char cpu_reg_names[10*3 + 22*4 /* GPR */
55 + 10*4 + 22*5 /* SPE GPRh */
56 + 10*4 + 22*5 /* FPR */
57 + 2*(10*6 + 22*7) /* AVRh, AVRl */
58 + 10*5 + 22*6 /* VSR */
59 + 8*5 /* CRF */];
60 static TCGv cpu_gpr[32];
61 static TCGv cpu_gprh[32];
62 static TCGv_i64 cpu_fpr[32];
63 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
64 static TCGv_i64 cpu_vsr[32];
65 static TCGv_i32 cpu_crf[8];
66 static TCGv cpu_nip;
67 static TCGv cpu_msr;
68 static TCGv cpu_ctr;
69 static TCGv cpu_lr;
70 #if defined(TARGET_PPC64)
71 static TCGv cpu_cfar;
72 #endif
73 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
74 static TCGv cpu_reserve;
75 static TCGv cpu_fpscr;
76 static TCGv_i32 cpu_access_type;
77
78 #include "exec/gen-icount.h"
79
80 void ppc_translate_init(void)
81 {
82 int i;
83 char* p;
84 size_t cpu_reg_names_size;
85 static int done_init = 0;
86
87 if (done_init)
88 return;
89
90 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
91 tcg_ctx.tcg_env = cpu_env;
92
93 p = cpu_reg_names;
94 cpu_reg_names_size = sizeof(cpu_reg_names);
95
96 for (i = 0; i < 8; i++) {
97 snprintf(p, cpu_reg_names_size, "crf%d", i);
98 cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
99 offsetof(CPUPPCState, crf[i]), p);
100 p += 5;
101 cpu_reg_names_size -= 5;
102 }
103
104 for (i = 0; i < 32; i++) {
105 snprintf(p, cpu_reg_names_size, "r%d", i);
106 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
107 offsetof(CPUPPCState, gpr[i]), p);
108 p += (i < 10) ? 3 : 4;
109 cpu_reg_names_size -= (i < 10) ? 3 : 4;
110 snprintf(p, cpu_reg_names_size, "r%dH", i);
111 cpu_gprh[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUPPCState, gprh[i]), p);
113 p += (i < 10) ? 4 : 5;
114 cpu_reg_names_size -= (i < 10) ? 4 : 5;
115
116 snprintf(p, cpu_reg_names_size, "fp%d", i);
117 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
118 offsetof(CPUPPCState, fpr[i]), p);
119 p += (i < 10) ? 4 : 5;
120 cpu_reg_names_size -= (i < 10) ? 4 : 5;
121
122 snprintf(p, cpu_reg_names_size, "avr%dH", i);
123 #ifdef HOST_WORDS_BIGENDIAN
124 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
125 offsetof(CPUPPCState, avr[i].u64[0]), p);
126 #else
127 cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
128 offsetof(CPUPPCState, avr[i].u64[1]), p);
129 #endif
130 p += (i < 10) ? 6 : 7;
131 cpu_reg_names_size -= (i < 10) ? 6 : 7;
132
133 snprintf(p, cpu_reg_names_size, "avr%dL", i);
134 #ifdef HOST_WORDS_BIGENDIAN
135 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
136 offsetof(CPUPPCState, avr[i].u64[1]), p);
137 #else
138 cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
139 offsetof(CPUPPCState, avr[i].u64[0]), p);
140 #endif
141 p += (i < 10) ? 6 : 7;
142 cpu_reg_names_size -= (i < 10) ? 6 : 7;
143 snprintf(p, cpu_reg_names_size, "vsr%d", i);
144 cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
145 offsetof(CPUPPCState, vsr[i]), p);
146 p += (i < 10) ? 5 : 6;
147 cpu_reg_names_size -= (i < 10) ? 5 : 6;
148 }
149
150 cpu_nip = tcg_global_mem_new(cpu_env,
151 offsetof(CPUPPCState, nip), "nip");
152
153 cpu_msr = tcg_global_mem_new(cpu_env,
154 offsetof(CPUPPCState, msr), "msr");
155
156 cpu_ctr = tcg_global_mem_new(cpu_env,
157 offsetof(CPUPPCState, ctr), "ctr");
158
159 cpu_lr = tcg_global_mem_new(cpu_env,
160 offsetof(CPUPPCState, lr), "lr");
161
162 #if defined(TARGET_PPC64)
163 cpu_cfar = tcg_global_mem_new(cpu_env,
164 offsetof(CPUPPCState, cfar), "cfar");
165 #endif
166
167 cpu_xer = tcg_global_mem_new(cpu_env,
168 offsetof(CPUPPCState, xer), "xer");
169 cpu_so = tcg_global_mem_new(cpu_env,
170 offsetof(CPUPPCState, so), "SO");
171 cpu_ov = tcg_global_mem_new(cpu_env,
172 offsetof(CPUPPCState, ov), "OV");
173 cpu_ca = tcg_global_mem_new(cpu_env,
174 offsetof(CPUPPCState, ca), "CA");
175
176 cpu_reserve = tcg_global_mem_new(cpu_env,
177 offsetof(CPUPPCState, reserve_addr),
178 "reserve_addr");
179
180 cpu_fpscr = tcg_global_mem_new(cpu_env,
181 offsetof(CPUPPCState, fpscr), "fpscr");
182
183 cpu_access_type = tcg_global_mem_new_i32(cpu_env,
184 offsetof(CPUPPCState, access_type), "access_type");
185
186 done_init = 1;
187 }
188
189 /* internal defines */
190 struct DisasContext {
191 struct TranslationBlock *tb;
192 target_ulong nip;
193 uint32_t opcode;
194 uint32_t exception;
195 /* Routine used to access memory */
196 bool pr, hv;
197 bool lazy_tlb_flush;
198 int mem_idx;
199 int access_type;
200 /* Translation flags */
201 int le_mode;
202 TCGMemOp default_tcg_memop_mask;
203 #if defined(TARGET_PPC64)
204 int sf_mode;
205 int has_cfar;
206 #endif
207 int fpu_enabled;
208 int altivec_enabled;
209 int vsx_enabled;
210 int spe_enabled;
211 int tm_enabled;
212 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
213 int singlestep_enabled;
214 uint64_t insns_flags;
215 uint64_t insns_flags2;
216 };
217
218 /* Return true iff byteswap is needed in a scalar memop */
219 static inline bool need_byteswap(const DisasContext *ctx)
220 {
221 #if defined(TARGET_WORDS_BIGENDIAN)
222 return ctx->le_mode;
223 #else
224 return !ctx->le_mode;
225 #endif
226 }
227
228 /* True when active word size < size of target_long. */
229 #ifdef TARGET_PPC64
230 # define NARROW_MODE(C) (!(C)->sf_mode)
231 #else
232 # define NARROW_MODE(C) 0
233 #endif
234
235 struct opc_handler_t {
236 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
237 uint32_t inval1;
238 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
239 uint32_t inval2;
240 /* instruction type */
241 uint64_t type;
242 /* extended instruction type */
243 uint64_t type2;
244 /* handler */
245 void (*handler)(DisasContext *ctx);
246 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
247 const char *oname;
248 #endif
249 #if defined(DO_PPC_STATISTICS)
250 uint64_t count;
251 #endif
252 };
253
254 static inline void gen_reset_fpstatus(void)
255 {
256 gen_helper_reset_fpstatus(cpu_env);
257 }
258
259 static inline void gen_compute_fprf(TCGv_i64 arg)
260 {
261 gen_helper_compute_fprf(cpu_env, arg);
262 gen_helper_float_check_status(cpu_env);
263 }
264
265 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
266 {
267 if (ctx->access_type != access_type) {
268 tcg_gen_movi_i32(cpu_access_type, access_type);
269 ctx->access_type = access_type;
270 }
271 }
272
273 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
274 {
275 if (NARROW_MODE(ctx)) {
276 nip = (uint32_t)nip;
277 }
278 tcg_gen_movi_tl(cpu_nip, nip);
279 }
280
281 void gen_update_current_nip(void *opaque)
282 {
283 DisasContext *ctx = opaque;
284
285 tcg_gen_movi_tl(cpu_nip, ctx->nip);
286 }
287
288 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
289 {
290 TCGv_i32 t0, t1;
291 if (ctx->exception == POWERPC_EXCP_NONE) {
292 gen_update_nip(ctx, ctx->nip);
293 }
294 t0 = tcg_const_i32(excp);
295 t1 = tcg_const_i32(error);
296 gen_helper_raise_exception_err(cpu_env, t0, t1);
297 tcg_temp_free_i32(t0);
298 tcg_temp_free_i32(t1);
299 ctx->exception = (excp);
300 }
301
302 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
303 {
304 TCGv_i32 t0;
305 if (ctx->exception == POWERPC_EXCP_NONE) {
306 gen_update_nip(ctx, ctx->nip);
307 }
308 t0 = tcg_const_i32(excp);
309 gen_helper_raise_exception(cpu_env, t0);
310 tcg_temp_free_i32(t0);
311 ctx->exception = (excp);
312 }
313
314 static inline void gen_debug_exception(DisasContext *ctx)
315 {
316 TCGv_i32 t0;
317
318 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
319 (ctx->exception != POWERPC_EXCP_SYNC)) {
320 gen_update_nip(ctx, ctx->nip);
321 }
322 t0 = tcg_const_i32(EXCP_DEBUG);
323 gen_helper_raise_exception(cpu_env, t0);
324 tcg_temp_free_i32(t0);
325 }
326
327 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
328 {
329 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
330 }
331
332 /* Stop translation */
333 static inline void gen_stop_exception(DisasContext *ctx)
334 {
335 gen_update_nip(ctx, ctx->nip);
336 ctx->exception = POWERPC_EXCP_STOP;
337 }
338
339 #ifndef CONFIG_USER_ONLY
340 /* No need to update nip here, as execution flow will change */
341 static inline void gen_sync_exception(DisasContext *ctx)
342 {
343 ctx->exception = POWERPC_EXCP_SYNC;
344 }
345 #endif
346
347 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
348 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
349
350 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
351 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
352
353 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
354 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
355
356 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
357 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
358
359 typedef struct opcode_t {
360 unsigned char opc1, opc2, opc3;
361 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
362 unsigned char pad[5];
363 #else
364 unsigned char pad[1];
365 #endif
366 opc_handler_t handler;
367 const char *oname;
368 } opcode_t;
369
370 /*****************************************************************************/
371 /*** Instruction decoding ***/
372 #define EXTRACT_HELPER(name, shift, nb) \
373 static inline uint32_t name(uint32_t opcode) \
374 { \
375 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
376 }
377
378 #define EXTRACT_SHELPER(name, shift, nb) \
379 static inline int32_t name(uint32_t opcode) \
380 { \
381 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
382 }
383
384 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
385 static inline uint32_t name(uint32_t opcode) \
386 { \
387 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
388 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
389 }
390 /* Opcode part 1 */
391 EXTRACT_HELPER(opc1, 26, 6);
392 /* Opcode part 2 */
393 EXTRACT_HELPER(opc2, 1, 5);
394 /* Opcode part 3 */
395 EXTRACT_HELPER(opc3, 6, 5);
396 /* Update Cr0 flags */
397 EXTRACT_HELPER(Rc, 0, 1);
398 /* Update Cr6 flags (Altivec) */
399 EXTRACT_HELPER(Rc21, 10, 1);
400 /* Destination */
401 EXTRACT_HELPER(rD, 21, 5);
402 /* Source */
403 EXTRACT_HELPER(rS, 21, 5);
404 /* First operand */
405 EXTRACT_HELPER(rA, 16, 5);
406 /* Second operand */
407 EXTRACT_HELPER(rB, 11, 5);
408 /* Third operand */
409 EXTRACT_HELPER(rC, 6, 5);
410 /*** Get CRn ***/
411 EXTRACT_HELPER(crfD, 23, 3);
412 EXTRACT_HELPER(crfS, 18, 3);
413 EXTRACT_HELPER(crbD, 21, 5);
414 EXTRACT_HELPER(crbA, 16, 5);
415 EXTRACT_HELPER(crbB, 11, 5);
416 /* SPR / TBL */
417 EXTRACT_HELPER(_SPR, 11, 10);
418 static inline uint32_t SPR(uint32_t opcode)
419 {
420 uint32_t sprn = _SPR(opcode);
421
422 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
423 }
424 /*** Get constants ***/
425 /* 16 bits signed immediate value */
426 EXTRACT_SHELPER(SIMM, 0, 16);
427 /* 16 bits unsigned immediate value */
428 EXTRACT_HELPER(UIMM, 0, 16);
429 /* 5 bits signed immediate value */
430 EXTRACT_HELPER(SIMM5, 16, 5);
431 /* 5 bits signed immediate value */
432 EXTRACT_HELPER(UIMM5, 16, 5);
433 /* Bit count */
434 EXTRACT_HELPER(NB, 11, 5);
435 /* Shift count */
436 EXTRACT_HELPER(SH, 11, 5);
437 /* Vector shift count */
438 EXTRACT_HELPER(VSH, 6, 4);
439 /* Mask start */
440 EXTRACT_HELPER(MB, 6, 5);
441 /* Mask end */
442 EXTRACT_HELPER(ME, 1, 5);
443 /* Trap operand */
444 EXTRACT_HELPER(TO, 21, 5);
445
446 EXTRACT_HELPER(CRM, 12, 8);
447
448 #ifndef CONFIG_USER_ONLY
449 EXTRACT_HELPER(SR, 16, 4);
450 #endif
451
452 /* mtfsf/mtfsfi */
453 EXTRACT_HELPER(FPBF, 23, 3);
454 EXTRACT_HELPER(FPIMM, 12, 4);
455 EXTRACT_HELPER(FPL, 25, 1);
456 EXTRACT_HELPER(FPFLM, 17, 8);
457 EXTRACT_HELPER(FPW, 16, 1);
458
459 /*** Jump target decoding ***/
460 /* Immediate address */
461 static inline target_ulong LI(uint32_t opcode)
462 {
463 return (opcode >> 0) & 0x03FFFFFC;
464 }
465
466 static inline uint32_t BD(uint32_t opcode)
467 {
468 return (opcode >> 0) & 0xFFFC;
469 }
470
471 EXTRACT_HELPER(BO, 21, 5);
472 EXTRACT_HELPER(BI, 16, 5);
473 /* Absolute/relative address */
474 EXTRACT_HELPER(AA, 1, 1);
475 /* Link */
476 EXTRACT_HELPER(LK, 0, 1);
477
478 /* DFP Z22-form */
479 EXTRACT_HELPER(DCM, 10, 6)
480
481 /* DFP Z23-form */
482 EXTRACT_HELPER(RMC, 9, 2)
483
484 /* Create a mask between <start> and <end> bits */
485 static inline target_ulong MASK(uint32_t start, uint32_t end)
486 {
487 target_ulong ret;
488
489 #if defined(TARGET_PPC64)
490 if (likely(start == 0)) {
491 ret = UINT64_MAX << (63 - end);
492 } else if (likely(end == 63)) {
493 ret = UINT64_MAX >> start;
494 }
495 #else
496 if (likely(start == 0)) {
497 ret = UINT32_MAX << (31 - end);
498 } else if (likely(end == 31)) {
499 ret = UINT32_MAX >> start;
500 }
501 #endif
502 else {
503 ret = (((target_ulong)(-1ULL)) >> (start)) ^
504 (((target_ulong)(-1ULL) >> (end)) >> 1);
505 if (unlikely(start > end))
506 return ~ret;
507 }
508
509 return ret;
510 }
511
512 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
513 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
514 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
515 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
516 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
517 EXTRACT_HELPER(DM, 8, 2);
518 EXTRACT_HELPER(UIM, 16, 2);
519 EXTRACT_HELPER(SHW, 8, 2);
520 EXTRACT_HELPER(SP, 19, 2);
521 /*****************************************************************************/
522 /* PowerPC instructions table */
523
524 #if defined(DO_PPC_STATISTICS)
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 .oname = stringify(name), \
537 }, \
538 .oname = stringify(name), \
539 }
540 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
541 { \
542 .opc1 = op1, \
543 .opc2 = op2, \
544 .opc3 = op3, \
545 .pad = { 0, }, \
546 .handler = { \
547 .inval1 = invl1, \
548 .inval2 = invl2, \
549 .type = _typ, \
550 .type2 = _typ2, \
551 .handler = &gen_##name, \
552 .oname = stringify(name), \
553 }, \
554 .oname = stringify(name), \
555 }
556 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
557 { \
558 .opc1 = op1, \
559 .opc2 = op2, \
560 .opc3 = op3, \
561 .pad = { 0, }, \
562 .handler = { \
563 .inval1 = invl, \
564 .type = _typ, \
565 .type2 = _typ2, \
566 .handler = &gen_##name, \
567 .oname = onam, \
568 }, \
569 .oname = onam, \
570 }
571 #else
572 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
573 { \
574 .opc1 = op1, \
575 .opc2 = op2, \
576 .opc3 = op3, \
577 .pad = { 0, }, \
578 .handler = { \
579 .inval1 = invl, \
580 .type = _typ, \
581 .type2 = _typ2, \
582 .handler = &gen_##name, \
583 }, \
584 .oname = stringify(name), \
585 }
586 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
587 { \
588 .opc1 = op1, \
589 .opc2 = op2, \
590 .opc3 = op3, \
591 .pad = { 0, }, \
592 .handler = { \
593 .inval1 = invl1, \
594 .inval2 = invl2, \
595 .type = _typ, \
596 .type2 = _typ2, \
597 .handler = &gen_##name, \
598 }, \
599 .oname = stringify(name), \
600 }
601 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
602 { \
603 .opc1 = op1, \
604 .opc2 = op2, \
605 .opc3 = op3, \
606 .pad = { 0, }, \
607 .handler = { \
608 .inval1 = invl, \
609 .type = _typ, \
610 .type2 = _typ2, \
611 .handler = &gen_##name, \
612 }, \
613 .oname = onam, \
614 }
615 #endif
616
617 /* SPR load/store helpers */
618 static inline void gen_load_spr(TCGv t, int reg)
619 {
620 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
621 }
622
623 static inline void gen_store_spr(int reg, TCGv t)
624 {
625 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
626 }
627
628 /* Invalid instruction */
629 static void gen_invalid(DisasContext *ctx)
630 {
631 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
632 }
633
634 static opc_handler_t invalid_handler = {
635 .inval1 = 0xFFFFFFFF,
636 .inval2 = 0xFFFFFFFF,
637 .type = PPC_NONE,
638 .type2 = PPC_NONE,
639 .handler = gen_invalid,
640 };
641
642 /*** Integer comparison ***/
643
644 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
645 {
646 TCGv t0 = tcg_temp_new();
647 TCGv_i32 t1 = tcg_temp_new_i32();
648
649 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
650
651 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
652 tcg_gen_trunc_tl_i32(t1, t0);
653 tcg_gen_shli_i32(t1, t1, CRF_LT);
654 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
655
656 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
657 tcg_gen_trunc_tl_i32(t1, t0);
658 tcg_gen_shli_i32(t1, t1, CRF_GT);
659 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
660
661 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
662 tcg_gen_trunc_tl_i32(t1, t0);
663 tcg_gen_shli_i32(t1, t1, CRF_EQ);
664 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
665
666 tcg_temp_free(t0);
667 tcg_temp_free_i32(t1);
668 }
669
670 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
671 {
672 TCGv t0 = tcg_const_tl(arg1);
673 gen_op_cmp(arg0, t0, s, crf);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
678 {
679 TCGv t0, t1;
680 t0 = tcg_temp_new();
681 t1 = tcg_temp_new();
682 if (s) {
683 tcg_gen_ext32s_tl(t0, arg0);
684 tcg_gen_ext32s_tl(t1, arg1);
685 } else {
686 tcg_gen_ext32u_tl(t0, arg0);
687 tcg_gen_ext32u_tl(t1, arg1);
688 }
689 gen_op_cmp(t0, t1, s, crf);
690 tcg_temp_free(t1);
691 tcg_temp_free(t0);
692 }
693
694 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
695 {
696 TCGv t0 = tcg_const_tl(arg1);
697 gen_op_cmp32(arg0, t0, s, crf);
698 tcg_temp_free(t0);
699 }
700
701 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
702 {
703 if (NARROW_MODE(ctx)) {
704 gen_op_cmpi32(reg, 0, 1, 0);
705 } else {
706 gen_op_cmpi(reg, 0, 1, 0);
707 }
708 }
709
710 /* cmp */
711 static void gen_cmp(DisasContext *ctx)
712 {
713 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
714 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
715 1, crfD(ctx->opcode));
716 } else {
717 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
718 1, crfD(ctx->opcode));
719 }
720 }
721
722 /* cmpi */
723 static void gen_cmpi(DisasContext *ctx)
724 {
725 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
726 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
727 1, crfD(ctx->opcode));
728 } else {
729 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
730 1, crfD(ctx->opcode));
731 }
732 }
733
734 /* cmpl */
735 static void gen_cmpl(DisasContext *ctx)
736 {
737 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
738 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
739 0, crfD(ctx->opcode));
740 } else {
741 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
742 0, crfD(ctx->opcode));
743 }
744 }
745
746 /* cmpli */
747 static void gen_cmpli(DisasContext *ctx)
748 {
749 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
750 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
751 0, crfD(ctx->opcode));
752 } else {
753 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
754 0, crfD(ctx->opcode));
755 }
756 }
757
758 /* isel (PowerPC 2.03 specification) */
759 static void gen_isel(DisasContext *ctx)
760 {
761 uint32_t bi = rC(ctx->opcode);
762 uint32_t mask = 0x08 >> (bi & 0x03);
763 TCGv t0 = tcg_temp_new();
764 TCGv zr;
765
766 tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]);
767 tcg_gen_andi_tl(t0, t0, mask);
768
769 zr = tcg_const_tl(0);
770 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr,
771 rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr,
772 cpu_gpr[rB(ctx->opcode)]);
773 tcg_temp_free(zr);
774 tcg_temp_free(t0);
775 }
776
777 /* cmpb: PowerPC 2.05 specification */
778 static void gen_cmpb(DisasContext *ctx)
779 {
780 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
781 cpu_gpr[rB(ctx->opcode)]);
782 }
783
784 /*** Integer arithmetic ***/
785
786 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
787 TCGv arg1, TCGv arg2, int sub)
788 {
789 TCGv t0 = tcg_temp_new();
790
791 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
792 tcg_gen_xor_tl(t0, arg1, arg2);
793 if (sub) {
794 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
795 } else {
796 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
797 }
798 tcg_temp_free(t0);
799 if (NARROW_MODE(ctx)) {
800 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
801 }
802 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
803 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
804 }
805
806 /* Common add function */
807 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
808 TCGv arg2, bool add_ca, bool compute_ca,
809 bool compute_ov, bool compute_rc0)
810 {
811 TCGv t0 = ret;
812
813 if (compute_ca || compute_ov) {
814 t0 = tcg_temp_new();
815 }
816
817 if (compute_ca) {
818 if (NARROW_MODE(ctx)) {
819 /* Caution: a non-obvious corner case of the spec is that we
820 must produce the *entire* 64-bit addition, but produce the
821 carry into bit 32. */
822 TCGv t1 = tcg_temp_new();
823 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
824 tcg_gen_add_tl(t0, arg1, arg2);
825 if (add_ca) {
826 tcg_gen_add_tl(t0, t0, cpu_ca);
827 }
828 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
829 tcg_temp_free(t1);
830 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
831 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
832 } else {
833 TCGv zero = tcg_const_tl(0);
834 if (add_ca) {
835 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
836 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
837 } else {
838 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
839 }
840 tcg_temp_free(zero);
841 }
842 } else {
843 tcg_gen_add_tl(t0, arg1, arg2);
844 if (add_ca) {
845 tcg_gen_add_tl(t0, t0, cpu_ca);
846 }
847 }
848
849 if (compute_ov) {
850 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
851 }
852 if (unlikely(compute_rc0)) {
853 gen_set_Rc0(ctx, t0);
854 }
855
856 if (!TCGV_EQUAL(t0, ret)) {
857 tcg_gen_mov_tl(ret, t0);
858 tcg_temp_free(t0);
859 }
860 }
861 /* Add functions with two operands */
862 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
863 static void glue(gen_, name)(DisasContext *ctx) \
864 { \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 }
869 /* Add functions with one operand and one immediate */
870 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
871 add_ca, compute_ca, compute_ov) \
872 static void glue(gen_, name)(DisasContext *ctx) \
873 { \
874 TCGv t0 = tcg_const_tl(const_val); \
875 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
876 cpu_gpr[rA(ctx->opcode)], t0, \
877 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
878 tcg_temp_free(t0); \
879 }
880
881 /* add add. addo addo. */
882 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
883 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
884 /* addc addc. addco addco. */
885 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
886 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
887 /* adde adde. addeo addeo. */
888 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
889 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
890 /* addme addme. addmeo addmeo. */
891 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
892 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
893 /* addze addze. addzeo addzeo.*/
894 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
895 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
896 /* addi */
897 static void gen_addi(DisasContext *ctx)
898 {
899 target_long simm = SIMM(ctx->opcode);
900
901 if (rA(ctx->opcode) == 0) {
902 /* li case */
903 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
904 } else {
905 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
906 cpu_gpr[rA(ctx->opcode)], simm);
907 }
908 }
909 /* addic addic.*/
910 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
911 {
912 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
913 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
914 c, 0, 1, 0, compute_rc0);
915 tcg_temp_free(c);
916 }
917
918 static void gen_addic(DisasContext *ctx)
919 {
920 gen_op_addic(ctx, 0);
921 }
922
923 static void gen_addic_(DisasContext *ctx)
924 {
925 gen_op_addic(ctx, 1);
926 }
927
928 /* addis */
929 static void gen_addis(DisasContext *ctx)
930 {
931 target_long simm = SIMM(ctx->opcode);
932
933 if (rA(ctx->opcode) == 0) {
934 /* lis case */
935 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
936 } else {
937 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
938 cpu_gpr[rA(ctx->opcode)], simm << 16);
939 }
940 }
941
942 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
943 TCGv arg2, int sign, int compute_ov)
944 {
945 TCGLabel *l1 = gen_new_label();
946 TCGLabel *l2 = gen_new_label();
947 TCGv_i32 t0 = tcg_temp_local_new_i32();
948 TCGv_i32 t1 = tcg_temp_local_new_i32();
949
950 tcg_gen_trunc_tl_i32(t0, arg1);
951 tcg_gen_trunc_tl_i32(t1, arg2);
952 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
953 if (sign) {
954 TCGLabel *l3 = gen_new_label();
955 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
956 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
957 gen_set_label(l3);
958 tcg_gen_div_i32(t0, t0, t1);
959 } else {
960 tcg_gen_divu_i32(t0, t0, t1);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 0);
964 }
965 tcg_gen_br(l2);
966 gen_set_label(l1);
967 if (sign) {
968 tcg_gen_sari_i32(t0, t0, 31);
969 } else {
970 tcg_gen_movi_i32(t0, 0);
971 }
972 if (compute_ov) {
973 tcg_gen_movi_tl(cpu_ov, 1);
974 tcg_gen_movi_tl(cpu_so, 1);
975 }
976 gen_set_label(l2);
977 tcg_gen_extu_i32_tl(ret, t0);
978 tcg_temp_free_i32(t0);
979 tcg_temp_free_i32(t1);
980 if (unlikely(Rc(ctx->opcode) != 0))
981 gen_set_Rc0(ctx, ret);
982 }
983 /* Div functions */
984 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
985 static void glue(gen_, name)(DisasContext *ctx) \
986 { \
987 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
988 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
989 sign, compute_ov); \
990 }
991 /* divwu divwu. divwuo divwuo. */
992 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
993 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
994 /* divw divw. divwo divwo. */
995 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
996 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
997
998 /* div[wd]eu[o][.] */
999 #define GEN_DIVE(name, hlpr, compute_ov) \
1000 static void gen_##name(DisasContext *ctx) \
1001 { \
1002 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1003 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1004 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1005 tcg_temp_free_i32(t0); \
1006 if (unlikely(Rc(ctx->opcode) != 0)) { \
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1008 } \
1009 }
1010
1011 GEN_DIVE(divweu, divweu, 0);
1012 GEN_DIVE(divweuo, divweu, 1);
1013 GEN_DIVE(divwe, divwe, 0);
1014 GEN_DIVE(divweo, divwe, 1);
1015
1016 #if defined(TARGET_PPC64)
1017 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1018 TCGv arg2, int sign, int compute_ov)
1019 {
1020 TCGLabel *l1 = gen_new_label();
1021 TCGLabel *l2 = gen_new_label();
1022
1023 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1024 if (sign) {
1025 TCGLabel *l3 = gen_new_label();
1026 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1027 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1028 gen_set_label(l3);
1029 tcg_gen_div_i64(ret, arg1, arg2);
1030 } else {
1031 tcg_gen_divu_i64(ret, arg1, arg2);
1032 }
1033 if (compute_ov) {
1034 tcg_gen_movi_tl(cpu_ov, 0);
1035 }
1036 tcg_gen_br(l2);
1037 gen_set_label(l1);
1038 if (sign) {
1039 tcg_gen_sari_i64(ret, arg1, 63);
1040 } else {
1041 tcg_gen_movi_i64(ret, 0);
1042 }
1043 if (compute_ov) {
1044 tcg_gen_movi_tl(cpu_ov, 1);
1045 tcg_gen_movi_tl(cpu_so, 1);
1046 }
1047 gen_set_label(l2);
1048 if (unlikely(Rc(ctx->opcode) != 0))
1049 gen_set_Rc0(ctx, ret);
1050 }
1051 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1052 static void glue(gen_, name)(DisasContext *ctx) \
1053 { \
1054 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1055 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1056 sign, compute_ov); \
1057 }
1058 /* divwu divwu. divwuo divwuo. */
1059 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1060 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1061 /* divw divw. divwo divwo. */
1062 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1063 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1064
1065 GEN_DIVE(divdeu, divdeu, 0);
1066 GEN_DIVE(divdeuo, divdeu, 1);
1067 GEN_DIVE(divde, divde, 0);
1068 GEN_DIVE(divdeo, divde, 1);
1069 #endif
1070
1071 /* mulhw mulhw. */
1072 static void gen_mulhw(DisasContext *ctx)
1073 {
1074 TCGv_i32 t0 = tcg_temp_new_i32();
1075 TCGv_i32 t1 = tcg_temp_new_i32();
1076
1077 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1078 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1079 tcg_gen_muls2_i32(t0, t1, t0, t1);
1080 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1081 tcg_temp_free_i32(t0);
1082 tcg_temp_free_i32(t1);
1083 if (unlikely(Rc(ctx->opcode) != 0))
1084 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1085 }
1086
1087 /* mulhwu mulhwu. */
1088 static void gen_mulhwu(DisasContext *ctx)
1089 {
1090 TCGv_i32 t0 = tcg_temp_new_i32();
1091 TCGv_i32 t1 = tcg_temp_new_i32();
1092
1093 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1094 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1095 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1096 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1097 tcg_temp_free_i32(t0);
1098 tcg_temp_free_i32(t1);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mullw mullw. */
1104 static void gen_mullw(DisasContext *ctx)
1105 {
1106 #if defined(TARGET_PPC64)
1107 TCGv_i64 t0, t1;
1108 t0 = tcg_temp_new_i64();
1109 t1 = tcg_temp_new_i64();
1110 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1111 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1112 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1113 tcg_temp_free(t0);
1114 tcg_temp_free(t1);
1115 #else
1116 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1117 cpu_gpr[rB(ctx->opcode)]);
1118 #endif
1119 if (unlikely(Rc(ctx->opcode) != 0))
1120 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1121 }
1122
1123 /* mullwo mullwo. */
1124 static void gen_mullwo(DisasContext *ctx)
1125 {
1126 TCGv_i32 t0 = tcg_temp_new_i32();
1127 TCGv_i32 t1 = tcg_temp_new_i32();
1128
1129 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1130 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1131 tcg_gen_muls2_i32(t0, t1, t0, t1);
1132 #if defined(TARGET_PPC64)
1133 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1134 #else
1135 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1136 #endif
1137
1138 tcg_gen_sari_i32(t0, t0, 31);
1139 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1140 tcg_gen_extu_i32_tl(cpu_ov, t0);
1141 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1142
1143 tcg_temp_free_i32(t0);
1144 tcg_temp_free_i32(t1);
1145 if (unlikely(Rc(ctx->opcode) != 0))
1146 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1147 }
1148
1149 /* mulli */
1150 static void gen_mulli(DisasContext *ctx)
1151 {
1152 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1153 SIMM(ctx->opcode));
1154 }
1155
1156 #if defined(TARGET_PPC64)
1157 /* mulhd mulhd. */
1158 static void gen_mulhd(DisasContext *ctx)
1159 {
1160 TCGv lo = tcg_temp_new();
1161 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1162 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1163 tcg_temp_free(lo);
1164 if (unlikely(Rc(ctx->opcode) != 0)) {
1165 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1166 }
1167 }
1168
1169 /* mulhdu mulhdu. */
1170 static void gen_mulhdu(DisasContext *ctx)
1171 {
1172 TCGv lo = tcg_temp_new();
1173 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1174 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1175 tcg_temp_free(lo);
1176 if (unlikely(Rc(ctx->opcode) != 0)) {
1177 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1178 }
1179 }
1180
1181 /* mulld mulld. */
1182 static void gen_mulld(DisasContext *ctx)
1183 {
1184 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1185 cpu_gpr[rB(ctx->opcode)]);
1186 if (unlikely(Rc(ctx->opcode) != 0))
1187 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1188 }
1189
1190 /* mulldo mulldo. */
1191 static void gen_mulldo(DisasContext *ctx)
1192 {
1193 TCGv_i64 t0 = tcg_temp_new_i64();
1194 TCGv_i64 t1 = tcg_temp_new_i64();
1195
1196 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1197 cpu_gpr[rB(ctx->opcode)]);
1198 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1199
1200 tcg_gen_sari_i64(t0, t0, 63);
1201 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1202 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1203
1204 tcg_temp_free_i64(t0);
1205 tcg_temp_free_i64(t1);
1206
1207 if (unlikely(Rc(ctx->opcode) != 0)) {
1208 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1209 }
1210 }
1211 #endif
1212
1213 /* Common subf function */
1214 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1215 TCGv arg2, bool add_ca, bool compute_ca,
1216 bool compute_ov, bool compute_rc0)
1217 {
1218 TCGv t0 = ret;
1219
1220 if (compute_ca || compute_ov) {
1221 t0 = tcg_temp_new();
1222 }
1223
1224 if (compute_ca) {
1225 /* dest = ~arg1 + arg2 [+ ca]. */
1226 if (NARROW_MODE(ctx)) {
1227 /* Caution: a non-obvious corner case of the spec is that we
1228 must produce the *entire* 64-bit addition, but produce the
1229 carry into bit 32. */
1230 TCGv inv1 = tcg_temp_new();
1231 TCGv t1 = tcg_temp_new();
1232 tcg_gen_not_tl(inv1, arg1);
1233 if (add_ca) {
1234 tcg_gen_add_tl(t0, arg2, cpu_ca);
1235 } else {
1236 tcg_gen_addi_tl(t0, arg2, 1);
1237 }
1238 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1239 tcg_gen_add_tl(t0, t0, inv1);
1240 tcg_temp_free(inv1);
1241 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1242 tcg_temp_free(t1);
1243 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1244 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1245 } else if (add_ca) {
1246 TCGv zero, inv1 = tcg_temp_new();
1247 tcg_gen_not_tl(inv1, arg1);
1248 zero = tcg_const_tl(0);
1249 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1250 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1251 tcg_temp_free(zero);
1252 tcg_temp_free(inv1);
1253 } else {
1254 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1255 tcg_gen_sub_tl(t0, arg2, arg1);
1256 }
1257 } else if (add_ca) {
1258 /* Since we're ignoring carry-out, we can simplify the
1259 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1260 tcg_gen_sub_tl(t0, arg2, arg1);
1261 tcg_gen_add_tl(t0, t0, cpu_ca);
1262 tcg_gen_subi_tl(t0, t0, 1);
1263 } else {
1264 tcg_gen_sub_tl(t0, arg2, arg1);
1265 }
1266
1267 if (compute_ov) {
1268 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1269 }
1270 if (unlikely(compute_rc0)) {
1271 gen_set_Rc0(ctx, t0);
1272 }
1273
1274 if (!TCGV_EQUAL(t0, ret)) {
1275 tcg_gen_mov_tl(ret, t0);
1276 tcg_temp_free(t0);
1277 }
1278 }
1279 /* Sub functions with Two operands functions */
1280 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1281 static void glue(gen_, name)(DisasContext *ctx) \
1282 { \
1283 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1284 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1285 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1286 }
1287 /* Sub functions with one operand and one immediate */
1288 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1289 add_ca, compute_ca, compute_ov) \
1290 static void glue(gen_, name)(DisasContext *ctx) \
1291 { \
1292 TCGv t0 = tcg_const_tl(const_val); \
1293 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1294 cpu_gpr[rA(ctx->opcode)], t0, \
1295 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1296 tcg_temp_free(t0); \
1297 }
1298 /* subf subf. subfo subfo. */
1299 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1300 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1301 /* subfc subfc. subfco subfco. */
1302 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1303 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1304 /* subfe subfe. subfeo subfo. */
1305 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1306 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1307 /* subfme subfme. subfmeo subfmeo. */
1308 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1309 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1310 /* subfze subfze. subfzeo subfzeo.*/
1311 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1312 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1313
1314 /* subfic */
1315 static void gen_subfic(DisasContext *ctx)
1316 {
1317 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1318 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1319 c, 0, 1, 0, 0);
1320 tcg_temp_free(c);
1321 }
1322
1323 /* neg neg. nego nego. */
1324 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1325 {
1326 TCGv zero = tcg_const_tl(0);
1327 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1328 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1329 tcg_temp_free(zero);
1330 }
1331
1332 static void gen_neg(DisasContext *ctx)
1333 {
1334 gen_op_arith_neg(ctx, 0);
1335 }
1336
1337 static void gen_nego(DisasContext *ctx)
1338 {
1339 gen_op_arith_neg(ctx, 1);
1340 }
1341
1342 /*** Integer logical ***/
1343 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1344 static void glue(gen_, name)(DisasContext *ctx) \
1345 { \
1346 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1347 cpu_gpr[rB(ctx->opcode)]); \
1348 if (unlikely(Rc(ctx->opcode) != 0)) \
1349 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1350 }
1351
1352 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1353 static void glue(gen_, name)(DisasContext *ctx) \
1354 { \
1355 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1356 if (unlikely(Rc(ctx->opcode) != 0)) \
1357 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1358 }
1359
1360 /* and & and. */
1361 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1362 /* andc & andc. */
1363 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1364
1365 /* andi. */
1366 static void gen_andi_(DisasContext *ctx)
1367 {
1368 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1369 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1370 }
1371
1372 /* andis. */
1373 static void gen_andis_(DisasContext *ctx)
1374 {
1375 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1376 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1377 }
1378
1379 /* cntlzw */
1380 static void gen_cntlzw(DisasContext *ctx)
1381 {
1382 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1383 if (unlikely(Rc(ctx->opcode) != 0))
1384 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1385 }
1386 /* eqv & eqv. */
1387 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1388 /* extsb & extsb. */
1389 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1390 /* extsh & extsh. */
1391 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1392 /* nand & nand. */
1393 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1394 /* nor & nor. */
1395 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1396
1397 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1398 static void gen_pause(DisasContext *ctx)
1399 {
1400 TCGv_i32 t0 = tcg_const_i32(0);
1401 tcg_gen_st_i32(t0, cpu_env,
1402 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
1403 tcg_temp_free_i32(t0);
1404
1405 /* Stop translation, this gives other CPUs a chance to run */
1406 gen_exception_err(ctx, EXCP_HLT, 1);
1407 }
1408 #endif /* defined(TARGET_PPC64) */
1409
1410 /* or & or. */
1411 static void gen_or(DisasContext *ctx)
1412 {
1413 int rs, ra, rb;
1414
1415 rs = rS(ctx->opcode);
1416 ra = rA(ctx->opcode);
1417 rb = rB(ctx->opcode);
1418 /* Optimisation for mr. ri case */
1419 if (rs != ra || rs != rb) {
1420 if (rs != rb)
1421 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1422 else
1423 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1424 if (unlikely(Rc(ctx->opcode) != 0))
1425 gen_set_Rc0(ctx, cpu_gpr[ra]);
1426 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1427 gen_set_Rc0(ctx, cpu_gpr[rs]);
1428 #if defined(TARGET_PPC64)
1429 } else {
1430 int prio = 0;
1431
1432 switch (rs) {
1433 case 1:
1434 /* Set process priority to low */
1435 prio = 2;
1436 break;
1437 case 6:
1438 /* Set process priority to medium-low */
1439 prio = 3;
1440 break;
1441 case 2:
1442 /* Set process priority to normal */
1443 prio = 4;
1444 break;
1445 #if !defined(CONFIG_USER_ONLY)
1446 case 31:
1447 if (!ctx->pr) {
1448 /* Set process priority to very low */
1449 prio = 1;
1450 }
1451 break;
1452 case 5:
1453 if (!ctx->pr) {
1454 /* Set process priority to medium-hight */
1455 prio = 5;
1456 }
1457 break;
1458 case 3:
1459 if (!ctx->pr) {
1460 /* Set process priority to high */
1461 prio = 6;
1462 }
1463 break;
1464 case 7:
1465 if (ctx->hv && !ctx->pr) {
1466 /* Set process priority to very high */
1467 prio = 7;
1468 }
1469 break;
1470 #endif
1471 default:
1472 /* nop */
1473 break;
1474 }
1475 if (prio) {
1476 TCGv t0 = tcg_temp_new();
1477 gen_load_spr(t0, SPR_PPR);
1478 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1479 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1480 gen_store_spr(SPR_PPR, t0);
1481 tcg_temp_free(t0);
1482 /* Pause us out of TCG otherwise spin loops with smt_low
1483 * eat too much CPU and the kernel hangs
1484 */
1485 #if !defined(CONFIG_USER_ONLY)
1486 gen_pause(ctx);
1487 #endif
1488 }
1489 #endif
1490 }
1491 }
1492 /* orc & orc. */
1493 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1494
1495 /* xor & xor. */
1496 static void gen_xor(DisasContext *ctx)
1497 {
1498 /* Optimisation for "set to zero" case */
1499 if (rS(ctx->opcode) != rB(ctx->opcode))
1500 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1501 else
1502 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1503 if (unlikely(Rc(ctx->opcode) != 0))
1504 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1505 }
1506
1507 /* ori */
1508 static void gen_ori(DisasContext *ctx)
1509 {
1510 target_ulong uimm = UIMM(ctx->opcode);
1511
1512 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1513 return;
1514 }
1515 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1516 }
1517
1518 /* oris */
1519 static void gen_oris(DisasContext *ctx)
1520 {
1521 target_ulong uimm = UIMM(ctx->opcode);
1522
1523 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1524 /* NOP */
1525 return;
1526 }
1527 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1528 }
1529
1530 /* xori */
1531 static void gen_xori(DisasContext *ctx)
1532 {
1533 target_ulong uimm = UIMM(ctx->opcode);
1534
1535 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1536 /* NOP */
1537 return;
1538 }
1539 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1540 }
1541
1542 /* xoris */
1543 static void gen_xoris(DisasContext *ctx)
1544 {
1545 target_ulong uimm = UIMM(ctx->opcode);
1546
1547 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1548 /* NOP */
1549 return;
1550 }
1551 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1552 }
1553
1554 /* popcntb : PowerPC 2.03 specification */
1555 static void gen_popcntb(DisasContext *ctx)
1556 {
1557 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1558 }
1559
1560 static void gen_popcntw(DisasContext *ctx)
1561 {
1562 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1563 }
1564
1565 #if defined(TARGET_PPC64)
1566 /* popcntd: PowerPC 2.06 specification */
1567 static void gen_popcntd(DisasContext *ctx)
1568 {
1569 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1570 }
1571 #endif
1572
1573 /* prtyw: PowerPC 2.05 specification */
1574 static void gen_prtyw(DisasContext *ctx)
1575 {
1576 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1577 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1578 TCGv t0 = tcg_temp_new();
1579 tcg_gen_shri_tl(t0, rs, 16);
1580 tcg_gen_xor_tl(ra, rs, t0);
1581 tcg_gen_shri_tl(t0, ra, 8);
1582 tcg_gen_xor_tl(ra, ra, t0);
1583 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1584 tcg_temp_free(t0);
1585 }
1586
1587 #if defined(TARGET_PPC64)
1588 /* prtyd: PowerPC 2.05 specification */
1589 static void gen_prtyd(DisasContext *ctx)
1590 {
1591 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1592 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1593 TCGv t0 = tcg_temp_new();
1594 tcg_gen_shri_tl(t0, rs, 32);
1595 tcg_gen_xor_tl(ra, rs, t0);
1596 tcg_gen_shri_tl(t0, ra, 16);
1597 tcg_gen_xor_tl(ra, ra, t0);
1598 tcg_gen_shri_tl(t0, ra, 8);
1599 tcg_gen_xor_tl(ra, ra, t0);
1600 tcg_gen_andi_tl(ra, ra, 1);
1601 tcg_temp_free(t0);
1602 }
1603 #endif
1604
1605 #if defined(TARGET_PPC64)
1606 /* bpermd */
1607 static void gen_bpermd(DisasContext *ctx)
1608 {
1609 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1610 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1611 }
1612 #endif
1613
1614 #if defined(TARGET_PPC64)
1615 /* extsw & extsw. */
1616 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1617
1618 /* cntlzd */
1619 static void gen_cntlzd(DisasContext *ctx)
1620 {
1621 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1622 if (unlikely(Rc(ctx->opcode) != 0))
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625 #endif
1626
1627 /*** Integer rotate ***/
1628
1629 /* rlwimi & rlwimi. */
1630 static void gen_rlwimi(DisasContext *ctx)
1631 {
1632 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1633 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1634 uint32_t sh = SH(ctx->opcode);
1635 uint32_t mb = MB(ctx->opcode);
1636 uint32_t me = ME(ctx->opcode);
1637
1638 if (sh == (31-me) && mb <= me) {
1639 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1640 } else {
1641 target_ulong mask;
1642 TCGv t1;
1643
1644 #if defined(TARGET_PPC64)
1645 mb += 32;
1646 me += 32;
1647 #endif
1648 mask = MASK(mb, me);
1649
1650 t1 = tcg_temp_new();
1651 if (mask <= 0xffffffffu) {
1652 TCGv_i32 t0 = tcg_temp_new_i32();
1653 tcg_gen_trunc_tl_i32(t0, t_rs);
1654 tcg_gen_rotli_i32(t0, t0, sh);
1655 tcg_gen_extu_i32_tl(t1, t0);
1656 tcg_temp_free_i32(t0);
1657 } else {
1658 #if defined(TARGET_PPC64)
1659 tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
1660 tcg_gen_rotli_i64(t1, t1, sh);
1661 #else
1662 g_assert_not_reached();
1663 #endif
1664 }
1665
1666 tcg_gen_andi_tl(t1, t1, mask);
1667 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1668 tcg_gen_or_tl(t_ra, t_ra, t1);
1669 tcg_temp_free(t1);
1670 }
1671 if (unlikely(Rc(ctx->opcode) != 0)) {
1672 gen_set_Rc0(ctx, t_ra);
1673 }
1674 }
1675
1676 /* rlwinm & rlwinm. */
1677 static void gen_rlwinm(DisasContext *ctx)
1678 {
1679 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1680 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1681 uint32_t sh = SH(ctx->opcode);
1682 uint32_t mb = MB(ctx->opcode);
1683 uint32_t me = ME(ctx->opcode);
1684
1685 if (mb == 0 && me == (31 - sh)) {
1686 tcg_gen_shli_tl(t_ra, t_rs, sh);
1687 tcg_gen_ext32u_tl(t_ra, t_ra);
1688 } else if (sh != 0 && me == 31 && sh == (32 - mb)) {
1689 tcg_gen_ext32u_tl(t_ra, t_rs);
1690 tcg_gen_shri_tl(t_ra, t_ra, mb);
1691 } else {
1692 target_ulong mask;
1693 #if defined(TARGET_PPC64)
1694 mb += 32;
1695 me += 32;
1696 #endif
1697 mask = MASK(mb, me);
1698
1699 if (mask <= 0xffffffffu) {
1700 TCGv_i32 t0 = tcg_temp_new_i32();
1701 tcg_gen_trunc_tl_i32(t0, t_rs);
1702 tcg_gen_rotli_i32(t0, t0, sh);
1703 tcg_gen_andi_i32(t0, t0, mask);
1704 tcg_gen_extu_i32_tl(t_ra, t0);
1705 tcg_temp_free_i32(t0);
1706 } else {
1707 #if defined(TARGET_PPC64)
1708 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1709 tcg_gen_rotli_i64(t_ra, t_ra, sh);
1710 tcg_gen_andi_i64(t_ra, t_ra, mask);
1711 #else
1712 g_assert_not_reached();
1713 #endif
1714 }
1715 }
1716 if (unlikely(Rc(ctx->opcode) != 0)) {
1717 gen_set_Rc0(ctx, t_ra);
1718 }
1719 }
1720
1721 /* rlwnm & rlwnm. */
1722 static void gen_rlwnm(DisasContext *ctx)
1723 {
1724 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1725 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1726 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1727 uint32_t mb = MB(ctx->opcode);
1728 uint32_t me = ME(ctx->opcode);
1729 target_ulong mask;
1730
1731 #if defined(TARGET_PPC64)
1732 mb += 32;
1733 me += 32;
1734 #endif
1735 mask = MASK(mb, me);
1736
1737 if (mask <= 0xffffffffu) {
1738 TCGv_i32 t0 = tcg_temp_new_i32();
1739 TCGv_i32 t1 = tcg_temp_new_i32();
1740 tcg_gen_trunc_tl_i32(t0, t_rb);
1741 tcg_gen_trunc_tl_i32(t1, t_rs);
1742 tcg_gen_andi_i32(t0, t0, 0x1f);
1743 tcg_gen_rotl_i32(t1, t1, t0);
1744 tcg_gen_extu_i32_tl(t_ra, t1);
1745 tcg_temp_free_i32(t0);
1746 tcg_temp_free_i32(t1);
1747 } else {
1748 #if defined(TARGET_PPC64)
1749 TCGv_i64 t0 = tcg_temp_new_i64();
1750 tcg_gen_andi_i64(t0, t_rb, 0x1f);
1751 tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
1752 tcg_gen_rotl_i64(t_ra, t_ra, t0);
1753 tcg_temp_free_i64(t0);
1754 #else
1755 g_assert_not_reached();
1756 #endif
1757 }
1758
1759 tcg_gen_andi_tl(t_ra, t_ra, mask);
1760
1761 if (unlikely(Rc(ctx->opcode) != 0)) {
1762 gen_set_Rc0(ctx, t_ra);
1763 }
1764 }
1765
1766 #if defined(TARGET_PPC64)
1767 #define GEN_PPC64_R2(name, opc1, opc2) \
1768 static void glue(gen_, name##0)(DisasContext *ctx) \
1769 { \
1770 gen_##name(ctx, 0); \
1771 } \
1772 \
1773 static void glue(gen_, name##1)(DisasContext *ctx) \
1774 { \
1775 gen_##name(ctx, 1); \
1776 }
1777 #define GEN_PPC64_R4(name, opc1, opc2) \
1778 static void glue(gen_, name##0)(DisasContext *ctx) \
1779 { \
1780 gen_##name(ctx, 0, 0); \
1781 } \
1782 \
1783 static void glue(gen_, name##1)(DisasContext *ctx) \
1784 { \
1785 gen_##name(ctx, 0, 1); \
1786 } \
1787 \
1788 static void glue(gen_, name##2)(DisasContext *ctx) \
1789 { \
1790 gen_##name(ctx, 1, 0); \
1791 } \
1792 \
1793 static void glue(gen_, name##3)(DisasContext *ctx) \
1794 { \
1795 gen_##name(ctx, 1, 1); \
1796 }
1797
1798 static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh)
1799 {
1800 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1801 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1802
1803 if (sh != 0 && mb == 0 && me == (63 - sh)) {
1804 tcg_gen_shli_tl(t_ra, t_rs, sh);
1805 } else if (sh != 0 && me == 63 && sh == (64 - mb)) {
1806 tcg_gen_shri_tl(t_ra, t_rs, mb);
1807 } else {
1808 tcg_gen_rotli_tl(t_ra, t_rs, sh);
1809 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1810 }
1811 if (unlikely(Rc(ctx->opcode) != 0)) {
1812 gen_set_Rc0(ctx, t_ra);
1813 }
1814 }
1815
1816 /* rldicl - rldicl. */
1817 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1818 {
1819 uint32_t sh, mb;
1820
1821 sh = SH(ctx->opcode) | (shn << 5);
1822 mb = MB(ctx->opcode) | (mbn << 5);
1823 gen_rldinm(ctx, mb, 63, sh);
1824 }
1825 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1826
1827 /* rldicr - rldicr. */
1828 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1829 {
1830 uint32_t sh, me;
1831
1832 sh = SH(ctx->opcode) | (shn << 5);
1833 me = MB(ctx->opcode) | (men << 5);
1834 gen_rldinm(ctx, 0, me, sh);
1835 }
1836 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1837
1838 /* rldic - rldic. */
1839 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1840 {
1841 uint32_t sh, mb;
1842
1843 sh = SH(ctx->opcode) | (shn << 5);
1844 mb = MB(ctx->opcode) | (mbn << 5);
1845 gen_rldinm(ctx, mb, 63 - sh, sh);
1846 }
1847 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1848
1849 static void gen_rldnm(DisasContext *ctx, int mb, int me)
1850 {
1851 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1852 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1853 TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
1854 TCGv t0;
1855
1856 t0 = tcg_temp_new();
1857 tcg_gen_andi_tl(t0, t_rb, 0x3f);
1858 tcg_gen_rotl_tl(t_ra, t_rs, t0);
1859 tcg_temp_free(t0);
1860
1861 tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me));
1862 if (unlikely(Rc(ctx->opcode) != 0)) {
1863 gen_set_Rc0(ctx, t_ra);
1864 }
1865 }
1866
1867 /* rldcl - rldcl. */
1868 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1869 {
1870 uint32_t mb;
1871
1872 mb = MB(ctx->opcode) | (mbn << 5);
1873 gen_rldnm(ctx, mb, 63);
1874 }
1875 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1876
1877 /* rldcr - rldcr. */
1878 static inline void gen_rldcr(DisasContext *ctx, int men)
1879 {
1880 uint32_t me;
1881
1882 me = MB(ctx->opcode) | (men << 5);
1883 gen_rldnm(ctx, 0, me);
1884 }
1885 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1886
1887 /* rldimi - rldimi. */
1888 static void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1889 {
1890 TCGv t_ra = cpu_gpr[rA(ctx->opcode)];
1891 TCGv t_rs = cpu_gpr[rS(ctx->opcode)];
1892 uint32_t sh = SH(ctx->opcode) | (shn << 5);
1893 uint32_t mb = MB(ctx->opcode) | (mbn << 5);
1894 uint32_t me = 63 - sh;
1895
1896 if (mb <= me) {
1897 tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
1898 } else {
1899 target_ulong mask = MASK(mb, me);
1900 TCGv t1 = tcg_temp_new();
1901
1902 tcg_gen_rotli_tl(t1, t_rs, sh);
1903 tcg_gen_andi_tl(t1, t1, mask);
1904 tcg_gen_andi_tl(t_ra, t_ra, ~mask);
1905 tcg_gen_or_tl(t_ra, t_ra, t1);
1906 tcg_temp_free(t1);
1907 }
1908 if (unlikely(Rc(ctx->opcode) != 0)) {
1909 gen_set_Rc0(ctx, t_ra);
1910 }
1911 }
1912 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1913 #endif
1914
1915 /*** Integer shift ***/
1916
1917 /* slw & slw. */
1918 static void gen_slw(DisasContext *ctx)
1919 {
1920 TCGv t0, t1;
1921
1922 t0 = tcg_temp_new();
1923 /* AND rS with a mask that is 0 when rB >= 0x20 */
1924 #if defined(TARGET_PPC64)
1925 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1926 tcg_gen_sari_tl(t0, t0, 0x3f);
1927 #else
1928 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1929 tcg_gen_sari_tl(t0, t0, 0x1f);
1930 #endif
1931 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1932 t1 = tcg_temp_new();
1933 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1934 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1935 tcg_temp_free(t1);
1936 tcg_temp_free(t0);
1937 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1938 if (unlikely(Rc(ctx->opcode) != 0))
1939 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1940 }
1941
1942 /* sraw & sraw. */
1943 static void gen_sraw(DisasContext *ctx)
1944 {
1945 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1946 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1947 if (unlikely(Rc(ctx->opcode) != 0))
1948 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1949 }
1950
1951 /* srawi & srawi. */
1952 static void gen_srawi(DisasContext *ctx)
1953 {
1954 int sh = SH(ctx->opcode);
1955 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1956 TCGv src = cpu_gpr[rS(ctx->opcode)];
1957 if (sh == 0) {
1958 tcg_gen_ext32s_tl(dst, src);
1959 tcg_gen_movi_tl(cpu_ca, 0);
1960 } else {
1961 TCGv t0;
1962 tcg_gen_ext32s_tl(dst, src);
1963 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1964 t0 = tcg_temp_new();
1965 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1966 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1967 tcg_temp_free(t0);
1968 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1969 tcg_gen_sari_tl(dst, dst, sh);
1970 }
1971 if (unlikely(Rc(ctx->opcode) != 0)) {
1972 gen_set_Rc0(ctx, dst);
1973 }
1974 }
1975
1976 /* srw & srw. */
1977 static void gen_srw(DisasContext *ctx)
1978 {
1979 TCGv t0, t1;
1980
1981 t0 = tcg_temp_new();
1982 /* AND rS with a mask that is 0 when rB >= 0x20 */
1983 #if defined(TARGET_PPC64)
1984 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1985 tcg_gen_sari_tl(t0, t0, 0x3f);
1986 #else
1987 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1988 tcg_gen_sari_tl(t0, t0, 0x1f);
1989 #endif
1990 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1991 tcg_gen_ext32u_tl(t0, t0);
1992 t1 = tcg_temp_new();
1993 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1994 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1995 tcg_temp_free(t1);
1996 tcg_temp_free(t0);
1997 if (unlikely(Rc(ctx->opcode) != 0))
1998 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1999 }
2000
2001 #if defined(TARGET_PPC64)
2002 /* sld & sld. */
2003 static void gen_sld(DisasContext *ctx)
2004 {
2005 TCGv t0, t1;
2006
2007 t0 = tcg_temp_new();
2008 /* AND rS with a mask that is 0 when rB >= 0x40 */
2009 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2010 tcg_gen_sari_tl(t0, t0, 0x3f);
2011 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2012 t1 = tcg_temp_new();
2013 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2014 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2015 tcg_temp_free(t1);
2016 tcg_temp_free(t0);
2017 if (unlikely(Rc(ctx->opcode) != 0))
2018 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2019 }
2020
2021 /* srad & srad. */
2022 static void gen_srad(DisasContext *ctx)
2023 {
2024 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2025 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2026 if (unlikely(Rc(ctx->opcode) != 0))
2027 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2028 }
2029 /* sradi & sradi. */
2030 static inline void gen_sradi(DisasContext *ctx, int n)
2031 {
2032 int sh = SH(ctx->opcode) + (n << 5);
2033 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2034 TCGv src = cpu_gpr[rS(ctx->opcode)];
2035 if (sh == 0) {
2036 tcg_gen_mov_tl(dst, src);
2037 tcg_gen_movi_tl(cpu_ca, 0);
2038 } else {
2039 TCGv t0;
2040 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2041 t0 = tcg_temp_new();
2042 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2043 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2044 tcg_temp_free(t0);
2045 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2046 tcg_gen_sari_tl(dst, src, sh);
2047 }
2048 if (unlikely(Rc(ctx->opcode) != 0)) {
2049 gen_set_Rc0(ctx, dst);
2050 }
2051 }
2052
2053 static void gen_sradi0(DisasContext *ctx)
2054 {
2055 gen_sradi(ctx, 0);
2056 }
2057
2058 static void gen_sradi1(DisasContext *ctx)
2059 {
2060 gen_sradi(ctx, 1);
2061 }
2062
2063 /* srd & srd. */
2064 static void gen_srd(DisasContext *ctx)
2065 {
2066 TCGv t0, t1;
2067
2068 t0 = tcg_temp_new();
2069 /* AND rS with a mask that is 0 when rB >= 0x40 */
2070 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2071 tcg_gen_sari_tl(t0, t0, 0x3f);
2072 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2073 t1 = tcg_temp_new();
2074 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2075 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2076 tcg_temp_free(t1);
2077 tcg_temp_free(t0);
2078 if (unlikely(Rc(ctx->opcode) != 0))
2079 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2080 }
2081 #endif
2082
2083 #if defined(TARGET_PPC64)
2084 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2085 {
2086 TCGv_i32 tmp = tcg_temp_new_i32();
2087 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2088 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2089 tcg_temp_free_i32(tmp);
2090 }
2091 #else
2092 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2093 {
2094 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2095 }
2096 #endif
2097
2098 /*** Floating-Point arithmetic ***/
2099 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2100 static void gen_f##name(DisasContext *ctx) \
2101 { \
2102 if (unlikely(!ctx->fpu_enabled)) { \
2103 gen_exception(ctx, POWERPC_EXCP_FPU); \
2104 return; \
2105 } \
2106 /* NIP cannot be restored if the memory exception comes from an helper */ \
2107 gen_update_nip(ctx, ctx->nip - 4); \
2108 gen_reset_fpstatus(); \
2109 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2110 cpu_fpr[rA(ctx->opcode)], \
2111 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2112 if (isfloat) { \
2113 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2114 cpu_fpr[rD(ctx->opcode)]); \
2115 } \
2116 if (set_fprf) { \
2117 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2118 } \
2119 if (unlikely(Rc(ctx->opcode) != 0)) { \
2120 gen_set_cr1_from_fpscr(ctx); \
2121 } \
2122 }
2123
2124 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2125 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2126 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2127
2128 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2129 static void gen_f##name(DisasContext *ctx) \
2130 { \
2131 if (unlikely(!ctx->fpu_enabled)) { \
2132 gen_exception(ctx, POWERPC_EXCP_FPU); \
2133 return; \
2134 } \
2135 /* NIP cannot be restored if the memory exception comes from an helper */ \
2136 gen_update_nip(ctx, ctx->nip - 4); \
2137 gen_reset_fpstatus(); \
2138 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2139 cpu_fpr[rA(ctx->opcode)], \
2140 cpu_fpr[rB(ctx->opcode)]); \
2141 if (isfloat) { \
2142 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2143 cpu_fpr[rD(ctx->opcode)]); \
2144 } \
2145 if (set_fprf) { \
2146 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2147 } \
2148 if (unlikely(Rc(ctx->opcode) != 0)) { \
2149 gen_set_cr1_from_fpscr(ctx); \
2150 } \
2151 }
2152 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2153 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2154 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2155
2156 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2157 static void gen_f##name(DisasContext *ctx) \
2158 { \
2159 if (unlikely(!ctx->fpu_enabled)) { \
2160 gen_exception(ctx, POWERPC_EXCP_FPU); \
2161 return; \
2162 } \
2163 /* NIP cannot be restored if the memory exception comes from an helper */ \
2164 gen_update_nip(ctx, ctx->nip - 4); \
2165 gen_reset_fpstatus(); \
2166 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2167 cpu_fpr[rA(ctx->opcode)], \
2168 cpu_fpr[rC(ctx->opcode)]); \
2169 if (isfloat) { \
2170 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2171 cpu_fpr[rD(ctx->opcode)]); \
2172 } \
2173 if (set_fprf) { \
2174 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2175 } \
2176 if (unlikely(Rc(ctx->opcode) != 0)) { \
2177 gen_set_cr1_from_fpscr(ctx); \
2178 } \
2179 }
2180 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2181 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2182 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2183
2184 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2185 static void gen_f##name(DisasContext *ctx) \
2186 { \
2187 if (unlikely(!ctx->fpu_enabled)) { \
2188 gen_exception(ctx, POWERPC_EXCP_FPU); \
2189 return; \
2190 } \
2191 /* NIP cannot be restored if the memory exception comes from an helper */ \
2192 gen_update_nip(ctx, ctx->nip - 4); \
2193 gen_reset_fpstatus(); \
2194 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2195 cpu_fpr[rB(ctx->opcode)]); \
2196 if (set_fprf) { \
2197 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2198 } \
2199 if (unlikely(Rc(ctx->opcode) != 0)) { \
2200 gen_set_cr1_from_fpscr(ctx); \
2201 } \
2202 }
2203
2204 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2205 static void gen_f##name(DisasContext *ctx) \
2206 { \
2207 if (unlikely(!ctx->fpu_enabled)) { \
2208 gen_exception(ctx, POWERPC_EXCP_FPU); \
2209 return; \
2210 } \
2211 /* NIP cannot be restored if the memory exception comes from an helper */ \
2212 gen_update_nip(ctx, ctx->nip - 4); \
2213 gen_reset_fpstatus(); \
2214 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2215 cpu_fpr[rB(ctx->opcode)]); \
2216 if (set_fprf) { \
2217 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2218 } \
2219 if (unlikely(Rc(ctx->opcode) != 0)) { \
2220 gen_set_cr1_from_fpscr(ctx); \
2221 } \
2222 }
2223
2224 /* fadd - fadds */
2225 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2226 /* fdiv - fdivs */
2227 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2228 /* fmul - fmuls */
2229 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2230
2231 /* fre */
2232 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2233
2234 /* fres */
2235 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2236
2237 /* frsqrte */
2238 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2239
2240 /* frsqrtes */
2241 static void gen_frsqrtes(DisasContext *ctx)
2242 {
2243 if (unlikely(!ctx->fpu_enabled)) {
2244 gen_exception(ctx, POWERPC_EXCP_FPU);
2245 return;
2246 }
2247 /* NIP cannot be restored if the memory exception comes from an helper */
2248 gen_update_nip(ctx, ctx->nip - 4);
2249 gen_reset_fpstatus();
2250 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2251 cpu_fpr[rB(ctx->opcode)]);
2252 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2253 cpu_fpr[rD(ctx->opcode)]);
2254 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2255 if (unlikely(Rc(ctx->opcode) != 0)) {
2256 gen_set_cr1_from_fpscr(ctx);
2257 }
2258 }
2259
2260 /* fsel */
2261 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2262 /* fsub - fsubs */
2263 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2264 /* Optional: */
2265
2266 /* fsqrt */
2267 static void gen_fsqrt(DisasContext *ctx)
2268 {
2269 if (unlikely(!ctx->fpu_enabled)) {
2270 gen_exception(ctx, POWERPC_EXCP_FPU);
2271 return;
2272 }
2273 /* NIP cannot be restored if the memory exception comes from an helper */
2274 gen_update_nip(ctx, ctx->nip - 4);
2275 gen_reset_fpstatus();
2276 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2277 cpu_fpr[rB(ctx->opcode)]);
2278 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2279 if (unlikely(Rc(ctx->opcode) != 0)) {
2280 gen_set_cr1_from_fpscr(ctx);
2281 }
2282 }
2283
2284 static void gen_fsqrts(DisasContext *ctx)
2285 {
2286 if (unlikely(!ctx->fpu_enabled)) {
2287 gen_exception(ctx, POWERPC_EXCP_FPU);
2288 return;
2289 }
2290 /* NIP cannot be restored if the memory exception comes from an helper */
2291 gen_update_nip(ctx, ctx->nip - 4);
2292 gen_reset_fpstatus();
2293 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2294 cpu_fpr[rB(ctx->opcode)]);
2295 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2296 cpu_fpr[rD(ctx->opcode)]);
2297 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2298 if (unlikely(Rc(ctx->opcode) != 0)) {
2299 gen_set_cr1_from_fpscr(ctx);
2300 }
2301 }
2302
2303 /*** Floating-Point multiply-and-add ***/
2304 /* fmadd - fmadds */
2305 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2306 /* fmsub - fmsubs */
2307 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2308 /* fnmadd - fnmadds */
2309 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2310 /* fnmsub - fnmsubs */
2311 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2312
2313 /*** Floating-Point round & convert ***/
2314 /* fctiw */
2315 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2316 /* fctiwu */
2317 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2318 /* fctiwz */
2319 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2320 /* fctiwuz */
2321 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2322 /* frsp */
2323 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2324 /* fcfid */
2325 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2326 /* fcfids */
2327 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2328 /* fcfidu */
2329 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2330 /* fcfidus */
2331 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2332 /* fctid */
2333 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2334 /* fctidu */
2335 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2336 /* fctidz */
2337 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2338 /* fctidu */
2339 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2340
2341 /* frin */
2342 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2343 /* friz */
2344 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2345 /* frip */
2346 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2347 /* frim */
2348 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2349
2350 static void gen_ftdiv(DisasContext *ctx)
2351 {
2352 if (unlikely(!ctx->fpu_enabled)) {
2353 gen_exception(ctx, POWERPC_EXCP_FPU);
2354 return;
2355 }
2356 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2357 cpu_fpr[rB(ctx->opcode)]);
2358 }
2359
2360 static void gen_ftsqrt(DisasContext *ctx)
2361 {
2362 if (unlikely(!ctx->fpu_enabled)) {
2363 gen_exception(ctx, POWERPC_EXCP_FPU);
2364 return;
2365 }
2366 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2367 }
2368
2369
2370
2371 /*** Floating-Point compare ***/
2372
2373 /* fcmpo */
2374 static void gen_fcmpo(DisasContext *ctx)
2375 {
2376 TCGv_i32 crf;
2377 if (unlikely(!ctx->fpu_enabled)) {
2378 gen_exception(ctx, POWERPC_EXCP_FPU);
2379 return;
2380 }
2381 /* NIP cannot be restored if the memory exception comes from an helper */
2382 gen_update_nip(ctx, ctx->nip - 4);
2383 gen_reset_fpstatus();
2384 crf = tcg_const_i32(crfD(ctx->opcode));
2385 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2386 cpu_fpr[rB(ctx->opcode)], crf);
2387 tcg_temp_free_i32(crf);
2388 gen_helper_float_check_status(cpu_env);
2389 }
2390
2391 /* fcmpu */
2392 static void gen_fcmpu(DisasContext *ctx)
2393 {
2394 TCGv_i32 crf;
2395 if (unlikely(!ctx->fpu_enabled)) {
2396 gen_exception(ctx, POWERPC_EXCP_FPU);
2397 return;
2398 }
2399 /* NIP cannot be restored if the memory exception comes from an helper */
2400 gen_update_nip(ctx, ctx->nip - 4);
2401 gen_reset_fpstatus();
2402 crf = tcg_const_i32(crfD(ctx->opcode));
2403 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2404 cpu_fpr[rB(ctx->opcode)], crf);
2405 tcg_temp_free_i32(crf);
2406 gen_helper_float_check_status(cpu_env);
2407 }
2408
2409 /*** Floating-point move ***/
2410 /* fabs */
2411 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2412 static void gen_fabs(DisasContext *ctx)
2413 {
2414 if (unlikely(!ctx->fpu_enabled)) {
2415 gen_exception(ctx, POWERPC_EXCP_FPU);
2416 return;
2417 }
2418 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2419 ~(1ULL << 63));
2420 if (unlikely(Rc(ctx->opcode))) {
2421 gen_set_cr1_from_fpscr(ctx);
2422 }
2423 }
2424
2425 /* fmr - fmr. */
2426 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2427 static void gen_fmr(DisasContext *ctx)
2428 {
2429 if (unlikely(!ctx->fpu_enabled)) {
2430 gen_exception(ctx, POWERPC_EXCP_FPU);
2431 return;
2432 }
2433 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2434 if (unlikely(Rc(ctx->opcode))) {
2435 gen_set_cr1_from_fpscr(ctx);
2436 }
2437 }
2438
2439 /* fnabs */
2440 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2441 static void gen_fnabs(DisasContext *ctx)
2442 {
2443 if (unlikely(!ctx->fpu_enabled)) {
2444 gen_exception(ctx, POWERPC_EXCP_FPU);
2445 return;
2446 }
2447 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2448 1ULL << 63);
2449 if (unlikely(Rc(ctx->opcode))) {
2450 gen_set_cr1_from_fpscr(ctx);
2451 }
2452 }
2453
2454 /* fneg */
2455 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2456 static void gen_fneg(DisasContext *ctx)
2457 {
2458 if (unlikely(!ctx->fpu_enabled)) {
2459 gen_exception(ctx, POWERPC_EXCP_FPU);
2460 return;
2461 }
2462 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2463 1ULL << 63);
2464 if (unlikely(Rc(ctx->opcode))) {
2465 gen_set_cr1_from_fpscr(ctx);
2466 }
2467 }
2468
2469 /* fcpsgn: PowerPC 2.05 specification */
2470 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2471 static void gen_fcpsgn(DisasContext *ctx)
2472 {
2473 if (unlikely(!ctx->fpu_enabled)) {
2474 gen_exception(ctx, POWERPC_EXCP_FPU);
2475 return;
2476 }
2477 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2478 cpu_fpr[rB(ctx->opcode)], 0, 63);
2479 if (unlikely(Rc(ctx->opcode))) {
2480 gen_set_cr1_from_fpscr(ctx);
2481 }
2482 }
2483
2484 static void gen_fmrgew(DisasContext *ctx)
2485 {
2486 TCGv_i64 b0;
2487 if (unlikely(!ctx->fpu_enabled)) {
2488 gen_exception(ctx, POWERPC_EXCP_FPU);
2489 return;
2490 }
2491 b0 = tcg_temp_new_i64();
2492 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2493 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2494 b0, 0, 32);
2495 tcg_temp_free_i64(b0);
2496 }
2497
2498 static void gen_fmrgow(DisasContext *ctx)
2499 {
2500 if (unlikely(!ctx->fpu_enabled)) {
2501 gen_exception(ctx, POWERPC_EXCP_FPU);
2502 return;
2503 }
2504 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2505 cpu_fpr[rB(ctx->opcode)],
2506 cpu_fpr[rA(ctx->opcode)],
2507 32, 32);
2508 }
2509
2510 /*** Floating-Point status & ctrl register ***/
2511
2512 /* mcrfs */
2513 static void gen_mcrfs(DisasContext *ctx)
2514 {
2515 TCGv tmp = tcg_temp_new();
2516 TCGv_i32 tmask;
2517 TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2518 int bfa;
2519 int nibble;
2520 int shift;
2521
2522 if (unlikely(!ctx->fpu_enabled)) {
2523 gen_exception(ctx, POWERPC_EXCP_FPU);
2524 return;
2525 }
2526 bfa = crfS(ctx->opcode);
2527 nibble = 7 - bfa;
2528 shift = 4 * nibble;
2529 tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2530 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2531 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2532 tcg_temp_free(tmp);
2533 tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2534 /* Only the exception bits (including FX) should be cleared if read */
2535 tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2536 /* FEX and VX need to be updated, so don't set fpscr directly */
2537 tmask = tcg_const_i32(1 << nibble);
2538 gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2539 tcg_temp_free_i32(tmask);
2540 tcg_temp_free_i64(tnew_fpscr);
2541 }
2542
2543 /* mffs */
2544 static void gen_mffs(DisasContext *ctx)
2545 {
2546 if (unlikely(!ctx->fpu_enabled)) {
2547 gen_exception(ctx, POWERPC_EXCP_FPU);
2548 return;
2549 }
2550 gen_reset_fpstatus();
2551 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2552 if (unlikely(Rc(ctx->opcode))) {
2553 gen_set_cr1_from_fpscr(ctx);
2554 }
2555 }
2556
2557 /* mtfsb0 */
2558 static void gen_mtfsb0(DisasContext *ctx)
2559 {
2560 uint8_t crb;
2561
2562 if (unlikely(!ctx->fpu_enabled)) {
2563 gen_exception(ctx, POWERPC_EXCP_FPU);
2564 return;
2565 }
2566 crb = 31 - crbD(ctx->opcode);
2567 gen_reset_fpstatus();
2568 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2569 TCGv_i32 t0;
2570 /* NIP cannot be restored if the memory exception comes from an helper */
2571 gen_update_nip(ctx, ctx->nip - 4);
2572 t0 = tcg_const_i32(crb);
2573 gen_helper_fpscr_clrbit(cpu_env, t0);
2574 tcg_temp_free_i32(t0);
2575 }
2576 if (unlikely(Rc(ctx->opcode) != 0)) {
2577 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2578 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2579 }
2580 }
2581
2582 /* mtfsb1 */
2583 static void gen_mtfsb1(DisasContext *ctx)
2584 {
2585 uint8_t crb;
2586
2587 if (unlikely(!ctx->fpu_enabled)) {
2588 gen_exception(ctx, POWERPC_EXCP_FPU);
2589 return;
2590 }
2591 crb = 31 - crbD(ctx->opcode);
2592 gen_reset_fpstatus();
2593 /* XXX: we pretend we can only do IEEE floating-point computations */
2594 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2595 TCGv_i32 t0;
2596 /* NIP cannot be restored if the memory exception comes from an helper */
2597 gen_update_nip(ctx, ctx->nip - 4);
2598 t0 = tcg_const_i32(crb);
2599 gen_helper_fpscr_setbit(cpu_env, t0);
2600 tcg_temp_free_i32(t0);
2601 }
2602 if (unlikely(Rc(ctx->opcode) != 0)) {
2603 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2604 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2605 }
2606 /* We can raise a differed exception */
2607 gen_helper_float_check_status(cpu_env);
2608 }
2609
2610 /* mtfsf */
2611 static void gen_mtfsf(DisasContext *ctx)
2612 {
2613 TCGv_i32 t0;
2614 int flm, l, w;
2615
2616 if (unlikely(!ctx->fpu_enabled)) {
2617 gen_exception(ctx, POWERPC_EXCP_FPU);
2618 return;
2619 }
2620 flm = FPFLM(ctx->opcode);
2621 l = FPL(ctx->opcode);
2622 w = FPW(ctx->opcode);
2623 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2624 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2625 return;
2626 }
2627 /* NIP cannot be restored if the memory exception comes from an helper */
2628 gen_update_nip(ctx, ctx->nip - 4);
2629 gen_reset_fpstatus();
2630 if (l) {
2631 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2632 } else {
2633 t0 = tcg_const_i32(flm << (w * 8));
2634 }
2635 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2636 tcg_temp_free_i32(t0);
2637 if (unlikely(Rc(ctx->opcode) != 0)) {
2638 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2639 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2640 }
2641 /* We can raise a differed exception */
2642 gen_helper_float_check_status(cpu_env);
2643 }
2644
2645 /* mtfsfi */
2646 static void gen_mtfsfi(DisasContext *ctx)
2647 {
2648 int bf, sh, w;
2649 TCGv_i64 t0;
2650 TCGv_i32 t1;
2651
2652 if (unlikely(!ctx->fpu_enabled)) {
2653 gen_exception(ctx, POWERPC_EXCP_FPU);
2654 return;
2655 }
2656 w = FPW(ctx->opcode);
2657 bf = FPBF(ctx->opcode);
2658 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2659 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2660 return;
2661 }
2662 sh = (8 * w) + 7 - bf;
2663 /* NIP cannot be restored if the memory exception comes from an helper */
2664 gen_update_nip(ctx, ctx->nip - 4);
2665 gen_reset_fpstatus();
2666 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2667 t1 = tcg_const_i32(1 << sh);
2668 gen_helper_store_fpscr(cpu_env, t0, t1);
2669 tcg_temp_free_i64(t0);
2670 tcg_temp_free_i32(t1);
2671 if (unlikely(Rc(ctx->opcode) != 0)) {
2672 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2673 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2674 }
2675 /* We can raise a differed exception */
2676 gen_helper_float_check_status(cpu_env);
2677 }
2678
2679 /*** Addressing modes ***/
2680 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2681 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2682 target_long maskl)
2683 {
2684 target_long simm = SIMM(ctx->opcode);
2685
2686 simm &= ~maskl;
2687 if (rA(ctx->opcode) == 0) {
2688 if (NARROW_MODE(ctx)) {
2689 simm = (uint32_t)simm;
2690 }
2691 tcg_gen_movi_tl(EA, simm);
2692 } else if (likely(simm != 0)) {
2693 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2694 if (NARROW_MODE(ctx)) {
2695 tcg_gen_ext32u_tl(EA, EA);
2696 }
2697 } else {
2698 if (NARROW_MODE(ctx)) {
2699 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2700 } else {
2701 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2702 }
2703 }
2704 }
2705
2706 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2707 {
2708 if (rA(ctx->opcode) == 0) {
2709 if (NARROW_MODE(ctx)) {
2710 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2711 } else {
2712 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2713 }
2714 } else {
2715 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2716 if (NARROW_MODE(ctx)) {
2717 tcg_gen_ext32u_tl(EA, EA);
2718 }
2719 }
2720 }
2721
2722 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2723 {
2724 if (rA(ctx->opcode) == 0) {
2725 tcg_gen_movi_tl(EA, 0);
2726 } else if (NARROW_MODE(ctx)) {
2727 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2728 } else {
2729 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2730 }
2731 }
2732
2733 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2734 target_long val)
2735 {
2736 tcg_gen_addi_tl(ret, arg1, val);
2737 if (NARROW_MODE(ctx)) {
2738 tcg_gen_ext32u_tl(ret, ret);
2739 }
2740 }
2741
2742 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2743 {
2744 TCGLabel *l1 = gen_new_label();
2745 TCGv t0 = tcg_temp_new();
2746 TCGv_i32 t1, t2;
2747 /* NIP cannot be restored if the memory exception comes from an helper */
2748 gen_update_nip(ctx, ctx->nip - 4);
2749 tcg_gen_andi_tl(t0, EA, mask);
2750 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2751 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2752 t2 = tcg_const_i32(0);
2753 gen_helper_raise_exception_err(cpu_env, t1, t2);
2754 tcg_temp_free_i32(t1);
2755 tcg_temp_free_i32(t2);
2756 gen_set_label(l1);
2757 tcg_temp_free(t0);
2758 }
2759
2760 /*** Integer load ***/
2761 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2762 {
2763 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2764 }
2765
2766 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2767 {
2768 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2769 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2770 }
2771
2772 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2773 {
2774 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2775 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2776 }
2777
2778 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2779 {
2780 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2781 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2782 }
2783
2784 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2785 {
2786 TCGv tmp = tcg_temp_new();
2787 gen_qemu_ld32u(ctx, tmp, addr);
2788 tcg_gen_extu_tl_i64(val, tmp);
2789 tcg_temp_free(tmp);
2790 }
2791
2792 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2793 {
2794 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2795 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2796 }
2797
2798 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2799 {
2800 TCGv tmp = tcg_temp_new();
2801 gen_qemu_ld32s(ctx, tmp, addr);
2802 tcg_gen_ext_tl_i64(val, tmp);
2803 tcg_temp_free(tmp);
2804 }
2805
2806 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2807 {
2808 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2809 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2810 }
2811
2812 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2813 {
2814 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2815 }
2816
2817 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2818 {
2819 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2820 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2821 }
2822
2823 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2824 {
2825 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2826 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2827 }
2828
2829 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2830 {
2831 TCGv tmp = tcg_temp_new();
2832 tcg_gen_trunc_i64_tl(tmp, val);
2833 gen_qemu_st32(ctx, tmp, addr);
2834 tcg_temp_free(tmp);
2835 }
2836
2837 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2838 {
2839 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2840 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2841 }
2842
2843 #define GEN_LD(name, ldop, opc, type) \
2844 static void glue(gen_, name)(DisasContext *ctx) \
2845 { \
2846 TCGv EA; \
2847 gen_set_access_type(ctx, ACCESS_INT); \
2848 EA = tcg_temp_new(); \
2849 gen_addr_imm_index(ctx, EA, 0); \
2850 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2851 tcg_temp_free(EA); \
2852 }
2853
2854 #define GEN_LDU(name, ldop, opc, type) \
2855 static void glue(gen_, name##u)(DisasContext *ctx) \
2856 { \
2857 TCGv EA; \
2858 if (unlikely(rA(ctx->opcode) == 0 || \
2859 rA(ctx->opcode) == rD(ctx->opcode))) { \
2860 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2861 return; \
2862 } \
2863 gen_set_access_type(ctx, ACCESS_INT); \
2864 EA = tcg_temp_new(); \
2865 if (type == PPC_64B) \
2866 gen_addr_imm_index(ctx, EA, 0x03); \
2867 else \
2868 gen_addr_imm_index(ctx, EA, 0); \
2869 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2870 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2871 tcg_temp_free(EA); \
2872 }
2873
2874 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2875 static void glue(gen_, name##ux)(DisasContext *ctx) \
2876 { \
2877 TCGv EA; \
2878 if (unlikely(rA(ctx->opcode) == 0 || \
2879 rA(ctx->opcode) == rD(ctx->opcode))) { \
2880 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2881 return; \
2882 } \
2883 gen_set_access_type(ctx, ACCESS_INT); \
2884 EA = tcg_temp_new(); \
2885 gen_addr_reg_index(ctx, EA); \
2886 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2887 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2888 tcg_temp_free(EA); \
2889 }
2890
2891 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2892 static void glue(gen_, name##x)(DisasContext *ctx) \
2893 { \
2894 TCGv EA; \
2895 gen_set_access_type(ctx, ACCESS_INT); \
2896 EA = tcg_temp_new(); \
2897 gen_addr_reg_index(ctx, EA); \
2898 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2899 tcg_temp_free(EA); \
2900 }
2901 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2902 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2903
2904 #define GEN_LDS(name, ldop, op, type) \
2905 GEN_LD(name, ldop, op | 0x20, type); \
2906 GEN_LDU(name, ldop, op | 0x21, type); \
2907 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2908 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2909
2910 /* lbz lbzu lbzux lbzx */
2911 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2912 /* lha lhau lhaux lhax */
2913 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2914 /* lhz lhzu lhzux lhzx */
2915 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2916 /* lwz lwzu lwzux lwzx */
2917 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2918 #if defined(TARGET_PPC64)
2919 /* lwaux */
2920 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2921 /* lwax */
2922 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2923 /* ldux */
2924 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2925 /* ldx */
2926 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2927
2928 static void gen_ld(DisasContext *ctx)
2929 {
2930 TCGv EA;
2931 if (Rc(ctx->opcode)) {
2932 if (unlikely(rA(ctx->opcode) == 0 ||
2933 rA(ctx->opcode) == rD(ctx->opcode))) {
2934 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2935 return;
2936 }
2937 }
2938 gen_set_access_type(ctx, ACCESS_INT);
2939 EA = tcg_temp_new();
2940 gen_addr_imm_index(ctx, EA, 0x03);
2941 if (ctx->opcode & 0x02) {
2942 /* lwa (lwau is undefined) */
2943 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2944 } else {
2945 /* ld - ldu */
2946 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2947 }
2948 if (Rc(ctx->opcode))
2949 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2950 tcg_temp_free(EA);
2951 }
2952
2953 /* lq */
2954 static void gen_lq(DisasContext *ctx)
2955 {
2956 int ra, rd;
2957 TCGv EA;
2958
2959 /* lq is a legal user mode instruction starting in ISA 2.07 */
2960 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2961 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2962
2963 if (!legal_in_user_mode && ctx->pr) {
2964 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2965 return;
2966 }
2967
2968 if (!le_is_supported && ctx->le_mode) {
2969 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2970 return;
2971 }
2972
2973 ra = rA(ctx->opcode);
2974 rd = rD(ctx->opcode);
2975 if (unlikely((rd & 1) || rd == ra)) {
2976 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2977 return;
2978 }
2979
2980 gen_set_access_type(ctx, ACCESS_INT);
2981 EA = tcg_temp_new();
2982 gen_addr_imm_index(ctx, EA, 0x0F);
2983
2984 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2985 64-bit byteswap already. */
2986 if (unlikely(ctx->le_mode)) {
2987 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2988 gen_addr_add(ctx, EA, EA, 8);
2989 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2990 } else {
2991 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2992 gen_addr_add(ctx, EA, EA, 8);
2993 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2994 }
2995 tcg_temp_free(EA);
2996 }
2997 #endif
2998
2999 /*** Integer store ***/
3000 #define GEN_ST(name, stop, opc, type) \
3001 static void glue(gen_, name)(DisasContext *ctx) \
3002 { \
3003 TCGv EA; \
3004 gen_set_access_type(ctx, ACCESS_INT); \
3005 EA = tcg_temp_new(); \
3006 gen_addr_imm_index(ctx, EA, 0); \
3007 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3008 tcg_temp_free(EA); \
3009 }
3010
3011 #define GEN_STU(name, stop, opc, type) \
3012 static void glue(gen_, stop##u)(DisasContext *ctx) \
3013 { \
3014 TCGv EA; \
3015 if (unlikely(rA(ctx->opcode) == 0)) { \
3016 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3017 return; \
3018 } \
3019 gen_set_access_type(ctx, ACCESS_INT); \
3020 EA = tcg_temp_new(); \
3021 if (type == PPC_64B) \
3022 gen_addr_imm_index(ctx, EA, 0x03); \
3023 else \
3024 gen_addr_imm_index(ctx, EA, 0); \
3025 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3026 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3027 tcg_temp_free(EA); \
3028 }
3029
3030 #define GEN_STUX(name, stop, opc2, opc3, type) \
3031 static void glue(gen_, name##ux)(DisasContext *ctx) \
3032 { \
3033 TCGv EA; \
3034 if (unlikely(rA(ctx->opcode) == 0)) { \
3035 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3036 return; \
3037 } \
3038 gen_set_access_type(ctx, ACCESS_INT); \
3039 EA = tcg_temp_new(); \
3040 gen_addr_reg_index(ctx, EA); \
3041 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3042 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3043 tcg_temp_free(EA); \
3044 }
3045
3046 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3047 static void glue(gen_, name##x)(DisasContext *ctx) \
3048 { \
3049 TCGv EA; \
3050 gen_set_access_type(ctx, ACCESS_INT); \
3051 EA = tcg_temp_new(); \
3052 gen_addr_reg_index(ctx, EA); \
3053 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3054 tcg_temp_free(EA); \
3055 }
3056 #define GEN_STX(name, stop, opc2, opc3, type) \
3057 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3058
3059 #define GEN_STS(name, stop, op, type) \
3060 GEN_ST(name, stop, op | 0x20, type); \
3061 GEN_STU(name, stop, op | 0x21, type); \
3062 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3063 GEN_STX(name, stop, 0x17, op | 0x00, type)
3064
3065 /* stb stbu stbux stbx */
3066 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3067 /* sth sthu sthux sthx */
3068 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3069 /* stw stwu stwux stwx */
3070 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3071 #if defined(TARGET_PPC64)
3072 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3073 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3074
3075 static void gen_std(DisasContext *ctx)
3076 {
3077 int rs;
3078 TCGv EA;
3079
3080 rs = rS(ctx->opcode);
3081 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3082 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3083 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3084
3085 if (!(ctx->insns_flags & PPC_64BX)) {
3086 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3087 }
3088
3089 if (!legal_in_user_mode && ctx->pr) {
3090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3091 return;
3092 }
3093
3094 if (!le_is_supported && ctx->le_mode) {
3095 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3096 return;
3097 }
3098
3099 if (unlikely(rs & 1)) {
3100 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3101 return;
3102 }
3103 gen_set_access_type(ctx, ACCESS_INT);
3104 EA = tcg_temp_new();
3105 gen_addr_imm_index(ctx, EA, 0x03);
3106
3107 /* We only need to swap high and low halves. gen_qemu_st64 does
3108 necessary 64-bit byteswap already. */
3109 if (unlikely(ctx->le_mode)) {
3110 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3111 gen_addr_add(ctx, EA, EA, 8);
3112 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3113 } else {
3114 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3115 gen_addr_add(ctx, EA, EA, 8);
3116 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3117 }
3118 tcg_temp_free(EA);
3119 } else {
3120 /* std / stdu*/
3121 if (Rc(ctx->opcode)) {
3122 if (unlikely(rA(ctx->opcode) == 0)) {
3123 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3124 return;
3125 }
3126 }
3127 gen_set_access_type(ctx, ACCESS_INT);
3128 EA = tcg_temp_new();
3129 gen_addr_imm_index(ctx, EA, 0x03);
3130 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3131 if (Rc(ctx->opcode))
3132 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3133 tcg_temp_free(EA);
3134 }
3135 }
3136 #endif
3137 /*** Integer load and store with byte reverse ***/
3138
3139 /* lhbrx */
3140 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3141 {
3142 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3143 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3144 }
3145 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3146
3147 /* lwbrx */
3148 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3149 {
3150 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3151 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3152 }
3153 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3154
3155 #if defined(TARGET_PPC64)
3156 /* ldbrx */
3157 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3158 {
3159 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3160 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3161 }
3162 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3163 #endif /* TARGET_PPC64 */
3164
3165 /* sthbrx */
3166 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3167 {
3168 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3169 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3170 }
3171 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3172
3173 /* stwbrx */
3174 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3175 {
3176 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3177 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3178 }
3179 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3180
3181 #if defined(TARGET_PPC64)
3182 /* stdbrx */
3183 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3184 {
3185 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3186 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3187 }
3188 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3189 #endif /* TARGET_PPC64 */
3190
3191 /*** Integer load and store multiple ***/
3192
3193 /* lmw */
3194 static void gen_lmw(DisasContext *ctx)
3195 {
3196 TCGv t0;
3197 TCGv_i32 t1;
3198 gen_set_access_type(ctx, ACCESS_INT);
3199 /* NIP cannot be restored if the memory exception comes from an helper */
3200 gen_update_nip(ctx, ctx->nip - 4);
3201 t0 = tcg_temp_new();
3202 t1 = tcg_const_i32(rD(ctx->opcode));
3203 gen_addr_imm_index(ctx, t0, 0);
3204 gen_helper_lmw(cpu_env, t0, t1);
3205 tcg_temp_free(t0);
3206 tcg_temp_free_i32(t1);
3207 }
3208
3209 /* stmw */
3210 static void gen_stmw(DisasContext *ctx)
3211 {
3212 TCGv t0;
3213 TCGv_i32 t1;
3214 gen_set_access_type(ctx, ACCESS_INT);
3215 /* NIP cannot be restored if the memory exception comes from an helper */
3216 gen_update_nip(ctx, ctx->nip - 4);
3217 t0 = tcg_temp_new();
3218 t1 = tcg_const_i32(rS(ctx->opcode));
3219 gen_addr_imm_index(ctx, t0, 0);
3220 gen_helper_stmw(cpu_env, t0, t1);
3221 tcg_temp_free(t0);
3222 tcg_temp_free_i32(t1);
3223 }
3224
3225 /*** Integer load and store strings ***/
3226
3227 /* lswi */
3228 /* PowerPC32 specification says we must generate an exception if
3229 * rA is in the range of registers to be loaded.
3230 * In an other hand, IBM says this is valid, but rA won't be loaded.
3231 * For now, I'll follow the spec...
3232 */
3233 static void gen_lswi(DisasContext *ctx)
3234 {
3235 TCGv t0;
3236 TCGv_i32 t1, t2;
3237 int nb = NB(ctx->opcode);
3238 int start = rD(ctx->opcode);
3239 int ra = rA(ctx->opcode);
3240 int nr;
3241
3242 if (nb == 0)
3243 nb = 32;
3244 nr = (nb + 3) / 4;
3245 if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3246 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3247 return;
3248 }
3249 gen_set_access_type(ctx, ACCESS_INT);
3250 /* NIP cannot be restored if the memory exception comes from an helper */
3251 gen_update_nip(ctx, ctx->nip - 4);
3252 t0 = tcg_temp_new();
3253 gen_addr_register(ctx, t0);
3254 t1 = tcg_const_i32(nb);
3255 t2 = tcg_const_i32(start);
3256 gen_helper_lsw(cpu_env, t0, t1, t2);
3257 tcg_temp_free(t0);
3258 tcg_temp_free_i32(t1);
3259 tcg_temp_free_i32(t2);
3260 }
3261
3262 /* lswx */
3263 static void gen_lswx(DisasContext *ctx)
3264 {
3265 TCGv t0;
3266 TCGv_i32 t1, t2, t3;
3267 gen_set_access_type(ctx, ACCESS_INT);
3268 /* NIP cannot be restored if the memory exception comes from an helper */
3269 gen_update_nip(ctx, ctx->nip - 4);
3270 t0 = tcg_temp_new();
3271 gen_addr_reg_index(ctx, t0);
3272 t1 = tcg_const_i32(rD(ctx->opcode));
3273 t2 = tcg_const_i32(rA(ctx->opcode));
3274 t3 = tcg_const_i32(rB(ctx->opcode));
3275 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3276 tcg_temp_free(t0);
3277 tcg_temp_free_i32(t1);
3278 tcg_temp_free_i32(t2);
3279 tcg_temp_free_i32(t3);
3280 }
3281
3282 /* stswi */
3283 static void gen_stswi(DisasContext *ctx)
3284 {
3285 TCGv t0;
3286 TCGv_i32 t1, t2;
3287 int nb = NB(ctx->opcode);
3288 gen_set_access_type(ctx, ACCESS_INT);
3289 /* NIP cannot be restored if the memory exception comes from an helper */
3290 gen_update_nip(ctx, ctx->nip - 4);
3291 t0 = tcg_temp_new();
3292 gen_addr_register(ctx, t0);
3293 if (nb == 0)
3294 nb = 32;
3295 t1 = tcg_const_i32(nb);
3296 t2 = tcg_const_i32(rS(ctx->opcode));
3297 gen_helper_stsw(cpu_env, t0, t1, t2);
3298 tcg_temp_free(t0);
3299 tcg_temp_free_i32(t1);
3300 tcg_temp_free_i32(t2);
3301 }
3302
3303 /* stswx */
3304 static void gen_stswx(DisasContext *ctx)
3305 {
3306 TCGv t0;
3307 TCGv_i32 t1, t2;
3308 gen_set_access_type(ctx, ACCESS_INT);
3309 /* NIP cannot be restored if the memory exception comes from an helper */
3310 gen_update_nip(ctx, ctx->nip - 4);
3311 t0 = tcg_temp_new();
3312 gen_addr_reg_index(ctx, t0);
3313 t1 = tcg_temp_new_i32();
3314 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3315 tcg_gen_andi_i32(t1, t1, 0x7F);
3316 t2 = tcg_const_i32(rS(ctx->opcode));
3317 gen_helper_stsw(cpu_env, t0, t1, t2);
3318 tcg_temp_free(t0);
3319 tcg_temp_free_i32(t1);
3320 tcg_temp_free_i32(t2);
3321 }
3322
3323 /*** Memory synchronisation ***/
3324 /* eieio */
3325 static void gen_eieio(DisasContext *ctx)
3326 {
3327 }
3328
3329 #if !defined(CONFIG_USER_ONLY)
3330 static inline void gen_check_tlb_flush(DisasContext *ctx)
3331 {
3332 TCGv_i32 t;
3333 TCGLabel *l;
3334
3335 if (!ctx->lazy_tlb_flush) {
3336 return;
3337 }
3338 l = gen_new_label();
3339 t = tcg_temp_new_i32();
3340 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
3341 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l);
3342 gen_helper_check_tlb_flush(cpu_env);
3343 gen_set_label(l);
3344 tcg_temp_free_i32(t);
3345 }
3346 #else
3347 static inline void gen_check_tlb_flush(DisasContext *ctx) { }
3348 #endif
3349
3350 /* isync */
3351 static void gen_isync(DisasContext *ctx)
3352 {
3353 /*
3354 * We need to check for a pending TLB flush. This can only happen in
3355 * kernel mode however so check MSR_PR
3356 */
3357 if (!ctx->pr) {
3358 gen_check_tlb_flush(ctx);
3359 }
3360 gen_stop_exception(ctx);
3361 }
3362
3363 #define LARX(name, len, loadop) \
3364 static void gen_##name(DisasContext *ctx) \
3365 { \
3366 TCGv t0; \
3367 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3368 gen_set_access_type(ctx, ACCESS_RES); \
3369 t0 = tcg_temp_local_new(); \
3370 gen_addr_reg_index(ctx, t0); \
3371 if ((len) > 1) { \
3372 gen_check_align(ctx, t0, (len)-1); \
3373 } \
3374 gen_qemu_##loadop(ctx, gpr, t0); \
3375 tcg_gen_mov_tl(cpu_reserve, t0); \
3376 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3377 tcg_temp_free(t0); \
3378 }
3379
3380 /* lwarx */
3381 LARX(lbarx, 1, ld8u);
3382 LARX(lharx, 2, ld16u);
3383 LARX(lwarx, 4, ld32u);
3384
3385
3386 #if defined(CONFIG_USER_ONLY)
3387 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3388 int reg, int size)
3389 {
3390 TCGv t0 = tcg_temp_new();
3391 uint32_t save_exception = ctx->exception;
3392
3393 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3394 tcg_gen_movi_tl(t0, (size << 5) | reg);
3395 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3396 tcg_temp_free(t0);
3397 gen_update_nip(ctx, ctx->nip-4);
3398 ctx->exception = POWERPC_EXCP_BRANCH;
3399 gen_exception(ctx, POWERPC_EXCP_STCX);
3400 ctx->exception = save_exception;
3401 }
3402 #else
3403 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3404 int reg, int size)
3405 {
3406 TCGLabel *l1;
3407
3408 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3409 l1 = gen_new_label();
3410 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3411 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3412 #if defined(TARGET_PPC64)
3413 if (size == 8) {
3414 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3415 } else
3416 #endif
3417 if (size == 4) {
3418 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3419 } else if (size == 2) {
3420 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3421 #if defined(TARGET_PPC64)
3422 } else if (size == 16) {
3423 TCGv gpr1, gpr2 , EA8;
3424 if (unlikely(ctx->le_mode)) {
3425 gpr1 = cpu_gpr[reg+1];
3426 gpr2 = cpu_gpr[reg];
3427 } else {
3428 gpr1 = cpu_gpr[reg];
3429 gpr2 = cpu_gpr[reg+1];
3430 }
3431 gen_qemu_st64(ctx, gpr1, EA);
3432 EA8 = tcg_temp_local_new();
3433 gen_addr_add(ctx, EA8, EA, 8);
3434 gen_qemu_st64(ctx, gpr2, EA8);
3435 tcg_temp_free(EA8);
3436 #endif
3437 } else {
3438 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3439 }
3440 gen_set_label(l1);
3441 tcg_gen_movi_tl(cpu_reserve, -1);
3442 }
3443 #endif
3444
3445 #define STCX(name, len) \
3446 static void gen_##name(DisasContext *ctx) \
3447 { \
3448 TCGv t0; \
3449 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3450 gen_inval_exception(ctx, \
3451 POWERPC_EXCP_INVAL_INVAL); \
3452 return; \
3453 } \
3454 gen_set_access_type(ctx, ACCESS_RES); \
3455 t0 = tcg_temp_local_new(); \
3456 gen_addr_reg_index(ctx, t0); \
3457 if (len > 1) { \
3458 gen_check_align(ctx, t0, (len)-1); \
3459 } \
3460 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3461 tcg_temp_free(t0); \
3462 }
3463
3464 STCX(stbcx_, 1);
3465 STCX(sthcx_, 2);
3466 STCX(stwcx_, 4);
3467
3468 #if defined(TARGET_PPC64)
3469 /* ldarx */
3470 LARX(ldarx, 8, ld64);
3471
3472 /* lqarx */
3473 static void gen_lqarx(DisasContext *ctx)
3474 {
3475 TCGv EA;
3476 int rd = rD(ctx->opcode);
3477 TCGv gpr1, gpr2;
3478
3479 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3480 (rd == rB(ctx->opcode)))) {
3481 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3482 return;
3483 }
3484
3485 gen_set_access_type(ctx, ACCESS_RES);
3486 EA = tcg_temp_local_new();
3487 gen_addr_reg_index(ctx, EA);
3488 gen_check_align(ctx, EA, 15);
3489 if (unlikely(ctx->le_mode)) {
3490 gpr1 = cpu_gpr[rd+1];
3491 gpr2 = cpu_gpr[rd];
3492 } else {
3493 gpr1 = cpu_gpr[rd];
3494 gpr2 = cpu_gpr[rd+1];
3495 }
3496 gen_qemu_ld64(ctx, gpr1, EA);
3497 tcg_gen_mov_tl(cpu_reserve, EA);
3498
3499 gen_addr_add(ctx, EA, EA, 8);
3500 gen_qemu_ld64(ctx, gpr2, EA);
3501
3502 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3503 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3504
3505 tcg_temp_free(EA);
3506 }
3507
3508 /* stdcx. */
3509 STCX(stdcx_, 8);
3510 STCX(stqcx_, 16);
3511 #endif /* defined(TARGET_PPC64) */
3512
3513 /* sync */
3514 static void gen_sync(DisasContext *ctx)
3515 {
3516 uint32_t l = (ctx->opcode >> 21) & 3;
3517
3518 /*
3519 * We may need to check for a pending TLB flush.
3520 *
3521 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3522 *
3523 * Additionally, this can only happen in kernel mode however so
3524 * check MSR_PR as well.
3525 */
3526 if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) {
3527 gen_check_tlb_flush(ctx);
3528 }
3529 }
3530
3531 /* wait */
3532 static void gen_wait(DisasContext *ctx)
3533 {
3534 TCGv_i32 t0 = tcg_const_i32(1);
3535 tcg_gen_st_i32(t0, cpu_env,
3536 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3537 tcg_temp_free_i32(t0);
3538 /* Stop translation, as the CPU is supposed to sleep from now */
3539 gen_exception_err(ctx, EXCP_HLT, 1);
3540 }
3541
3542 /*** Floating-point load ***/
3543 #define GEN_LDF(name, ldop, opc, type) \
3544 static void glue(gen_, name)(DisasContext *ctx) \
3545 { \
3546 TCGv EA; \
3547 if (unlikely(!ctx->fpu_enabled)) { \
3548 gen_exception(ctx, POWERPC_EXCP_FPU); \
3549 return; \
3550 } \
3551 gen_set_access_type(ctx, ACCESS_FLOAT); \
3552 EA = tcg_temp_new(); \
3553 gen_addr_imm_index(ctx, EA, 0); \
3554 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3555 tcg_temp_free(EA); \
3556 }
3557
3558 #define GEN_LDUF(name, ldop, opc, type) \
3559 static void glue(gen_, name##u)(DisasContext *ctx) \
3560 { \
3561 TCGv EA; \
3562 if (unlikely(!ctx->fpu_enabled)) { \
3563 gen_exception(ctx, POWERPC_EXCP_FPU); \
3564 return; \
3565 } \
3566 if (unlikely(rA(ctx->opcode) == 0)) { \
3567 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3568 return; \
3569 } \
3570 gen_set_access_type(ctx, ACCESS_FLOAT); \
3571 EA = tcg_temp_new(); \
3572 gen_addr_imm_index(ctx, EA, 0); \
3573 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3574 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3575 tcg_temp_free(EA); \
3576 }
3577
3578 #define GEN_LDUXF(name, ldop, opc, type) \
3579 static void glue(gen_, name##ux)(DisasContext *ctx) \
3580 { \
3581 TCGv EA; \
3582 if (unlikely(!ctx->fpu_enabled)) { \
3583 gen_exception(ctx, POWERPC_EXCP_FPU); \
3584 return; \
3585 } \
3586 if (unlikely(rA(ctx->opcode) == 0)) { \
3587 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3588 return; \
3589 } \
3590 gen_set_access_type(ctx, ACCESS_FLOAT); \
3591 EA = tcg_temp_new(); \
3592 gen_addr_reg_index(ctx, EA); \
3593 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3594 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3595 tcg_temp_free(EA); \
3596 }
3597
3598 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3599 static void glue(gen_, name##x)(DisasContext *ctx) \
3600 { \
3601 TCGv EA; \
3602 if (unlikely(!ctx->fpu_enabled)) { \
3603 gen_exception(ctx, POWERPC_EXCP_FPU); \
3604 return; \
3605 } \
3606 gen_set_access_type(ctx, ACCESS_FLOAT); \
3607 EA = tcg_temp_new(); \
3608 gen_addr_reg_index(ctx, EA); \
3609 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3610 tcg_temp_free(EA); \
3611 }
3612
3613 #define GEN_LDFS(name, ldop, op, type) \
3614 GEN_LDF(name, ldop, op | 0x20, type); \
3615 GEN_LDUF(name, ldop, op | 0x21, type); \
3616 GEN_LDUXF(name, ldop, op | 0x01, type); \
3617 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3618
3619 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3620 {
3621 TCGv t0 = tcg_temp_new();
3622 TCGv_i32 t1 = tcg_temp_new_i32();
3623 gen_qemu_ld32u(ctx, t0, arg2);
3624 tcg_gen_trunc_tl_i32(t1, t0);
3625 tcg_temp_free(t0);
3626 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3627 tcg_temp_free_i32(t1);
3628 }
3629
3630 /* lfd lfdu lfdux lfdx */
3631 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3632 /* lfs lfsu lfsux lfsx */
3633 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3634
3635 /* lfdp */
3636 static void gen_lfdp(DisasContext *ctx)
3637 {
3638 TCGv EA;
3639 if (unlikely(!ctx->fpu_enabled)) {
3640 gen_exception(ctx, POWERPC_EXCP_FPU);
3641 return;
3642 }
3643 gen_set_access_type(ctx, ACCESS_FLOAT);
3644 EA = tcg_temp_new();
3645 gen_addr_imm_index(ctx, EA, 0);
3646 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3647 64-bit byteswap already. */
3648 if (unlikely(ctx->le_mode)) {
3649 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3650 tcg_gen_addi_tl(EA, EA, 8);
3651 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3652 } else {
3653 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3654 tcg_gen_addi_tl(EA, EA, 8);
3655 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3656 }
3657 tcg_temp_free(EA);
3658 }
3659
3660 /* lfdpx */
3661 static void gen_lfdpx(DisasContext *ctx)
3662 {
3663 TCGv EA;
3664 if (unlikely(!ctx->fpu_enabled)) {
3665 gen_exception(ctx, POWERPC_EXCP_FPU);
3666 return;
3667 }
3668 gen_set_access_type(ctx, ACCESS_FLOAT);
3669 EA = tcg_temp_new();
3670 gen_addr_reg_index(ctx, EA);
3671 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3672 64-bit byteswap already. */
3673 if (unlikely(ctx->le_mode)) {
3674 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3675 tcg_gen_addi_tl(EA, EA, 8);
3676 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3677 } else {
3678 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3679 tcg_gen_addi_tl(EA, EA, 8);
3680 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3681 }
3682 tcg_temp_free(EA);
3683 }
3684
3685 /* lfiwax */
3686 static void gen_lfiwax(DisasContext *ctx)
3687 {
3688 TCGv EA;
3689 TCGv t0;
3690 if (unlikely(!ctx->fpu_enabled)) {
3691 gen_exception(ctx, POWERPC_EXCP_FPU);
3692 return;
3693 }
3694 gen_set_access_type(ctx, ACCESS_FLOAT);
3695 EA = tcg_temp_new();
3696 t0 = tcg_temp_new();
3697 gen_addr_reg_index(ctx, EA);
3698 gen_qemu_ld32s(ctx, t0, EA);
3699 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3700 tcg_temp_free(EA);
3701 tcg_temp_free(t0);
3702 }
3703
3704 /* lfiwzx */
3705 static void gen_lfiwzx(DisasContext *ctx)
3706 {
3707 TCGv EA;
3708 if (unlikely(!ctx->fpu_enabled)) {
3709 gen_exception(ctx, POWERPC_EXCP_FPU);
3710 return;
3711 }
3712 gen_set_access_type(ctx, ACCESS_FLOAT);
3713 EA = tcg_temp_new();
3714 gen_addr_reg_index(ctx, EA);
3715 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3716 tcg_temp_free(EA);
3717 }
3718 /*** Floating-point store ***/
3719 #define GEN_STF(name, stop, opc, type) \
3720 static void glue(gen_, name)(DisasContext *ctx) \
3721 { \
3722 TCGv EA; \
3723 if (unlikely(!ctx->fpu_enabled)) { \
3724 gen_exception(ctx, POWERPC_EXCP_FPU); \
3725 return; \
3726 } \
3727 gen_set_access_type(ctx, ACCESS_FLOAT); \
3728 EA = tcg_temp_new(); \
3729 gen_addr_imm_index(ctx, EA, 0); \
3730 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3731 tcg_temp_free(EA); \
3732 }
3733
3734 #define GEN_STUF(name, stop, opc, type) \
3735 static void glue(gen_, name##u)(DisasContext *ctx) \
3736 { \
3737 TCGv EA; \
3738 if (unlikely(!ctx->fpu_enabled)) { \
3739 gen_exception(ctx, POWERPC_EXCP_FPU); \
3740 return; \
3741 } \
3742 if (unlikely(rA(ctx->opcode) == 0)) { \
3743 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3744 return; \
3745 } \
3746 gen_set_access_type(ctx, ACCESS_FLOAT); \
3747 EA = tcg_temp_new(); \
3748 gen_addr_imm_index(ctx, EA, 0); \
3749 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3750 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3751 tcg_temp_free(EA); \
3752 }
3753
3754 #define GEN_STUXF(name, stop, opc, type) \
3755 static void glue(gen_, name##ux)(DisasContext *ctx) \
3756 { \
3757 TCGv EA; \
3758 if (unlikely(!ctx->fpu_enabled)) { \
3759 gen_exception(ctx, POWERPC_EXCP_FPU); \
3760 return; \
3761 } \
3762 if (unlikely(rA(ctx->opcode) == 0)) { \
3763 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3764 return; \
3765 } \
3766 gen_set_access_type(ctx, ACCESS_FLOAT); \
3767 EA = tcg_temp_new(); \
3768 gen_addr_reg_index(ctx, EA); \
3769 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3770 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3771 tcg_temp_free(EA); \
3772 }
3773
3774 #define GEN_STXF(name, stop, opc2, opc3, type) \
3775 static void glue(gen_, name##x)(DisasContext *ctx) \
3776 { \
3777 TCGv EA; \
3778 if (unlikely(!ctx->fpu_enabled)) { \
3779 gen_exception(ctx, POWERPC_EXCP_FPU); \
3780 return; \
3781 } \
3782 gen_set_access_type(ctx, ACCESS_FLOAT); \
3783 EA = tcg_temp_new(); \
3784 gen_addr_reg_index(ctx, EA); \
3785 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3786 tcg_temp_free(EA); \
3787 }
3788
3789 #define GEN_STFS(name, stop, op, type) \
3790 GEN_STF(name, stop, op | 0x20, type); \
3791 GEN_STUF(name, stop, op | 0x21, type); \
3792 GEN_STUXF(name, stop, op | 0x01, type); \
3793 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3794
3795 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3796 {
3797 TCGv_i32 t0 = tcg_temp_new_i32();
3798 TCGv t1 = tcg_temp_new();
3799 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3800 tcg_gen_extu_i32_tl(t1, t0);
3801 tcg_temp_free_i32(t0);
3802 gen_qemu_st32(ctx, t1, arg2);
3803 tcg_temp_free(t1);
3804 }
3805
3806 /* stfd stfdu stfdux stfdx */
3807 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3808 /* stfs stfsu stfsux stfsx */
3809 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3810
3811 /* stfdp */
3812 static void gen_stfdp(DisasContext *ctx)
3813 {
3814 TCGv EA;
3815 if (unlikely(!ctx->fpu_enabled)) {
3816 gen_exception(ctx, POWERPC_EXCP_FPU);
3817 return;
3818 }
3819 gen_set_access_type(ctx, ACCESS_FLOAT);
3820 EA = tcg_temp_new();
3821 gen_addr_imm_index(ctx, EA, 0);
3822 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3823 64-bit byteswap already. */
3824 if (unlikely(ctx->le_mode)) {
3825 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3826 tcg_gen_addi_tl(EA, EA, 8);
3827 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3828 } else {
3829 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3830 tcg_gen_addi_tl(EA, EA, 8);
3831 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3832 }
3833 tcg_temp_free(EA);
3834 }
3835
3836 /* stfdpx */
3837 static void gen_stfdpx(DisasContext *ctx)
3838 {
3839 TCGv EA;
3840 if (unlikely(!ctx->fpu_enabled)) {
3841 gen_exception(ctx, POWERPC_EXCP_FPU);
3842 return;
3843 }
3844 gen_set_access_type(ctx, ACCESS_FLOAT);
3845 EA = tcg_temp_new();
3846 gen_addr_reg_index(ctx, EA);
3847 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3848 64-bit byteswap already. */
3849 if (unlikely(ctx->le_mode)) {
3850 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3851 tcg_gen_addi_tl(EA, EA, 8);
3852 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3853 } else {
3854 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3855 tcg_gen_addi_tl(EA, EA, 8);
3856 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3857 }
3858 tcg_temp_free(EA);
3859 }
3860
3861 /* Optional: */
3862 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3863 {
3864 TCGv t0 = tcg_temp_new();
3865 tcg_gen_trunc_i64_tl(t0, arg1),
3866 gen_qemu_st32(ctx, t0, arg2);
3867 tcg_temp_free(t0);
3868 }
3869 /* stfiwx */
3870 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3871
3872 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3873 {
3874 #if defined(TARGET_PPC64)
3875 if (ctx->has_cfar)
3876 tcg_gen_movi_tl(cpu_cfar, nip);
3877 #endif
3878 }
3879
3880 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
3881 {
3882 if (unlikely(ctx->singlestep_enabled)) {
3883 return false;
3884 }
3885
3886 #ifndef CONFIG_USER_ONLY
3887 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
3888 #else
3889 return true;
3890 #endif
3891 }
3892
3893 /*** Branch ***/
3894 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3895 {
3896 if (NARROW_MODE(ctx)) {
3897 dest = (uint32_t) dest;
3898 }
3899 if (use_goto_tb(ctx, dest)) {
3900 tcg_gen_goto_tb(n);
3901 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3902 tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
3903 } else {
3904 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3905 if (unlikely(ctx->singlestep_enabled)) {
3906 if ((ctx->singlestep_enabled &
3907 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3908 (ctx->exception == POWERPC_EXCP_BRANCH ||
3909 ctx->exception == POWERPC_EXCP_TRACE)) {
3910 target_ulong tmp = ctx->nip;
3911 ctx->nip = dest;
3912 gen_exception(ctx, POWERPC_EXCP_TRACE);
3913 ctx->nip = tmp;
3914 }
3915 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3916 gen_debug_exception(ctx);
3917 }
3918 }
3919 tcg_gen_exit_tb(0);
3920 }
3921 }
3922
3923 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3924 {
3925 if (NARROW_MODE(ctx)) {
3926 nip = (uint32_t)nip;
3927 }
3928 tcg_gen_movi_tl(cpu_lr, nip);
3929 }
3930
3931 /* b ba bl bla */
3932 static void gen_b(DisasContext *ctx)
3933 {
3934 target_ulong li, target;
3935
3936 ctx->exception = POWERPC_EXCP_BRANCH;
3937 /* sign extend LI */
3938 li = LI(ctx->opcode);
3939 li = (li ^ 0x02000000) - 0x02000000;
3940 if (likely(AA(ctx->opcode) == 0)) {
3941 target = ctx->nip + li - 4;
3942 } else {
3943 target = li;
3944 }
3945 if (LK(ctx->opcode)) {
3946 gen_setlr(ctx, ctx->nip);
3947 }
3948 gen_update_cfar(ctx, ctx->nip);
3949 gen_goto_tb(ctx, 0, target);
3950 }
3951
3952 #define BCOND_IM 0
3953 #define BCOND_LR 1
3954 #define BCOND_CTR 2
3955 #define BCOND_TAR 3
3956
3957 static inline void gen_bcond(DisasContext *ctx, int type)
3958 {
3959 uint32_t bo = BO(ctx->opcode);
3960 TCGLabel *l1;
3961 TCGv target;
3962
3963 ctx->exception = POWERPC_EXCP_BRANCH;
3964 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3965 target = tcg_temp_local_new();
3966 if (type == BCOND_CTR)
3967 tcg_gen_mov_tl(target, cpu_ctr);
3968 else if (type == BCOND_TAR)
3969 gen_load_spr(target, SPR_TAR);
3970 else
3971 tcg_gen_mov_tl(target, cpu_lr);
3972 } else {
3973 TCGV_UNUSED(target);
3974 }
3975 if (LK(ctx->opcode))
3976 gen_setlr(ctx, ctx->nip);
3977 l1 = gen_new_label();
3978 if ((bo & 0x4) == 0) {
3979 /* Decrement and test CTR */
3980 TCGv temp = tcg_temp_new();
3981 if (unlikely(type == BCOND_CTR)) {
3982 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3983 return;
3984 }
3985 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3986 if (NARROW_MODE(ctx)) {
3987 tcg_gen_ext32u_tl(temp, cpu_ctr);
3988 } else {
3989 tcg_gen_mov_tl(temp, cpu_ctr);
3990 }
3991 if (bo & 0x2) {
3992 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3993 } else {
3994 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3995 }
3996 tcg_temp_free(temp);
3997 }
3998 if ((bo & 0x10) == 0) {
3999 /* Test CR */
4000 uint32_t bi = BI(ctx->opcode);
4001 uint32_t mask = 0x08 >> (bi & 0x03);
4002 TCGv_i32 temp = tcg_temp_new_i32();
4003
4004 if (bo & 0x8) {
4005 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4006 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
4007 } else {
4008 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
4009 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
4010 }
4011 tcg_temp_free_i32(temp);
4012 }
4013 gen_update_cfar(ctx, ctx->nip);
4014 if (type == BCOND_IM) {
4015 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
4016 if (likely(AA(ctx->opcode) == 0)) {
4017 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
4018 } else {
4019 gen_goto_tb(ctx, 0, li);
4020 }
4021 gen_set_label(l1);
4022 gen_goto_tb(ctx, 1, ctx->nip);
4023 } else {
4024 if (NARROW_MODE(ctx)) {
4025 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
4026 } else {
4027 tcg_gen_andi_tl(cpu_nip, target, ~3);
4028 }
4029 tcg_gen_exit_tb(0);
4030 gen_set_label(l1);
4031 gen_update_nip(ctx, ctx->nip);
4032 tcg_gen_exit_tb(0);
4033 }
4034 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
4035 tcg_temp_free(target);
4036 }
4037 }
4038
4039 static void gen_bc(DisasContext *ctx)
4040 {
4041 gen_bcond(ctx, BCOND_IM);
4042 }
4043
4044 static void gen_bcctr(DisasContext *ctx)
4045 {
4046 gen_bcond(ctx, BCOND_CTR);
4047 }
4048
4049 static void gen_bclr(DisasContext *ctx)
4050 {
4051 gen_bcond(ctx, BCOND_LR);
4052 }
4053
4054 static void gen_bctar(DisasContext *ctx)
4055 {
4056 gen_bcond(ctx, BCOND_TAR);
4057 }
4058
4059 /*** Condition register logical ***/
4060 #define GEN_CRLOGIC(name, tcg_op, opc) \
4061 static void glue(gen_, name)(DisasContext *ctx) \
4062 { \
4063 uint8_t bitmask; \
4064 int sh; \
4065 TCGv_i32 t0, t1; \
4066 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
4067 t0 = tcg_temp_new_i32(); \
4068 if (sh > 0) \
4069 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
4070 else if (sh < 0) \
4071 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
4072 else \
4073 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
4074 t1 = tcg_temp_new_i32(); \
4075 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
4076 if (sh > 0) \
4077 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4078 else if (sh < 0) \
4079 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4080 else \
4081 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4082 tcg_op(t0, t0, t1); \
4083 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4084 tcg_gen_andi_i32(t0, t0, bitmask); \
4085 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4086 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4087 tcg_temp_free_i32(t0); \
4088 tcg_temp_free_i32(t1); \
4089 }
4090
4091 /* crand */
4092 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4093 /* crandc */
4094 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4095 /* creqv */
4096 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4097 /* crnand */
4098 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4099 /* crnor */
4100 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4101 /* cror */
4102 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4103 /* crorc */
4104 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4105 /* crxor */
4106 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4107
4108 /* mcrf */
4109 static void gen_mcrf(DisasContext *ctx)
4110 {
4111 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4112 }
4113
4114 /*** System linkage ***/
4115
4116 /* rfi (supervisor only) */
4117 static void gen_rfi(DisasContext *ctx)
4118 {
4119 #if defined(CONFIG_USER_ONLY)
4120 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4121 #else
4122 /* Restore CPU state */
4123 if (unlikely(ctx->pr)) {
4124 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4125 return;
4126 }
4127 gen_update_cfar(ctx, ctx->nip);
4128 gen_helper_rfi(cpu_env);
4129 gen_sync_exception(ctx);
4130 #endif
4131 }
4132
4133 #if defined(TARGET_PPC64)
4134 static void gen_rfid(DisasContext *ctx)
4135 {
4136 #if defined(CONFIG_USER_ONLY)
4137 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4138 #else
4139 /* Restore CPU state */
4140 if (unlikely(ctx->pr)) {
4141 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4142 return;
4143 }
4144 gen_update_cfar(ctx, ctx->nip);
4145 gen_helper_rfid(cpu_env);
4146 gen_sync_exception(ctx);
4147 #endif
4148 }
4149
4150 static void gen_hrfid(DisasContext *ctx)
4151 {
4152 #if defined(CONFIG_USER_ONLY)
4153 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4154 #else
4155 /* Restore CPU state */
4156 if (unlikely(ctx->pr || !ctx->hv)) {
4157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4158 return;
4159 }
4160 gen_helper_hrfid(cpu_env);
4161 gen_sync_exception(ctx);
4162 #endif
4163 }
4164 #endif
4165
4166 /* sc */
4167 #if defined(CONFIG_USER_ONLY)
4168 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4169 #else
4170 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4171 #endif
4172 static void gen_sc(DisasContext *ctx)
4173 {
4174 uint32_t lev;
4175
4176 lev = (ctx->opcode >> 5) & 0x7F;
4177 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4178 }
4179
4180 /*** Trap ***/
4181
4182 /* tw */
4183 static void gen_tw(DisasContext *ctx)
4184 {
4185 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4186 /* Update the nip since this might generate a trap exception */
4187 gen_update_nip(ctx, ctx->nip);
4188 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4189 t0);
4190 tcg_temp_free_i32(t0);
4191 }
4192
4193 /* twi */
4194 static void gen_twi(DisasContext *ctx)
4195 {
4196 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4197 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4198 /* Update the nip since this might generate a trap exception */
4199 gen_update_nip(ctx, ctx->nip);
4200 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4201 tcg_temp_free(t0);
4202 tcg_temp_free_i32(t1);
4203 }
4204
4205 #if defined(TARGET_PPC64)
4206 /* td */
4207 static void gen_td(DisasContext *ctx)
4208 {
4209 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4210 /* Update the nip since this might generate a trap exception */
4211 gen_update_nip(ctx, ctx->nip);
4212 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4213 t0);
4214 tcg_temp_free_i32(t0);
4215 }
4216
4217 /* tdi */
4218 static void gen_tdi(DisasContext *ctx)
4219 {
4220 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4221 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4222 /* Update the nip since this might generate a trap exception */
4223 gen_update_nip(ctx, ctx->nip);
4224 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4225 tcg_temp_free(t0);
4226 tcg_temp_free_i32(t1);
4227 }
4228 #endif
4229
4230 /*** Processor control ***/
4231
4232 static void gen_read_xer(TCGv dst)
4233 {
4234 TCGv t0 = tcg_temp_new();
4235 TCGv t1 = tcg_temp_new();
4236 TCGv t2 = tcg_temp_new();
4237 tcg_gen_mov_tl(dst, cpu_xer);
4238 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4239 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4240 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4241 tcg_gen_or_tl(t0, t0, t1);
4242 tcg_gen_or_tl(dst, dst, t2);
4243 tcg_gen_or_tl(dst, dst, t0);
4244 tcg_temp_free(t0);
4245 tcg_temp_free(t1);
4246 tcg_temp_free(t2);
4247 }
4248
4249 static void gen_write_xer(TCGv src)
4250 {
4251 tcg_gen_andi_tl(cpu_xer, src,
4252 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4253 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4254 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4255 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4256 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4257 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4258 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4259 }
4260
4261 /* mcrxr */
4262 static void gen_mcrxr(DisasContext *ctx)
4263 {
4264 TCGv_i32 t0 = tcg_temp_new_i32();
4265 TCGv_i32 t1 = tcg_temp_new_i32();
4266 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4267
4268 tcg_gen_trunc_tl_i32(t0, cpu_so);
4269 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4270 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4271 tcg_gen_shli_i32(t0, t0, 3);
4272 tcg_gen_shli_i32(t1, t1, 2);
4273 tcg_gen_shli_i32(dst, dst, 1);
4274 tcg_gen_or_i32(dst, dst, t0);
4275 tcg_gen_or_i32(dst, dst, t1);
4276 tcg_temp_free_i32(t0);
4277 tcg_temp_free_i32(t1);
4278
4279 tcg_gen_movi_tl(cpu_so, 0);
4280 tcg_gen_movi_tl(cpu_ov, 0);
4281 tcg_gen_movi_tl(cpu_ca, 0);
4282 }
4283
4284 /* mfcr mfocrf */
4285 static void gen_mfcr(DisasContext *ctx)
4286 {
4287 uint32_t crm, crn;
4288
4289 if (likely(ctx->opcode & 0x00100000)) {
4290 crm = CRM(ctx->opcode);
4291 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4292 crn = ctz32 (crm);
4293 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4294 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4295 cpu_gpr[rD(ctx->opcode)], crn * 4);
4296 }
4297 } else {
4298 TCGv_i32 t0 = tcg_temp_new_i32();
4299 tcg_gen_mov_i32(t0, cpu_crf[0]);
4300 tcg_gen_shli_i32(t0, t0, 4);
4301 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4302 tcg_gen_shli_i32(t0, t0, 4);
4303 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4304 tcg_gen_shli_i32(t0, t0, 4);
4305 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4306 tcg_gen_shli_i32(t0, t0, 4);
4307 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4308 tcg_gen_shli_i32(t0, t0, 4);
4309 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4310 tcg_gen_shli_i32(t0, t0, 4);
4311 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4312 tcg_gen_shli_i32(t0, t0, 4);
4313 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4314 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4315 tcg_temp_free_i32(t0);
4316 }
4317 }
4318
4319 /* mfmsr */
4320 static void gen_mfmsr(DisasContext *ctx)
4321 {
4322 #if defined(CONFIG_USER_ONLY)
4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4324 #else
4325 if (unlikely(ctx->pr)) {
4326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4327 return;
4328 }
4329 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4330 #endif
4331 }
4332
4333 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4334 {
4335 #if 0
4336 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4337 printf("ERROR: try to access SPR %d !\n", sprn);
4338 #endif
4339 }
4340 #define SPR_NOACCESS (&spr_noaccess)
4341
4342 /* mfspr */
4343 static inline void gen_op_mfspr(DisasContext *ctx)
4344 {
4345 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4346 uint32_t sprn = SPR(ctx->opcode);
4347
4348 #if defined(CONFIG_USER_ONLY)
4349 read_cb = ctx->spr_cb[sprn].uea_read;
4350 #else
4351 if (ctx->pr) {
4352 read_cb = ctx->spr_cb[sprn].uea_read;
4353 } else if (ctx->hv) {
4354 read_cb = ctx->spr_cb[sprn].hea_read;
4355 } else {
4356 read_cb = ctx->spr_cb[sprn].oea_read;
4357 }
4358 #endif
4359 if (likely(read_cb != NULL)) {
4360 if (likely(read_cb != SPR_NOACCESS)) {
4361 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4362 } else {
4363 /* Privilege exception */
4364 /* This is a hack to avoid warnings when running Linux:
4365 * this OS breaks the PowerPC virtualisation model,
4366 * allowing userland application to read the PVR
4367 */
4368 if (sprn != SPR_PVR) {
4369 fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4370 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4371 if (qemu_log_separate()) {
4372 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4373 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4374 }
4375 }
4376 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4377 }
4378 } else {
4379 /* Not defined */
4380 fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4381 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4382 if (qemu_log_separate()) {
4383 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4384 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4385 }
4386 /* Only generate an exception in user space, otherwise this is a nop */
4387 if (ctx->pr) {
4388 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4389 }
4390 }
4391 }
4392
4393 static void gen_mfspr(DisasContext *ctx)
4394 {
4395 gen_op_mfspr(ctx);
4396 }
4397
4398 /* mftb */
4399 static void gen_mftb(DisasContext *ctx)
4400 {
4401 gen_op_mfspr(ctx);
4402 }
4403
4404 /* mtcrf mtocrf*/
4405 static void gen_mtcrf(DisasContext *ctx)
4406 {
4407 uint32_t crm, crn;
4408
4409 crm = CRM(ctx->opcode);
4410 if (likely((ctx->opcode & 0x00100000))) {
4411 if (crm && ((crm & (crm - 1)) == 0)) {
4412 TCGv_i32 temp = tcg_temp_new_i32();
4413 crn = ctz32 (crm);
4414 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4415 tcg_gen_shri_i32(temp, temp, crn * 4);
4416 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4417 tcg_temp_free_i32(temp);
4418 }
4419 } else {
4420 TCGv_i32 temp = tcg_temp_new_i32();
4421 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4422 for (crn = 0 ; crn < 8 ; crn++) {
4423 if (crm & (1 << crn)) {
4424 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4425 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4426 }
4427 }
4428 tcg_temp_free_i32(temp);
4429 }
4430 }
4431
4432 /* mtmsr */
4433 #if defined(TARGET_PPC64)
4434 static void gen_mtmsrd(DisasContext *ctx)
4435 {
4436 #if defined(CONFIG_USER_ONLY)
4437 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4438 #else
4439 if (unlikely(ctx->pr)) {
4440 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4441 return;
4442 }
4443 if (ctx->opcode & 0x00010000) {
4444 /* Special form that does not need any synchronisation */
4445 TCGv t0 = tcg_temp_new();
4446 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4447 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4448 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4449 tcg_temp_free(t0);
4450 } else {
4451 /* XXX: we need to update nip before the store
4452 * if we enter power saving mode, we will exit the loop
4453 * directly from ppc_store_msr
4454 */
4455 gen_update_nip(ctx, ctx->nip);
4456 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4457 /* Must stop the translation as machine state (may have) changed */
4458 /* Note that mtmsr is not always defined as context-synchronizing */
4459 gen_stop_exception(ctx);
4460 }
4461 #endif
4462 }
4463 #endif
4464
4465 static void gen_mtmsr(DisasContext *ctx)
4466 {
4467 #if defined(CONFIG_USER_ONLY)
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4469 #else
4470 if (unlikely(ctx->pr)) {
4471 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4472 return;
4473 }
4474 if (ctx->opcode & 0x00010000) {
4475 /* Special form that does not need any synchronisation */
4476 TCGv t0 = tcg_temp_new();
4477 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4478 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE)));
4479 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4480 tcg_temp_free(t0);
4481 } else {
4482 TCGv msr = tcg_temp_new();
4483
4484 /* XXX: we need to update nip before the store
4485 * if we enter power saving mode, we will exit the loop
4486 * directly from ppc_store_msr
4487 */
4488 gen_update_nip(ctx, ctx->nip);
4489 #if defined(TARGET_PPC64)
4490 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4491 #else
4492 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4493 #endif
4494 gen_helper_store_msr(cpu_env, msr);
4495 tcg_temp_free(msr);
4496 /* Must stop the translation as machine state (may have) changed */
4497 /* Note that mtmsr is not always defined as context-synchronizing */
4498 gen_stop_exception(ctx);
4499 }
4500 #endif
4501 }
4502
4503 /* mtspr */
4504 static void gen_mtspr(DisasContext *ctx)
4505 {
4506 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4507 uint32_t sprn = SPR(ctx->opcode);
4508
4509 #if defined(CONFIG_USER_ONLY)
4510 write_cb = ctx->spr_cb[sprn].uea_write;
4511 #else
4512 if (ctx->pr) {
4513 write_cb = ctx->spr_cb[sprn].uea_write;
4514 } else if (ctx->hv) {
4515 write_cb = ctx->spr_cb[sprn].hea_write;
4516 } else {
4517 write_cb = ctx->spr_cb[sprn].oea_write;
4518 }
4519 #endif
4520 if (likely(write_cb != NULL)) {
4521 if (likely(write_cb != SPR_NOACCESS)) {
4522 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4523 } else {
4524 /* Privilege exception */
4525 fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4526 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4527 if (qemu_log_separate()) {
4528 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4529 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4530 }
4531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4532 }
4533 } else {
4534 /* Not defined */
4535 if (qemu_log_separate()) {
4536 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4537 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4538 }
4539 fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4540 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4541
4542 /* Only generate an exception in user space, otherwise this is a nop */
4543 if (ctx->pr) {
4544 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4545 }
4546 }
4547 }
4548
4549 /*** Cache management ***/
4550
4551 /* dcbf */
4552 static void gen_dcbf(DisasContext *ctx)
4553 {
4554 /* XXX: specification says this is treated as a load by the MMU */
4555 TCGv t0;
4556 gen_set_access_type(ctx, ACCESS_CACHE);
4557 t0 = tcg_temp_new();
4558 gen_addr_reg_index(ctx, t0);
4559 gen_qemu_ld8u(ctx, t0, t0);
4560 tcg_temp_free(t0);
4561 }
4562
4563 /* dcbi (Supervisor only) */
4564 static void gen_dcbi(DisasContext *ctx)
4565 {
4566 #if defined(CONFIG_USER_ONLY)
4567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4568 #else
4569 TCGv EA, val;
4570 if (unlikely(ctx->pr)) {
4571 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4572 return;
4573 }
4574 EA = tcg_temp_new();
4575 gen_set_access_type(ctx, ACCESS_CACHE);
4576 gen_addr_reg_index(ctx, EA);
4577 val = tcg_temp_new();
4578 /* XXX: specification says this should be treated as a store by the MMU */
4579 gen_qemu_ld8u(ctx, val, EA);
4580 gen_qemu_st8(ctx, val, EA);
4581 tcg_temp_free(val);
4582 tcg_temp_free(EA);
4583 #endif
4584 }
4585
4586 /* dcdst */
4587 static void gen_dcbst(DisasContext *ctx)
4588 {
4589 /* XXX: specification say this is treated as a load by the MMU */
4590 TCGv t0;
4591 gen_set_access_type(ctx, ACCESS_CACHE);
4592 t0 = tcg_temp_new();
4593 gen_addr_reg_index(ctx, t0);
4594 gen_qemu_ld8u(ctx, t0, t0);
4595 tcg_temp_free(t0);
4596 }
4597
4598 /* dcbt */
4599 static void gen_dcbt(DisasContext *ctx)
4600 {
4601 /* interpreted as no-op */
4602 /* XXX: specification say this is treated as a load by the MMU
4603 * but does not generate any exception
4604 */
4605 }
4606
4607 /* dcbtst */
4608 static void gen_dcbtst(DisasContext *ctx)
4609 {
4610 /* interpreted as no-op */
4611 /* XXX: specification say this is treated as a load by the MMU
4612 * but does not generate any exception
4613 */
4614 }
4615
4616 /* dcbtls */
4617 static void gen_dcbtls(DisasContext *ctx)
4618 {
4619 /* Always fails locking the cache */
4620 TCGv t0 = tcg_temp_new();
4621 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4622 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4623 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4624 tcg_temp_free(t0);
4625 }
4626
4627 /* dcbz */
4628 static void gen_dcbz(DisasContext *ctx)
4629 {
4630 TCGv tcgv_addr;
4631 TCGv_i32 tcgv_is_dcbzl;
4632 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4633
4634 gen_set_access_type(ctx, ACCESS_CACHE);
4635 /* NIP cannot be restored if the memory exception comes from an helper */
4636 gen_update_nip(ctx, ctx->nip - 4);
4637 tcgv_addr = tcg_temp_new();
4638 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4639
4640 gen_addr_reg_index(ctx, tcgv_addr);
4641 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4642
4643 tcg_temp_free(tcgv_addr);
4644 tcg_temp_free_i32(tcgv_is_dcbzl);
4645 }
4646
4647 /* dst / dstt */
4648 static void gen_dst(DisasContext *ctx)
4649 {
4650 if (rA(ctx->opcode) == 0) {
4651 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4652 } else {
4653 /* interpreted as no-op */
4654 }
4655 }
4656
4657 /* dstst /dststt */
4658 static void gen_dstst(DisasContext *ctx)
4659 {
4660 if (rA(ctx->opcode) == 0) {
4661 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4662 } else {
4663 /* interpreted as no-op */
4664 }
4665
4666 }
4667
4668 /* dss / dssall */
4669 static void gen_dss(DisasContext *ctx)
4670 {
4671 /* interpreted as no-op */
4672 }
4673
4674 /* icbi */
4675 static void gen_icbi(DisasContext *ctx)
4676 {
4677 TCGv t0;
4678 gen_set_access_type(ctx, ACCESS_CACHE);
4679 /* NIP cannot be restored if the memory exception comes from an helper */
4680 gen_update_nip(ctx, ctx->nip - 4);
4681 t0 = tcg_temp_new();
4682 gen_addr_reg_index(ctx, t0);
4683 gen_helper_icbi(cpu_env, t0);
4684 tcg_temp_free(t0);
4685 }
4686
4687 /* Optional: */
4688 /* dcba */
4689 static void gen_dcba(DisasContext *ctx)
4690 {
4691 /* interpreted as no-op */
4692 /* XXX: specification say this is treated as a store by the MMU
4693 * but does not generate any exception
4694 */
4695 }
4696
4697 /*** Segment register manipulation ***/
4698 /* Supervisor only: */
4699
4700 /* mfsr */
4701 static void gen_mfsr(DisasContext *ctx)
4702 {
4703 #if defined(CONFIG_USER_ONLY)
4704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4705 #else
4706 TCGv t0;
4707 if (unlikely(ctx->pr)) {
4708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4709 return;
4710 }
4711 t0 = tcg_const_tl(SR(ctx->opcode));
4712 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4713 tcg_temp_free(t0);
4714 #endif
4715 }
4716
4717 /* mfsrin */
4718 static void gen_mfsrin(DisasContext *ctx)
4719 {
4720 #if defined(CONFIG_USER_ONLY)
4721 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4722 #else
4723 TCGv t0;
4724 if (unlikely(ctx->pr)) {
4725 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4726 return;
4727 }
4728 t0 = tcg_temp_new();
4729 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4730 tcg_gen_andi_tl(t0, t0, 0xF);
4731 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4732 tcg_temp_free(t0);
4733 #endif
4734 }
4735
4736 /* mtsr */
4737 static void gen_mtsr(DisasContext *ctx)
4738 {
4739 #if defined(CONFIG_USER_ONLY)
4740 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4741 #else
4742 TCGv t0;
4743 if (unlikely(ctx->pr)) {
4744 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4745 return;
4746 }
4747 t0 = tcg_const_tl(SR(ctx->opcode));
4748 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4749 tcg_temp_free(t0);
4750 #endif
4751 }
4752
4753 /* mtsrin */
4754 static void gen_mtsrin(DisasContext *ctx)
4755 {
4756 #if defined(CONFIG_USER_ONLY)
4757 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4758 #else
4759 TCGv t0;
4760 if (unlikely(ctx->pr)) {
4761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4762 return;
4763 }
4764 t0 = tcg_temp_new();
4765 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4766 tcg_gen_andi_tl(t0, t0, 0xF);
4767 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4768 tcg_temp_free(t0);
4769 #endif
4770 }
4771
4772 #if defined(TARGET_PPC64)
4773 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4774
4775 /* mfsr */
4776 static void gen_mfsr_64b(DisasContext *ctx)
4777 {
4778 #if defined(CONFIG_USER_ONLY)
4779 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4780 #else
4781 TCGv t0;
4782 if (unlikely(ctx->pr)) {
4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4784 return;
4785 }
4786 t0 = tcg_const_tl(SR(ctx->opcode));
4787 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4788 tcg_temp_free(t0);
4789 #endif
4790 }
4791
4792 /* mfsrin */
4793 static void gen_mfsrin_64b(DisasContext *ctx)
4794 {
4795 #if defined(CONFIG_USER_ONLY)
4796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4797 #else
4798 TCGv t0;
4799 if (unlikely(ctx->pr)) {
4800 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4801 return;
4802 }
4803 t0 = tcg_temp_new();
4804 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4805 tcg_gen_andi_tl(t0, t0, 0xF);
4806 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4807 tcg_temp_free(t0);
4808 #endif
4809 }
4810
4811 /* mtsr */
4812 static void gen_mtsr_64b(DisasContext *ctx)
4813 {
4814 #if defined(CONFIG_USER_ONLY)
4815 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4816 #else
4817 TCGv t0;
4818 if (unlikely(ctx->pr)) {
4819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4820 return;
4821 }
4822 t0 = tcg_const_tl(SR(ctx->opcode));
4823 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4824 tcg_temp_free(t0);
4825 #endif
4826 }
4827
4828 /* mtsrin */
4829 static void gen_mtsrin_64b(DisasContext *ctx)
4830 {
4831 #if defined(CONFIG_USER_ONLY)
4832 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4833 #else
4834 TCGv t0;
4835 if (unlikely(ctx->pr)) {
4836 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4837 return;
4838 }
4839 t0 = tcg_temp_new();
4840 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4841 tcg_gen_andi_tl(t0, t0, 0xF);
4842 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4843 tcg_temp_free(t0);
4844 #endif
4845 }
4846
4847 /* slbmte */
4848 static void gen_slbmte(DisasContext *ctx)
4849 {
4850 #if defined(CONFIG_USER_ONLY)
4851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4852 #else
4853 if (unlikely(ctx->pr)) {
4854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4855 return;
4856 }
4857 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4858 cpu_gpr[rS(ctx->opcode)]);
4859 #endif
4860 }
4861
4862 static void gen_slbmfee(DisasContext *ctx)
4863 {
4864 #if defined(CONFIG_USER_ONLY)
4865 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4866 #else
4867 if (unlikely(ctx->pr)) {
4868 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4869 return;
4870 }
4871 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4872 cpu_gpr[rB(ctx->opcode)]);
4873 #endif
4874 }
4875
4876 static void gen_slbmfev(DisasContext *ctx)
4877 {
4878 #if defined(CONFIG_USER_ONLY)
4879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4880 #else
4881 if (unlikely(ctx->pr)) {
4882 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4883 return;
4884 }
4885 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4886 cpu_gpr[rB(ctx->opcode)]);
4887 #endif
4888 }
4889
4890 static void gen_slbfee_(DisasContext *ctx)
4891 {
4892 #if defined(CONFIG_USER_ONLY)
4893 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4894 #else
4895 TCGLabel *l1, *l2;
4896
4897 if (unlikely(ctx->pr)) {
4898 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4899 return;
4900 }
4901 gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4902 cpu_gpr[rB(ctx->opcode)]);
4903 l1 = gen_new_label();
4904 l2 = gen_new_label();
4905 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
4906 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
4907 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
4908 tcg_gen_br(l2);
4909 gen_set_label(l1);
4910 tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
4911 gen_set_label(l2);
4912 #endif
4913 }
4914 #endif /* defined(TARGET_PPC64) */
4915
4916 /*** Lookaside buffer management ***/
4917 /* Optional & supervisor only: */
4918
4919 /* tlbia */
4920 static void gen_tlbia(DisasContext *ctx)
4921 {
4922 #if defined(CONFIG_USER_ONLY)
4923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4924 #else
4925 if (unlikely(ctx->pr || !ctx->hv)) {
4926 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4927 return;
4928 }
4929 gen_helper_tlbia(cpu_env);
4930 #endif
4931 }
4932
4933 /* tlbiel */
4934 static void gen_tlbiel(DisasContext *ctx)
4935 {
4936 #if defined(CONFIG_USER_ONLY)
4937 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4938 #else
4939 if (unlikely(ctx->pr)) {
4940 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4941 return;
4942 }
4943 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4944 #endif
4945 }
4946
4947 /* tlbie */
4948 static void gen_tlbie(DisasContext *ctx)
4949 {
4950 #if defined(CONFIG_USER_ONLY)
4951 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4952 #else
4953 if (unlikely(ctx->pr || !ctx->hv)) {
4954 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4955 return;
4956 }
4957 if (NARROW_MODE(ctx)) {
4958 TCGv t0 = tcg_temp_new();
4959 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4960 gen_helper_tlbie(cpu_env, t0);
4961 tcg_temp_free(t0);
4962 } else {
4963 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4964 }
4965 #endif
4966 }
4967
4968 /* tlbsync */
4969 static void gen_tlbsync(DisasContext *ctx)
4970 {
4971 #if defined(CONFIG_USER_ONLY)
4972 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4973 #else
4974 if (unlikely(ctx->pr || !ctx->hv)) {
4975 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4976 return;
4977 }
4978 /* tlbsync is a nop for server, ptesync handles delayed tlb flush,
4979 * embedded however needs to deal with tlbsync. We don't try to be
4980 * fancy and swallow the overhead of checking for both.
4981 */
4982 gen_check_tlb_flush(ctx);
4983 #endif
4984 }
4985
4986 #if defined(TARGET_PPC64)
4987 /* slbia */
4988 static void gen_slbia(DisasContext *ctx)
4989 {
4990 #if defined(CONFIG_USER_ONLY)
4991 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4992 #else
4993 if (unlikely(ctx->pr)) {
4994 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4995 return;
4996 }
4997 gen_helper_slbia(cpu_env);
4998 #endif
4999 }
5000
5001 /* slbie */
5002 static void gen_slbie(DisasContext *ctx)
5003 {
5004 #if defined(CONFIG_USER_ONLY)
5005 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5006 #else
5007 if (unlikely(ctx->pr)) {
5008 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5009 return;
5010 }
5011 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5012 #endif
5013 }
5014 #endif
5015
5016 /*** External control ***/
5017 /* Optional: */
5018
5019 /* eciwx */
5020 static void gen_eciwx(DisasContext *ctx)
5021 {
5022 TCGv t0;
5023 /* Should check EAR[E] ! */
5024 gen_set_access_type(ctx, ACCESS_EXT);
5025 t0 = tcg_temp_new();
5026 gen_addr_reg_index(ctx, t0);
5027 gen_check_align(ctx, t0, 0x03);
5028 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5029 tcg_temp_free(t0);
5030 }
5031
5032 /* ecowx */
5033 static void gen_ecowx(DisasContext *ctx)
5034 {
5035 TCGv t0;
5036 /* Should check EAR[E] ! */
5037 gen_set_access_type(ctx, ACCESS_EXT);
5038 t0 = tcg_temp_new();
5039 gen_addr_reg_index(ctx, t0);
5040 gen_check_align(ctx, t0, 0x03);
5041 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
5042 tcg_temp_free(t0);
5043 }
5044
5045 /* PowerPC 601 specific instructions */
5046
5047 /* abs - abs. */
5048 static void gen_abs(DisasContext *ctx)
5049 {
5050 TCGLabel *l1 = gen_new_label();
5051 TCGLabel *l2 = gen_new_label();
5052 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
5053 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5054 tcg_gen_br(l2);
5055 gen_set_label(l1);
5056 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5057 gen_set_label(l2);
5058 if (unlikely(Rc(ctx->opcode) != 0))
5059 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5060 }
5061
5062 /* abso - abso. */
5063 static void gen_abso(DisasContext *ctx)
5064 {
5065 TCGLabel *l1 = gen_new_label();
5066 TCGLabel *l2 = gen_new_label();
5067 TCGLabel *l3 = gen_new_label();
5068 /* Start with XER OV disabled, the most likely case */
5069 tcg_gen_movi_tl(cpu_ov, 0);
5070 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
5071 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
5072 tcg_gen_movi_tl(cpu_ov, 1);
5073 tcg_gen_movi_tl(cpu_so, 1);
5074 tcg_gen_br(l2);
5075 gen_set_label(l1);
5076 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5077 tcg_gen_br(l3);
5078 gen_set_label(l2);
5079 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5080 gen_set_label(l3);
5081 if (unlikely(Rc(ctx->opcode) != 0))
5082 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5083 }
5084
5085 /* clcs */
5086 static void gen_clcs(DisasContext *ctx)
5087 {
5088 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
5089 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5090 tcg_temp_free_i32(t0);
5091 /* Rc=1 sets CR0 to an undefined state */
5092 }
5093
5094 /* div - div. */
5095 static void gen_div(DisasContext *ctx)
5096 {
5097 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5098 cpu_gpr[rB(ctx->opcode)]);
5099 if (unlikely(Rc(ctx->opcode) != 0))
5100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5101 }
5102
5103 /* divo - divo. */
5104 static void gen_divo(DisasContext *ctx)
5105 {
5106 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5107 cpu_gpr[rB(ctx->opcode)]);
5108 if (unlikely(Rc(ctx->opcode) != 0))
5109 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5110 }
5111
5112 /* divs - divs. */
5113 static void gen_divs(DisasContext *ctx)
5114 {
5115 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
5116 cpu_gpr[rB(ctx->opcode)]);
5117 if (unlikely(Rc(ctx->opcode) != 0))
5118 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5119 }
5120
5121 /* divso - divso. */
5122 static void gen_divso(DisasContext *ctx)
5123 {
5124 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5125 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5126 if (unlikely(Rc(ctx->opcode) != 0))
5127 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5128 }
5129
5130 /* doz - doz. */
5131 static void gen_doz(DisasContext *ctx)
5132 {
5133 TCGLabel *l1 = gen_new_label();
5134 TCGLabel *l2 = gen_new_label();
5135 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5136 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5137 tcg_gen_br(l2);
5138 gen_set_label(l1);
5139 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5140 gen_set_label(l2);
5141 if (unlikely(Rc(ctx->opcode) != 0))
5142 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5143 }
5144
5145 /* dozo - dozo. */
5146 static void gen_dozo(DisasContext *ctx)
5147 {
5148 TCGLabel *l1 = gen_new_label();
5149 TCGLabel *l2 = gen_new_label();
5150 TCGv t0 = tcg_temp_new();
5151 TCGv t1 = tcg_temp_new();
5152 TCGv t2 = tcg_temp_new();
5153 /* Start with XER OV disabled, the most likely case */
5154 tcg_gen_movi_tl(cpu_ov, 0);
5155 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5156 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5157 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5158 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5159 tcg_gen_andc_tl(t1, t1, t2);
5160 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5161 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5162 tcg_gen_movi_tl(cpu_ov, 1);
5163 tcg_gen_movi_tl(cpu_so, 1);
5164 tcg_gen_br(l2);
5165 gen_set_label(l1);
5166 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5167 gen_set_label(l2);
5168 tcg_temp_free(t0);
5169 tcg_temp_free(t1);
5170 tcg_temp_free(t2);
5171 if (unlikely(Rc(ctx->opcode) != 0))
5172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5173 }
5174
5175 /* dozi */
5176 static void gen_dozi(DisasContext *ctx)
5177 {
5178 target_long simm = SIMM(ctx->opcode);
5179 TCGLabel *l1 = gen_new_label();
5180 TCGLabel *l2 = gen_new_label();
5181 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5182 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5183 tcg_gen_br(l2);
5184 gen_set_label(l1);
5185 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5186 gen_set_label(l2);
5187 if (unlikely(Rc(ctx->opcode) != 0))
5188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5189 }
5190
5191 /* lscbx - lscbx. */
5192 static void gen_lscbx(DisasContext *ctx)
5193 {
5194 TCGv t0 = tcg_temp_new();
5195 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5196 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5197 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5198
5199 gen_addr_reg_index(ctx, t0);
5200 /* NIP cannot be restored if the memory exception comes from an helper */
5201 gen_update_nip(ctx, ctx->nip - 4);
5202 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5203 tcg_temp_free_i32(t1);
5204 tcg_temp_free_i32(t2);
5205 tcg_temp_free_i32(t3);
5206 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5207 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5208 if (unlikely(Rc(ctx->opcode) != 0))
5209 gen_set_Rc0(ctx, t0);
5210 tcg_temp_free(t0);
5211 }
5212
5213 /* maskg - maskg. */
5214 static void gen_maskg(DisasContext *ctx)
5215 {
5216 TCGLabel *l1 = gen_new_label();
5217 TCGv t0 = tcg_temp_new();
5218 TCGv t1 = tcg_temp_new();
5219 TCGv t2 = tcg_temp_new();
5220 TCGv t3 = tcg_temp_new();
5221 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5222 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5223 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5224 tcg_gen_addi_tl(t2, t0, 1);
5225 tcg_gen_shr_tl(t2, t3, t2);
5226 tcg_gen_shr_tl(t3, t3, t1);
5227 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5228 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5229 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5230 gen_set_label(l1);
5231 tcg_temp_free(t0);
5232 tcg_temp_free(t1);
5233 tcg_temp_free(t2);
5234 tcg_temp_free(t3);
5235 if (unlikely(Rc(ctx->opcode) != 0))
5236 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5237 }
5238
5239 /* maskir - maskir. */
5240 static void gen_maskir(DisasContext *ctx)
5241 {
5242 TCGv t0 = tcg_temp_new();
5243 TCGv t1 = tcg_temp_new();
5244 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5245 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5246 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5247 tcg_temp_free(t0);
5248 tcg_temp_free(t1);
5249 if (unlikely(Rc(ctx->opcode) != 0))
5250 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5251 }
5252
5253 /* mul - mul. */
5254 static void gen_mul(DisasContext *ctx)
5255 {
5256 TCGv_i64 t0 = tcg_temp_new_i64();
5257 TCGv_i64 t1 = tcg_temp_new_i64();
5258 TCGv t2 = tcg_temp_new();
5259 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5260 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5261 tcg_gen_mul_i64(t0, t0, t1);
5262 tcg_gen_trunc_i64_tl(t2, t0);
5263 gen_store_spr(SPR_MQ, t2);
5264 tcg_gen_shri_i64(t1, t0, 32);
5265 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5266 tcg_temp_free_i64(t0);
5267 tcg_temp_free_i64(t1);
5268 tcg_temp_free(t2);
5269 if (unlikely(Rc(ctx->opcode) != 0))
5270 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5271 }
5272
5273 /* mulo - mulo. */
5274 static void gen_mulo(DisasContext *ctx)
5275 {
5276 TCGLabel *l1 = gen_new_label();
5277 TCGv_i64 t0 = tcg_temp_new_i64();
5278 TCGv_i64 t1 = tcg_temp_new_i64();
5279 TCGv t2 = tcg_temp_new();
5280 /* Start with XER OV disabled, the most likely case */
5281 tcg_gen_movi_tl(cpu_ov, 0);
5282 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5283 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5284 tcg_gen_mul_i64(t0, t0, t1);
5285 tcg_gen_trunc_i64_tl(t2, t0);
5286 gen_store_spr(SPR_MQ, t2);
5287 tcg_gen_shri_i64(t1, t0, 32);
5288 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5289 tcg_gen_ext32s_i64(t1, t0);
5290 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5291 tcg_gen_movi_tl(cpu_ov, 1);
5292 tcg_gen_movi_tl(cpu_so, 1);
5293 gen_set_label(l1);
5294 tcg_temp_free_i64(t0);
5295 tcg_temp_free_i64(t1);
5296 tcg_temp_free(t2);
5297 if (unlikely(Rc(ctx->opcode) != 0))
5298 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5299 }
5300
5301 /* nabs - nabs. */
5302 static void gen_nabs(DisasContext *ctx)
5303 {
5304 TCGLabel *l1 = gen_new_label();
5305 TCGLabel *l2 = gen_new_label();
5306 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5307 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5308 tcg_gen_br(l2);
5309 gen_set_label(l1);
5310 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5311 gen_set_label(l2);
5312 if (unlikely(Rc(ctx->opcode) != 0))
5313 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5314 }
5315
5316 /* nabso - nabso. */
5317 static void gen_nabso(DisasContext *ctx)
5318 {
5319 TCGLabel *l1 = gen_new_label();
5320 TCGLabel *l2 = gen_new_label();
5321 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5322 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5323 tcg_gen_br(l2);
5324 gen_set_label(l1);
5325 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5326 gen_set_label(l2);
5327 /* nabs never overflows */
5328 tcg_gen_movi_tl(cpu_ov, 0);
5329 if (unlikely(Rc(ctx->opcode) != 0))
5330 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5331 }
5332
5333 /* rlmi - rlmi. */
5334 static void gen_rlmi(DisasContext *ctx)
5335 {
5336 uint32_t mb = MB(ctx->opcode);
5337 uint32_t me = ME(ctx->opcode);
5338 TCGv t0 = tcg_temp_new();
5339 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5340 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5341 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5342 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5343 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5344 tcg_temp_free(t0);
5345 if (unlikely(Rc(ctx->opcode) != 0))
5346 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5347 }
5348
5349 /* rrib - rrib. */
5350 static void gen_rrib(DisasContext *ctx)
5351 {
5352 TCGv t0 = tcg_temp_new();
5353 TCGv t1 = tcg_temp_new();
5354 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5355 tcg_gen_movi_tl(t1, 0x80000000);
5356 tcg_gen_shr_tl(t1, t1, t0);
5357 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5358 tcg_gen_and_tl(t0, t0, t1);
5359 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5360 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5361 tcg_temp_free(t0);
5362 tcg_temp_free(t1);
5363 if (unlikely(Rc(ctx->opcode) != 0))
5364 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5365 }
5366
5367 /* sle - sle. */
5368 static void gen_sle(DisasContext *ctx)
5369 {
5370 TCGv t0 = tcg_temp_new();
5371 TCGv t1 = tcg_temp_new();
5372 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5373 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5374 tcg_gen_subfi_tl(t1, 32, t1);
5375 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5376 tcg_gen_or_tl(t1, t0, t1);
5377 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5378 gen_store_spr(SPR_MQ, t1);
5379 tcg_temp_free(t0);
5380 tcg_temp_free(t1);
5381 if (unlikely(Rc(ctx->opcode) != 0))
5382 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5383 }
5384
5385 /* sleq - sleq. */
5386 static void gen_sleq(DisasContext *ctx)
5387 {
5388 TCGv t0 = tcg_temp_new();
5389 TCGv t1 = tcg_temp_new();
5390 TCGv t2 = tcg_temp_new();
5391 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5392 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5393 tcg_gen_shl_tl(t2, t2, t0);
5394 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5395 gen_load_spr(t1, SPR_MQ);
5396 gen_store_spr(SPR_MQ, t0);
5397 tcg_gen_and_tl(t0, t0, t2);
5398 tcg_gen_andc_tl(t1, t1, t2);
5399 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5400 tcg_temp_free(t0);
5401 tcg_temp_free(t1);
5402 tcg_temp_free(t2);
5403 if (unlikely(Rc(ctx->opcode) != 0))
5404 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5405 }
5406
5407 /* sliq - sliq. */
5408 static void gen_sliq(DisasContext *ctx)
5409 {
5410 int sh = SH(ctx->opcode);
5411 TCGv t0 = tcg_temp_new();
5412 TCGv t1 = tcg_temp_new();
5413 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5414 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5415 tcg_gen_or_tl(t1, t0, t1);
5416 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5417 gen_store_spr(SPR_MQ, t1);
5418 tcg_temp_free(t0);
5419 tcg_temp_free(t1);
5420 if (unlikely(Rc(ctx->opcode) != 0))
5421 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5422 }
5423
5424 /* slliq - slliq. */
5425 static void gen_slliq(DisasContext *ctx)
5426 {
5427 int sh = SH(ctx->opcode);
5428 TCGv t0 = tcg_temp_new();
5429 TCGv t1 = tcg_temp_new();
5430 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5431 gen_load_spr(t1, SPR_MQ);
5432 gen_store_spr(SPR_MQ, t0);
5433 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5434 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5435 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5436 tcg_temp_free(t0);
5437 tcg_temp_free(t1);
5438 if (unlikely(Rc(ctx->opcode) != 0))
5439 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5440 }
5441
5442 /* sllq - sllq. */
5443 static void gen_sllq(DisasContext *ctx)
5444 {
5445 TCGLabel *l1 = gen_new_label();
5446 TCGLabel *l2 = gen_new_label();
5447 TCGv t0 = tcg_temp_local_new();
5448 TCGv t1 = tcg_temp_local_new();
5449 TCGv t2 = tcg_temp_local_new();
5450 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5451 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5452 tcg_gen_shl_tl(t1, t1, t2);
5453 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5454 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5455 gen_load_spr(t0, SPR_MQ);
5456 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5457 tcg_gen_br(l2);
5458 gen_set_label(l1);
5459 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5460 gen_load_spr(t2, SPR_MQ);
5461 tcg_gen_andc_tl(t1, t2, t1);
5462 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5463 gen_set_label(l2);
5464 tcg_temp_free(t0);
5465 tcg_temp_free(t1);
5466 tcg_temp_free(t2);
5467 if (unlikely(Rc(ctx->opcode) != 0))
5468 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5469 }
5470
5471 /* slq - slq. */
5472 static void gen_slq(DisasContext *ctx)
5473 {
5474 TCGLabel *l1 = gen_new_label();
5475 TCGv t0 = tcg_temp_new();
5476 TCGv t1 = tcg_temp_new();
5477 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5478 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5479 tcg_gen_subfi_tl(t1, 32, t1);
5480 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5481 tcg_gen_or_tl(t1, t0, t1);
5482 gen_store_spr(SPR_MQ, t1);
5483 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5484 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5485 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5486 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5487 gen_set_label(l1);
5488 tcg_temp_free(t0);
5489 tcg_temp_free(t1);
5490 if (unlikely(Rc(ctx->opcode) != 0))
5491 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5492 }
5493
5494 /* sraiq - sraiq. */
5495 static void gen_sraiq(DisasContext *ctx)
5496 {
5497 int sh = SH(ctx->opcode);
5498 TCGLabel *l1 = gen_new_label();
5499 TCGv t0 = tcg_temp_new();
5500 TCGv t1 = tcg_temp_new();
5501 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5502 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5503 tcg_gen_or_tl(t0, t0, t1);
5504 gen_store_spr(SPR_MQ, t0);
5505 tcg_gen_movi_tl(cpu_ca, 0);
5506 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5507 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5508 tcg_gen_movi_tl(cpu_ca, 1);
5509 gen_set_label(l1);
5510 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5511 tcg_temp_free(t0);
5512 tcg_temp_free(t1);
5513 if (unlikely(Rc(ctx->opcode) != 0))
5514 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5515 }
5516
5517 /* sraq - sraq. */
5518 static void gen_sraq(DisasContext *ctx)
5519 {
5520 TCGLabel *l1 = gen_new_label();
5521 TCGLabel *l2 = gen_new_label();
5522 TCGv t0 = tcg_temp_new();
5523 TCGv t1 = tcg_temp_local_new();
5524 TCGv t2 = tcg_temp_local_new();
5525 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5526 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5527 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5528 tcg_gen_subfi_tl(t2, 32, t2);
5529 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5530 tcg_gen_or_tl(t0, t0, t2);
5531 gen_store_spr(SPR_MQ, t0);
5532 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5533 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5534 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5535 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5536 gen_set_label(l1);
5537 tcg_temp_free(t0);
5538 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5539 tcg_gen_movi_tl(cpu_ca, 0);
5540 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5541 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5542 tcg_gen_movi_tl(cpu_ca, 1);
5543 gen_set_label(l2);
5544 tcg_temp_free(t1);
5545 tcg_temp_free(t2);
5546 if (unlikely(Rc(ctx->opcode) != 0))
5547 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5548 }
5549
5550 /* sre - sre. */
5551 static void gen_sre(DisasContext *ctx)
5552 {
5553 TCGv t0 = tcg_temp_new();
5554 TCGv t1 = tcg_temp_new();
5555 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5556 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5557 tcg_gen_subfi_tl(t1, 32, t1);
5558 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5559 tcg_gen_or_tl(t1, t0, t1);
5560 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5561 gen_store_spr(SPR_MQ, t1);
5562 tcg_temp_free(t0);
5563 tcg_temp_free(t1);
5564 if (unlikely(Rc(ctx->opcode) != 0))
5565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5566 }
5567
5568 /* srea - srea. */
5569 static void gen_srea(DisasContext *ctx)
5570 {
5571 TCGv t0 = tcg_temp_new();
5572 TCGv t1 = tcg_temp_new();
5573 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5574 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5575 gen_store_spr(SPR_MQ, t0);
5576 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5577 tcg_temp_free(t0);
5578 tcg_temp_free(t1);
5579 if (unlikely(Rc(ctx->opcode) != 0))
5580 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5581 }
5582
5583 /* sreq */
5584 static void gen_sreq(DisasContext *ctx)
5585 {
5586 TCGv t0 = tcg_temp_new();
5587 TCGv t1 = tcg_temp_new();
5588 TCGv t2 = tcg_temp_new();
5589 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5590 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5591 tcg_gen_shr_tl(t1, t1, t0);
5592 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5593 gen_load_spr(t2, SPR_MQ);
5594 gen_store_spr(SPR_MQ, t0);
5595 tcg_gen_and_tl(t0, t0, t1);
5596 tcg_gen_andc_tl(t2, t2, t1);
5597 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5598 tcg_temp_free(t0);
5599 tcg_temp_free(t1);
5600 tcg_temp_free(t2);
5601 if (unlikely(Rc(ctx->opcode) != 0))
5602 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5603 }
5604
5605 /* sriq */
5606 static void gen_sriq(DisasContext *ctx)
5607 {
5608 int sh = SH(ctx->opcode);
5609 TCGv t0 = tcg_temp_new();
5610 TCGv t1 = tcg_temp_new();
5611 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5612 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5613 tcg_gen_or_tl(t1, t0, t1);
5614 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5615 gen_store_spr(SPR_MQ, t1);
5616 tcg_temp_free(t0);
5617 tcg_temp_free(t1);
5618 if (unlikely(Rc(ctx->opcode) != 0))
5619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5620 }
5621
5622 /* srliq */
5623 static void gen_srliq(DisasContext *ctx)
5624 {
5625 int sh = SH(ctx->opcode);
5626 TCGv t0 = tcg_temp_new();
5627 TCGv t1 = tcg_temp_new();
5628 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5629 gen_load_spr(t1, SPR_MQ);
5630 gen_store_spr(SPR_MQ, t0);
5631 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5632 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5633 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5634 tcg_temp_free(t0);
5635 tcg_temp_free(t1);
5636 if (unlikely(Rc(ctx->opcode) != 0))
5637 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5638 }
5639
5640 /* srlq */
5641 static void gen_srlq(DisasContext *ctx)
5642 {
5643 TCGLabel *l1 = gen_new_label();
5644 TCGLabel *l2 = gen_new_label();
5645 TCGv t0 = tcg_temp_local_new();
5646 TCGv t1 = tcg_temp_local_new();
5647 TCGv t2 = tcg_temp_local_new();
5648 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5649 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5650 tcg_gen_shr_tl(t2, t1, t2);
5651 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5652 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5653 gen_load_spr(t0, SPR_MQ);
5654 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5655 tcg_gen_br(l2);
5656 gen_set_label(l1);
5657 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5658 tcg_gen_and_tl(t0, t0, t2);
5659 gen_load_spr(t1, SPR_MQ);
5660 tcg_gen_andc_tl(t1, t1, t2);
5661 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5662 gen_set_label(l2);
5663 tcg_temp_free(t0);
5664 tcg_temp_free(t1);
5665 tcg_temp_free(t2);
5666 if (unlikely(Rc(ctx->opcode) != 0))
5667 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5668 }
5669
5670 /* srq */
5671 static void gen_srq(DisasContext *ctx)
5672 {
5673 TCGLabel *l1 = gen_new_label();
5674 TCGv t0 = tcg_temp_new();
5675 TCGv t1 = tcg_temp_new();
5676 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5677 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5678 tcg_gen_subfi_tl(t1, 32, t1);
5679 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5680 tcg_gen_or_tl(t1, t0, t1);
5681 gen_store_spr(SPR_MQ, t1);
5682 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5683 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5684 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5685 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5686 gen_set_label(l1);
5687 tcg_temp_free(t0);
5688 tcg_temp_free(t1);
5689 if (unlikely(Rc(ctx->opcode) != 0))
5690 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5691 }
5692
5693 /* PowerPC 602 specific instructions */
5694
5695 /* dsa */
5696 static void gen_dsa(DisasContext *ctx)
5697 {
5698 /* XXX: TODO */
5699 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5700 }
5701
5702 /* esa */
5703 static void gen_esa(DisasContext *ctx)
5704 {
5705 /* XXX: TODO */
5706 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5707 }
5708
5709 /* mfrom */
5710 static void gen_mfrom(DisasContext *ctx)
5711 {
5712 #if defined(CONFIG_USER_ONLY)
5713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5714 #else
5715 if (unlikely(ctx->pr)) {
5716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5717 return;
5718 }
5719 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5720 #endif
5721 }
5722
5723 /* 602 - 603 - G2 TLB management */
5724
5725 /* tlbld */
5726 static void gen_tlbld_6xx(DisasContext *ctx)
5727 {
5728 #if defined(CONFIG_USER_ONLY)
5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5730 #else
5731 if (unlikely(ctx->pr)) {
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 return;
5734 }
5735 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5736 #endif
5737 }
5738
5739 /* tlbli */
5740 static void gen_tlbli_6xx(DisasContext *ctx)
5741 {
5742 #if defined(CONFIG_USER_ONLY)
5743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5744 #else
5745 if (unlikely(ctx->pr)) {
5746 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5747 return;
5748 }
5749 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5750 #endif
5751 }
5752
5753 /* 74xx TLB management */
5754
5755 /* tlbld */
5756 static void gen_tlbld_74xx(DisasContext *ctx)
5757 {
5758 #if defined(CONFIG_USER_ONLY)
5759 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5760 #else
5761 if (unlikely(ctx->pr)) {
5762 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5763 return;
5764 }
5765 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5766 #endif
5767 }
5768
5769 /* tlbli */
5770 static void gen_tlbli_74xx(DisasContext *ctx)
5771 {
5772 #if defined(CONFIG_USER_ONLY)
5773 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5774 #else
5775 if (unlikely(ctx->pr)) {
5776 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5777 return;
5778 }
5779 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5780 #endif
5781 }
5782
5783 /* POWER instructions not in PowerPC 601 */
5784
5785 /* clf */
5786 static void gen_clf(DisasContext *ctx)
5787 {
5788 /* Cache line flush: implemented as no-op */
5789 }
5790
5791 /* cli */
5792 static void gen_cli(DisasContext *ctx)
5793 {
5794 /* Cache line invalidate: privileged and treated as no-op */
5795 #if defined(CONFIG_USER_ONLY)
5796 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5797 #else
5798 if (unlikely(ctx->pr)) {
5799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5800 return;
5801 }
5802 #endif
5803 }
5804
5805 /* dclst */
5806 static void gen_dclst(DisasContext *ctx)
5807 {
5808 /* Data cache line store: treated as no-op */
5809 }
5810
5811 static void gen_mfsri(DisasContext *ctx)
5812 {
5813 #if defined(CONFIG_USER_ONLY)
5814 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5815 #else
5816 int ra = rA(ctx->opcode);
5817 int rd = rD(ctx->opcode);
5818 TCGv t0;
5819 if (unlikely(ctx->pr)) {
5820 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5821 return;
5822 }
5823 t0 = tcg_temp_new();
5824 gen_addr_reg_index(ctx, t0);
5825 tcg_gen_shri_tl(t0, t0, 28);
5826 tcg_gen_andi_tl(t0, t0, 0xF);
5827 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5828 tcg_temp_free(t0);
5829 if (ra != 0 && ra != rd)
5830 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5831 #endif
5832 }
5833
5834 static void gen_rac(DisasContext *ctx)
5835 {
5836 #if defined(CONFIG_USER_ONLY)
5837 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5838 #else
5839 TCGv t0;
5840 if (unlikely(ctx->pr)) {
5841 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5842 return;
5843 }
5844 t0 = tcg_temp_new();
5845 gen_addr_reg_index(ctx, t0);
5846 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5847 tcg_temp_free(t0);
5848 #endif
5849 }
5850
5851 static void gen_rfsvc(DisasContext *ctx)
5852 {
5853 #if defined(CONFIG_USER_ONLY)
5854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5855 #else
5856 if (unlikely(ctx->pr)) {
5857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5858 return;
5859 }
5860 gen_helper_rfsvc(cpu_env);
5861 gen_sync_exception(ctx);
5862 #endif
5863 }
5864
5865 /* svc is not implemented for now */
5866
5867 /* POWER2 specific instructions */
5868 /* Quad manipulation (load/store two floats at a time) */
5869
5870 /* lfq */
5871 static void gen_lfq(DisasContext *ctx)
5872 {
5873 int rd = rD(ctx->opcode);
5874 TCGv t0;
5875 gen_set_access_type(ctx, ACCESS_FLOAT);
5876 t0 = tcg_temp_new();
5877 gen_addr_imm_index(ctx, t0, 0);
5878 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5879 gen_addr_add(ctx, t0, t0, 8);
5880 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5881 tcg_temp_free(t0);
5882 }
5883
5884 /* lfqu */
5885 static void gen_lfqu(DisasContext *ctx)
5886 {
5887 int ra = rA(ctx->opcode);
5888 int rd = rD(ctx->opcode);
5889 TCGv t0, t1;
5890 gen_set_access_type(ctx, ACCESS_FLOAT);
5891 t0 = tcg_temp_new();
5892 t1 = tcg_temp_new();
5893 gen_addr_imm_index(ctx, t0, 0);
5894 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5895 gen_addr_add(ctx, t1, t0, 8);
5896 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5897 if (ra != 0)
5898 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5899 tcg_temp_free(t0);
5900 tcg_temp_free(t1);
5901 }
5902
5903 /* lfqux */
5904 static void gen_lfqux(DisasContext *ctx)
5905 {
5906 int ra = rA(ctx->opcode);
5907 int rd = rD(ctx->opcode);
5908 gen_set_access_type(ctx, ACCESS_FLOAT);
5909 TCGv t0, t1;
5910 t0 = tcg_temp_new();
5911 gen_addr_reg_index(ctx, t0);
5912 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5913 t1 = tcg_temp_new();
5914 gen_addr_add(ctx, t1, t0, 8);
5915 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5916 tcg_temp_free(t1);
5917 if (ra != 0)
5918 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5919 tcg_temp_free(t0);
5920 }
5921
5922 /* lfqx */
5923 static void gen_lfqx(DisasContext *ctx)
5924 {
5925 int rd = rD(ctx->opcode);
5926 TCGv t0;
5927 gen_set_access_type(ctx, ACCESS_FLOAT);
5928 t0 = tcg_temp_new();
5929 gen_addr_reg_index(ctx, t0);
5930 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5931 gen_addr_add(ctx, t0, t0, 8);
5932 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5933 tcg_temp_free(t0);
5934 }
5935
5936 /* stfq */
5937 static void gen_stfq(DisasContext *ctx)
5938 {
5939 int rd = rD(ctx->opcode);
5940 TCGv t0;
5941 gen_set_access_type(ctx, ACCESS_FLOAT);
5942 t0 = tcg_temp_new();
5943 gen_addr_imm_index(ctx, t0, 0);
5944 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5945 gen_addr_add(ctx, t0, t0, 8);
5946 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5947 tcg_temp_free(t0);
5948 }
5949
5950 /* stfqu */
5951 static void gen_stfqu(DisasContext *ctx)
5952 {
5953 int ra = rA(ctx->opcode);
5954 int rd = rD(ctx->opcode);
5955 TCGv t0, t1;
5956 gen_set_access_type(ctx, ACCESS_FLOAT);
5957 t0 = tcg_temp_new();
5958 gen_addr_imm_index(ctx, t0, 0);
5959 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5960 t1 = tcg_temp_new();
5961 gen_addr_add(ctx, t1, t0, 8);
5962 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5963 tcg_temp_free(t1);
5964 if (ra != 0)
5965 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5966 tcg_temp_free(t0);
5967 }
5968
5969 /* stfqux */
5970 static void gen_stfqux(DisasContext *ctx)
5971 {
5972 int ra = rA(ctx->opcode);
5973 int rd = rD(ctx->opcode);
5974 TCGv t0, t1;
5975 gen_set_access_type(ctx, ACCESS_FLOAT);
5976 t0 = tcg_temp_new();
5977 gen_addr_reg_index(ctx, t0);
5978 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5979 t1 = tcg_temp_new();
5980 gen_addr_add(ctx, t1, t0, 8);
5981 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5982 tcg_temp_free(t1);
5983 if (ra != 0)
5984 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5985 tcg_temp_free(t0);
5986 }
5987
5988 /* stfqx */
5989 static void gen_stfqx(DisasContext *ctx)
5990 {
5991 int rd = rD(ctx->opcode);
5992 TCGv t0;
5993 gen_set_access_type(ctx, ACCESS_FLOAT);
5994 t0 = tcg_temp_new();
5995 gen_addr_reg_index(ctx, t0);
5996 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5997 gen_addr_add(ctx, t0, t0, 8);
5998 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5999 tcg_temp_free(t0);
6000 }
6001
6002 /* BookE specific instructions */
6003
6004 /* XXX: not implemented on 440 ? */
6005 static void gen_mfapidi(DisasContext *ctx)
6006 {
6007 /* XXX: TODO */
6008 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6009 }
6010
6011 /* XXX: not implemented on 440 ? */
6012 static void gen_tlbiva(DisasContext *ctx)
6013 {
6014 #if defined(CONFIG_USER_ONLY)
6015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6016 #else
6017 TCGv t0;
6018 if (unlikely(ctx->pr)) {
6019 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6020 return;
6021 }
6022 t0 = tcg_temp_new();
6023 gen_addr_reg_index(ctx, t0);
6024 gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6025 tcg_temp_free(t0);
6026 #endif
6027 }
6028
6029 /* All 405 MAC instructions are translated here */
6030 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
6031 int ra, int rb, int rt, int Rc)
6032 {
6033 TCGv t0, t1;
6034
6035 t0 = tcg_temp_local_new();
6036 t1 = tcg_temp_local_new();
6037
6038 switch (opc3 & 0x0D) {
6039 case 0x05:
6040 /* macchw - macchw. - macchwo - macchwo. */
6041 /* macchws - macchws. - macchwso - macchwso. */
6042 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
6043 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
6044 /* mulchw - mulchw. */
6045 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6046 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6047 tcg_gen_ext16s_tl(t1, t1);
6048 break;
6049 case 0x04:
6050 /* macchwu - macchwu. - macchwuo - macchwuo. */
6051 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
6052 /* mulchwu - mulchwu. */
6053 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6054 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6055 tcg_gen_ext16u_tl(t1, t1);
6056 break;
6057 case 0x01:
6058 /* machhw - machhw. - machhwo - machhwo. */
6059 /* machhws - machhws. - machhwso - machhwso. */
6060 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
6061 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
6062 /* mulhhw - mulhhw. */
6063 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
6064 tcg_gen_ext16s_tl(t0, t0);
6065 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
6066 tcg_gen_ext16s_tl(t1, t1);
6067 break;
6068 case 0x00:
6069 /* machhwu - machhwu. - machhwuo - machhwuo. */
6070 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
6071 /* mulhhwu - mulhhwu. */
6072 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
6073 tcg_gen_ext16u_tl(t0, t0);
6074 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
6075 tcg_gen_ext16u_tl(t1, t1);
6076 break;
6077 case 0x0D:
6078 /* maclhw - maclhw. - maclhwo - maclhwo. */
6079 /* maclhws - maclhws. - maclhwso - maclhwso. */
6080 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
6081 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
6082 /* mullhw - mullhw. */
6083 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
6084 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
6085 break;
6086 case 0x0C:
6087 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
6088 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
6089 /* mullhwu - mullhwu. */
6090 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
6091 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
6092 break;
6093 }
6094 if (opc2 & 0x04) {
6095 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
6096 tcg_gen_mul_tl(t1, t0, t1);
6097 if (opc2 & 0x02) {
6098 /* nmultiply-and-accumulate (0x0E) */
6099 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
6100 } else {
6101 /* multiply-and-accumulate (0x0C) */
6102 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
6103 }
6104
6105 if (opc3 & 0x12) {
6106 /* Check overflow and/or saturate */
6107 TCGLabel *l1 = gen_new_label();
6108
6109 if (opc3 & 0x10) {
6110 /* Start with XER OV disabled, the most likely case */
6111 tcg_gen_movi_tl(cpu_ov, 0);
6112 }
6113 if (opc3 & 0x01) {
6114 /* Signed */
6115 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
6116 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
6117 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
6118 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
6119 if (opc3 & 0x02) {
6120 /* Saturate */
6121 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
6122 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
6123 }
6124 } else {
6125 /* Unsigned */
6126 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6127 if (opc3 & 0x02) {
6128 /* Saturate */
6129 tcg_gen_movi_tl(t0, UINT32_MAX);
6130 }
6131 }
6132 if (opc3 & 0x10) {
6133 /* Check overflow */
6134 tcg_gen_movi_tl(cpu_ov, 1);
6135 tcg_gen_movi_tl(cpu_so, 1);
6136 }
6137 gen_set_label(l1);
6138 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6139 }
6140 } else {
6141 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6142 }
6143 tcg_temp_free(t0);
6144 tcg_temp_free(t1);
6145 if (unlikely(Rc) != 0) {
6146 /* Update Rc0 */
6147 gen_set_Rc0(ctx, cpu_gpr[rt]);
6148 }
6149 }
6150
6151 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6152 static void glue(gen_, name)(DisasContext *ctx) \
6153 { \
6154 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6155 rD(ctx->opcode), Rc(ctx->opcode)); \
6156 }
6157
6158 /* macchw - macchw. */
6159 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6160 /* macchwo - macchwo. */
6161 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6162 /* macchws - macchws. */
6163 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6164 /* macchwso - macchwso. */
6165 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6166 /* macchwsu - macchwsu. */
6167 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6168 /* macchwsuo - macchwsuo. */
6169 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6170 /* macchwu - macchwu. */
6171 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6172 /* macchwuo - macchwuo. */
6173 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6174 /* machhw - machhw. */
6175 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6176 /* machhwo - machhwo. */
6177 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6178 /* machhws - machhws. */
6179 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6180 /* machhwso - machhwso. */
6181 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6182 /* machhwsu - machhwsu. */
6183 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6184 /* machhwsuo - machhwsuo. */
6185 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6186 /* machhwu - machhwu. */
6187 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6188 /* machhwuo - machhwuo. */
6189 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6190 /* maclhw - maclhw. */
6191 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6192 /* maclhwo - maclhwo. */
6193 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6194 /* maclhws - maclhws. */
6195 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6196 /* maclhwso - maclhwso. */
6197 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6198 /* maclhwu - maclhwu. */
6199 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6200 /* maclhwuo - maclhwuo. */
6201 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6202 /* maclhwsu - maclhwsu. */
6203 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6204 /* maclhwsuo - maclhwsuo. */
6205 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6206 /* nmacchw - nmacchw. */
6207 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6208 /* nmacchwo - nmacchwo. */
6209 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6210 /* nmacchws - nmacchws. */
6211 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6212 /* nmacchwso - nmacchwso. */
6213 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6214 /* nmachhw - nmachhw. */
6215 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6216 /* nmachhwo - nmachhwo. */
6217 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6218 /* nmachhws - nmachhws. */
6219 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6220 /* nmachhwso - nmachhwso. */
6221 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6222 /* nmaclhw - nmaclhw. */
6223 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6224 /* nmaclhwo - nmaclhwo. */
6225 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6226 /* nmaclhws - nmaclhws. */
6227 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6228 /* nmaclhwso - nmaclhwso. */
6229 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6230
6231 /* mulchw - mulchw. */
6232 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6233 /* mulchwu - mulchwu. */
6234 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6235 /* mulhhw - mulhhw. */
6236 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6237 /* mulhhwu - mulhhwu. */
6238 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6239 /* mullhw - mullhw. */
6240 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6241 /* mullhwu - mullhwu. */
6242 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6243
6244 /* mfdcr */
6245 static void gen_mfdcr(DisasContext *ctx)
6246 {
6247 #if defined(CONFIG_USER_ONLY)
6248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6249 #else
6250 TCGv dcrn;
6251 if (unlikely(ctx->pr)) {
6252 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6253 return;
6254 }
6255 /* NIP cannot be restored if the memory exception comes from an helper */
6256 gen_update_nip(ctx, ctx->nip - 4);
6257 dcrn = tcg_const_tl(SPR(ctx->opcode));
6258 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6259 tcg_temp_free(dcrn);
6260 #endif
6261 }
6262
6263 /* mtdcr */
6264 static void gen_mtdcr(DisasContext *ctx)
6265 {
6266 #if defined(CONFIG_USER_ONLY)
6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6268 #else
6269 TCGv dcrn;
6270 if (unlikely(ctx->pr)) {
6271 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6272 return;
6273 }
6274 /* NIP cannot be restored if the memory exception comes from an helper */
6275 gen_update_nip(ctx, ctx->nip - 4);
6276 dcrn = tcg_const_tl(SPR(ctx->opcode));
6277 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6278 tcg_temp_free(dcrn);
6279 #endif
6280 }
6281
6282 /* mfdcrx */
6283 /* XXX: not implemented on 440 ? */
6284 static void gen_mfdcrx(DisasContext *ctx)
6285 {
6286 #if defined(CONFIG_USER_ONLY)
6287 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6288 #else
6289 if (unlikely(ctx->pr)) {
6290 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6291 return;
6292 }
6293 /* NIP cannot be restored if the memory exception comes from an helper */
6294 gen_update_nip(ctx, ctx->nip - 4);
6295 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6296 cpu_gpr[rA(ctx->opcode)]);
6297 /* Note: Rc update flag set leads to undefined state of Rc0 */
6298 #endif
6299 }
6300
6301 /* mtdcrx */
6302 /* XXX: not implemented on 440 ? */
6303 static void gen_mtdcrx(DisasContext *ctx)
6304 {
6305 #if defined(CONFIG_USER_ONLY)
6306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6307 #else
6308 if (unlikely(ctx->pr)) {
6309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6310 return;
6311 }
6312 /* NIP cannot be restored if the memory exception comes from an helper */
6313 gen_update_nip(ctx, ctx->nip - 4);
6314 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6315 cpu_gpr[rS(ctx->opcode)]);
6316 /* Note: Rc update flag set leads to undefined state of Rc0 */
6317 #endif
6318 }
6319
6320 /* mfdcrux (PPC 460) : user-mode access to DCR */
6321 static void gen_mfdcrux(DisasContext *ctx)
6322 {
6323 /* NIP cannot be restored if the memory exception comes from an helper */
6324 gen_update_nip(ctx, ctx->nip - 4);
6325 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6326 cpu_gpr[rA(ctx->opcode)]);
6327 /* Note: Rc update flag set leads to undefined state of Rc0 */
6328 }
6329
6330 /* mtdcrux (PPC 460) : user-mode access to DCR */
6331 static void gen_mtdcrux(DisasContext *ctx)
6332 {
6333 /* NIP cannot be restored if the memory exception comes from an helper */
6334 gen_update_nip(ctx, ctx->nip - 4);
6335 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6336 cpu_gpr[rS(ctx->opcode)]);
6337 /* Note: Rc update flag set leads to undefined state of Rc0 */
6338 }
6339
6340 /* dccci */
6341 static void gen_dccci(DisasContext *ctx)
6342 {
6343 #if defined(CONFIG_USER_ONLY)
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 #else
6346 if (unlikely(ctx->pr)) {
6347 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6348 return;
6349 }
6350 /* interpreted as no-op */
6351 #endif
6352 }
6353
6354 /* dcread */
6355 static void gen_dcread(DisasContext *ctx)
6356 {
6357 #if defined(CONFIG_USER_ONLY)
6358 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6359 #else
6360 TCGv EA, val;
6361 if (unlikely(ctx->pr)) {
6362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6363 return;
6364 }
6365 gen_set_access_type(ctx, ACCESS_CACHE);
6366 EA = tcg_temp_new();
6367 gen_addr_reg_index(ctx, EA);
6368 val = tcg_temp_new();
6369 gen_qemu_ld32u(ctx, val, EA);
6370 tcg_temp_free(val);
6371 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6372 tcg_temp_free(EA);
6373 #endif
6374 }
6375
6376 /* icbt */
6377 static void gen_icbt_40x(DisasContext *ctx)
6378 {
6379 /* interpreted as no-op */
6380 /* XXX: specification say this is treated as a load by the MMU
6381 * but does not generate any exception
6382 */
6383 }
6384
6385 /* iccci */
6386 static void gen_iccci(DisasContext *ctx)
6387 {
6388 #if defined(CONFIG_USER_ONLY)
6389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6390 #else
6391 if (unlikely(ctx->pr)) {
6392 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6393 return;
6394 }
6395 /* interpreted as no-op */
6396 #endif
6397 }
6398
6399 /* icread */
6400 static void gen_icread(DisasContext *ctx)
6401 {
6402 #if defined(CONFIG_USER_ONLY)
6403 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6404 #else
6405 if (unlikely(ctx->pr)) {
6406 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6407 return;
6408 }
6409 /* interpreted as no-op */
6410 #endif
6411 }
6412
6413 /* rfci (supervisor only) */
6414 static void gen_rfci_40x(DisasContext *ctx)
6415 {
6416 #if defined(CONFIG_USER_ONLY)
6417 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6418 #else
6419 if (unlikely(ctx->pr)) {
6420 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6421 return;
6422 }
6423 /* Restore CPU state */
6424 gen_helper_40x_rfci(cpu_env);
6425 gen_sync_exception(ctx);
6426 #endif
6427 }
6428
6429 static void gen_rfci(DisasContext *ctx)
6430 {
6431 #if defined(CONFIG_USER_ONLY)
6432 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6433 #else
6434 if (unlikely(ctx->pr)) {
6435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6436 return;
6437 }
6438 /* Restore CPU state */
6439 gen_helper_rfci(cpu_env);
6440 gen_sync_exception(ctx);
6441 #endif
6442 }
6443
6444 /* BookE specific */
6445
6446 /* XXX: not implemented on 440 ? */
6447 static void gen_rfdi(DisasContext *ctx)
6448 {
6449 #if defined(CONFIG_USER_ONLY)
6450 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6451 #else
6452 if (unlikely(ctx->pr)) {
6453 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6454 return;
6455 }
6456 /* Restore CPU state */
6457 gen_helper_rfdi(cpu_env);
6458 gen_sync_exception(ctx);
6459 #endif
6460 }
6461
6462 /* XXX: not implemented on 440 ? */
6463 static void gen_rfmci(DisasContext *ctx)
6464 {
6465 #if defined(CONFIG_USER_ONLY)
6466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6467 #else
6468 if (unlikely(ctx->pr)) {
6469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6470 return;
6471 }
6472 /* Restore CPU state */
6473 gen_helper_rfmci(cpu_env);
6474 gen_sync_exception(ctx);
6475 #endif
6476 }
6477
6478 /* TLB management - PowerPC 405 implementation */
6479
6480 /* tlbre */
6481 static void gen_tlbre_40x(DisasContext *ctx)
6482 {
6483 #if defined(CONFIG_USER_ONLY)
6484 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6485 #else
6486 if (unlikely(ctx->pr)) {
6487 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6488 return;
6489 }
6490 switch (rB(ctx->opcode)) {
6491 case 0:
6492 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6493 cpu_gpr[rA(ctx->opcode)]);
6494 break;
6495 case 1:
6496 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6497 cpu_gpr[rA(ctx->opcode)]);
6498 break;
6499 default:
6500 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6501 break;
6502 }
6503 #endif
6504 }
6505
6506 /* tlbsx - tlbsx. */
6507 static void gen_tlbsx_40x(DisasContext *ctx)
6508 {
6509 #if defined(CONFIG_USER_ONLY)
6510 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6511 #else
6512 TCGv t0;
6513 if (unlikely(ctx->pr)) {
6514 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6515 return;
6516 }
6517 t0 = tcg_temp_new();
6518 gen_addr_reg_index(ctx, t0);
6519 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6520 tcg_temp_free(t0);
6521 if (Rc(ctx->opcode)) {
6522 TCGLabel *l1 = gen_new_label();
6523 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6524 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6525 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6526 gen_set_label(l1);
6527 }
6528 #endif
6529 }
6530
6531 /* tlbwe */
6532 static void gen_tlbwe_40x(DisasContext *ctx)
6533 {
6534 #if defined(CONFIG_USER_ONLY)
6535 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6536 #else
6537 if (unlikely(ctx->pr)) {
6538 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6539 return;
6540 }
6541 switch (rB(ctx->opcode)) {
6542 case 0:
6543 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6544 cpu_gpr[rS(ctx->opcode)]);
6545 break;
6546 case 1:
6547 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6548 cpu_gpr[rS(ctx->opcode)]);
6549 break;
6550 default:
6551 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6552 break;
6553 }
6554 #endif
6555 }
6556
6557 /* TLB management - PowerPC 440 implementation */
6558
6559 /* tlbre */
6560 static void gen_tlbre_440(DisasContext *ctx)
6561 {
6562 #if defined(CONFIG_USER_ONLY)
6563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6564 #else
6565 if (unlikely(ctx->pr)) {
6566 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6567 return;
6568 }
6569 switch (rB(ctx->opcode)) {
6570 case 0:
6571 case 1:
6572 case 2:
6573 {
6574 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6575 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6576 t0, cpu_gpr[rA(ctx->opcode)]);
6577 tcg_temp_free_i32(t0);
6578 }
6579 break;
6580 default:
6581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6582 break;
6583 }
6584 #endif
6585 }
6586
6587 /* tlbsx - tlbsx. */
6588 static void gen_tlbsx_440(DisasContext *ctx)
6589 {
6590 #if defined(CONFIG_USER_ONLY)
6591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6592 #else
6593 TCGv t0;
6594 if (unlikely(ctx->pr)) {
6595 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6596 return;
6597 }
6598 t0 = tcg_temp_new();
6599 gen_addr_reg_index(ctx, t0);
6600 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6601 tcg_temp_free(t0);
6602 if (Rc(ctx->opcode)) {
6603 TCGLabel *l1 = gen_new_label();
6604 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6605 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6606 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6607 gen_set_label(l1);
6608 }
6609 #endif
6610 }
6611
6612 /* tlbwe */
6613 static void gen_tlbwe_440(DisasContext *ctx)
6614 {
6615 #if defined(CONFIG_USER_ONLY)
6616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6617 #else
6618 if (unlikely(ctx->pr)) {
6619 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6620 return;
6621 }
6622 switch (rB(ctx->opcode)) {
6623 case 0:
6624 case 1:
6625 case 2:
6626 {
6627 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6628 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6629 cpu_gpr[rS(ctx->opcode)]);
6630 tcg_temp_free_i32(t0);
6631 }
6632 break;
6633 default:
6634 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6635 break;
6636 }
6637 #endif
6638 }
6639
6640 /* TLB management - PowerPC BookE 2.06 implementation */
6641
6642 /* tlbre */
6643 static void gen_tlbre_booke206(DisasContext *ctx)
6644 {
6645 #if defined(CONFIG_USER_ONLY)
6646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6647 #else
6648 if (unlikely(ctx->pr)) {
6649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6650 return;
6651 }
6652
6653 gen_helper_booke206_tlbre(cpu_env);
6654 #endif
6655 }
6656
6657 /* tlbsx - tlbsx. */
6658 static void gen_tlbsx_booke206(DisasContext *ctx)
6659 {
6660 #if defined(CONFIG_USER_ONLY)
6661 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6662 #else
6663 TCGv t0;
6664 if (unlikely(ctx->pr)) {
6665 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6666 return;
6667 }
6668
6669 if (rA(ctx->opcode)) {
6670 t0 = tcg_temp_new();
6671 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6672 } else {
6673 t0 = tcg_const_tl(0);
6674 }
6675
6676 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6677 gen_helper_booke206_tlbsx(cpu_env, t0);
6678 tcg_temp_free(t0);
6679 #endif
6680 }
6681
6682 /* tlbwe */
6683 static void gen_tlbwe_booke206(DisasContext *ctx)
6684 {
6685 #if defined(CONFIG_USER_ONLY)
6686 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6687 #else
6688 if (unlikely(ctx->pr)) {
6689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6690 return;
6691 }
6692 gen_update_nip(ctx, ctx->nip - 4);
6693 gen_helper_booke206_tlbwe(cpu_env);
6694 #endif
6695 }
6696
6697 static void gen_tlbivax_booke206(DisasContext *ctx)
6698 {
6699 #if defined(CONFIG_USER_ONLY)
6700 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6701 #else
6702 TCGv t0;
6703 if (unlikely(ctx->pr)) {
6704 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6705 return;
6706 }
6707
6708 t0 = tcg_temp_new();
6709 gen_addr_reg_index(ctx, t0);
6710
6711 gen_helper_booke206_tlbivax(cpu_env, t0);
6712 tcg_temp_free(t0);
6713 #endif
6714 }
6715
6716 static void gen_tlbilx_booke206(DisasContext *ctx)
6717 {
6718 #if defined(CONFIG_USER_ONLY)
6719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6720 #else
6721 TCGv t0;
6722 if (unlikely(ctx->pr)) {
6723 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6724 return;
6725 }
6726
6727 t0 = tcg_temp_new();
6728 gen_addr_reg_index(ctx, t0);
6729
6730 switch((ctx->opcode >> 21) & 0x3) {
6731 case 0:
6732 gen_helper_booke206_tlbilx0(cpu_env, t0);
6733 break;
6734 case 1:
6735 gen_helper_booke206_tlbilx1(cpu_env, t0);
6736 break;
6737 case 3:
6738 gen_helper_booke206_tlbilx3(cpu_env, t0);
6739 break;
6740 default:
6741 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6742 break;
6743 }
6744
6745 tcg_temp_free(t0);
6746 #endif
6747 }
6748
6749
6750 /* wrtee */
6751 static void gen_wrtee(DisasContext *ctx)
6752 {
6753 #if defined(CONFIG_USER_ONLY)
6754 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6755 #else
6756 TCGv t0;
6757 if (unlikely(ctx->pr)) {
6758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6759 return;
6760 }
6761 t0 = tcg_temp_new();
6762 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6763 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6764 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6765 tcg_temp_free(t0);
6766 /* Stop translation to have a chance to raise an exception
6767 * if we just set msr_ee to 1
6768 */
6769 gen_stop_exception(ctx);
6770 #endif
6771 }
6772
6773 /* wrteei */
6774 static void gen_wrteei(DisasContext *ctx)
6775 {
6776 #if defined(CONFIG_USER_ONLY)
6777 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6778 #else
6779 if (unlikely(ctx->pr)) {
6780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6781 return;
6782 }
6783 if (ctx->opcode & 0x00008000) {
6784 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6785 /* Stop translation to have a chance to raise an exception */
6786 gen_stop_exception(ctx);
6787 } else {
6788 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6789 }
6790 #endif
6791 }
6792
6793 /* PowerPC 440 specific instructions */
6794
6795 /* dlmzb */
6796 static void gen_dlmzb(DisasContext *ctx)
6797 {
6798 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6799 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6800 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6801 tcg_temp_free_i32(t0);
6802 }
6803
6804 /* mbar replaces eieio on 440 */
6805 static void gen_mbar(DisasContext *ctx)
6806 {
6807 /* interpreted as no-op */
6808 }
6809
6810 /* msync replaces sync on 440 */
6811 static void gen_msync_4xx(DisasContext *ctx)
6812 {
6813 /* interpreted as no-op */
6814 }
6815
6816 /* icbt */
6817 static void gen_icbt_440(DisasContext *ctx)
6818 {
6819 /* interpreted as no-op */
6820 /* XXX: specification say this is treated as a load by the MMU
6821 * but does not generate any exception
6822 */
6823 }
6824
6825 /* Embedded.Processor Control */
6826
6827 static void gen_msgclr(DisasContext *ctx)
6828 {
6829 #if defined(CONFIG_USER_ONLY)
6830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6831 #else
6832 if (unlikely(ctx->pr)) {
6833 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6834 return;
6835 }
6836
6837 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6838 #endif
6839 }
6840
6841 static void gen_msgsnd(DisasContext *ctx)
6842 {
6843 #if defined(CONFIG_USER_ONLY)
6844 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6845 #else
6846 if (unlikely(ctx->pr)) {
6847 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6848 return;
6849 }
6850
6851 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6852 #endif
6853 }
6854
6855 /*** Altivec vector extension ***/
6856 /* Altivec registers moves */
6857
6858 static inline TCGv_ptr gen_avr_ptr(int reg)
6859 {
6860 TCGv_ptr r = tcg_temp_new_ptr();
6861 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6862 return r;
6863 }
6864
6865 #define GEN_VR_LDX(name, opc2, opc3) \
6866 static void glue(gen_, name)(DisasContext *ctx) \
6867 { \
6868 TCGv EA; \
6869 if (unlikely(!ctx->altivec_enabled)) { \
6870 gen_exception(ctx, POWERPC_EXCP_VPU); \
6871 return; \
6872 } \
6873 gen_set_access_type(ctx, ACCESS_INT); \
6874 EA = tcg_temp_new(); \
6875 gen_addr_reg_index(ctx, EA); \
6876 tcg_gen_andi_tl(EA, EA, ~0xf); \
6877 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6878 64-bit byteswap already. */ \
6879 if (ctx->le_mode) { \
6880 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6881 tcg_gen_addi_tl(EA, EA, 8); \
6882 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6883 } else { \
6884 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6885 tcg_gen_addi_tl(EA, EA, 8); \
6886 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6887 } \
6888 tcg_temp_free(EA); \
6889 }
6890
6891 #define GEN_VR_STX(name, opc2, opc3) \
6892 static void gen_st##name(DisasContext *ctx) \
6893 { \
6894 TCGv EA; \
6895 if (unlikely(!ctx->altivec_enabled)) { \
6896 gen_exception(ctx, POWERPC_EXCP_VPU); \
6897 return; \
6898 } \
6899 gen_set_access_type(ctx, ACCESS_INT); \
6900 EA = tcg_temp_new(); \
6901 gen_addr_reg_index(ctx, EA); \
6902 tcg_gen_andi_tl(EA, EA, ~0xf); \
6903 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6904 64-bit byteswap already. */ \
6905 if (ctx->le_mode) { \
6906 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6907 tcg_gen_addi_tl(EA, EA, 8); \
6908 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6909 } else { \
6910 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6911 tcg_gen_addi_tl(EA, EA, 8); \
6912 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6913 } \
6914 tcg_temp_free(EA); \
6915 }
6916
6917 #define GEN_VR_LVE(name, opc2, opc3, size) \
6918 static void gen_lve##name(DisasContext *ctx) \
6919 { \
6920 TCGv EA; \
6921 TCGv_ptr rs; \
6922 if (unlikely(!ctx->altivec_enabled)) { \
6923 gen_exception(ctx, POWERPC_EXCP_VPU); \
6924 return; \
6925 } \
6926 gen_set_access_type(ctx, ACCESS_INT); \
6927 EA = tcg_temp_new(); \
6928 gen_addr_reg_index(ctx, EA); \
6929 if (size > 1) { \
6930 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6931 } \
6932 rs = gen_avr_ptr(rS(ctx->opcode)); \
6933 gen_helper_lve##name(cpu_env, rs, EA); \
6934 tcg_temp_free(EA); \
6935 tcg_temp_free_ptr(rs); \
6936 }
6937
6938 #define GEN_VR_STVE(name, opc2, opc3, size) \
6939 static void gen_stve##name(DisasContext *ctx) \
6940 { \
6941 TCGv EA; \
6942 TCGv_ptr rs; \
6943 if (unlikely(!ctx->altivec_enabled)) { \
6944 gen_exception(ctx, POWERPC_EXCP_VPU); \
6945 return; \
6946 } \
6947 gen_set_access_type(ctx, ACCESS_INT); \
6948 EA = tcg_temp_new(); \
6949 gen_addr_reg_index(ctx, EA); \
6950 if (size > 1) { \
6951 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6952 } \
6953 rs = gen_avr_ptr(rS(ctx->opcode)); \
6954 gen_helper_stve##name(cpu_env, rs, EA); \
6955 tcg_temp_free(EA); \
6956 tcg_temp_free_ptr(rs); \
6957 }
6958
6959 GEN_VR_LDX(lvx, 0x07, 0x03);
6960 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6961 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6962
6963 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6964 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6965 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6966
6967 GEN_VR_STX(svx, 0x07, 0x07);
6968 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6969 GEN_VR_STX(svxl, 0x07, 0x0F);
6970
6971 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6972 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6973 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6974
6975 static void gen_lvsl(DisasContext *ctx)
6976 {
6977 TCGv_ptr rd;
6978 TCGv EA;
6979 if (unlikely(!ctx->altivec_enabled)) {
6980 gen_exception(ctx, POWERPC_EXCP_VPU);
6981 return;
6982 }
6983 EA = tcg_temp_new();
6984 gen_addr_reg_index(ctx, EA);
6985 rd = gen_avr_ptr(rD(ctx->opcode));
6986 gen_helper_lvsl(rd, EA);
6987 tcg_temp_free(EA);
6988 tcg_temp_free_ptr(rd);
6989 }
6990
6991 static void gen_lvsr(DisasContext *ctx)
6992 {
6993 TCGv_ptr rd;
6994 TCGv EA;
6995 if (unlikely(!ctx->altivec_enabled)) {
6996 gen_exception(ctx, POWERPC_EXCP_VPU);
6997 return;
6998 }
6999 EA = tcg_temp_new();
7000 gen_addr_reg_index(ctx, EA);
7001 rd = gen_avr_ptr(rD(ctx->opcode));
7002 gen_helper_lvsr(rd, EA);
7003 tcg_temp_free(EA);
7004 tcg_temp_free_ptr(rd);
7005 }
7006
7007 static void gen_mfvscr(DisasContext *ctx)
7008 {
7009 TCGv_i32 t;
7010 if (unlikely(!ctx->altivec_enabled)) {
7011 gen_exception(ctx, POWERPC_EXCP_VPU);
7012 return;
7013 }
7014 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
7015 t = tcg_temp_new_i32();
7016 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
7017 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
7018 tcg_temp_free_i32(t);
7019 }
7020
7021 static void gen_mtvscr(DisasContext *ctx)
7022 {
7023 TCGv_ptr p;
7024 if (unlikely(!ctx->altivec_enabled)) {
7025 gen_exception(ctx, POWERPC_EXCP_VPU);
7026 return;
7027 }
7028 p = gen_avr_ptr(rB(ctx->opcode));
7029 gen_helper_mtvscr(cpu_env, p);
7030 tcg_temp_free_ptr(p);
7031 }
7032
7033 /* Logical operations */
7034 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
7035 static void glue(gen_, name)(DisasContext *ctx) \
7036 { \
7037 if (unlikely(!ctx->altivec_enabled)) { \
7038 gen_exception(ctx, POWERPC_EXCP_VPU); \
7039 return; \
7040 } \
7041 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
7042 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
7043 }
7044
7045 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
7046 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
7047 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
7048 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
7049 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
7050 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
7051 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
7052 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
7053
7054 #define GEN_VXFORM(name, opc2, opc3) \
7055 static void glue(gen_, name)(DisasContext *ctx) \
7056 { \
7057 TCGv_ptr ra, rb, rd; \
7058 if (unlikely(!ctx->altivec_enabled)) { \
7059 gen_exception(ctx, POWERPC_EXCP_VPU); \
7060 return; \
7061 } \
7062 ra = gen_avr_ptr(rA(ctx->opcode)); \
7063 rb = gen_avr_ptr(rB(ctx->opcode)); \
7064 rd = gen_avr_ptr(rD(ctx->opcode)); \
7065 gen_helper_##name (rd, ra, rb); \
7066 tcg_temp_free_ptr(ra); \
7067 tcg_temp_free_ptr(rb); \
7068 tcg_temp_free_ptr(rd); \
7069 }
7070
7071 #define GEN_VXFORM_ENV(name, opc2, opc3) \
7072 static void glue(gen_, name)(DisasContext *ctx) \
7073 { \
7074 TCGv_ptr ra, rb, rd; \
7075 if (unlikely(!ctx->altivec_enabled)) { \
7076 gen_exception(ctx, POWERPC_EXCP_VPU); \
7077 return; \
7078 } \
7079 ra = gen_avr_ptr(rA(ctx->opcode)); \
7080 rb = gen_avr_ptr(rB(ctx->opcode)); \
7081 rd = gen_avr_ptr(rD(ctx->opcode)); \
7082 gen_helper_##name(cpu_env, rd, ra, rb); \
7083 tcg_temp_free_ptr(ra); \
7084 tcg_temp_free_ptr(rb); \
7085 tcg_temp_free_ptr(rd); \
7086 }
7087
7088 #define GEN_VXFORM3(name, opc2, opc3) \
7089 static void glue(gen_, name)(DisasContext *ctx) \
7090 { \
7091 TCGv_ptr ra, rb, rc, rd; \
7092 if (unlikely(!ctx->altivec_enabled)) { \
7093 gen_exception(ctx, POWERPC_EXCP_VPU); \
7094 return; \
7095 } \
7096 ra = gen_avr_ptr(rA(ctx->opcode)); \
7097 rb = gen_avr_ptr(rB(ctx->opcode)); \
7098 rc = gen_avr_ptr(rC(ctx->opcode)); \
7099 rd = gen_avr_ptr(rD(ctx->opcode)); \
7100 gen_helper_##name(rd, ra, rb, rc); \
7101 tcg_temp_free_ptr(ra); \
7102 tcg_temp_free_ptr(rb); \
7103 tcg_temp_free_ptr(rc); \
7104 tcg_temp_free_ptr(rd); \
7105 }
7106
7107 /*
7108 * Support for Altivec instruction pairs that use bit 31 (Rc) as
7109 * an opcode bit. In general, these pairs come from different
7110 * versions of the ISA, so we must also support a pair of flags for
7111 * each instruction.
7112 */
7113 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7114 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7115 { \
7116 if ((Rc(ctx->opcode) == 0) && \
7117 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7118 gen_##name0(ctx); \
7119 } else if ((Rc(ctx->opcode) == 1) && \
7120 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7121 gen_##name1(ctx); \
7122 } else { \
7123 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7124 } \
7125 }
7126
7127 GEN_VXFORM(vaddubm, 0, 0);
7128 GEN_VXFORM(vadduhm, 0, 1);
7129 GEN_VXFORM(vadduwm, 0, 2);
7130 GEN_VXFORM(vaddudm, 0, 3);
7131 GEN_VXFORM(vsububm, 0, 16);
7132 GEN_VXFORM(vsubuhm, 0, 17);
7133 GEN_VXFORM(vsubuwm, 0, 18);
7134 GEN_VXFORM(vsubudm, 0, 19);
7135 GEN_VXFORM(vmaxub, 1, 0);
7136 GEN_VXFORM(vmaxuh, 1, 1);
7137 GEN_VXFORM(vmaxuw, 1, 2);
7138 GEN_VXFORM(vmaxud, 1, 3);
7139 GEN_VXFORM(vmaxsb, 1, 4);
7140 GEN_VXFORM(vmaxsh, 1, 5);
7141 GEN_VXFORM(vmaxsw, 1, 6);
7142 GEN_VXFORM(vmaxsd, 1, 7);
7143 GEN_VXFORM(vminub, 1, 8);
7144 GEN_VXFORM(vminuh, 1, 9);
7145 GEN_VXFORM(vminuw, 1, 10);
7146 GEN_VXFORM(vminud, 1, 11);
7147 GEN_VXFORM(vminsb, 1, 12);
7148 GEN_VXFORM(vminsh, 1, 13);
7149 GEN_VXFORM(vminsw, 1, 14);
7150 GEN_VXFORM(vminsd, 1, 15);
7151 GEN_VXFORM(vavgub, 1, 16);
7152 GEN_VXFORM(vavguh, 1, 17);
7153 GEN_VXFORM(vavguw, 1, 18);
7154 GEN_VXFORM(vavgsb, 1, 20);
7155 GEN_VXFORM(vavgsh, 1, 21);
7156 GEN_VXFORM(vavgsw, 1, 22);
7157 GEN_VXFORM(vmrghb, 6, 0);
7158 GEN_VXFORM(vmrghh, 6, 1);
7159 GEN_VXFORM(vmrghw, 6, 2);
7160 GEN_VXFORM(vmrglb, 6, 4);
7161 GEN_VXFORM(vmrglh, 6, 5);
7162 GEN_VXFORM(vmrglw, 6, 6);
7163
7164 static void gen_vmrgew(DisasContext *ctx)
7165 {
7166 TCGv_i64 tmp;
7167 int VT, VA, VB;
7168 if (unlikely(!ctx->altivec_enabled)) {
7169 gen_exception(ctx, POWERPC_EXCP_VPU);
7170 return;
7171 }
7172 VT = rD(ctx->opcode);
7173 VA = rA(ctx->opcode);
7174 VB = rB(ctx->opcode);
7175 tmp = tcg_temp_new_i64();
7176 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7177 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7178 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7179 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7180 tcg_temp_free_i64(tmp);
7181 }
7182
7183 static void gen_vmrgow(DisasContext *ctx)
7184 {
7185 int VT, VA, VB;
7186 if (unlikely(!ctx->altivec_enabled)) {
7187 gen_exception(ctx, POWERPC_EXCP_VPU);
7188 return;
7189 }
7190 VT = rD(ctx->opcode);
7191 VA = rA(ctx->opcode);
7192 VB = rB(ctx->opcode);
7193
7194 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7195 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7196 }
7197
7198 GEN_VXFORM(vmuloub, 4, 0);
7199 GEN_VXFORM(vmulouh, 4, 1);
7200 GEN_VXFORM(vmulouw, 4, 2);
7201 GEN_VXFORM(vmuluwm, 4, 2);
7202 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7203 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7204 GEN_VXFORM(vmulosb, 4, 4);
7205 GEN_VXFORM(vmulosh, 4, 5);
7206 GEN_VXFORM(vmulosw, 4, 6);
7207 GEN_VXFORM(vmuleub, 4, 8);
7208 GEN_VXFORM(vmuleuh, 4, 9);
7209 GEN_VXFORM(vmuleuw, 4, 10);
7210 GEN_VXFORM(vmulesb, 4, 12);
7211 GEN_VXFORM(vmulesh, 4, 13);
7212 GEN_VXFORM(vmulesw, 4, 14);
7213 GEN_VXFORM(vslb, 2, 4);
7214 GEN_VXFORM(vslh, 2, 5);
7215 GEN_VXFORM(vslw, 2, 6);
7216 GEN_VXFORM(vsld, 2, 23);
7217 GEN_VXFORM(vsrb, 2, 8);
7218 GEN_VXFORM(vsrh, 2, 9);
7219 GEN_VXFORM(vsrw, 2, 10);
7220 GEN_VXFORM(vsrd, 2, 27);
7221 GEN_VXFORM(vsrab, 2, 12);
7222 GEN_VXFORM(vsrah, 2, 13);
7223 GEN_VXFORM(vsraw, 2, 14);
7224 GEN_VXFORM(vsrad, 2, 15);
7225 GEN_VXFORM(vslo, 6, 16);
7226 GEN_VXFORM(vsro, 6, 17);
7227 GEN_VXFORM(vaddcuw, 0, 6);
7228 GEN_VXFORM(vsubcuw, 0, 22);
7229 GEN_VXFORM_ENV(vaddubs, 0, 8);
7230 GEN_VXFORM_ENV(vadduhs, 0, 9);
7231 GEN_VXFORM_ENV(vadduws, 0, 10);
7232 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7233 GEN_VXFORM_ENV(vaddshs, 0, 13);
7234 GEN_VXFORM_ENV(vaddsws, 0, 14);
7235 GEN_VXFORM_ENV(vsububs, 0, 24);
7236 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7237 GEN_VXFORM_ENV(vsubuws, 0, 26);
7238 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7239 GEN_VXFORM_ENV(vsubshs, 0, 29);
7240 GEN_VXFORM_ENV(vsubsws, 0, 30);
7241 GEN_VXFORM(vadduqm, 0, 4);
7242 GEN_VXFORM(vaddcuq, 0, 5);
7243 GEN_VXFORM3(vaddeuqm, 30, 0);
7244 GEN_VXFORM3(vaddecuq, 30, 0);
7245 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7246 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7247 GEN_VXFORM(vsubuqm, 0, 20);
7248 GEN_VXFORM(vsubcuq, 0, 21);
7249 GEN_VXFORM3(vsubeuqm, 31, 0);
7250 GEN_VXFORM3(vsubecuq, 31, 0);
7251 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7252 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7253 GEN_VXFORM(vrlb, 2, 0);
7254 GEN_VXFORM(vrlh, 2, 1);
7255 GEN_VXFORM(vrlw, 2, 2);
7256 GEN_VXFORM(vrld, 2, 3);
7257 GEN_VXFORM(vsl, 2, 7);
7258 GEN_VXFORM(vsr, 2, 11);
7259 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7260 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7261 GEN_VXFORM_ENV(vpkudum, 7, 17);
7262 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7263 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7264 GEN_VXFORM_ENV(vpkudus, 7, 19);
7265 GEN_VXFORM_ENV(vpkshus, 7, 4);
7266 GEN_VXFORM_ENV(vpkswus, 7, 5);
7267 GEN_VXFORM_ENV(vpksdus, 7, 21);
7268 GEN_VXFORM_ENV(vpkshss, 7, 6);
7269 GEN_VXFORM_ENV(vpkswss, 7, 7);
7270 GEN_VXFORM_ENV(vpksdss, 7, 23);
7271 GEN_VXFORM(vpkpx, 7, 12);
7272 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7273 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7274 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7275 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7276 GEN_VXFORM_ENV(vsumsws, 4, 30);
7277 GEN_VXFORM_ENV(vaddfp, 5, 0);
7278 GEN_VXFORM_ENV(vsubfp, 5, 1);
7279 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7280 GEN_VXFORM_ENV(vminfp, 5, 17);
7281
7282 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7283 static void glue(gen_, name)(DisasContext *ctx) \
7284 { \
7285 TCGv_ptr ra, rb, rd; \
7286 if (unlikely(!ctx->altivec_enabled)) { \
7287 gen_exception(ctx, POWERPC_EXCP_VPU); \
7288 return; \
7289 } \
7290 ra = gen_avr_ptr(rA(ctx->opcode)); \
7291 rb = gen_avr_ptr(rB(ctx->opcode)); \
7292 rd = gen_avr_ptr(rD(ctx->opcode)); \
7293 gen_helper_##opname(cpu_env, rd, ra, rb); \
7294 tcg_temp_free_ptr(ra); \
7295 tcg_temp_free_ptr(rb); \
7296 tcg_temp_free_ptr(rd); \
7297 }
7298
7299 #define GEN_VXRFORM(name, opc2, opc3) \
7300 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7301 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7302
7303 /*
7304 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7305 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7306 * come from different versions of the ISA, so we must also support a
7307 * pair of flags for each instruction.
7308 */
7309 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7310 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7311 { \
7312 if ((Rc(ctx->opcode) == 0) && \
7313 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7314 if (Rc21(ctx->opcode) == 0) { \
7315 gen_##name0(ctx); \
7316 } else { \
7317 gen_##name0##_(ctx); \
7318 } \
7319 } else if ((Rc(ctx->opcode) == 1) && \
7320 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7321 if (Rc21(ctx->opcode) == 0) { \
7322 gen_##name1(ctx); \
7323 } else { \
7324 gen_##name1##_(ctx); \
7325 } \
7326 } else { \
7327 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7328 } \
7329 }
7330
7331 GEN_VXRFORM(vcmpequb, 3, 0)
7332 GEN_VXRFORM(vcmpequh, 3, 1)
7333 GEN_VXRFORM(vcmpequw, 3, 2)
7334 GEN_VXRFORM(vcmpequd, 3, 3)
7335 GEN_VXRFORM(vcmpgtsb, 3, 12)
7336 GEN_VXRFORM(vcmpgtsh, 3, 13)
7337 GEN_VXRFORM(vcmpgtsw, 3, 14)
7338 GEN_VXRFORM(vcmpgtsd, 3, 15)
7339 GEN_VXRFORM(vcmpgtub, 3, 8)
7340 GEN_VXRFORM(vcmpgtuh, 3, 9)
7341 GEN_VXRFORM(vcmpgtuw, 3, 10)
7342 GEN_VXRFORM(vcmpgtud, 3, 11)
7343 GEN_VXRFORM(vcmpeqfp, 3, 3)
7344 GEN_VXRFORM(vcmpgefp, 3, 7)
7345 GEN_VXRFORM(vcmpgtfp, 3, 11)
7346 GEN_VXRFORM(vcmpbfp, 3, 15)
7347
7348 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7349 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7350 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7351 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7352 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7353 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7354
7355 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7356 static void glue(gen_, name)(DisasContext *ctx) \
7357 { \
7358 TCGv_ptr rd; \
7359 TCGv_i32 simm; \
7360 if (unlikely(!ctx->altivec_enabled)) { \
7361 gen_exception(ctx, POWERPC_EXCP_VPU); \
7362 return; \
7363 } \
7364 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7365 rd = gen_avr_ptr(rD(ctx->opcode)); \
7366 gen_helper_##name (rd, simm); \
7367 tcg_temp_free_i32(simm); \
7368 tcg_temp_free_ptr(rd); \
7369 }
7370
7371 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7372 GEN_VXFORM_SIMM(vspltish, 6, 13);
7373 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7374
7375 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7376 static void glue(gen_, name)(DisasContext *ctx) \
7377 { \
7378 TCGv_ptr rb, rd; \
7379 if (unlikely(!ctx->altivec_enabled)) { \
7380 gen_exception(ctx, POWERPC_EXCP_VPU); \
7381 return; \
7382 } \
7383 rb = gen_avr_ptr(rB(ctx->opcode)); \
7384 rd = gen_avr_ptr(rD(ctx->opcode)); \
7385 gen_helper_##name (rd, rb); \
7386 tcg_temp_free_ptr(rb); \
7387 tcg_temp_free_ptr(rd); \
7388 }
7389
7390 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7391 static void glue(gen_, name)(DisasContext *ctx) \
7392 { \
7393 TCGv_ptr rb, rd; \
7394 \
7395 if (unlikely(!ctx->altivec_enabled)) { \
7396 gen_exception(ctx, POWERPC_EXCP_VPU); \
7397 return; \
7398 } \
7399 rb = gen_avr_ptr(rB(ctx->opcode)); \
7400 rd = gen_avr_ptr(rD(ctx->opcode)); \
7401 gen_helper_##name(cpu_env, rd, rb); \
7402 tcg_temp_free_ptr(rb); \
7403 tcg_temp_free_ptr(rd); \
7404 }
7405
7406 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7407 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7408 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7409 GEN_VXFORM_NOA(vupklsb, 7, 10);
7410 GEN_VXFORM_NOA(vupklsh, 7, 11);
7411 GEN_VXFORM_NOA(vupklsw, 7, 27);
7412 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7413 GEN_VXFORM_NOA(vupklpx, 7, 15);
7414 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7415 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7416 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7417 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7418 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7419 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7420 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7421 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7422
7423 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7424 static void glue(gen_, name)(DisasContext *ctx) \
7425 { \
7426 TCGv_ptr rd; \
7427 TCGv_i32 simm; \
7428 if (unlikely(!ctx->altivec_enabled)) { \
7429 gen_exception(ctx, POWERPC_EXCP_VPU); \
7430 return; \
7431 } \
7432 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7433 rd = gen_avr_ptr(rD(ctx->opcode)); \
7434 gen_helper_##name (rd, simm); \
7435 tcg_temp_free_i32(simm); \
7436 tcg_temp_free_ptr(rd); \
7437 }
7438
7439 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7440 static void glue(gen_, name)(DisasContext *ctx) \
7441 { \
7442 TCGv_ptr rb, rd; \
7443 TCGv_i32 uimm; \
7444 if (unlikely(!ctx->altivec_enabled)) { \
7445 gen_exception(ctx, POWERPC_EXCP_VPU); \
7446 return; \
7447 } \
7448 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7449 rb = gen_avr_ptr(rB(ctx->opcode)); \
7450 rd = gen_avr_ptr(rD(ctx->opcode)); \
7451 gen_helper_##name (rd, rb, uimm); \
7452 tcg_temp_free_i32(uimm); \
7453 tcg_temp_free_ptr(rb); \
7454 tcg_temp_free_ptr(rd); \
7455 }
7456
7457 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7458 static void glue(gen_, name)(DisasContext *ctx) \
7459 { \
7460 TCGv_ptr rb, rd; \
7461 TCGv_i32 uimm; \
7462 \
7463 if (unlikely(!ctx->altivec_enabled)) { \
7464 gen_exception(ctx, POWERPC_EXCP_VPU); \
7465 return; \
7466 } \
7467 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7468 rb = gen_avr_ptr(rB(ctx->opcode)); \
7469 rd = gen_avr_ptr(rD(ctx->opcode)); \
7470 gen_helper_##name(cpu_env, rd, rb, uimm); \
7471 tcg_temp_free_i32(uimm); \
7472 tcg_temp_free_ptr(rb); \
7473 tcg_temp_free_ptr(rd); \
7474 }
7475
7476 GEN_VXFORM_UIMM(vspltb, 6, 8);
7477 GEN_VXFORM_UIMM(vsplth, 6, 9);
7478 GEN_VXFORM_UIMM(vspltw, 6, 10);
7479 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7480 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7481 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7482 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7483
7484 static void gen_vsldoi(DisasContext *ctx)
7485 {
7486 TCGv_ptr ra, rb, rd;
7487 TCGv_i32 sh;
7488 if (unlikely(!ctx->altivec_enabled)) {
7489 gen_exception(ctx, POWERPC_EXCP_VPU);
7490 return;
7491 }
7492 ra = gen_avr_ptr(rA(ctx->opcode));
7493 rb = gen_avr_ptr(rB(ctx->opcode));
7494 rd = gen_avr_ptr(rD(ctx->opcode));
7495 sh = tcg_const_i32(VSH(ctx->opcode));
7496 gen_helper_vsldoi (rd, ra, rb, sh);
7497 tcg_temp_free_ptr(ra);
7498 tcg_temp_free_ptr(rb);
7499 tcg_temp_free_ptr(rd);
7500 tcg_temp_free_i32(sh);
7501 }
7502
7503 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7504 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7505 { \
7506 TCGv_ptr ra, rb, rc, rd; \
7507 if (unlikely(!ctx->altivec_enabled)) { \
7508 gen_exception(ctx, POWERPC_EXCP_VPU); \
7509 return; \
7510 } \
7511 ra = gen_avr_ptr(rA(ctx->opcode)); \
7512 rb = gen_avr_ptr(rB(ctx->opcode)); \
7513 rc = gen_avr_ptr(rC(ctx->opcode)); \
7514 rd = gen_avr_ptr(rD(ctx->opcode)); \
7515 if (Rc(ctx->opcode)) { \
7516 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7517 } else { \
7518 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7519 } \
7520 tcg_temp_free_ptr(ra); \
7521 tcg_temp_free_ptr(rb); \
7522 tcg_temp_free_ptr(rc); \
7523 tcg_temp_free_ptr(rd); \
7524 }
7525
7526 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7527
7528 static void gen_vmladduhm(DisasContext *ctx)
7529 {
7530 TCGv_ptr ra, rb, rc, rd;
7531 if (unlikely(!ctx->altivec_enabled)) {
7532 gen_exception(ctx, POWERPC_EXCP_VPU);
7533 return;
7534 }
7535 ra = gen_avr_ptr(rA(ctx->opcode));
7536 rb = gen_avr_ptr(rB(ctx->opcode));
7537 rc = gen_avr_ptr(rC(ctx->opcode));
7538 rd = gen_avr_ptr(rD(ctx->opcode));
7539 gen_helper_vmladduhm(rd, ra, rb, rc);
7540 tcg_temp_free_ptr(ra);
7541 tcg_temp_free_ptr(rb);
7542 tcg_temp_free_ptr(rc);
7543 tcg_temp_free_ptr(rd);
7544 }
7545
7546 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7547 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7548 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7549 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7550 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7551
7552 GEN_VXFORM_NOA(vclzb, 1, 28)
7553 GEN_VXFORM_NOA(vclzh, 1, 29)
7554 GEN_VXFORM_NOA(vclzw, 1, 30)
7555 GEN_VXFORM_NOA(vclzd, 1, 31)
7556 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7557 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7558 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7559 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7560 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7561 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7562 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7563 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7564 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7565 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7566 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7567 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7568 GEN_VXFORM(vbpermq, 6, 21);
7569 GEN_VXFORM_NOA(vgbbd, 6, 20);
7570 GEN_VXFORM(vpmsumb, 4, 16)
7571 GEN_VXFORM(vpmsumh, 4, 17)
7572 GEN_VXFORM(vpmsumw, 4, 18)
7573 GEN_VXFORM(vpmsumd, 4, 19)
7574
7575 #define GEN_BCD(op) \
7576 static void gen_##op(DisasContext *ctx) \
7577 { \
7578 TCGv_ptr ra, rb, rd; \
7579 TCGv_i32 ps; \
7580 \
7581 if (unlikely(!ctx->altivec_enabled)) { \
7582 gen_exception(ctx, POWERPC_EXCP_VPU); \
7583 return; \
7584 } \
7585 \
7586 ra = gen_avr_ptr(rA(ctx->opcode)); \
7587 rb = gen_avr_ptr(rB(ctx->opcode)); \
7588 rd = gen_avr_ptr(rD(ctx->opcode)); \
7589 \
7590 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7591 \
7592 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7593 \
7594 tcg_temp_free_ptr(ra); \
7595 tcg_temp_free_ptr(rb); \
7596 tcg_temp_free_ptr(rd); \
7597 tcg_temp_free_i32(ps); \
7598 }
7599
7600 GEN_BCD(bcdadd)
7601 GEN_BCD(bcdsub)
7602
7603 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7604 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7605 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7606 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7607 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7608 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7609 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7610 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7611
7612 static void gen_vsbox(DisasContext *ctx)
7613 {
7614 TCGv_ptr ra, rd;
7615 if (unlikely(!ctx->altivec_enabled)) {
7616 gen_exception(ctx, POWERPC_EXCP_VPU);
7617 return;
7618 }
7619 ra = gen_avr_ptr(rA(ctx->opcode));
7620 rd = gen_avr_ptr(rD(ctx->opcode));
7621 gen_helper_vsbox(rd, ra);
7622 tcg_temp_free_ptr(ra);
7623 tcg_temp_free_ptr(rd);
7624 }
7625
7626 GEN_VXFORM(vcipher, 4, 20)
7627 GEN_VXFORM(vcipherlast, 4, 20)
7628 GEN_VXFORM(vncipher, 4, 21)
7629 GEN_VXFORM(vncipherlast, 4, 21)
7630
7631 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7632 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7633 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7634 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7635
7636 #define VSHASIGMA(op) \
7637 static void gen_##op(DisasContext *ctx) \
7638 { \
7639 TCGv_ptr ra, rd; \
7640 TCGv_i32 st_six; \
7641 if (unlikely(!ctx->altivec_enabled)) { \
7642 gen_exception(ctx, POWERPC_EXCP_VPU); \
7643 return; \
7644 } \
7645 ra = gen_avr_ptr(rA(ctx->opcode)); \
7646 rd = gen_avr_ptr(rD(ctx->opcode)); \
7647 st_six = tcg_const_i32(rB(ctx->opcode)); \
7648 gen_helper_##op(rd, ra, st_six); \
7649 tcg_temp_free_ptr(ra); \
7650 tcg_temp_free_ptr(rd); \
7651 tcg_temp_free_i32(st_six); \
7652 }
7653
7654 VSHASIGMA(vshasigmaw)
7655 VSHASIGMA(vshasigmad)
7656
7657 GEN_VXFORM3(vpermxor, 22, 0xFF)
7658 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7659 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7660
7661 /*** VSX extension ***/
7662
7663 static inline TCGv_i64 cpu_vsrh(int n)
7664 {
7665 if (n < 32) {
7666 return cpu_fpr[n];
7667 } else {
7668 return cpu_avrh[n-32];
7669 }
7670 }
7671
7672 static inline TCGv_i64 cpu_vsrl(int n)
7673 {
7674 if (n < 32) {
7675 return cpu_vsr[n];
7676 } else {
7677 return cpu_avrl[n-32];
7678 }
7679 }
7680
7681 #define VSX_LOAD_SCALAR(name, operation) \
7682 static void gen_##name(DisasContext *ctx) \
7683 { \
7684 TCGv EA; \
7685 if (unlikely(!ctx->vsx_enabled)) { \
7686 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7687 return; \
7688 } \
7689 gen_set_access_type(ctx, ACCESS_INT); \
7690 EA = tcg_temp_new(); \
7691 gen_addr_reg_index(ctx, EA); \
7692 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7693 /* NOTE: cpu_vsrl is undefined */ \
7694 tcg_temp_free(EA); \
7695 }
7696
7697 VSX_LOAD_SCALAR(lxsdx, ld64)
7698 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7699 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7700 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7701
7702 static void gen_lxvd2x(DisasContext *ctx)
7703 {
7704 TCGv EA;
7705 if (unlikely(!ctx->vsx_enabled)) {
7706 gen_exception(ctx, POWERPC_EXCP_VSXU);
7707 return;
7708 }
7709 gen_set_access_type(ctx, ACCESS_INT);
7710 EA = tcg_temp_new();
7711 gen_addr_reg_index(ctx, EA);
7712 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7713 tcg_gen_addi_tl(EA, EA, 8);
7714 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7715 tcg_temp_free(EA);
7716 }
7717
7718 static void gen_lxvdsx(DisasContext *ctx)
7719 {
7720 TCGv EA;
7721 if (unlikely(!ctx->vsx_enabled)) {
7722 gen_exception(ctx, POWERPC_EXCP_VSXU);
7723 return;
7724 }
7725 gen_set_access_type(ctx, ACCESS_INT);
7726 EA = tcg_temp_new();
7727 gen_addr_reg_index(ctx, EA);
7728 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7729 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7730 tcg_temp_free(EA);
7731 }
7732
7733 static void gen_lxvw4x(DisasContext *ctx)
7734 {
7735 TCGv EA;
7736 TCGv_i64 tmp;
7737 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7738 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7739 if (unlikely(!ctx->vsx_enabled)) {
7740 gen_exception(ctx, POWERPC_EXCP_VSXU);
7741 return;
7742 }
7743 gen_set_access_type(ctx, ACCESS_INT);
7744 EA = tcg_temp_new();
7745 tmp = tcg_temp_new_i64();
7746
7747 gen_addr_reg_index(ctx, EA);
7748 gen_qemu_ld32u_i64(ctx, tmp, EA);
7749 tcg_gen_addi_tl(EA, EA, 4);
7750 gen_qemu_ld32u_i64(ctx, xth, EA);
7751 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7752
7753 tcg_gen_addi_tl(EA, EA, 4);
7754 gen_qemu_ld32u_i64(ctx, tmp, EA);
7755 tcg_gen_addi_tl(EA, EA, 4);
7756 gen_qemu_ld32u_i64(ctx, xtl, EA);
7757 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7758
7759 tcg_temp_free(EA);
7760 tcg_temp_free_i64(tmp);
7761 }
7762
7763 #define VSX_STORE_SCALAR(name, operation) \
7764 static void gen_##name(DisasContext *ctx) \
7765 { \
7766 TCGv EA; \
7767 if (unlikely(!ctx->vsx_enabled)) { \
7768 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7769 return; \
7770 } \
7771 gen_set_access_type(ctx, ACCESS_INT); \
7772 EA = tcg_temp_new(); \
7773 gen_addr_reg_index(ctx, EA); \
7774 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7775 tcg_temp_free(EA); \
7776 }
7777
7778 VSX_STORE_SCALAR(stxsdx, st64)
7779 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7780 VSX_STORE_SCALAR(stxsspx, st32fs)
7781
7782 static void gen_stxvd2x(DisasContext *ctx)
7783 {
7784 TCGv EA;
7785 if (unlikely(!ctx->vsx_enabled)) {
7786 gen_exception(ctx, POWERPC_EXCP_VSXU);
7787 return;
7788 }
7789 gen_set_access_type(ctx, ACCESS_INT);
7790 EA = tcg_temp_new();
7791 gen_addr_reg_index(ctx, EA);
7792 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7793 tcg_gen_addi_tl(EA, EA, 8);
7794 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7795 tcg_temp_free(EA);
7796 }
7797
7798 static void gen_stxvw4x(DisasContext *ctx)
7799 {
7800 TCGv_i64 tmp;
7801 TCGv EA;
7802 if (unlikely(!ctx->vsx_enabled)) {
7803 gen_exception(ctx, POWERPC_EXCP_VSXU);
7804 return;
7805 }
7806 gen_set_access_type(ctx, ACCESS_INT);
7807 EA = tcg_temp_new();
7808 gen_addr_reg_index(ctx, EA);
7809 tmp = tcg_temp_new_i64();
7810
7811 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7812 gen_qemu_st32_i64(ctx, tmp, EA);
7813 tcg_gen_addi_tl(EA, EA, 4);
7814 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7815
7816 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7817 tcg_gen_addi_tl(EA, EA, 4);
7818 gen_qemu_st32_i64(ctx, tmp, EA);
7819 tcg_gen_addi_tl(EA, EA, 4);
7820 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7821
7822 tcg_temp_free(EA);
7823 tcg_temp_free_i64(tmp);
7824 }
7825
7826 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7827 static void gen_##name(DisasContext *ctx) \
7828 { \
7829 if (xS(ctx->opcode) < 32) { \
7830 if (unlikely(!ctx->fpu_enabled)) { \
7831 gen_exception(ctx, POWERPC_EXCP_FPU); \
7832 return; \
7833 } \
7834 } else { \
7835 if (unlikely(!ctx->altivec_enabled)) { \
7836 gen_exception(ctx, POWERPC_EXCP_VPU); \
7837 return; \
7838 } \
7839 } \
7840 TCGv_i64 tmp = tcg_temp_new_i64(); \
7841 tcg_gen_##tcgop1(tmp, source); \
7842 tcg_gen_##tcgop2(target, tmp); \
7843 tcg_temp_free_i64(tmp); \
7844 }
7845
7846
7847 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7848 cpu_vsrh(xS(ctx->opcode)))
7849 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7850 cpu_gpr[rA(ctx->opcode)])
7851 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7852 cpu_gpr[rA(ctx->opcode)])
7853
7854 #if defined(TARGET_PPC64)
7855 #define MV_VSRD(name, target, source) \
7856 static void gen_##name(DisasContext *ctx) \
7857 { \
7858 if (xS(ctx->opcode) < 32) { \
7859 if (unlikely(!ctx->fpu_enabled)) { \
7860 gen_exception(ctx, POWERPC_EXCP_FPU); \
7861 return; \
7862 } \
7863 } else { \
7864 if (unlikely(!ctx->altivec_enabled)) { \
7865 gen_exception(ctx, POWERPC_EXCP_VPU); \
7866 return; \
7867 } \
7868 } \
7869 tcg_gen_mov_i64(target, source); \
7870 }
7871
7872 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7873 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7874
7875 #endif
7876
7877 static void gen_xxpermdi(DisasContext *ctx)
7878 {
7879 if (unlikely(!ctx->vsx_enabled)) {
7880 gen_exception(ctx, POWERPC_EXCP_VSXU);
7881 return;
7882 }
7883
7884 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7885 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7886 TCGv_i64 xh, xl;
7887
7888 xh = tcg_temp_new_i64();
7889 xl = tcg_temp_new_i64();
7890
7891 if ((DM(ctx->opcode) & 2) == 0) {
7892 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7893 } else {
7894 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7895 }
7896 if ((DM(ctx->opcode) & 1) == 0) {
7897 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7898 } else {
7899 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7900 }
7901
7902 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7903 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7904
7905 tcg_temp_free_i64(xh);
7906 tcg_temp_free_i64(xl);
7907 } else {
7908 if ((DM(ctx->opcode) & 2) == 0) {
7909 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7910 } else {
7911 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7912 }
7913 if ((DM(ctx->opcode) & 1) == 0) {
7914 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7915 } else {
7916 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7917 }
7918 }
7919 }
7920
7921 #define OP_ABS 1
7922 #define OP_NABS 2
7923 #define OP_NEG 3
7924 #define OP_CPSGN 4
7925 #define SGN_MASK_DP 0x8000000000000000ull
7926 #define SGN_MASK_SP 0x8000000080000000ull
7927
7928 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7929 static void glue(gen_, name)(DisasContext * ctx) \
7930 { \
7931 TCGv_i64 xb, sgm; \
7932 if (unlikely(!ctx->vsx_enabled)) { \
7933 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7934 return; \
7935 } \
7936 xb = tcg_temp_new_i64(); \
7937 sgm = tcg_temp_new_i64(); \
7938 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7939 tcg_gen_movi_i64(sgm, sgn_mask); \
7940 switch (op) { \
7941 case OP_ABS: { \
7942 tcg_gen_andc_i64(xb, xb, sgm); \
7943 break; \
7944 } \
7945 case OP_NABS: { \
7946 tcg_gen_or_i64(xb, xb, sgm); \
7947 break; \
7948 } \
7949 case OP_NEG: { \
7950 tcg_gen_xor_i64(xb, xb, sgm); \
7951 break; \
7952 } \
7953 case OP_CPSGN: { \
7954 TCGv_i64 xa = tcg_temp_new_i64(); \
7955 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7956 tcg_gen_and_i64(xa, xa, sgm); \
7957 tcg_gen_andc_i64(xb, xb, sgm); \
7958 tcg_gen_or_i64(xb, xb, xa); \
7959 tcg_temp_free_i64(xa); \
7960 break; \
7961 } \
7962 } \
7963 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7964 tcg_temp_free_i64(xb); \
7965 tcg_temp_free_i64(sgm); \
7966 }
7967
7968 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7969 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7970 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7971 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7972
7973 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7974 static void glue(gen_, name)(DisasContext * ctx) \
7975 { \
7976 TCGv_i64 xbh, xbl, sgm; \
7977 if (unlikely(!ctx->vsx_enabled)) { \
7978 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7979 return; \
7980 } \
7981 xbh = tcg_temp_new_i64(); \
7982 xbl = tcg_temp_new_i64(); \
7983 sgm = tcg_temp_new_i64(); \
7984 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7985 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7986 tcg_gen_movi_i64(sgm, sgn_mask); \
7987 switch (op) { \
7988 case OP_ABS: { \
7989 tcg_gen_andc_i64(xbh, xbh, sgm); \
7990 tcg_gen_andc_i64(xbl, xbl, sgm); \
7991 break; \
7992 } \
7993 case OP_NABS: { \
7994 tcg_gen_or_i64(xbh, xbh, sgm); \
7995 tcg_gen_or_i64(xbl, xbl, sgm); \
7996 break; \
7997 } \
7998 case OP_NEG: { \
7999 tcg_gen_xor_i64(xbh, xbh, sgm); \
8000 tcg_gen_xor_i64(xbl, xbl, sgm); \
8001 break; \
8002 } \
8003 case OP_CPSGN: { \
8004 TCGv_i64 xah = tcg_temp_new_i64(); \
8005 TCGv_i64 xal = tcg_temp_new_i64(); \
8006 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
8007 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
8008 tcg_gen_and_i64(xah, xah, sgm); \
8009 tcg_gen_and_i64(xal, xal, sgm); \
8010 tcg_gen_andc_i64(xbh, xbh, sgm); \
8011 tcg_gen_andc_i64(xbl, xbl, sgm); \
8012 tcg_gen_or_i64(xbh, xbh, xah); \
8013 tcg_gen_or_i64(xbl, xbl, xal); \
8014 tcg_temp_free_i64(xah); \
8015 tcg_temp_free_i64(xal); \
8016 break; \
8017 } \
8018 } \
8019 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
8020 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
8021 tcg_temp_free_i64(xbh); \
8022 tcg_temp_free_i64(xbl); \
8023 tcg_temp_free_i64(sgm); \
8024 }
8025
8026 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
8027 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
8028 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
8029 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
8030 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
8031 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
8032 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
8033 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
8034
8035 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
8036 static void gen_##name(DisasContext * ctx) \
8037 { \
8038 TCGv_i32 opc; \
8039 if (unlikely(!ctx->vsx_enabled)) { \
8040 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8041 return; \
8042 } \
8043 /* NIP cannot be restored if the memory exception comes from an helper */ \
8044 gen_update_nip(ctx, ctx->nip - 4); \
8045 opc = tcg_const_i32(ctx->opcode); \
8046 gen_helper_##name(cpu_env, opc); \
8047 tcg_temp_free_i32(opc); \
8048 }
8049
8050 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
8051 static void gen_##name(DisasContext * ctx) \
8052 { \
8053 if (unlikely(!ctx->vsx_enabled)) { \
8054 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8055 return; \
8056 } \
8057 /* NIP cannot be restored if the exception comes */ \
8058 /* from a helper. */ \
8059 gen_update_nip(ctx, ctx->nip - 4); \
8060 \
8061 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
8062 cpu_vsrh(xB(ctx->opcode))); \
8063 }
8064
8065 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
8069 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
8070 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
8071 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
8072 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
8073 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
8074 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
8075 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
8076 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
8077 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
8078 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
8079 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
8080 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
8081 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
8082 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
8083 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
8084 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
8085 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
8086 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
8087 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
8088 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
8089 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
8090 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
8091 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
8092 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
8093 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
8094 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
8095 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
8096 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
8097 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
8098 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
8099 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
8100 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
8101 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
8102
8103 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
8104 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
8105 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
8106 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
8107 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
8108 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
8109 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
8110 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
8111 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
8112 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
8113 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
8114 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
8115 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
8116 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
8117 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
8118 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
8119 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
8120
8121 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
8122 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
8123 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
8124 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8125 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8126 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8127 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8128 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8129 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8130 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8131 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8132 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8133 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8134 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8135 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8136 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8137 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8138 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8139 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8140 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8141 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8142 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8143 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8144 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8145 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8146 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8147 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8148 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8149 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8150 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8151 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8152 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8153 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8154 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8155 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8156 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8157
8158 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8159 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8160 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8161 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8162 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8163 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8164 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8165 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8166 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8167 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8168 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8169 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8170 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8171 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8172 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8173 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8174 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8175 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8176 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8177 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8178 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8179 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8180 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8181 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8182 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8183 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8184 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8185 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8186 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8187 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8188 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8189 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8190 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8191 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8192 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8193 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8194
8195 #define VSX_LOGICAL(name, tcg_op) \
8196 static void glue(gen_, name)(DisasContext * ctx) \
8197 { \
8198 if (unlikely(!ctx->vsx_enabled)) { \
8199 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8200 return; \
8201 } \
8202 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8203 cpu_vsrh(xB(ctx->opcode))); \
8204 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8205 cpu_vsrl(xB(ctx->opcode))); \
8206 }
8207
8208 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8209 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8210 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8211 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8212 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8213 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8214 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8215 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8216
8217 #define VSX_XXMRG(name, high) \
8218 static void glue(gen_, name)(DisasContext * ctx) \
8219 { \
8220 TCGv_i64 a0, a1, b0, b1; \
8221 if (unlikely(!ctx->vsx_enabled)) { \
8222 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8223 return; \
8224 } \
8225 a0 = tcg_temp_new_i64(); \
8226 a1 = tcg_temp_new_i64(); \
8227 b0 = tcg_temp_new_i64(); \
8228 b1 = tcg_temp_new_i64(); \
8229 if (high) { \
8230 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8231 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8232 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8233 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8234 } else { \
8235 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8236 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8237 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8238 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8239 } \
8240 tcg_gen_shri_i64(a0, a0, 32); \
8241 tcg_gen_shri_i64(b0, b0, 32); \
8242 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8243 b0, a0, 32, 32); \
8244 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8245 b1, a1, 32, 32); \
8246 tcg_temp_free_i64(a0); \
8247 tcg_temp_free_i64(a1); \
8248 tcg_temp_free_i64(b0); \
8249 tcg_temp_free_i64(b1); \
8250 }
8251
8252 VSX_XXMRG(xxmrghw, 1)
8253 VSX_XXMRG(xxmrglw, 0)
8254
8255 static void gen_xxsel(DisasContext * ctx)
8256 {
8257 TCGv_i64 a, b, c;
8258 if (unlikely(!ctx->vsx_enabled)) {
8259 gen_exception(ctx, POWERPC_EXCP_VSXU);
8260 return;
8261 }
8262 a = tcg_temp_new_i64();
8263 b = tcg_temp_new_i64();
8264 c = tcg_temp_new_i64();
8265
8266 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8267 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8268 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8269
8270 tcg_gen_and_i64(b, b, c);
8271 tcg_gen_andc_i64(a, a, c);
8272 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8273
8274 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8275 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8276 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8277
8278 tcg_gen_and_i64(b, b, c);
8279 tcg_gen_andc_i64(a, a, c);
8280 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8281
8282 tcg_temp_free_i64(a);
8283 tcg_temp_free_i64(b);
8284 tcg_temp_free_i64(c);
8285 }
8286
8287 static void gen_xxspltw(DisasContext *ctx)
8288 {
8289 TCGv_i64 b, b2;
8290 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8291 cpu_vsrl(xB(ctx->opcode)) :
8292 cpu_vsrh(xB(ctx->opcode));
8293
8294 if (unlikely(!ctx->vsx_enabled)) {
8295 gen_exception(ctx, POWERPC_EXCP_VSXU);
8296 return;
8297 }
8298
8299 b = tcg_temp_new_i64();
8300 b2 = tcg_temp_new_i64();
8301
8302 if (UIM(ctx->opcode) & 1) {
8303 tcg_gen_ext32u_i64(b, vsr);
8304 } else {
8305 tcg_gen_shri_i64(b, vsr, 32);
8306 }
8307
8308 tcg_gen_shli_i64(b2, b, 32);
8309 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8310 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8311
8312 tcg_temp_free_i64(b);
8313 tcg_temp_free_i64(b2);
8314 }
8315
8316 static void gen_xxsldwi(DisasContext *ctx)
8317 {
8318 TCGv_i64 xth, xtl;
8319 if (unlikely(!ctx->vsx_enabled)) {
8320 gen_exception(ctx, POWERPC_EXCP_VSXU);
8321 return;
8322 }
8323 xth = tcg_temp_new_i64();
8324 xtl = tcg_temp_new_i64();
8325
8326 switch (SHW(ctx->opcode)) {
8327 case 0: {
8328 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8329 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8330 break;
8331 }
8332 case 1: {
8333 TCGv_i64 t0 = tcg_temp_new_i64();
8334 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8335 tcg_gen_shli_i64(xth, xth, 32);
8336 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8337 tcg_gen_shri_i64(t0, t0, 32);
8338 tcg_gen_or_i64(xth, xth, t0);
8339 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8340 tcg_gen_shli_i64(xtl, xtl, 32);
8341 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8342 tcg_gen_shri_i64(t0, t0, 32);
8343 tcg_gen_or_i64(xtl, xtl, t0);
8344 tcg_temp_free_i64(t0);
8345 break;
8346 }
8347 case 2: {
8348 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8349 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8350 break;
8351 }
8352 case 3: {
8353 TCGv_i64 t0 = tcg_temp_new_i64();
8354 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8355 tcg_gen_shli_i64(xth, xth, 32);
8356 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8357 tcg_gen_shri_i64(t0, t0, 32);
8358 tcg_gen_or_i64(xth, xth, t0);
8359 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8360 tcg_gen_shli_i64(xtl, xtl, 32);
8361 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8362 tcg_gen_shri_i64(t0, t0, 32);
8363 tcg_gen_or_i64(xtl, xtl, t0);
8364 tcg_temp_free_i64(t0);
8365 break;
8366 }
8367 }
8368
8369 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8370 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8371
8372 tcg_temp_free_i64(xth);
8373 tcg_temp_free_i64(xtl);
8374 }
8375
8376 /*** Decimal Floating Point ***/
8377
8378 static inline TCGv_ptr gen_fprp_ptr(int reg)
8379 {
8380 TCGv_ptr r = tcg_temp_new_ptr();
8381 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8382 return r;
8383 }
8384
8385 #define GEN_DFP_T_A_B_Rc(name) \
8386 static void gen_##name(DisasContext *ctx) \
8387 { \
8388 TCGv_ptr rd, ra, rb; \
8389 if (unlikely(!ctx->fpu_enabled)) { \
8390 gen_exception(ctx, POWERPC_EXCP_FPU); \
8391 return; \
8392 } \
8393 gen_update_nip(ctx, ctx->nip - 4); \
8394 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8395 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8396 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8397 gen_helper_##name(cpu_env, rd, ra, rb); \
8398 if (unlikely(Rc(ctx->opcode) != 0)) { \
8399 gen_set_cr1_from_fpscr(ctx); \
8400 } \
8401 tcg_temp_free_ptr(rd); \
8402 tcg_temp_free_ptr(ra); \
8403 tcg_temp_free_ptr(rb); \
8404 }
8405
8406 #define GEN_DFP_BF_A_B(name) \
8407 static void gen_##name(DisasContext *ctx) \
8408 { \
8409 TCGv_ptr ra, rb; \
8410 if (unlikely(!ctx->fpu_enabled)) { \
8411 gen_exception(ctx, POWERPC_EXCP_FPU); \
8412 return; \
8413 } \
8414 gen_update_nip(ctx, ctx->nip - 4); \
8415 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8416 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8417 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8418 cpu_env, ra, rb); \
8419 tcg_temp_free_ptr(ra); \
8420 tcg_temp_free_ptr(rb); \
8421 }
8422
8423 #define GEN_DFP_BF_A_DCM(name) \
8424 static void gen_##name(DisasContext *ctx) \
8425 { \
8426 TCGv_ptr ra; \
8427 TCGv_i32 dcm; \
8428 if (unlikely(!ctx->fpu_enabled)) { \
8429 gen_exception(ctx, POWERPC_EXCP_FPU); \
8430 return; \
8431 } \
8432 gen_update_nip(ctx, ctx->nip - 4); \
8433 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8434 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8435 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8436 cpu_env, ra, dcm); \
8437 tcg_temp_free_ptr(ra); \
8438 tcg_temp_free_i32(dcm); \
8439 }
8440
8441 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8442 static void gen_##name(DisasContext *ctx) \
8443 { \
8444 TCGv_ptr rt, rb; \
8445 TCGv_i32 u32_1, u32_2; \
8446 if (unlikely(!ctx->fpu_enabled)) { \
8447 gen_exception(ctx, POWERPC_EXCP_FPU); \
8448 return; \
8449 } \
8450 gen_update_nip(ctx, ctx->nip - 4); \
8451 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8452 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8453 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8454 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8455 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8456 if (unlikely(Rc(ctx->opcode) != 0)) { \
8457 gen_set_cr1_from_fpscr(ctx); \
8458 } \
8459 tcg_temp_free_ptr(rt); \
8460 tcg_temp_free_ptr(rb); \
8461 tcg_temp_free_i32(u32_1); \
8462 tcg_temp_free_i32(u32_2); \
8463 }
8464
8465 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8466 static void gen_##name(DisasContext *ctx) \
8467 { \
8468 TCGv_ptr rt, ra, rb; \
8469 TCGv_i32 i32; \
8470 if (unlikely(!ctx->fpu_enabled)) { \
8471 gen_exception(ctx, POWERPC_EXCP_FPU); \
8472 return; \
8473 } \
8474 gen_update_nip(ctx, ctx->nip - 4); \
8475 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8476 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8477 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8478 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8479 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8480 if (unlikely(Rc(ctx->opcode) != 0)) { \
8481 gen_set_cr1_from_fpscr(ctx); \
8482 } \
8483 tcg_temp_free_ptr(rt); \
8484 tcg_temp_free_ptr(rb); \
8485 tcg_temp_free_ptr(ra); \
8486 tcg_temp_free_i32(i32); \
8487 }
8488
8489 #define GEN_DFP_T_B_Rc(name) \
8490 static void gen_##name(DisasContext *ctx) \
8491 { \
8492 TCGv_ptr rt, rb; \
8493 if (unlikely(!ctx->fpu_enabled)) { \
8494 gen_exception(ctx, POWERPC_EXCP_FPU); \
8495 return; \
8496 } \
8497 gen_update_nip(ctx, ctx->nip - 4); \
8498 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8499 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8500 gen_helper_##name(cpu_env, rt, rb); \
8501 if (unlikely(Rc(ctx->opcode) != 0)) { \
8502 gen_set_cr1_from_fpscr(ctx); \
8503 } \
8504 tcg_temp_free_ptr(rt); \
8505 tcg_temp_free_ptr(rb); \
8506 }
8507
8508 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8509 static void gen_##name(DisasContext *ctx) \
8510 { \
8511 TCGv_ptr rt, rs; \
8512 TCGv_i32 i32; \
8513 if (unlikely(!ctx->fpu_enabled)) { \
8514 gen_exception(ctx, POWERPC_EXCP_FPU); \
8515 return; \
8516 } \
8517 gen_update_nip(ctx, ctx->nip - 4); \
8518 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8519 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8520 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8521 gen_helper_##name(cpu_env, rt, rs, i32); \
8522 if (unlikely(Rc(ctx->opcode) != 0)) { \
8523 gen_set_cr1_from_fpscr(ctx); \
8524 } \
8525 tcg_temp_free_ptr(rt); \
8526 tcg_temp_free_ptr(rs); \
8527 tcg_temp_free_i32(i32); \
8528 }
8529
8530 GEN_DFP_T_A_B_Rc(dadd)
8531 GEN_DFP_T_A_B_Rc(daddq)
8532 GEN_DFP_T_A_B_Rc(dsub)
8533 GEN_DFP_T_A_B_Rc(dsubq)
8534 GEN_DFP_T_A_B_Rc(dmul)
8535 GEN_DFP_T_A_B_Rc(dmulq)
8536 GEN_DFP_T_A_B_Rc(ddiv)
8537 GEN_DFP_T_A_B_Rc(ddivq)
8538 GEN_DFP_BF_A_B(dcmpu)
8539 GEN_DFP_BF_A_B(dcmpuq)
8540 GEN_DFP_BF_A_B(dcmpo)
8541 GEN_DFP_BF_A_B(dcmpoq)
8542 GEN_DFP_BF_A_DCM(dtstdc)
8543 GEN_DFP_BF_A_DCM(dtstdcq)
8544 GEN_DFP_BF_A_DCM(dtstdg)
8545 GEN_DFP_BF_A_DCM(dtstdgq)
8546 GEN_DFP_BF_A_B(dtstex)
8547 GEN_DFP_BF_A_B(dtstexq)
8548 GEN_DFP_BF_A_B(dtstsf)
8549 GEN_DFP_BF_A_B(dtstsfq)
8550 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8551 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8552 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8553 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8554 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8555 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8556 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8557 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8558 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8559 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8560 GEN_DFP_T_B_Rc(dctdp)
8561 GEN_DFP_T_B_Rc(dctqpq)
8562 GEN_DFP_T_B_Rc(drsp)
8563 GEN_DFP_T_B_Rc(drdpq)
8564 GEN_DFP_T_B_Rc(dcffix)
8565 GEN_DFP_T_B_Rc(dcffixq)
8566 GEN_DFP_T_B_Rc(dctfix)
8567 GEN_DFP_T_B_Rc(dctfixq)
8568 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8569 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8570 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8571 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8572 GEN_DFP_T_B_Rc(dxex)
8573 GEN_DFP_T_B_Rc(dxexq)
8574 GEN_DFP_T_A_B_Rc(diex)
8575 GEN_DFP_T_A_B_Rc(diexq)
8576 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8577 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8578 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8579 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8580
8581 /*** SPE extension ***/
8582 /* Register moves */
8583
8584 static inline void gen_evmra(DisasContext *ctx)
8585 {
8586
8587 if (unlikely(!ctx->spe_enabled)) {
8588 gen_exception(ctx, POWERPC_EXCP_SPEU);
8589 return;
8590 }
8591
8592 TCGv_i64 tmp = tcg_temp_new_i64();
8593
8594 /* tmp := rA_lo + rA_hi << 32 */
8595 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8596
8597 /* spe_acc := tmp */
8598 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8599 tcg_temp_free_i64(tmp);
8600
8601 /* rD := rA */
8602 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8603 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8604 }
8605
8606 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8607 {
8608 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8609 }
8610
8611 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8612 {
8613 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8614 }
8615
8616 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8617 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8618 { \
8619 if (Rc(ctx->opcode)) \
8620 gen_##name1(ctx); \
8621 else \
8622 gen_##name0(ctx); \
8623 }
8624
8625 /* Handler for undefined SPE opcodes */
8626 static inline void gen_speundef(DisasContext *ctx)
8627 {
8628 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8629 }
8630
8631 /* SPE logic */
8632 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8633 static inline void gen_##name(DisasContext *ctx) \
8634 { \
8635 if (unlikely(!ctx->spe_enabled)) { \
8636 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8637 return; \
8638 } \
8639 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8640 cpu_gpr[rB(ctx->opcode)]); \
8641 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8642 cpu_gprh[rB(ctx->opcode)]); \
8643 }
8644
8645 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8646 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8647 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8648 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8649 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8650 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8651 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8652 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8653
8654 /* SPE logic immediate */
8655 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8656 static inline void gen_##name(DisasContext *ctx) \
8657 { \
8658 TCGv_i32 t0; \
8659 if (unlikely(!ctx->spe_enabled)) { \
8660 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8661 return; \
8662 } \
8663 t0 = tcg_temp_new_i32(); \
8664 \
8665 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8666 tcg_opi(t0, t0, rB(ctx->opcode)); \
8667 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8668 \
8669 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8670 tcg_opi(t0, t0, rB(ctx->opcode)); \
8671 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8672 \
8673 tcg_temp_free_i32(t0); \
8674 }
8675 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8676 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8677 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8678 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8679
8680 /* SPE arithmetic */
8681 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8682 static inline void gen_##name(DisasContext *ctx) \
8683 { \
8684 TCGv_i32 t0; \
8685 if (unlikely(!ctx->spe_enabled)) { \
8686 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8687 return; \
8688 } \
8689 t0 = tcg_temp_new_i32(); \
8690 \
8691 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8692 tcg_op(t0, t0); \
8693 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8694 \
8695 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8696 tcg_op(t0, t0); \
8697 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8698 \
8699 tcg_temp_free_i32(t0); \
8700 }
8701
8702 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8703 {
8704 TCGLabel *l1 = gen_new_label();
8705 TCGLabel *l2 = gen_new_label();
8706
8707 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8708 tcg_gen_neg_i32(ret, arg1);
8709 tcg_gen_br(l2);
8710 gen_set_label(l1);
8711 tcg_gen_mov_i32(ret, arg1);
8712 gen_set_label(l2);
8713 }
8714 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8715 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8716 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8717 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8718 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8719 {
8720 tcg_gen_addi_i32(ret, arg1, 0x8000);
8721 tcg_gen_ext16u_i32(ret, ret);
8722 }
8723 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8724 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8725 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8726
8727 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8728 static inline void gen_##name(DisasContext *ctx) \
8729 { \
8730 TCGv_i32 t0, t1; \
8731 if (unlikely(!ctx->spe_enabled)) { \
8732 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8733 return; \
8734 } \
8735 t0 = tcg_temp_new_i32(); \
8736 t1 = tcg_temp_new_i32(); \
8737 \
8738 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8739 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8740 tcg_op(t0, t0, t1); \
8741 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8742 \
8743 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8744 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8745 tcg_op(t0, t0, t1); \
8746 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8747 \
8748 tcg_temp_free_i32(t0); \
8749 tcg_temp_free_i32(t1); \
8750 }
8751
8752 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8753 {
8754 TCGLabel *l1 = gen_new_label();
8755 TCGLabel *l2 = gen_new_label();
8756 TCGv_i32 t0 = tcg_temp_local_new_i32();
8757
8758 /* No error here: 6 bits are used */
8759 tcg_gen_andi_i32(t0, arg2, 0x3F);
8760 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8761 tcg_gen_shr_i32(ret, arg1, t0);
8762 tcg_gen_br(l2);
8763 gen_set_label(l1);
8764 tcg_gen_movi_i32(ret, 0);
8765 gen_set_label(l2);
8766 tcg_temp_free_i32(t0);
8767 }
8768 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8769 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8770 {
8771 TCGLabel *l1 = gen_new_label();
8772 TCGLabel *l2 = gen_new_label();
8773 TCGv_i32 t0 = tcg_temp_local_new_i32();
8774
8775 /* No error here: 6 bits are used */
8776 tcg_gen_andi_i32(t0, arg2, 0x3F);
8777 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8778 tcg_gen_sar_i32(ret, arg1, t0);
8779 tcg_gen_br(l2);
8780 gen_set_label(l1);
8781 tcg_gen_movi_i32(ret, 0);
8782 gen_set_label(l2);
8783 tcg_temp_free_i32(t0);
8784 }
8785 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8786 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8787 {
8788 TCGLabel *l1 = gen_new_label();
8789 TCGLabel *l2 = gen_new_label();
8790 TCGv_i32 t0 = tcg_temp_local_new_i32();
8791
8792 /* No error here: 6 bits are used */
8793 tcg_gen_andi_i32(t0, arg2, 0x3F);
8794 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8795 tcg_gen_shl_i32(ret, arg1, t0);
8796 tcg_gen_br(l2);
8797 gen_set_label(l1);
8798 tcg_gen_movi_i32(ret, 0);
8799 gen_set_label(l2);
8800 tcg_temp_free_i32(t0);
8801 }
8802 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8803 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8804 {
8805 TCGv_i32 t0 = tcg_temp_new_i32();
8806 tcg_gen_andi_i32(t0, arg2, 0x1F);
8807 tcg_gen_rotl_i32(ret, arg1, t0);
8808 tcg_temp_free_i32(t0);
8809 }
8810 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8811 static inline void gen_evmergehi(DisasContext *ctx)
8812 {
8813 if (unlikely(!ctx->spe_enabled)) {
8814 gen_exception(ctx, POWERPC_EXCP_SPEU);
8815 return;
8816 }
8817 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8818 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8819 }
8820 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8821 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8822 {
8823 tcg_gen_sub_i32(ret, arg2, arg1);
8824 }
8825 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8826
8827 /* SPE arithmetic immediate */
8828 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8829 static inline void gen_##name(DisasContext *ctx) \
8830 { \
8831 TCGv_i32 t0; \
8832 if (unlikely(!ctx->spe_enabled)) { \
8833 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8834 return; \
8835 } \
8836 t0 = tcg_temp_new_i32(); \
8837 \
8838 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8839 tcg_op(t0, t0, rA(ctx->opcode)); \
8840 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8841 \
8842 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8843 tcg_op(t0, t0, rA(ctx->opcode)); \
8844 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8845 \
8846 tcg_temp_free_i32(t0); \
8847 }
8848 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8849 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8850
8851 /* SPE comparison */
8852 #define GEN_SPEOP_COMP(name, tcg_cond) \
8853 static inline void gen_##name(DisasContext *ctx) \
8854 { \
8855 if (unlikely(!ctx->spe_enabled)) { \
8856 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8857 return; \
8858 } \
8859 TCGLabel *l1 = gen_new_label(); \
8860 TCGLabel *l2 = gen_new_label(); \
8861 TCGLabel *l3 = gen_new_label(); \
8862 TCGLabel *l4 = gen_new_label(); \
8863 \
8864 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8865 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8866 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8867 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8868 \
8869 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8870 cpu_gpr[rB(ctx->opcode)], l1); \
8871 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8872 tcg_gen_br(l2); \
8873 gen_set_label(l1); \
8874 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8875 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8876 gen_set_label(l2); \
8877 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8878 cpu_gprh[rB(ctx->opcode)], l3); \
8879 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8880 ~(CRF_CH | CRF_CH_AND_CL)); \
8881 tcg_gen_br(l4); \
8882 gen_set_label(l3); \
8883 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8884 CRF_CH | CRF_CH_OR_CL); \
8885 gen_set_label(l4); \
8886 }
8887 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8888 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8889 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8890 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8891 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8892
8893 /* SPE misc */
8894 static inline void gen_brinc(DisasContext *ctx)
8895 {
8896 /* Note: brinc is usable even if SPE is disabled */
8897 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8898 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8899 }
8900 static inline void gen_evmergelo(DisasContext *ctx)
8901 {
8902 if (unlikely(!ctx->spe_enabled)) {
8903 gen_exception(ctx, POWERPC_EXCP_SPEU);
8904 return;
8905 }
8906 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8907 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8908 }
8909 static inline void gen_evmergehilo(DisasContext *ctx)
8910 {
8911 if (unlikely(!ctx->spe_enabled)) {
8912 gen_exception(ctx, POWERPC_EXCP_SPEU);
8913 return;
8914 }
8915 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8916 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8917 }
8918 static inline void gen_evmergelohi(DisasContext *ctx)
8919 {
8920 if (unlikely(!ctx->spe_enabled)) {
8921 gen_exception(ctx, POWERPC_EXCP_SPEU);
8922 return;
8923 }
8924 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8925 TCGv tmp = tcg_temp_new();
8926 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8927 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8928 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8929 tcg_temp_free(tmp);
8930 } else {
8931 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8932 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8933 }
8934 }
8935 static inline void gen_evsplati(DisasContext *ctx)
8936 {
8937 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8938
8939 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8940 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8941 }
8942 static inline void gen_evsplatfi(DisasContext *ctx)
8943 {
8944 uint64_t imm = rA(ctx->opcode) << 27;
8945
8946 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8947 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8948 }
8949
8950 static inline void gen_evsel(DisasContext *ctx)
8951 {
8952 TCGLabel *l1 = gen_new_label();
8953 TCGLabel *l2 = gen_new_label();
8954 TCGLabel *l3 = gen_new_label();
8955 TCGLabel *l4 = gen_new_label();
8956 TCGv_i32 t0 = tcg_temp_local_new_i32();
8957
8958 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8959 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8960 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8961 tcg_gen_br(l2);
8962 gen_set_label(l1);
8963 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8964 gen_set_label(l2);
8965 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8966 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8967 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8968 tcg_gen_br(l4);
8969 gen_set_label(l3);
8970 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8971 gen_set_label(l4);
8972 tcg_temp_free_i32(t0);
8973 }
8974
8975 static void gen_evsel0(DisasContext *ctx)
8976 {
8977 gen_evsel(ctx);
8978 }
8979
8980 static void gen_evsel1(DisasContext *ctx)
8981 {
8982 gen_evsel(ctx);
8983 }
8984
8985 static void gen_evsel2(DisasContext *ctx)
8986 {
8987 gen_evsel(ctx);
8988 }
8989
8990 static void gen_evsel3(DisasContext *ctx)
8991 {
8992 gen_evsel(ctx);
8993 }
8994
8995 /* Multiply */
8996
8997 static inline void gen_evmwumi(DisasContext *ctx)
8998 {
8999 TCGv_i64 t0, t1;
9000
9001 if (unlikely(!ctx->spe_enabled)) {
9002 gen_exception(ctx, POWERPC_EXCP_SPEU);
9003 return;
9004 }
9005
9006 t0 = tcg_temp_new_i64();
9007 t1 = tcg_temp_new_i64();
9008
9009 /* t0 := rA; t1 := rB */
9010 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9011 tcg_gen_ext32u_i64(t0, t0);
9012 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9013 tcg_gen_ext32u_i64(t1, t1);
9014
9015 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9016
9017 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9018
9019 tcg_temp_free_i64(t0);
9020 tcg_temp_free_i64(t1);
9021 }
9022
9023 static inline void gen_evmwumia(DisasContext *ctx)
9024 {
9025 TCGv_i64 tmp;
9026
9027 if (unlikely(!ctx->spe_enabled)) {
9028 gen_exception(ctx, POWERPC_EXCP_SPEU);
9029 return;
9030 }
9031
9032 gen_evmwumi(ctx); /* rD := rA * rB */
9033
9034 tmp = tcg_temp_new_i64();
9035
9036 /* acc := rD */
9037 gen_load_gpr64(tmp, rD(ctx->opcode));
9038 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9039 tcg_temp_free_i64(tmp);
9040 }
9041
9042 static inline void gen_evmwumiaa(DisasContext *ctx)
9043 {
9044 TCGv_i64 acc;
9045 TCGv_i64 tmp;
9046
9047 if (unlikely(!ctx->spe_enabled)) {
9048 gen_exception(ctx, POWERPC_EXCP_SPEU);
9049 return;
9050 }
9051
9052 gen_evmwumi(ctx); /* rD := rA * rB */
9053
9054 acc = tcg_temp_new_i64();
9055 tmp = tcg_temp_new_i64();
9056
9057 /* tmp := rD */
9058 gen_load_gpr64(tmp, rD(ctx->opcode));
9059
9060 /* Load acc */
9061 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9062
9063 /* acc := tmp + acc */
9064 tcg_gen_add_i64(acc, acc, tmp);
9065
9066 /* Store acc */
9067 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9068
9069 /* rD := acc */
9070 gen_store_gpr64(rD(ctx->opcode), acc);
9071
9072 tcg_temp_free_i64(acc);
9073 tcg_temp_free_i64(tmp);
9074 }
9075
9076 static inline void gen_evmwsmi(DisasContext *ctx)
9077 {
9078 TCGv_i64 t0, t1;
9079
9080 if (unlikely(!ctx->spe_enabled)) {
9081 gen_exception(ctx, POWERPC_EXCP_SPEU);
9082 return;
9083 }
9084
9085 t0 = tcg_temp_new_i64();
9086 t1 = tcg_temp_new_i64();
9087
9088 /* t0 := rA; t1 := rB */
9089 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
9090 tcg_gen_ext32s_i64(t0, t0);
9091 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
9092 tcg_gen_ext32s_i64(t1, t1);
9093
9094 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
9095
9096 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
9097
9098 tcg_temp_free_i64(t0);
9099 tcg_temp_free_i64(t1);
9100 }
9101
9102 static inline void gen_evmwsmia(DisasContext *ctx)
9103 {
9104 TCGv_i64 tmp;
9105
9106 gen_evmwsmi(ctx); /* rD := rA * rB */
9107
9108 tmp = tcg_temp_new_i64();
9109
9110 /* acc := rD */
9111 gen_load_gpr64(tmp, rD(ctx->opcode));
9112 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
9113
9114 tcg_temp_free_i64(tmp);
9115 }
9116
9117 static inline void gen_evmwsmiaa(DisasContext *ctx)
9118 {
9119 TCGv_i64 acc = tcg_temp_new_i64();
9120 TCGv_i64 tmp = tcg_temp_new_i64();
9121
9122 gen_evmwsmi(ctx); /* rD := rA * rB */
9123
9124 acc = tcg_temp_new_i64();
9125 tmp = tcg_temp_new_i64();
9126
9127 /* tmp := rD */
9128 gen_load_gpr64(tmp, rD(ctx->opcode));
9129
9130 /* Load acc */
9131 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9132
9133 /* acc := tmp + acc */
9134 tcg_gen_add_i64(acc, acc, tmp);
9135
9136 /* Store acc */
9137 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9138
9139 /* rD := acc */
9140 gen_store_gpr64(rD(ctx->opcode), acc);
9141
9142 tcg_temp_free_i64(acc);
9143 tcg_temp_free_i64(tmp);
9144 }
9145
9146 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9147 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9148 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9149 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9150 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9151 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9152 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9153 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9154 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9155 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9156 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9157 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9158 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9159 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9160 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9161 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9162 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9163 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9164 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9165 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9166 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9167 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9168 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9169 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9170 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9171 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9172 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9173 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9174 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9175
9176 /* SPE load and stores */
9177 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9178 {
9179 target_ulong uimm = rB(ctx->opcode);
9180
9181 if (rA(ctx->opcode) == 0) {
9182 tcg_gen_movi_tl(EA, uimm << sh);
9183 } else {
9184 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9185 if (NARROW_MODE(ctx)) {
9186 tcg_gen_ext32u_tl(EA, EA);
9187 }
9188 }
9189 }
9190
9191 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9192 {
9193 TCGv_i64 t0 = tcg_temp_new_i64();
9194 gen_qemu_ld64(ctx, t0, addr);
9195 gen_store_gpr64(rD(ctx->opcode), t0);
9196 tcg_temp_free_i64(t0);
9197 }
9198
9199 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9200 {
9201 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9202 gen_addr_add(ctx, addr, addr, 4);
9203 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9204 }
9205
9206 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9207 {
9208 TCGv t0 = tcg_temp_new();
9209 gen_qemu_ld16u(ctx, t0, addr);
9210 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9211 gen_addr_add(ctx, addr, addr, 2);
9212 gen_qemu_ld16u(ctx, t0, addr);
9213 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9214 gen_addr_add(ctx, addr, addr, 2);
9215 gen_qemu_ld16u(ctx, t0, addr);
9216 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9217 gen_addr_add(ctx, addr, addr, 2);
9218 gen_qemu_ld16u(ctx, t0, addr);
9219 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9220 tcg_temp_free(t0);
9221 }
9222
9223 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9224 {
9225 TCGv t0 = tcg_temp_new();
9226 gen_qemu_ld16u(ctx, t0, addr);
9227 tcg_gen_shli_tl(t0, t0, 16);
9228 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9229 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9230 tcg_temp_free(t0);
9231 }
9232
9233 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9234 {
9235 TCGv t0 = tcg_temp_new();
9236 gen_qemu_ld16u(ctx, t0, addr);
9237 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9238 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9239 tcg_temp_free(t0);
9240 }
9241
9242 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9243 {
9244 TCGv t0 = tcg_temp_new();
9245 gen_qemu_ld16s(ctx, t0, addr);
9246 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9247 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9248 tcg_temp_free(t0);
9249 }
9250
9251 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9252 {
9253 TCGv t0 = tcg_temp_new();
9254 gen_qemu_ld16u(ctx, t0, addr);
9255 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9256 gen_addr_add(ctx, addr, addr, 2);
9257 gen_qemu_ld16u(ctx, t0, addr);
9258 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9259 tcg_temp_free(t0);
9260 }
9261
9262 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9263 {
9264 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9265 gen_addr_add(ctx, addr, addr, 2);
9266 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9267 }
9268
9269 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9270 {
9271 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9272 gen_addr_add(ctx, addr, addr, 2);
9273 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9274 }
9275
9276 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9277 {
9278 TCGv t0 = tcg_temp_new();
9279 gen_qemu_ld32u(ctx, t0, addr);
9280 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9281 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9282 tcg_temp_free(t0);
9283 }
9284
9285 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9286 {
9287 TCGv t0 = tcg_temp_new();
9288 gen_qemu_ld16u(ctx, t0, addr);
9289 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9290 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9291 gen_addr_add(ctx, addr, addr, 2);
9292 gen_qemu_ld16u(ctx, t0, addr);
9293 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9294 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9295 tcg_temp_free(t0);
9296 }
9297
9298 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9299 {
9300 TCGv_i64 t0 = tcg_temp_new_i64();
9301 gen_load_gpr64(t0, rS(ctx->opcode));
9302 gen_qemu_st64(ctx, t0, addr);
9303 tcg_temp_free_i64(t0);
9304 }
9305
9306 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9307 {
9308 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9309 gen_addr_add(ctx, addr, addr, 4);
9310 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9311 }
9312
9313 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9314 {
9315 TCGv t0 = tcg_temp_new();
9316 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9317 gen_qemu_st16(ctx, t0, addr);
9318 gen_addr_add(ctx, addr, addr, 2);
9319 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9320 gen_addr_add(ctx, addr, addr, 2);
9321 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9322 gen_qemu_st16(ctx, t0, addr);
9323 tcg_temp_free(t0);
9324 gen_addr_add(ctx, addr, addr, 2);
9325 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9326 }
9327
9328 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9329 {
9330 TCGv t0 = tcg_temp_new();
9331 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9332 gen_qemu_st16(ctx, t0, addr);
9333 gen_addr_add(ctx, addr, addr, 2);
9334 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9335 gen_qemu_st16(ctx, t0, addr);
9336 tcg_temp_free(t0);
9337 }
9338
9339 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9340 {
9341 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9342 gen_addr_add(ctx, addr, addr, 2);
9343 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9344 }
9345
9346 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9347 {
9348 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9349 }
9350
9351 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9352 {
9353 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9354 }
9355
9356 #define GEN_SPEOP_LDST(name, opc2, sh) \
9357 static void glue(gen_, name)(DisasContext *ctx) \
9358 { \
9359 TCGv t0; \
9360 if (unlikely(!ctx->spe_enabled)) { \
9361 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9362 return; \
9363 } \
9364 gen_set_access_type(ctx, ACCESS_INT); \
9365 t0 = tcg_temp_new(); \
9366 if (Rc(ctx->opcode)) { \
9367 gen_addr_spe_imm_index(ctx, t0, sh); \
9368 } else { \
9369 gen_addr_reg_index(ctx, t0); \
9370 } \
9371 gen_op_##name(ctx, t0); \
9372 tcg_temp_free(t0); \
9373 }
9374
9375 GEN_SPEOP_LDST(evldd, 0x00, 3);
9376 GEN_SPEOP_LDST(evldw, 0x01, 3);
9377 GEN_SPEOP_LDST(evldh, 0x02, 3);
9378 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9379 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9380 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9381 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9382 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9383 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9384 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9385 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9386
9387 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9388 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9389 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9390 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9391 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9392 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9393 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9394
9395 /* Multiply and add - TODO */
9396 #if 0
9397 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9398 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9399 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9400 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9401 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9402 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9403 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9404 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9405 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9406 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9407 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9408 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9409
9410 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9411 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9412 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9413 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9414 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9415 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9416 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9417 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9418 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9419 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9420 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9421 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9422
9423 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9424 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9425 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9426 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9427 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9428
9429 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9430 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9431 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9432 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9433 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9434 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9435 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9436 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9437 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9438 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9439 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9440 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9441
9442 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9443 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9444 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9445 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9446
9447 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9448 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9449 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9450 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9451 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9452 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9453 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9454 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9455 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9456 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9457 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9458 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9459
9460 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9461 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9462 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9463 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9464 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9465 #endif
9466
9467 /*** SPE floating-point extension ***/
9468 #define GEN_SPEFPUOP_CONV_32_32(name) \
9469 static inline void gen_##name(DisasContext *ctx) \
9470 { \
9471 TCGv_i32 t0 = tcg_temp_new_i32(); \
9472 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9473 gen_helper_##name(t0, cpu_env, t0); \
9474 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9475 tcg_temp_free_i32(t0); \
9476 }
9477 #define GEN_SPEFPUOP_CONV_32_64(name) \
9478 static inline void gen_##name(DisasContext *ctx) \
9479 { \
9480 TCGv_i64 t0 = tcg_temp_new_i64(); \
9481 TCGv_i32 t1 = tcg_temp_new_i32(); \
9482 gen_load_gpr64(t0, rB(ctx->opcode)); \
9483 gen_helper_##name(t1, cpu_env, t0); \
9484 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9485 tcg_temp_free_i64(t0); \
9486 tcg_temp_free_i32(t1); \
9487 }
9488 #define GEN_SPEFPUOP_CONV_64_32(name) \
9489 static inline void gen_##name(DisasContext *ctx) \
9490 { \
9491 TCGv_i64 t0 = tcg_temp_new_i64(); \
9492 TCGv_i32 t1 = tcg_temp_new_i32(); \
9493 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9494 gen_helper_##name(t0, cpu_env, t1); \
9495 gen_store_gpr64(rD(ctx->opcode), t0); \
9496 tcg_temp_free_i64(t0); \
9497 tcg_temp_free_i32(t1); \
9498 }
9499 #define GEN_SPEFPUOP_CONV_64_64(name) \
9500 static inline void gen_##name(DisasContext *ctx) \
9501 { \
9502 TCGv_i64 t0 = tcg_temp_new_i64(); \
9503 gen_load_gpr64(t0, rB(ctx->opcode)); \
9504 gen_helper_##name(t0, cpu_env, t0); \
9505 gen_store_gpr64(rD(ctx->opcode), t0); \
9506 tcg_temp_free_i64(t0); \
9507 }
9508 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9509 static inline void gen_##name(DisasContext *ctx) \
9510 { \
9511 TCGv_i32 t0, t1; \
9512 if (unlikely(!ctx->spe_enabled)) { \
9513 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9514 return; \
9515 } \
9516 t0 = tcg_temp_new_i32(); \
9517 t1 = tcg_temp_new_i32(); \
9518 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9519 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9520 gen_helper_##name(t0, cpu_env, t0, t1); \
9521 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9522 \
9523 tcg_temp_free_i32(t0); \
9524 tcg_temp_free_i32(t1); \
9525 }
9526 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9527 static inline void gen_##name(DisasContext *ctx) \
9528 { \
9529 TCGv_i64 t0, t1; \
9530 if (unlikely(!ctx->spe_enabled)) { \
9531 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9532 return; \
9533 } \
9534 t0 = tcg_temp_new_i64(); \
9535 t1 = tcg_temp_new_i64(); \
9536 gen_load_gpr64(t0, rA(ctx->opcode)); \
9537 gen_load_gpr64(t1, rB(ctx->opcode)); \
9538 gen_helper_##name(t0, cpu_env, t0, t1); \
9539 gen_store_gpr64(rD(ctx->opcode), t0); \
9540 tcg_temp_free_i64(t0); \
9541 tcg_temp_free_i64(t1); \
9542 }
9543 #define GEN_SPEFPUOP_COMP_32(name) \
9544 static inline void gen_##name(DisasContext *ctx) \
9545 { \
9546 TCGv_i32 t0, t1; \
9547 if (unlikely(!ctx->spe_enabled)) { \
9548 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9549 return; \
9550 } \
9551 t0 = tcg_temp_new_i32(); \
9552 t1 = tcg_temp_new_i32(); \
9553 \
9554 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9555 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9556 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9557 \
9558 tcg_temp_free_i32(t0); \
9559 tcg_temp_free_i32(t1); \
9560 }
9561 #define GEN_SPEFPUOP_COMP_64(name) \
9562 static inline void gen_##name(DisasContext *ctx) \
9563 { \
9564 TCGv_i64 t0, t1; \
9565 if (unlikely(!ctx->spe_enabled)) { \
9566 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9567 return; \
9568 } \
9569 t0 = tcg_temp_new_i64(); \
9570 t1 = tcg_temp_new_i64(); \
9571 gen_load_gpr64(t0, rA(ctx->opcode)); \
9572 gen_load_gpr64(t1, rB(ctx->opcode)); \
9573 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9574 tcg_temp_free_i64(t0); \
9575 tcg_temp_free_i64(t1); \
9576 }
9577
9578 /* Single precision floating-point vectors operations */
9579 /* Arithmetic */
9580 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9581 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9582 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9583 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9584 static inline void gen_evfsabs(DisasContext *ctx)
9585 {
9586 if (unlikely(!ctx->spe_enabled)) {
9587 gen_exception(ctx, POWERPC_EXCP_SPEU);
9588 return;
9589 }
9590 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9591 ~0x80000000);
9592 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9593 ~0x80000000);
9594 }
9595 static inline void gen_evfsnabs(DisasContext *ctx)
9596 {
9597 if (unlikely(!ctx->spe_enabled)) {
9598 gen_exception(ctx, POWERPC_EXCP_SPEU);
9599 return;
9600 }
9601 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9602 0x80000000);
9603 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9604 0x80000000);
9605 }
9606 static inline void gen_evfsneg(DisasContext *ctx)
9607 {
9608 if (unlikely(!ctx->spe_enabled)) {
9609 gen_exception(ctx, POWERPC_EXCP_SPEU);
9610 return;
9611 }
9612 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9613 0x80000000);
9614 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9615 0x80000000);
9616 }
9617
9618 /* Conversion */
9619 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9620 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9621 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9622 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9623 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9624 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9625 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9626 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9627 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9628 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9629
9630 /* Comparison */
9631 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9632 GEN_SPEFPUOP_COMP_64(evfscmplt);
9633 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9634 GEN_SPEFPUOP_COMP_64(evfststgt);
9635 GEN_SPEFPUOP_COMP_64(evfststlt);
9636 GEN_SPEFPUOP_COMP_64(evfststeq);
9637
9638 /* Opcodes definitions */
9639 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9640 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9641 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9642 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9643 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9644 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9645 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9646 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9647 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9648 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9649 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9650 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9651 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9652 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9653
9654 /* Single precision floating-point operations */
9655 /* Arithmetic */
9656 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9657 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9658 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9659 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9660 static inline void gen_efsabs(DisasContext *ctx)
9661 {
9662 if (unlikely(!ctx->spe_enabled)) {
9663 gen_exception(ctx, POWERPC_EXCP_SPEU);
9664 return;
9665 }
9666 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9667 }
9668 static inline void gen_efsnabs(DisasContext *ctx)
9669 {
9670 if (unlikely(!ctx->spe_enabled)) {
9671 gen_exception(ctx, POWERPC_EXCP_SPEU);
9672 return;
9673 }
9674 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9675 }
9676 static inline void gen_efsneg(DisasContext *ctx)
9677 {
9678 if (unlikely(!ctx->spe_enabled)) {
9679 gen_exception(ctx, POWERPC_EXCP_SPEU);
9680 return;
9681 }
9682 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9683 }
9684
9685 /* Conversion */
9686 GEN_SPEFPUOP_CONV_32_32(efscfui);
9687 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9688 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9689 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9690 GEN_SPEFPUOP_CONV_32_32(efsctui);
9691 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9692 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9693 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9694 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9695 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9696 GEN_SPEFPUOP_CONV_32_64(efscfd);
9697
9698 /* Comparison */
9699 GEN_SPEFPUOP_COMP_32(efscmpgt);
9700 GEN_SPEFPUOP_COMP_32(efscmplt);
9701 GEN_SPEFPUOP_COMP_32(efscmpeq);
9702 GEN_SPEFPUOP_COMP_32(efststgt);
9703 GEN_SPEFPUOP_COMP_32(efststlt);
9704 GEN_SPEFPUOP_COMP_32(efststeq);
9705
9706 /* Opcodes definitions */
9707 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9708 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9709 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9710 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9711 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9712 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9713 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9714 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9715 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9716 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9717 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9718 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9719 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9720 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9721
9722 /* Double precision floating-point operations */
9723 /* Arithmetic */
9724 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9725 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9726 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9727 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9728 static inline void gen_efdabs(DisasContext *ctx)
9729 {
9730 if (unlikely(!ctx->spe_enabled)) {
9731 gen_exception(ctx, POWERPC_EXCP_SPEU);
9732 return;
9733 }
9734 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9735 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9736 ~0x80000000);
9737 }
9738 static inline void gen_efdnabs(DisasContext *ctx)
9739 {
9740 if (unlikely(!ctx->spe_enabled)) {
9741 gen_exception(ctx, POWERPC_EXCP_SPEU);
9742 return;
9743 }
9744 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9745 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9746 0x80000000);
9747 }
9748 static inline void gen_efdneg(DisasContext *ctx)
9749 {
9750 if (unlikely(!ctx->spe_enabled)) {
9751 gen_exception(ctx, POWERPC_EXCP_SPEU);
9752 return;
9753 }
9754 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9755 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9756 0x80000000);
9757 }
9758
9759 /* Conversion */
9760 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9761 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9762 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9763 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9764 GEN_SPEFPUOP_CONV_32_64(efdctui);
9765 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9766 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9767 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9768 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9769 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9770 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9771 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9772 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9773 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9774 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9775
9776 /* Comparison */
9777 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9778 GEN_SPEFPUOP_COMP_64(efdcmplt);
9779 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9780 GEN_SPEFPUOP_COMP_64(efdtstgt);
9781 GEN_SPEFPUOP_COMP_64(efdtstlt);
9782 GEN_SPEFPUOP_COMP_64(efdtsteq);
9783
9784 /* Opcodes definitions */
9785 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9786 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9787 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9788 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9789 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9790 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9791 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9792 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9793 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9794 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9795 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9796 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9797 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9798 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9799 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9800 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9801
9802 static void gen_tbegin(DisasContext *ctx)
9803 {
9804 if (unlikely(!ctx->tm_enabled)) {
9805 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9806 return;
9807 }
9808 gen_helper_tbegin(cpu_env);
9809 }
9810
9811 #define GEN_TM_NOOP(name) \
9812 static inline void gen_##name(DisasContext *ctx) \
9813 { \
9814 if (unlikely(!ctx->tm_enabled)) { \
9815 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9816 return; \
9817 } \
9818 /* Because tbegin always fails in QEMU, these user \
9819 * space instructions all have a simple implementation: \
9820 * \
9821 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9822 * = 0b0 || 0b00 || 0b0 \
9823 */ \
9824 tcg_gen_movi_i32(cpu_crf[0], 0); \
9825 }
9826
9827 GEN_TM_NOOP(tend);
9828 GEN_TM_NOOP(tabort);
9829 GEN_TM_NOOP(tabortwc);
9830 GEN_TM_NOOP(tabortwci);
9831 GEN_TM_NOOP(tabortdc);
9832 GEN_TM_NOOP(tabortdci);
9833 GEN_TM_NOOP(tsr);
9834
9835 static void gen_tcheck(DisasContext *ctx)
9836 {
9837 if (unlikely(!ctx->tm_enabled)) {
9838 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9839 return;
9840 }
9841 /* Because tbegin always fails, the tcheck implementation
9842 * is simple:
9843 *
9844 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9845 * = 0b1 || 0b00 || 0b0
9846 */
9847 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9848 }
9849
9850 #if defined(CONFIG_USER_ONLY)
9851 #define GEN_TM_PRIV_NOOP(name) \
9852 static inline void gen_##name(DisasContext *ctx) \
9853 { \
9854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9855 }
9856
9857 #else
9858
9859 #define GEN_TM_PRIV_NOOP(name) \
9860 static inline void gen_##name(DisasContext *ctx) \
9861 { \
9862 if (unlikely(ctx->pr)) { \
9863 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9864 return; \
9865 } \
9866 if (unlikely(!ctx->tm_enabled)) { \
9867 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9868 return; \
9869 } \
9870 /* Because tbegin always fails, the implementation is \
9871 * simple: \
9872 * \
9873 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9874 * = 0b0 || 0b00 | 0b0 \
9875 */ \
9876 tcg_gen_movi_i32(cpu_crf[0], 0); \
9877 }
9878
9879 #endif
9880
9881 GEN_TM_PRIV_NOOP(treclaim);
9882 GEN_TM_PRIV_NOOP(trechkpt);
9883
9884 static opcode_t opcodes[] = {
9885 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9886 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9887 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9888 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9889 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9890 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9891 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9892 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9893 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9894 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9895 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9896 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9897 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9898 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9899 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9900 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9901 #if defined(TARGET_PPC64)
9902 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9903 #endif
9904 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9905 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9906 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9907 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9908 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9909 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9910 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9911 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9912 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9913 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9914 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9915 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9916 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9917 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9918 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9919 #if defined(TARGET_PPC64)
9920 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9921 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9922 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9923 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9924 #endif
9925 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9926 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9927 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9928 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9929 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9930 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9931 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9932 #if defined(TARGET_PPC64)
9933 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9934 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9935 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9936 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9937 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9938 #endif
9939 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9940 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9941 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9942 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9943 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9944 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9945 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9946 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9947 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9948 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9949 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9950 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9951 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9952 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9953 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9954 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9955 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9956 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9957 #if defined(TARGET_PPC64)
9958 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9959 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9960 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9961 #endif
9962 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9963 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9964 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9965 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9966 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9967 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9968 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9969 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9970 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9971 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9972 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9973 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9974 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9975 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9976 #if defined(TARGET_PPC64)
9977 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9978 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9979 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9980 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9981 #endif
9982 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9983 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9984 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9985 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9986 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9987 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9988 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9989 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9990 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9991 #if defined(TARGET_PPC64)
9992 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9993 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9994 #endif
9995 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9996 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9997 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9998 #if defined(TARGET_PPC64)
9999 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
10000 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
10001 #endif
10002 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
10003 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
10004 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
10005 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
10006 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
10007 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
10008 #if defined(TARGET_PPC64)
10009 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
10010 #endif
10011 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC),
10012 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC),
10013 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
10014 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
10015 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
10016 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
10017 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
10018 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
10019 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
10020 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
10021 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
10022 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
10023 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
10024 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
10025 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
10026 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
10027 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
10028 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
10029 #if defined(TARGET_PPC64)
10030 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
10031 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
10032 PPC_SEGMENT_64B),
10033 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
10034 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
10035 PPC_SEGMENT_64B),
10036 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
10037 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
10038 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
10039 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
10040 #endif
10041 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
10042 /* XXX Those instructions will need to be handled differently for
10043 * different ISA versions */
10044 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
10045 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
10046 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
10047 #if defined(TARGET_PPC64)
10048 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
10049 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
10050 #endif
10051 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
10052 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
10053 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
10054 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
10055 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
10056 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
10057 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
10058 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
10059 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
10060 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
10061 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
10062 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10063 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
10064 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
10065 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
10066 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
10067 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
10068 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
10069 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
10070 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
10071 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
10072 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
10073 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
10074 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
10075 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
10076 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
10077 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
10078 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
10079 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
10080 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
10081 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
10082 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
10083 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
10084 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
10085 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
10086 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
10087 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
10088 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
10089 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
10090 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
10091 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
10092 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
10093 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
10094 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
10095 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
10096 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
10097 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
10098 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
10099 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
10100 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10101 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10102 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
10103 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
10104 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10105 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
10106 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
10107 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
10108 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
10109 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
10110 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
10111 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
10112 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
10113 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
10114 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
10115 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
10116 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
10117 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
10118 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
10119 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
10120 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
10121 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
10122 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10123 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10124 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10125 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10126 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10127 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10128 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10129 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10130 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10131 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10132 PPC_NONE, PPC2_BOOKE206),
10133 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10134 PPC_NONE, PPC2_BOOKE206),
10135 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10136 PPC_NONE, PPC2_BOOKE206),
10137 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10138 PPC_NONE, PPC2_BOOKE206),
10139 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10140 PPC_NONE, PPC2_BOOKE206),
10141 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10142 PPC_NONE, PPC2_PRCNTL),
10143 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10144 PPC_NONE, PPC2_PRCNTL),
10145 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10146 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10147 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10148 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10149 PPC_BOOKE, PPC2_BOOKE206),
10150 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10151 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10152 PPC_BOOKE, PPC2_BOOKE206),
10153 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10154 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10155 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10156 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10157 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10158 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10159 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10160 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10161 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10162
10163 #undef GEN_INT_ARITH_ADD
10164 #undef GEN_INT_ARITH_ADD_CONST
10165 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10166 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10167 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10168 add_ca, compute_ca, compute_ov) \
10169 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10170 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10171 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10172 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10173 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10174 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10175 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10176 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10177 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10178 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10179 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10180
10181 #undef GEN_INT_ARITH_DIVW
10182 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10183 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10184 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10185 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10186 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10187 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10188 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10189 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10190 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10191 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10192
10193 #if defined(TARGET_PPC64)
10194 #undef GEN_INT_ARITH_DIVD
10195 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10196 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10197 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10198 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10199 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10200 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10201
10202 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10203 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10204 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10205 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10206
10207 #undef GEN_INT_ARITH_MUL_HELPER
10208 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10209 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10210 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10211 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10212 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10213 #endif
10214
10215 #undef GEN_INT_ARITH_SUBF
10216 #undef GEN_INT_ARITH_SUBF_CONST
10217 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10218 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10219 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10220 add_ca, compute_ca, compute_ov) \
10221 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10222 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10223 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10224 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10225 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10226 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10227 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10228 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10229 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10230 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10231 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10232
10233 #undef GEN_LOGICAL1
10234 #undef GEN_LOGICAL2
10235 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10236 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10237 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10238 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10239 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10240 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10241 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10242 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10243 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10244 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10245 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10246 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10247 #if defined(TARGET_PPC64)
10248 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10249 #endif
10250
10251 #if defined(TARGET_PPC64)
10252 #undef GEN_PPC64_R2
10253 #undef GEN_PPC64_R4
10254 #define GEN_PPC64_R2(name, opc1, opc2) \
10255 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10256 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10257 PPC_64B)
10258 #define GEN_PPC64_R4(name, opc1, opc2) \
10259 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10260 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10261 PPC_64B), \
10262 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10263 PPC_64B), \
10264 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10265 PPC_64B)
10266 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10267 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10268 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10269 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10270 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10271 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10272 #endif
10273
10274 #undef _GEN_FLOAT_ACB
10275 #undef GEN_FLOAT_ACB
10276 #undef _GEN_FLOAT_AB
10277 #undef GEN_FLOAT_AB
10278 #undef _GEN_FLOAT_AC
10279 #undef GEN_FLOAT_AC
10280 #undef GEN_FLOAT_B
10281 #undef GEN_FLOAT_BS
10282 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10283 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10284 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10285 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10286 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10287 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10288 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10289 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10290 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10291 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10292 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10293 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10294 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10295 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10296 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10297 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10298 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10299 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10300 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10301
10302 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10303 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10304 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10305 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10306 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10307 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10308 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10309 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10310 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10311 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10312 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10313 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10314 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10315 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10316 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10317 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10318 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10319 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10320 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10321 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10322 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10323 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10324 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10325 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10326 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10327 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10328 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10329 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10330 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10331 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10332 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10333
10334 #undef GEN_LD
10335 #undef GEN_LDU
10336 #undef GEN_LDUX
10337 #undef GEN_LDX_E
10338 #undef GEN_LDS
10339 #define GEN_LD(name, ldop, opc, type) \
10340 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10341 #define GEN_LDU(name, ldop, opc, type) \
10342 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10343 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10344 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10345 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10346 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10347 #define GEN_LDS(name, ldop, op, type) \
10348 GEN_LD(name, ldop, op | 0x20, type) \
10349 GEN_LDU(name, ldop, op | 0x21, type) \
10350 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10351 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10352
10353 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10354 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10355 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10356 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10357 #if defined(TARGET_PPC64)
10358 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10359 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10360 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10361 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10362 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10363 #endif
10364 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10365 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10366
10367 #undef GEN_ST
10368 #undef GEN_STU
10369 #undef GEN_STUX
10370 #undef GEN_STX_E
10371 #undef GEN_STS
10372 #define GEN_ST(name, stop, opc, type) \
10373 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10374 #define GEN_STU(name, stop, opc, type) \
10375 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10376 #define GEN_STUX(name, stop, opc2, opc3, type) \
10377 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10378 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10379 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10380 #define GEN_STS(name, stop, op, type) \
10381 GEN_ST(name, stop, op | 0x20, type) \
10382 GEN_STU(name, stop, op | 0x21, type) \
10383 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10384 GEN_STX(name, stop, 0x17, op | 0x00, type)
10385
10386 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10387 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10388 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10389 #if defined(TARGET_PPC64)
10390 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10391 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10392 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10393 #endif
10394 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10395 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10396
10397 #undef GEN_LDF
10398 #undef GEN_LDUF
10399 #undef GEN_LDUXF
10400 #undef GEN_LDXF
10401 #undef GEN_LDFS
10402 #define GEN_LDF(name, ldop, opc, type) \
10403 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10404 #define GEN_LDUF(name, ldop, opc, type) \
10405 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10406 #define GEN_LDUXF(name, ldop, opc, type) \
10407 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10408 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10409 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10410 #define GEN_LDFS(name, ldop, op, type) \
10411 GEN_LDF(name, ldop, op | 0x20, type) \
10412 GEN_LDUF(name, ldop, op | 0x21, type) \
10413 GEN_LDUXF(name, ldop, op | 0x01, type) \
10414 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10415
10416 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10417 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10418 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10419 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10420 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10421 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10422
10423 #undef GEN_STF
10424 #undef GEN_STUF
10425 #undef GEN_STUXF
10426 #undef GEN_STXF
10427 #undef GEN_STFS
10428 #define GEN_STF(name, stop, opc, type) \
10429 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10430 #define GEN_STUF(name, stop, opc, type) \
10431 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10432 #define GEN_STUXF(name, stop, opc, type) \
10433 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10434 #define GEN_STXF(name, stop, opc2, opc3, type) \
10435 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10436 #define GEN_STFS(name, stop, op, type) \
10437 GEN_STF(name, stop, op | 0x20, type) \
10438 GEN_STUF(name, stop, op | 0x21, type) \
10439 GEN_STUXF(name, stop, op | 0x01, type) \
10440 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10441
10442 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10443 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10444 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10445 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10446 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10447
10448 #undef GEN_CRLOGIC
10449 #define GEN_CRLOGIC(name, tcg_op, opc) \
10450 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10451 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10452 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10453 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10454 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10455 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10456 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10457 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10458 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10459
10460 #undef GEN_MAC_HANDLER
10461 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10462 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10463 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10464 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10465 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10466 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10467 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10468 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10469 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10470 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10471 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10472 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10473 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10474 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10475 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10476 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10477 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10478 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10479 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10480 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10481 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10482 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10483 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10484 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10485 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10486 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10487 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10488 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10489 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10490 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10491 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10492 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10493 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10494 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10495 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10496 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10497 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10498 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10499 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10500 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10501 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10502 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10503 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10504 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10505
10506 #undef GEN_VR_LDX
10507 #undef GEN_VR_STX
10508 #undef GEN_VR_LVE
10509 #undef GEN_VR_STVE
10510 #define GEN_VR_LDX(name, opc2, opc3) \
10511 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10512 #define GEN_VR_STX(name, opc2, opc3) \
10513 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10514 #define GEN_VR_LVE(name, opc2, opc3) \
10515 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10516 #define GEN_VR_STVE(name, opc2, opc3) \
10517 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10518 GEN_VR_LDX(lvx, 0x07, 0x03),
10519 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10520 GEN_VR_LVE(bx, 0x07, 0x00),
10521 GEN_VR_LVE(hx, 0x07, 0x01),
10522 GEN_VR_LVE(wx, 0x07, 0x02),
10523 GEN_VR_STX(svx, 0x07, 0x07),
10524 GEN_VR_STX(svxl, 0x07, 0x0F),
10525 GEN_VR_STVE(bx, 0x07, 0x04),
10526 GEN_VR_STVE(hx, 0x07, 0x05),
10527 GEN_VR_STVE(wx, 0x07, 0x06),
10528
10529 #undef GEN_VX_LOGICAL
10530 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10531 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10532
10533 #undef GEN_VX_LOGICAL_207
10534 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10535 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10536
10537 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10538 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10539 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10540 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10541 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10542 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10543 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10544 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10545
10546 #undef GEN_VXFORM
10547 #define GEN_VXFORM(name, opc2, opc3) \
10548 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10549
10550 #undef GEN_VXFORM_207
10551 #define GEN_VXFORM_207(name, opc2, opc3) \
10552 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10553
10554 #undef GEN_VXFORM_DUAL
10555 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10556 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10557
10558 #undef GEN_VXRFORM_DUAL
10559 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10560 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10561 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10562
10563 GEN_VXFORM(vaddubm, 0, 0),
10564 GEN_VXFORM(vadduhm, 0, 1),
10565 GEN_VXFORM(vadduwm, 0, 2),
10566 GEN_VXFORM_207(vaddudm, 0, 3),
10567 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10568 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10569 GEN_VXFORM(vsubuwm, 0, 18),
10570 GEN_VXFORM_207(vsubudm, 0, 19),
10571 GEN_VXFORM(vmaxub, 1, 0),
10572 GEN_VXFORM(vmaxuh, 1, 1),
10573 GEN_VXFORM(vmaxuw, 1, 2),
10574 GEN_VXFORM_207(vmaxud, 1, 3),
10575 GEN_VXFORM(vmaxsb, 1, 4),
10576 GEN_VXFORM(vmaxsh, 1, 5),
10577 GEN_VXFORM(vmaxsw, 1, 6),
10578 GEN_VXFORM_207(vmaxsd, 1, 7),
10579 GEN_VXFORM(vminub, 1, 8),
10580 GEN_VXFORM(vminuh, 1, 9),
10581 GEN_VXFORM(vminuw, 1, 10),
10582 GEN_VXFORM_207(vminud, 1, 11),
10583 GEN_VXFORM(vminsb, 1, 12),
10584 GEN_VXFORM(vminsh, 1, 13),
10585 GEN_VXFORM(vminsw, 1, 14),
10586 GEN_VXFORM_207(vminsd, 1, 15),
10587 GEN_VXFORM(vavgub, 1, 16),
10588 GEN_VXFORM(vavguh, 1, 17),
10589 GEN_VXFORM(vavguw, 1, 18),
10590 GEN_VXFORM(vavgsb, 1, 20),
10591 GEN_VXFORM(vavgsh, 1, 21),
10592 GEN_VXFORM(vavgsw, 1, 22),
10593 GEN_VXFORM(vmrghb, 6, 0),
10594 GEN_VXFORM(vmrghh, 6, 1),
10595 GEN_VXFORM(vmrghw, 6, 2),
10596 GEN_VXFORM(vmrglb, 6, 4),
10597 GEN_VXFORM(vmrglh, 6, 5),
10598 GEN_VXFORM(vmrglw, 6, 6),
10599 GEN_VXFORM_207(vmrgew, 6, 30),
10600 GEN_VXFORM_207(vmrgow, 6, 26),
10601 GEN_VXFORM(vmuloub, 4, 0),
10602 GEN_VXFORM(vmulouh, 4, 1),
10603 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10604 GEN_VXFORM(vmulosb, 4, 4),
10605 GEN_VXFORM(vmulosh, 4, 5),
10606 GEN_VXFORM_207(vmulosw, 4, 6),
10607 GEN_VXFORM(vmuleub, 4, 8),
10608 GEN_VXFORM(vmuleuh, 4, 9),
10609 GEN_VXFORM_207(vmuleuw, 4, 10),
10610 GEN_VXFORM(vmulesb, 4, 12),
10611 GEN_VXFORM(vmulesh, 4, 13),
10612 GEN_VXFORM_207(vmulesw, 4, 14),
10613 GEN_VXFORM(vslb, 2, 4),
10614 GEN_VXFORM(vslh, 2, 5),
10615 GEN_VXFORM(vslw, 2, 6),
10616 GEN_VXFORM_207(vsld, 2, 23),
10617 GEN_VXFORM(vsrb, 2, 8),
10618 GEN_VXFORM(vsrh, 2, 9),
10619 GEN_VXFORM(vsrw, 2, 10),
10620 GEN_VXFORM_207(vsrd, 2, 27),
10621 GEN_VXFORM(vsrab, 2, 12),
10622 GEN_VXFORM(vsrah, 2, 13),
10623 GEN_VXFORM(vsraw, 2, 14),
10624 GEN_VXFORM_207(vsrad, 2, 15),
10625 GEN_VXFORM(vslo, 6, 16),
10626 GEN_VXFORM(vsro, 6, 17),
10627 GEN_VXFORM(vaddcuw, 0, 6),
10628 GEN_VXFORM(vsubcuw, 0, 22),
10629 GEN_VXFORM(vaddubs, 0, 8),
10630 GEN_VXFORM(vadduhs, 0, 9),
10631 GEN_VXFORM(vadduws, 0, 10),
10632 GEN_VXFORM(vaddsbs, 0, 12),
10633 GEN_VXFORM(vaddshs, 0, 13),
10634 GEN_VXFORM(vaddsws, 0, 14),
10635 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10636 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10637 GEN_VXFORM(vsubuws, 0, 26),
10638 GEN_VXFORM(vsubsbs, 0, 28),
10639 GEN_VXFORM(vsubshs, 0, 29),
10640 GEN_VXFORM(vsubsws, 0, 30),
10641 GEN_VXFORM_207(vadduqm, 0, 4),
10642 GEN_VXFORM_207(vaddcuq, 0, 5),
10643 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10644 GEN_VXFORM_207(vsubuqm, 0, 20),
10645 GEN_VXFORM_207(vsubcuq, 0, 21),
10646 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10647 GEN_VXFORM(vrlb, 2, 0),
10648 GEN_VXFORM(vrlh, 2, 1),
10649 GEN_VXFORM(vrlw, 2, 2),
10650 GEN_VXFORM_207(vrld, 2, 3),
10651 GEN_VXFORM(vsl, 2, 7),
10652 GEN_VXFORM(vsr, 2, 11),
10653 GEN_VXFORM(vpkuhum, 7, 0),
10654 GEN_VXFORM(vpkuwum, 7, 1),
10655 GEN_VXFORM_207(vpkudum, 7, 17),
10656 GEN_VXFORM(vpkuhus, 7, 2),
10657 GEN_VXFORM(vpkuwus, 7, 3),
10658 GEN_VXFORM_207(vpkudus, 7, 19),
10659 GEN_VXFORM(vpkshus, 7, 4),
10660 GEN_VXFORM(vpkswus, 7, 5),
10661 GEN_VXFORM_207(vpksdus, 7, 21),
10662 GEN_VXFORM(vpkshss, 7, 6),
10663 GEN_VXFORM(vpkswss, 7, 7),
10664 GEN_VXFORM_207(vpksdss, 7, 23),
10665 GEN_VXFORM(vpkpx, 7, 12),
10666 GEN_VXFORM(vsum4ubs, 4, 24),
10667 GEN_VXFORM(vsum4sbs, 4, 28),
10668 GEN_VXFORM(vsum4shs, 4, 25),
10669 GEN_VXFORM(vsum2sws, 4, 26),
10670 GEN_VXFORM(vsumsws, 4, 30),
10671 GEN_VXFORM(vaddfp, 5, 0),
10672 GEN_VXFORM(vsubfp, 5, 1),
10673 GEN_VXFORM(vmaxfp, 5, 16),
10674 GEN_VXFORM(vminfp, 5, 17),
10675
10676 #undef GEN_VXRFORM1
10677 #undef GEN_VXRFORM
10678 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10679 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10680 #define GEN_VXRFORM(name, opc2, opc3) \
10681 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10682 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10683 GEN_VXRFORM(vcmpequb, 3, 0)
10684 GEN_VXRFORM(vcmpequh, 3, 1)
10685 GEN_VXRFORM(vcmpequw, 3, 2)
10686 GEN_VXRFORM(vcmpgtsb, 3, 12)
10687 GEN_VXRFORM(vcmpgtsh, 3, 13)
10688 GEN_VXRFORM(vcmpgtsw, 3, 14)
10689 GEN_VXRFORM(vcmpgtub, 3, 8)
10690 GEN_VXRFORM(vcmpgtuh, 3, 9)
10691 GEN_VXRFORM(vcmpgtuw, 3, 10)
10692 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10693 GEN_VXRFORM(vcmpgefp, 3, 7)
10694 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10695 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10696
10697 #undef GEN_VXFORM_SIMM
10698 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10699 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10700 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10701 GEN_VXFORM_SIMM(vspltish, 6, 13),
10702 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10703
10704 #undef GEN_VXFORM_NOA
10705 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10706 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10707 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10708 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10709 GEN_VXFORM_207(vupkhsw, 7, 25),
10710 GEN_VXFORM_NOA(vupklsb, 7, 10),
10711 GEN_VXFORM_NOA(vupklsh, 7, 11),
10712 GEN_VXFORM_207(vupklsw, 7, 27),
10713 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10714 GEN_VXFORM_NOA(vupklpx, 7, 15),
10715 GEN_VXFORM_NOA(vrefp, 5, 4),
10716 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10717 GEN_VXFORM_NOA(vexptefp, 5, 6),
10718 GEN_VXFORM_NOA(vlogefp, 5, 7),
10719 GEN_VXFORM_NOA(vrfim, 5, 11),
10720 GEN_VXFORM_NOA(vrfin, 5, 8),
10721 GEN_VXFORM_NOA(vrfip, 5, 10),
10722 GEN_VXFORM_NOA(vrfiz, 5, 9),
10723
10724 #undef GEN_VXFORM_UIMM
10725 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10726 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10727 GEN_VXFORM_UIMM(vspltb, 6, 8),
10728 GEN_VXFORM_UIMM(vsplth, 6, 9),
10729 GEN_VXFORM_UIMM(vspltw, 6, 10),
10730 GEN_VXFORM_UIMM(vcfux, 5, 12),
10731 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10732 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10733 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10734
10735 #undef GEN_VAFORM_PAIRED
10736 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10737 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10738 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10739 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10740 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10741 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10742 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10743 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10744
10745 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10746 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10747 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10748 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10749
10750 GEN_VXFORM_207(vbpermq, 6, 21),
10751 GEN_VXFORM_207(vgbbd, 6, 20),
10752 GEN_VXFORM_207(vpmsumb, 4, 16),
10753 GEN_VXFORM_207(vpmsumh, 4, 17),
10754 GEN_VXFORM_207(vpmsumw, 4, 18),
10755 GEN_VXFORM_207(vpmsumd, 4, 19),
10756
10757 GEN_VXFORM_207(vsbox, 4, 23),
10758
10759 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10760 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10761
10762 GEN_VXFORM_207(vshasigmaw, 1, 26),
10763 GEN_VXFORM_207(vshasigmad, 1, 27),
10764
10765 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10766
10767 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10768 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10769 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10770 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10771 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10772 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10773 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10774
10775 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10776 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10777 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10778 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10779 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10780
10781 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10782 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10783 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10784 #if defined(TARGET_PPC64)
10785 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10786 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10787 #endif
10788
10789 #undef GEN_XX2FORM
10790 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10791 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10792 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10793
10794 #undef GEN_XX3FORM
10795 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10796 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10797 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10798 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10799 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10800
10801 #undef GEN_XX2IFORM
10802 #define GEN_XX2IFORM(name, opc2, opc3, fl2) \
10803 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 1, PPC_NONE, fl2), \
10804 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 1, PPC_NONE, fl2), \
10805 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 1, PPC_NONE, fl2), \
10806 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 1, PPC_NONE, fl2)
10807
10808 #undef GEN_XX3_RC_FORM
10809 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10810 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10811 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10812 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10813 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10814 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10815 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10816 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10817 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10818
10819 #undef GEN_XX3FORM_DM
10820 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10821 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10822 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10823 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10824 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10825 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10826 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10827 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10828 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10829 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10830 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10831 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10832 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10833 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10834 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10835 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10836 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10837
10838 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10839 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10840 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10841 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10842
10843 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10844 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10845 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10846 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10847 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10848 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10849 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10850 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10851
10852 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10853 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10854 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10855 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10856 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10857 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10858 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10859 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10860 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10861 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10862 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10863 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10864 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10865 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10866 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10867 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10868 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10869 GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10870 GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10871 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10872 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10873 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10874 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10875 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10876 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10877 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10878 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10879 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10880 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10881 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10882 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10883 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10884 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10885 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10886 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10887 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10888
10889 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10890 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10891 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10892 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10893 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10894 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10895 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10896 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10897 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10898 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10899 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10900 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10901 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10902 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10903 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10904 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10905 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10906 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10907
10908 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10909 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10910 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10911 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10912 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10913 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10914 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10915 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10916 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10917 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10918 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10919 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10920 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10921 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10922 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10923 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10924 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10925 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10926 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10927 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10928 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10929 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10930 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10931 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10932 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10933 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10934 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10935 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10936 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10937 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10938 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10939 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10940 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10941 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10942 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10943 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10944
10945 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10946 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10947 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10948 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10949 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10950 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10951 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10952 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10953 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10954 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10955 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10956 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10957 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10958 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10959 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10960 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10961 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10962 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10963 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10964 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10965 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10966 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10967 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10968 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10969 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10970 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10971 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10972 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10973 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10974 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10975 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10976 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10977 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10978 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10979 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10980 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10981
10982 #undef VSX_LOGICAL
10983 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10984 GEN_XX3FORM(name, opc2, opc3, fl2)
10985
10986 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10987 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10988 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10989 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10990 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10991 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10992 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10993 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10994 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10995 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10996 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10997 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10998
10999 #define GEN_XXSEL_ROW(opc3) \
11000 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
11001 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
11002 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
11003 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
11004 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
11005 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
11006 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
11007 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
11008
11009 GEN_XXSEL_ROW(0x00)
11010 GEN_XXSEL_ROW(0x01)
11011 GEN_XXSEL_ROW(0x02)
11012 GEN_XXSEL_ROW(0x03)
11013 GEN_XXSEL_ROW(0x04)
11014 GEN_XXSEL_ROW(0x05)
11015 GEN_XXSEL_ROW(0x06)
11016 GEN_XXSEL_ROW(0x07)
11017 GEN_XXSEL_ROW(0x08)
11018 GEN_XXSEL_ROW(0x09)
11019 GEN_XXSEL_ROW(0x0A)
11020 GEN_XXSEL_ROW(0x0B)
11021 GEN_XXSEL_ROW(0x0C)
11022 GEN_XXSEL_ROW(0x0D)
11023 GEN_XXSEL_ROW(0x0E)
11024 GEN_XXSEL_ROW(0x0F)
11025 GEN_XXSEL_ROW(0x10)
11026 GEN_XXSEL_ROW(0x11)
11027 GEN_XXSEL_ROW(0x12)
11028 GEN_XXSEL_ROW(0x13)
11029 GEN_XXSEL_ROW(0x14)
11030 GEN_XXSEL_ROW(0x15)
11031 GEN_XXSEL_ROW(0x16)
11032 GEN_XXSEL_ROW(0x17)
11033 GEN_XXSEL_ROW(0x18)
11034 GEN_XXSEL_ROW(0x19)
11035 GEN_XXSEL_ROW(0x1A)
11036 GEN_XXSEL_ROW(0x1B)
11037 GEN_XXSEL_ROW(0x1C)
11038 GEN_XXSEL_ROW(0x1D)
11039 GEN_XXSEL_ROW(0x1E)
11040 GEN_XXSEL_ROW(0x1F)
11041
11042 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
11043
11044 #undef GEN_DFP_T_A_B_Rc
11045 #undef GEN_DFP_BF_A_B
11046 #undef GEN_DFP_BF_A_DCM
11047 #undef GEN_DFP_T_B_U32_U32_Rc
11048 #undef GEN_DFP_T_A_B_I32_Rc
11049 #undef GEN_DFP_T_B_Rc
11050 #undef GEN_DFP_T_FPR_I32_Rc
11051
11052 #define _GEN_DFP_LONG(name, op1, op2, mask) \
11053 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
11054
11055 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
11056 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11057 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11058
11059 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
11060 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11061 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11062 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11063 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11064
11065 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
11066 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
11067
11068 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
11069 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11070 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
11071
11072 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
11073 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
11074 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
11075 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
11076 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
11077
11078 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
11079 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
11080
11081 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
11082 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
11083
11084 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
11085 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
11086
11087 #define GEN_DFP_T_B_Rc(name, op1, op2) \
11088 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
11089
11090 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
11091 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
11092
11093 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
11094 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
11095
11096 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
11097 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
11098
11099 #define GEN_DFP_BF_A_B(name, op1, op2) \
11100 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
11101
11102 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
11103 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
11104
11105 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
11106 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
11107
11108 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
11109 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
11110
11111 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
11112 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
11113
11114 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
11115 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11116
11117 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
11118 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
11119
11120 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
11121 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
11122
11123 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
11124 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
11125
11126 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
11127 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
11128
11129 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11130 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11131
11132 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11133 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11134
11135 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11136 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11137
11138 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11139 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11140
11141 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11142 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11143
11144 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11145 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11146
11147 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11148 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11149
11150 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11151 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11152
11153 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11154 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11155 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11156 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11157 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11158 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11159 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11160 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11161 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11162 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11163 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11164 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11165 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11166 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11167 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11168 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11169 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11170 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11171 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11172 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11173 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11174 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11175 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11176 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11177 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11178 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11179 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11180 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11181 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11182 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11183 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11184 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11185 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11186 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11187 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11188 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11189 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11190 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11191 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11192 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11193 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11194 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11195 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11196 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11197 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11198 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11199 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11200 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11201 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11202 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11203
11204 #undef GEN_SPE
11205 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11206 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11207 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11208 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11209 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11210 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11211 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11212 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11213 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11214 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11215 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11216 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11217 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11218 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11219 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11220 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11221 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11222 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11223 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11224 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11225 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11226 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11227 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11228 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11229 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11230 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11231 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11232 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11233 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11234 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11235 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11236
11237 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11238 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11239 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11240 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11241 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11242 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11243 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11244 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11245 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11246 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11247 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11248 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11249 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11250 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11251
11252 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11253 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11254 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11255 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11256 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11257 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11258 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11259 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11260 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11261 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11262 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11263 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11264 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11265 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11266
11267 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11268 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11269 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11270 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11271 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11272 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11273 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11274 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11275 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11276 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11277 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11278 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11279 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11280 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11281 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11282 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11283
11284 #undef GEN_SPEOP_LDST
11285 #define GEN_SPEOP_LDST(name, opc2, sh) \
11286 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11287 GEN_SPEOP_LDST(evldd, 0x00, 3),
11288 GEN_SPEOP_LDST(evldw, 0x01, 3),
11289 GEN_SPEOP_LDST(evldh, 0x02, 3),
11290 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11291 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11292 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11293 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11294 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11295 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11296 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11297 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11298
11299 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11300 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11301 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11302 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11303 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11304 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11305 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11306
11307 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11308 PPC_NONE, PPC2_TM),
11309 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11310 PPC_NONE, PPC2_TM),
11311 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11312 PPC_NONE, PPC2_TM),
11313 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11314 PPC_NONE, PPC2_TM),
11315 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11316 PPC_NONE, PPC2_TM),
11317 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11318 PPC_NONE, PPC2_TM),
11319 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11320 PPC_NONE, PPC2_TM),
11321 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11322 PPC_NONE, PPC2_TM),
11323 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11324 PPC_NONE, PPC2_TM),
11325 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11326 PPC_NONE, PPC2_TM),
11327 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11328 PPC_NONE, PPC2_TM),
11329 };
11330
11331 #include "helper_regs.h"
11332 #include "translate_init.c"
11333
11334 /*****************************************************************************/
11335 /* Misc PowerPC helpers */
11336 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11337 int flags)
11338 {
11339 #define RGPL 4
11340 #define RFPL 4
11341
11342 PowerPCCPU *cpu = POWERPC_CPU(cs);
11343 CPUPPCState *env = &cpu->env;
11344 int i;
11345
11346 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11347 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
11348 env->nip, env->lr, env->ctr, cpu_read_xer(env),
11349 cs->cpu_index);
11350 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11351 TARGET_FMT_lx " iidx %d didx %d\n",
11352 env->msr, env->spr[SPR_HID0],
11353 env->hflags, env->immu_idx, env->dmmu_idx);
11354 #if !defined(NO_TIMER_DUMP)
11355 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11356 #if !defined(CONFIG_USER_ONLY)
11357 " DECR %08" PRIu32
11358 #endif
11359 "\n",
11360 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11361 #if !defined(CONFIG_USER_ONLY)
11362 , cpu_ppc_load_decr(env)
11363 #endif
11364 );
11365 #endif
11366 for (i = 0; i < 32; i++) {
11367 if ((i & (RGPL - 1)) == 0)
11368 cpu_fprintf(f, "GPR%02d", i);
11369 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11370 if ((i & (RGPL - 1)) == (RGPL - 1))
11371 cpu_fprintf(f, "\n");
11372 }
11373 cpu_fprintf(f, "CR ");
11374 for (i = 0; i < 8; i++)
11375 cpu_fprintf(f, "%01x", env->crf[i]);
11376 cpu_fprintf(f, " [");
11377 for (i = 0; i < 8; i++) {
11378 char a = '-';
11379 if (env->crf[i] & 0x08)
11380 a = 'L';
11381 else if (env->crf[i] & 0x04)
11382 a = 'G';
11383 else if (env->crf[i] & 0x02)
11384 a = 'E';
11385 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11386 }
11387 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11388 env->reserve_addr);
11389 for (i = 0; i < 32; i++) {
11390 if ((i & (RFPL - 1)) == 0)
11391 cpu_fprintf(f, "FPR%02d", i);
11392 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11393 if ((i & (RFPL - 1)) == (RFPL - 1))
11394 cpu_fprintf(f, "\n");
11395 }
11396 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11397 #if !defined(CONFIG_USER_ONLY)
11398 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11399 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11400 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11401 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11402
11403 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11404 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11405 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11406 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11407
11408 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11409 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11410 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11411 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11412
11413 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11414 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11415 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11416 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11417 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11418
11419 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11420 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11421 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11422 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11423
11424 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11425 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11426 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11427 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11428
11429 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11430 " EPR " TARGET_FMT_lx "\n",
11431 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11432 env->spr[SPR_BOOKE_EPR]);
11433
11434 /* FSL-specific */
11435 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11436 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11437 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11438 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11439
11440 /*
11441 * IVORs are left out as they are large and do not change often --
11442 * they can be read with "p $ivor0", "p $ivor1", etc.
11443 */
11444 }
11445
11446 #if defined(TARGET_PPC64)
11447 if (env->flags & POWERPC_FLAG_CFAR) {
11448 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11449 }
11450 #endif
11451
11452 switch (env->mmu_model) {
11453 case POWERPC_MMU_32B:
11454 case POWERPC_MMU_601:
11455 case POWERPC_MMU_SOFT_6xx:
11456 case POWERPC_MMU_SOFT_74xx:
11457 #if defined(TARGET_PPC64)
11458 case POWERPC_MMU_64B:
11459 case POWERPC_MMU_2_03:
11460 case POWERPC_MMU_2_06:
11461 case POWERPC_MMU_2_06a:
11462 case POWERPC_MMU_2_07:
11463 case POWERPC_MMU_2_07a:
11464 #endif
11465 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11466 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11467 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11468 break;
11469 case POWERPC_MMU_BOOKE206:
11470 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11471 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11472 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11473 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11474
11475 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11476 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11477 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11478 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11479
11480 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11481 " TLB1CFG " TARGET_FMT_lx "\n",
11482 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11483 env->spr[SPR_BOOKE_TLB1CFG]);
11484 break;
11485 default:
11486 break;
11487 }
11488 #endif
11489
11490 #undef RGPL
11491 #undef RFPL
11492 }
11493
11494 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11495 fprintf_function cpu_fprintf, int flags)
11496 {
11497 #if defined(DO_PPC_STATISTICS)
11498 PowerPCCPU *cpu = POWERPC_CPU(cs);
11499 opc_handler_t **t1, **t2, **t3, *handler;
11500 int op1, op2, op3;
11501
11502 t1 = cpu->env.opcodes;
11503 for (op1 = 0; op1 < 64; op1++) {
11504 handler = t1[op1];
11505 if (is_indirect_opcode(handler)) {
11506 t2 = ind_table(handler);
11507 for (op2 = 0; op2 < 32; op2++) {
11508 handler = t2[op2];
11509 if (is_indirect_opcode(handler)) {
11510 t3 = ind_table(handler);
11511 for (op3 = 0; op3 < 32; op3++) {
11512 handler = t3[op3];
11513 if (handler->count == 0)
11514 continue;
11515 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11516 "%016" PRIx64 " %" PRId64 "\n",
11517 op1, op2, op3, op1, (op3 << 5) | op2,
11518 handler->oname,
11519 handler->count, handler->count);
11520 }
11521 } else {
11522 if (handler->count == 0)
11523 continue;
11524 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11525 "%016" PRIx64 " %" PRId64 "\n",
11526 op1, op2, op1, op2, handler->oname,
11527 handler->count, handler->count);
11528 }
11529 }
11530 } else {
11531 if (handler->count == 0)
11532 continue;
11533 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11534 " %" PRId64 "\n",
11535 op1, op1, handler->oname,
11536 handler->count, handler->count);
11537 }
11538 }
11539 #endif
11540 }
11541
11542 /*****************************************************************************/
11543 void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
11544 {
11545 PowerPCCPU *cpu = ppc_env_get_cpu(env);
11546 CPUState *cs = CPU(cpu);
11547 DisasContext ctx, *ctxp = &ctx;
11548 opc_handler_t **table, *handler;
11549 target_ulong pc_start;
11550 int num_insns;
11551 int max_insns;
11552
11553 pc_start = tb->pc;
11554 ctx.nip = pc_start;
11555 ctx.tb = tb;
11556 ctx.exception = POWERPC_EXCP_NONE;
11557 ctx.spr_cb = env->spr_cb;
11558 ctx.pr = msr_pr;
11559 ctx.mem_idx = env->dmmu_idx;
11560 #if !defined(CONFIG_USER_ONLY)
11561 ctx.hv = msr_hv || !env->has_hv_mode;
11562 #endif
11563 ctx.insns_flags = env->insns_flags;
11564 ctx.insns_flags2 = env->insns_flags2;
11565 ctx.access_type = -1;
11566 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11567 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11568 #if defined(TARGET_PPC64)
11569 ctx.sf_mode = msr_is_64bit(env, env->msr);
11570 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11571 #endif
11572 if (env->mmu_model == POWERPC_MMU_32B ||
11573 env->mmu_model == POWERPC_MMU_601 ||
11574 (env->mmu_model & POWERPC_MMU_64B))
11575 ctx.lazy_tlb_flush = true;
11576
11577 ctx.fpu_enabled = msr_fp;
11578 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11579 ctx.spe_enabled = msr_spe;
11580 else
11581 ctx.spe_enabled = 0;
11582 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11583 ctx.altivec_enabled = msr_vr;
11584 else
11585 ctx.altivec_enabled = 0;
11586 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11587 ctx.vsx_enabled = msr_vsx;
11588 } else {
11589 ctx.vsx_enabled = 0;
11590 }
11591 #if defined(TARGET_PPC64)
11592 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11593 ctx.tm_enabled = msr_tm;
11594 } else {
11595 ctx.tm_enabled = 0;
11596 }
11597 #endif
11598 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11599 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11600 else
11601 ctx.singlestep_enabled = 0;
11602 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11603 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11604 if (unlikely(cs->singlestep_enabled)) {
11605 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11606 }
11607 #if defined (DO_SINGLE_STEP) && 0
11608 /* Single step trace mode */
11609 msr_se = 1;
11610 #endif
11611 num_insns = 0;
11612 max_insns = tb->cflags & CF_COUNT_MASK;
11613 if (max_insns == 0) {
11614 max_insns = CF_COUNT_MASK;
11615 }
11616 if (max_insns > TCG_MAX_INSNS) {
11617 max_insns = TCG_MAX_INSNS;
11618 }
11619
11620 gen_tb_start(tb);
11621 tcg_clear_temp_count();
11622 /* Set env in case of segfault during code fetch */
11623 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11624 tcg_gen_insn_start(ctx.nip);
11625 num_insns++;
11626
11627 if (unlikely(cpu_breakpoint_test(cs, ctx.nip, BP_ANY))) {
11628 gen_debug_exception(ctxp);
11629 /* The address covered by the breakpoint must be included in
11630 [tb->pc, tb->pc + tb->size) in order to for it to be
11631 properly cleared -- thus we increment the PC here so that
11632 the logic setting tb->size below does the right thing. */
11633 ctx.nip += 4;
11634 break;
11635 }
11636
11637 LOG_DISAS("----------------\n");
11638 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11639 ctx.nip, ctx.mem_idx, (int)msr_ir);
11640 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO))
11641 gen_io_start();
11642 if (unlikely(need_byteswap(&ctx))) {
11643 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11644 } else {
11645 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11646 }
11647 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11648 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11649 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11650 ctx.nip += 4;
11651 table = env->opcodes;
11652 handler = table[opc1(ctx.opcode)];
11653 if (is_indirect_opcode(handler)) {
11654 table = ind_table(handler);
11655 handler = table[opc2(ctx.opcode)];
11656 if (is_indirect_opcode(handler)) {
11657 table = ind_table(handler);
11658 handler = table[opc3(ctx.opcode)];
11659 }
11660 }
11661 /* Is opcode *REALLY* valid ? */
11662 if (unlikely(handler->handler == &gen_invalid)) {
11663 qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
11664 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11665 opc1(ctx.opcode), opc2(ctx.opcode),
11666 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11667 } else {
11668 uint32_t inval;
11669
11670 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11671 inval = handler->inval2;
11672 } else {
11673 inval = handler->inval1;
11674 }
11675
11676 if (unlikely((ctx.opcode & inval) != 0)) {
11677 qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
11678 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11679 ctx.opcode & inval, opc1(ctx.opcode),
11680 opc2(ctx.opcode), opc3(ctx.opcode),
11681 ctx.opcode, ctx.nip - 4);
11682 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11683 break;
11684 }
11685 }
11686 (*(handler->handler))(&ctx);
11687 #if defined(DO_PPC_STATISTICS)
11688 handler->count++;
11689 #endif
11690 /* Check trace mode exceptions */
11691 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11692 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11693 ctx.exception != POWERPC_SYSCALL &&
11694 ctx.exception != POWERPC_EXCP_TRAP &&
11695 ctx.exception != POWERPC_EXCP_BRANCH)) {
11696 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11697 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11698 (cs->singlestep_enabled) ||
11699 singlestep ||
11700 num_insns >= max_insns)) {
11701 /* if we reach a page boundary or are single stepping, stop
11702 * generation
11703 */
11704 break;
11705 }
11706 if (tcg_check_temp_count()) {
11707 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11708 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11709 ctx.opcode);
11710 exit(1);
11711 }
11712 }
11713 if (tb->cflags & CF_LAST_IO)
11714 gen_io_end();
11715 if (ctx.exception == POWERPC_EXCP_NONE) {
11716 gen_goto_tb(&ctx, 0, ctx.nip);
11717 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11718 if (unlikely(cs->singlestep_enabled)) {
11719 gen_debug_exception(ctxp);
11720 }
11721 /* Generate the return instruction */
11722 tcg_gen_exit_tb(0);
11723 }
11724 gen_tb_end(tb, num_insns);
11725
11726 tb->size = ctx.nip - pc_start;
11727 tb->icount = num_insns;
11728
11729 #if defined(DEBUG_DISAS)
11730 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
11731 && qemu_log_in_addr_range(pc_start)) {
11732 int flags;
11733 flags = env->bfd_mach;
11734 flags |= ctx.le_mode << 16;
11735 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11736 log_target_disas(cs, pc_start, ctx.nip - pc_start, flags);
11737 qemu_log("\n");
11738 }
11739 #endif
11740 }
11741
11742 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
11743 target_ulong *data)
11744 {
11745 env->nip = data[0];
11746 }
AR7 emulation for QEMU