target/riscv/instmap.h

   1 /*
   2  * RISC-V emulation for qemu: Instruction decode helpers
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define MASK_OP_MAJOR(op)  (op & 0x7F)
  20 enum {
  21     /* rv32i, rv64i, rv32m */
  22     OPC_RISC_LUI    = (0x37),
  23     OPC_RISC_AUIPC  = (0x17),
  24     OPC_RISC_JAL    = (0x6F),
  25     OPC_RISC_JALR   = (0x67),
  26     OPC_RISC_BRANCH = (0x63),
  27     OPC_RISC_LOAD   = (0x03),
  28     OPC_RISC_STORE  = (0x23),
  29     OPC_RISC_ARITH_IMM  = (0x13),
  30     OPC_RISC_ARITH      = (0x33),
  31     OPC_RISC_FENCE      = (0x0F),
  32     OPC_RISC_SYSTEM     = (0x73),
  33
  34     /* rv64i, rv64m */
  35     OPC_RISC_ARITH_IMM_W = (0x1B),
  36     OPC_RISC_ARITH_W = (0x3B),
  37
  38     /* rv32a, rv64a */
  39     OPC_RISC_ATOMIC = (0x2F),
  40
  41     /* floating point */
  42     OPC_RISC_FP_LOAD = (0x7),
  43     OPC_RISC_FP_STORE = (0x27),
  44
  45     OPC_RISC_FMADD = (0x43),
  46     OPC_RISC_FMSUB = (0x47),
  47     OPC_RISC_FNMSUB = (0x4B),
  48     OPC_RISC_FNMADD = (0x4F),
  49
  50     OPC_RISC_FP_ARITH = (0x53),
  51 };
  52
  53 #define MASK_OP_ARITH(op)   (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \
  54                             (0x7F << 25))))
  55 enum {
  56     OPC_RISC_ADD   = OPC_RISC_ARITH | (0x0 << 12) | (0x00 << 25),
  57     OPC_RISC_SUB   = OPC_RISC_ARITH | (0x0 << 12) | (0x20 << 25),
  58     OPC_RISC_SLL   = OPC_RISC_ARITH | (0x1 << 12) | (0x00 << 25),
  59     OPC_RISC_SLT   = OPC_RISC_ARITH | (0x2 << 12) | (0x00 << 25),
  60     OPC_RISC_SLTU  = OPC_RISC_ARITH | (0x3 << 12) | (0x00 << 25),
  61     OPC_RISC_XOR   = OPC_RISC_ARITH | (0x4 << 12) | (0x00 << 25),
  62     OPC_RISC_SRL   = OPC_RISC_ARITH | (0x5 << 12) | (0x00 << 25),
  63     OPC_RISC_SRA   = OPC_RISC_ARITH | (0x5 << 12) | (0x20 << 25),
  64     OPC_RISC_OR    = OPC_RISC_ARITH | (0x6 << 12) | (0x00 << 25),
  65     OPC_RISC_AND   = OPC_RISC_ARITH | (0x7 << 12) | (0x00 << 25),
  66
  67     /* RV64M */
  68     OPC_RISC_MUL    = OPC_RISC_ARITH | (0x0 << 12) | (0x01 << 25),
  69     OPC_RISC_MULH   = OPC_RISC_ARITH | (0x1 << 12) | (0x01 << 25),
  70     OPC_RISC_MULHSU = OPC_RISC_ARITH | (0x2 << 12) | (0x01 << 25),
  71     OPC_RISC_MULHU  = OPC_RISC_ARITH | (0x3 << 12) | (0x01 << 25),
  72
  73     OPC_RISC_DIV    = OPC_RISC_ARITH | (0x4 << 12) | (0x01 << 25),
  74     OPC_RISC_DIVU   = OPC_RISC_ARITH | (0x5 << 12) | (0x01 << 25),
  75     OPC_RISC_REM    = OPC_RISC_ARITH | (0x6 << 12) | (0x01 << 25),
  76     OPC_RISC_REMU   = OPC_RISC_ARITH | (0x7 << 12) | (0x01 << 25),
  77 };
  78
  79
  80 #define MASK_OP_ARITH_IMM(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
  81 enum {
  82     OPC_RISC_ADDI   = OPC_RISC_ARITH_IMM | (0x0 << 12),
  83     OPC_RISC_SLTI   = OPC_RISC_ARITH_IMM | (0x2 << 12),
  84     OPC_RISC_SLTIU  = OPC_RISC_ARITH_IMM | (0x3 << 12),
  85     OPC_RISC_XORI   = OPC_RISC_ARITH_IMM | (0x4 << 12),
  86     OPC_RISC_ORI    = OPC_RISC_ARITH_IMM | (0x6 << 12),
  87     OPC_RISC_ANDI   = OPC_RISC_ARITH_IMM | (0x7 << 12),
  88     OPC_RISC_SLLI   = OPC_RISC_ARITH_IMM | (0x1 << 12), /* additional part of
  89                                                            IMM */
  90     OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM | (0x5 << 12) /* SRAI, SRLI */
  91 };
  92
  93 #define MASK_OP_BRANCH(op)     (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
  94 enum {
  95     OPC_RISC_BEQ  = OPC_RISC_BRANCH  | (0x0  << 12),
  96     OPC_RISC_BNE  = OPC_RISC_BRANCH  | (0x1  << 12),
  97     OPC_RISC_BLT  = OPC_RISC_BRANCH  | (0x4  << 12),
  98     OPC_RISC_BGE  = OPC_RISC_BRANCH  | (0x5  << 12),
  99     OPC_RISC_BLTU = OPC_RISC_BRANCH  | (0x6  << 12),
 100     OPC_RISC_BGEU = OPC_RISC_BRANCH  | (0x7  << 12)
 101 };
 102
 103 enum {
 104     OPC_RISC_ADDIW   = OPC_RISC_ARITH_IMM_W | (0x0 << 12),
 105     OPC_RISC_SLLIW   = OPC_RISC_ARITH_IMM_W | (0x1 << 12), /* additional part of
 106                                                               IMM */
 107     OPC_RISC_SHIFT_RIGHT_IW = OPC_RISC_ARITH_IMM_W | (0x5 << 12) /* SRAI, SRLI
 108                                                                   */
 109 };
 110
 111 enum {
 112     OPC_RISC_ADDW   = OPC_RISC_ARITH_W | (0x0 << 12) | (0x00 << 25),
 113     OPC_RISC_SUBW   = OPC_RISC_ARITH_W | (0x0 << 12) | (0x20 << 25),
 114     OPC_RISC_SLLW   = OPC_RISC_ARITH_W | (0x1 << 12) | (0x00 << 25),
 115     OPC_RISC_SRLW   = OPC_RISC_ARITH_W | (0x5 << 12) | (0x00 << 25),
 116     OPC_RISC_SRAW   = OPC_RISC_ARITH_W | (0x5 << 12) | (0x20 << 25),
 117
 118     /* RV64M */
 119     OPC_RISC_MULW   = OPC_RISC_ARITH_W | (0x0 << 12) | (0x01 << 25),
 120     OPC_RISC_DIVW   = OPC_RISC_ARITH_W | (0x4 << 12) | (0x01 << 25),
 121     OPC_RISC_DIVUW  = OPC_RISC_ARITH_W | (0x5 << 12) | (0x01 << 25),
 122     OPC_RISC_REMW   = OPC_RISC_ARITH_W | (0x6 << 12) | (0x01 << 25),
 123     OPC_RISC_REMUW  = OPC_RISC_ARITH_W | (0x7 << 12) | (0x01 << 25),
 124 };
 125
 126 #define MASK_OP_LOAD(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
 127 enum {
 128     OPC_RISC_LB   = OPC_RISC_LOAD | (0x0 << 12),
 129     OPC_RISC_LH   = OPC_RISC_LOAD | (0x1 << 12),
 130     OPC_RISC_LW   = OPC_RISC_LOAD | (0x2 << 12),
 131     OPC_RISC_LD   = OPC_RISC_LOAD | (0x3 << 12),
 132     OPC_RISC_LBU  = OPC_RISC_LOAD | (0x4 << 12),
 133     OPC_RISC_LHU  = OPC_RISC_LOAD | (0x5 << 12),
 134     OPC_RISC_LWU  = OPC_RISC_LOAD | (0x6 << 12),
 135 };
 136
 137 #define MASK_OP_STORE(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
 138 enum {
 139     OPC_RISC_SB   = OPC_RISC_STORE | (0x0 << 12),
 140     OPC_RISC_SH   = OPC_RISC_STORE | (0x1 << 12),
 141     OPC_RISC_SW   = OPC_RISC_STORE | (0x2 << 12),
 142     OPC_RISC_SD   = OPC_RISC_STORE | (0x3 << 12),
 143 };
 144
 145 #define MASK_OP_JALR(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
 146 /* no enum since OPC_RISC_JALR is the actual value */
 147
 148 #define MASK_OP_ATOMIC(op) \
 149     (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | (0x7F << 25))))
 150 #define MASK_OP_ATOMIC_NO_AQ_RL_SZ(op) \
 151     (MASK_OP_MAJOR(op) | (op & (0x1F << 27)))
 152
 153 enum {
 154     OPC_RISC_LR          = OPC_RISC_ATOMIC | (0x02 << 27),
 155     OPC_RISC_SC          = OPC_RISC_ATOMIC | (0x03 << 27),
 156     OPC_RISC_AMOSWAP     = OPC_RISC_ATOMIC | (0x01 << 27),
 157     OPC_RISC_AMOADD      = OPC_RISC_ATOMIC | (0x00 << 27),
 158     OPC_RISC_AMOXOR      = OPC_RISC_ATOMIC | (0x04 << 27),
 159     OPC_RISC_AMOAND      = OPC_RISC_ATOMIC | (0x0C << 27),
 160     OPC_RISC_AMOOR       = OPC_RISC_ATOMIC | (0x08 << 27),
 161     OPC_RISC_AMOMIN      = OPC_RISC_ATOMIC | (0x10 << 27),
 162     OPC_RISC_AMOMAX      = OPC_RISC_ATOMIC | (0x14 << 27),
 163     OPC_RISC_AMOMINU     = OPC_RISC_ATOMIC | (0x18 << 27),
 164     OPC_RISC_AMOMAXU     = OPC_RISC_ATOMIC | (0x1C << 27),
 165 };
 166
 167 #define MASK_OP_SYSTEM(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
 168 enum {
 169     OPC_RISC_ECALL       = OPC_RISC_SYSTEM | (0x0 << 12),
 170     OPC_RISC_EBREAK      = OPC_RISC_SYSTEM | (0x0 << 12),
 171     OPC_RISC_ERET        = OPC_RISC_SYSTEM | (0x0 << 12),
 172     OPC_RISC_MRTS        = OPC_RISC_SYSTEM | (0x0 << 12),
 173     OPC_RISC_MRTH        = OPC_RISC_SYSTEM | (0x0 << 12),
 174     OPC_RISC_HRTS        = OPC_RISC_SYSTEM | (0x0 << 12),
 175     OPC_RISC_WFI         = OPC_RISC_SYSTEM | (0x0 << 12),
 176     OPC_RISC_SFENCEVM    = OPC_RISC_SYSTEM | (0x0 << 12),
 177
 178     OPC_RISC_CSRRW       = OPC_RISC_SYSTEM | (0x1 << 12),
 179     OPC_RISC_CSRRS       = OPC_RISC_SYSTEM | (0x2 << 12),
 180     OPC_RISC_CSRRC       = OPC_RISC_SYSTEM | (0x3 << 12),
 181     OPC_RISC_CSRRWI      = OPC_RISC_SYSTEM | (0x5 << 12),
 182     OPC_RISC_CSRRSI      = OPC_RISC_SYSTEM | (0x6 << 12),
 183     OPC_RISC_CSRRCI      = OPC_RISC_SYSTEM | (0x7 << 12),
 184 };
 185
 186 #define MASK_OP_FP_LOAD(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
 187 enum {
 188     OPC_RISC_FLW   = OPC_RISC_FP_LOAD | (0x2 << 12),
 189     OPC_RISC_FLD   = OPC_RISC_FP_LOAD | (0x3 << 12),
 190 };
 191
 192 #define MASK_OP_FP_STORE(op)   (MASK_OP_MAJOR(op) | (op & (0x7 << 12)))
 193 enum {
 194     OPC_RISC_FSW   = OPC_RISC_FP_STORE | (0x2 << 12),
 195     OPC_RISC_FSD   = OPC_RISC_FP_STORE | (0x3 << 12),
 196 };
 197
 198 #define MASK_OP_FP_FMADD(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
 199 enum {
 200     OPC_RISC_FMADD_S = OPC_RISC_FMADD | (0x0 << 25),
 201     OPC_RISC_FMADD_D = OPC_RISC_FMADD | (0x1 << 25),
 202 };
 203
 204 #define MASK_OP_FP_FMSUB(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
 205 enum {
 206     OPC_RISC_FMSUB_S = OPC_RISC_FMSUB | (0x0 << 25),
 207     OPC_RISC_FMSUB_D = OPC_RISC_FMSUB | (0x1 << 25),
 208 };
 209
 210 #define MASK_OP_FP_FNMADD(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
 211 enum {
 212     OPC_RISC_FNMADD_S = OPC_RISC_FNMADD | (0x0 << 25),
 213     OPC_RISC_FNMADD_D = OPC_RISC_FNMADD | (0x1 << 25),
 214 };
 215
 216 #define MASK_OP_FP_FNMSUB(op)   (MASK_OP_MAJOR(op) | (op & (0x3 << 25)))
 217 enum {
 218     OPC_RISC_FNMSUB_S = OPC_RISC_FNMSUB | (0x0 << 25),
 219     OPC_RISC_FNMSUB_D = OPC_RISC_FNMSUB | (0x1 << 25),
 220 };
 221
 222 #define MASK_OP_FP_ARITH(op)   (MASK_OP_MAJOR(op) | (op & (0x7F << 25)))
 223 enum {
 224     /* float */
 225     OPC_RISC_FADD_S    = OPC_RISC_FP_ARITH | (0x0 << 25),
 226     OPC_RISC_FSUB_S    = OPC_RISC_FP_ARITH | (0x4 << 25),
 227     OPC_RISC_FMUL_S    = OPC_RISC_FP_ARITH | (0x8 << 25),
 228     OPC_RISC_FDIV_S    = OPC_RISC_FP_ARITH | (0xC << 25),
 229
 230     OPC_RISC_FSGNJ_S   = OPC_RISC_FP_ARITH | (0x10 << 25),
 231     OPC_RISC_FSGNJN_S  = OPC_RISC_FP_ARITH | (0x10 << 25),
 232     OPC_RISC_FSGNJX_S  = OPC_RISC_FP_ARITH | (0x10 << 25),
 233
 234     OPC_RISC_FMIN_S    = OPC_RISC_FP_ARITH | (0x14 << 25),
 235     OPC_RISC_FMAX_S    = OPC_RISC_FP_ARITH | (0x14 << 25),
 236
 237     OPC_RISC_FSQRT_S   = OPC_RISC_FP_ARITH | (0x2C << 25),
 238
 239     OPC_RISC_FEQ_S     = OPC_RISC_FP_ARITH | (0x50 << 25),
 240     OPC_RISC_FLT_S     = OPC_RISC_FP_ARITH | (0x50 << 25),
 241     OPC_RISC_FLE_S     = OPC_RISC_FP_ARITH | (0x50 << 25),
 242
 243     OPC_RISC_FCVT_W_S  = OPC_RISC_FP_ARITH | (0x60 << 25),
 244     OPC_RISC_FCVT_WU_S = OPC_RISC_FP_ARITH | (0x60 << 25),
 245     OPC_RISC_FCVT_L_S  = OPC_RISC_FP_ARITH | (0x60 << 25),
 246     OPC_RISC_FCVT_LU_S = OPC_RISC_FP_ARITH | (0x60 << 25),
 247
 248     OPC_RISC_FCVT_S_W  = OPC_RISC_FP_ARITH | (0x68 << 25),
 249     OPC_RISC_FCVT_S_WU = OPC_RISC_FP_ARITH | (0x68 << 25),
 250     OPC_RISC_FCVT_S_L  = OPC_RISC_FP_ARITH | (0x68 << 25),
 251     OPC_RISC_FCVT_S_LU = OPC_RISC_FP_ARITH | (0x68 << 25),
 252
 253     OPC_RISC_FMV_X_S   = OPC_RISC_FP_ARITH | (0x70 << 25),
 254     OPC_RISC_FCLASS_S  = OPC_RISC_FP_ARITH | (0x70 << 25),
 255
 256     OPC_RISC_FMV_S_X   = OPC_RISC_FP_ARITH | (0x78 << 25),
 257
 258     /* double */
 259     OPC_RISC_FADD_D    = OPC_RISC_FP_ARITH | (0x1 << 25),
 260     OPC_RISC_FSUB_D    = OPC_RISC_FP_ARITH | (0x5 << 25),
 261     OPC_RISC_FMUL_D    = OPC_RISC_FP_ARITH | (0x9 << 25),
 262     OPC_RISC_FDIV_D    = OPC_RISC_FP_ARITH | (0xD << 25),
 263
 264     OPC_RISC_FSGNJ_D   = OPC_RISC_FP_ARITH | (0x11 << 25),
 265     OPC_RISC_FSGNJN_D  = OPC_RISC_FP_ARITH | (0x11 << 25),
 266     OPC_RISC_FSGNJX_D  = OPC_RISC_FP_ARITH | (0x11 << 25),
 267
 268     OPC_RISC_FMIN_D    = OPC_RISC_FP_ARITH | (0x15 << 25),
 269     OPC_RISC_FMAX_D    = OPC_RISC_FP_ARITH | (0x15 << 25),
 270
 271     OPC_RISC_FCVT_S_D = OPC_RISC_FP_ARITH | (0x20 << 25),
 272
 273     OPC_RISC_FCVT_D_S = OPC_RISC_FP_ARITH | (0x21 << 25),
 274
 275     OPC_RISC_FSQRT_D   = OPC_RISC_FP_ARITH | (0x2D << 25),
 276
 277     OPC_RISC_FEQ_D     = OPC_RISC_FP_ARITH | (0x51 << 25),
 278     OPC_RISC_FLT_D     = OPC_RISC_FP_ARITH | (0x51 << 25),
 279     OPC_RISC_FLE_D     = OPC_RISC_FP_ARITH | (0x51 << 25),
 280
 281     OPC_RISC_FCVT_W_D  = OPC_RISC_FP_ARITH | (0x61 << 25),
 282     OPC_RISC_FCVT_WU_D = OPC_RISC_FP_ARITH | (0x61 << 25),
 283     OPC_RISC_FCVT_L_D  = OPC_RISC_FP_ARITH | (0x61 << 25),
 284     OPC_RISC_FCVT_LU_D = OPC_RISC_FP_ARITH | (0x61 << 25),
 285
 286     OPC_RISC_FCVT_D_W  = OPC_RISC_FP_ARITH | (0x69 << 25),
 287     OPC_RISC_FCVT_D_WU = OPC_RISC_FP_ARITH | (0x69 << 25),
 288     OPC_RISC_FCVT_D_L  = OPC_RISC_FP_ARITH | (0x69 << 25),
 289     OPC_RISC_FCVT_D_LU = OPC_RISC_FP_ARITH | (0x69 << 25),
 290
 291     OPC_RISC_FMV_X_D   = OPC_RISC_FP_ARITH | (0x71 << 25),
 292     OPC_RISC_FCLASS_D  = OPC_RISC_FP_ARITH | (0x71 << 25),
 293
 294     OPC_RISC_FMV_D_X   = OPC_RISC_FP_ARITH | (0x79 << 25),
 295 };
 296
 297 #define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \
 298                          | (extract32(inst, 25, 6) << 5) \
 299                          | (extract32(inst, 7, 1) << 11) \
 300                          | (sextract64(inst, 31, 1) << 12))
 301
 302 #define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \
 303                              | (sextract64(inst, 25, 7) << 5))
 304
 305 #define GET_JAL_IMM(inst) ((extract32(inst, 21, 10) << 1) \
 306                            | (extract32(inst, 20, 1) << 11) \
 307                            | (extract32(inst, 12, 8) << 12) \
 308                            | (sextract64(inst, 31, 1) << 20))
 309
 310 #define GET_RM(inst)   extract32(inst, 12, 3)
 311 #define GET_RS3(inst)  extract32(inst, 27, 5)
 312 #define GET_RS1(inst)  extract32(inst, 15, 5)
 313 #define GET_RS2(inst)  extract32(inst, 20, 5)
 314 #define GET_RD(inst)   extract32(inst, 7, 5)
 315 #define GET_IMM(inst)  sextract64(inst, 20, 12)
 316
 317 /* RVC decoding macros */
 318 #define GET_C_IMM(inst)             (extract32(inst, 2, 5) \
 319                                     | (sextract64(inst, 12, 1) << 5))
 320 #define GET_C_ZIMM(inst)            (extract32(inst, 2, 5) \
 321                                     | (extract32(inst, 12, 1) << 5))
 322 #define GET_C_ADDI4SPN_IMM(inst)    ((extract32(inst, 6, 1) << 2) \
 323                                     | (extract32(inst, 5, 1) << 3) \
 324                                     | (extract32(inst, 11, 2) << 4) \
 325                                     | (extract32(inst, 7, 4) << 6))
 326 #define GET_C_ADDI16SP_IMM(inst)    ((extract32(inst, 6, 1) << 4) \
 327                                     | (extract32(inst, 2, 1) << 5) \
 328                                     | (extract32(inst, 5, 1) << 6) \
 329                                     | (extract32(inst, 3, 2) << 7) \
 330                                     | (sextract64(inst, 12, 1) << 9))
 331 #define GET_C_LWSP_IMM(inst)        ((extract32(inst, 4, 3) << 2) \
 332                                     | (extract32(inst, 12, 1) << 5) \
 333                                     | (extract32(inst, 2, 2) << 6))
 334 #define GET_C_LDSP_IMM(inst)        ((extract32(inst, 5, 2) << 3) \
 335                                     | (extract32(inst, 12, 1) << 5) \
 336                                     | (extract32(inst, 2, 3) << 6))
 337 #define GET_C_SWSP_IMM(inst)        ((extract32(inst, 9, 4) << 2) \
 338                                     | (extract32(inst, 7, 2) << 6))
 339 #define GET_C_SDSP_IMM(inst)        ((extract32(inst, 10, 3) << 3) \
 340                                     | (extract32(inst, 7, 3) << 6))
 341 #define GET_C_LW_IMM(inst)          ((extract32(inst, 6, 1) << 2) \
 342                                     | (extract32(inst, 10, 3) << 3) \
 343                                     | (extract32(inst, 5, 1) << 6))
 344 #define GET_C_LD_IMM(inst)          ((extract32(inst, 10, 3) << 3) \
 345                                     | (extract32(inst, 5, 2) << 6))
 346 #define GET_C_J_IMM(inst)           ((extract32(inst, 3, 3) << 1) \
 347                                     | (extract32(inst, 11, 1) << 4) \
 348                                     | (extract32(inst, 2, 1) << 5) \
 349                                     | (extract32(inst, 7, 1) << 6) \
 350                                     | (extract32(inst, 6, 1) << 7) \
 351                                     | (extract32(inst, 9, 2) << 8) \
 352                                     | (extract32(inst, 8, 1) << 10) \
 353                                     | (sextract64(inst, 12, 1) << 11))
 354 #define GET_C_B_IMM(inst)           ((extract32(inst, 3, 2) << 1) \
 355                                     | (extract32(inst, 10, 2) << 3) \
 356                                     | (extract32(inst, 2, 1) << 5) \
 357                                     | (extract32(inst, 5, 2) << 6) \
 358                                     | (sextract64(inst, 12, 1) << 8))
 359 #define GET_C_SIMM3(inst)           extract32(inst, 10, 3)
 360 #define GET_C_RD(inst)              GET_RD(inst)
 361 #define GET_C_RS1(inst)             GET_RD(inst)
 362 #define GET_C_RS2(inst)             extract32(inst, 2, 5)
 363 #define GET_C_RS1S(inst)            (8 + extract32(inst, 7, 3))
 364 #define GET_C_RS2S(inst)            (8 + extract32(inst, 2, 3))