target/arm/kvm32.c

   1 /*
   2  * ARM implementation of KVM hooks, 32 bit specific code.
   3  *
   4  * Copyright Christoffer Dall 2009-2010
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include <sys/ioctl.h>
  13
  14 #include <linux/kvm.h>
  15
  16 #include "qemu-common.h"
  17 #include "cpu.h"
  18 #include "qemu/timer.h"
  19 #include "sysemu/sysemu.h"
  20 #include "sysemu/kvm.h"
  21 #include "kvm_arm.h"
  22 #include "internals.h"
  23 #include "qemu/log.h"
  24
  25 static inline void set_feature(uint64_t *features, int feature)
  26 {
  27     *features |= 1ULL << feature;
  28 }
  29
  30 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
  31 {
  32     struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
  33
  34     assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
  35     return ioctl(fd, KVM_GET_ONE_REG, &idreg);
  36 }
  37
  38 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
  39 {
  40     /* Identify the feature bits corresponding to the host CPU, and
  41      * fill out the ARMHostCPUClass fields accordingly. To do this
  42      * we have to create a scratch VM, create a single CPU inside it,
  43      * and then query that CPU for the relevant ID registers.
  44      */
  45     int err = 0, fdarray[3];
  46     uint32_t midr, id_pfr0;
  47     uint64_t features = 0;
  48
  49     /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
  50      * we know these will only support creating one kind of guest CPU,
  51      * which is its preferred CPU type.
  52      */
  53     static const uint32_t cpus_to_try[] = {
  54         QEMU_KVM_ARM_TARGET_CORTEX_A15,
  55         QEMU_KVM_ARM_TARGET_NONE
  56     };
  57     struct kvm_vcpu_init init;
  58
  59     if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
  60         return false;
  61     }
  62
  63     ahcf->target = init.target;
  64
  65     /* This is not strictly blessed by the device tree binding docs yet,
  66      * but in practice the kernel does not care about this string so
  67      * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
  68      */
  69     ahcf->dtb_compatible = "arm,arm-v7";
  70
  71     err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
  72     err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
  73
  74     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
  75                           ARM_CP15_REG32(0, 0, 2, 0));
  76     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
  77                           ARM_CP15_REG32(0, 0, 2, 1));
  78     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
  79                           ARM_CP15_REG32(0, 0, 2, 2));
  80     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
  81                           ARM_CP15_REG32(0, 0, 2, 3));
  82     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
  83                           ARM_CP15_REG32(0, 0, 2, 4));
  84     err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
  85                           ARM_CP15_REG32(0, 0, 2, 5));
  86     if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
  87                        ARM_CP15_REG32(0, 0, 2, 7))) {
  88         /*
  89          * Older kernels don't support reading ID_ISAR6. This register was
  90          * only introduced in ARMv8, so we can assume that it is zero on a
  91          * CPU that a kernel this old is running on.
  92          */
  93         ahcf->isar.id_isar6 = 0;
  94     }
  95
  96     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
  97                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
  98                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
  99     err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
 100                           KVM_REG_ARM | KVM_REG_SIZE_U32 |
 101                           KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
 102     /*
 103      * FIXME: There is not yet a way to read MVFR2.
 104      * Fortunately there is not yet anything in there that affects migration.
 105      */
 106
 107     kvm_arm_destroy_scratch_host_vcpu(fdarray);
 108
 109     if (err < 0) {
 110         return false;
 111     }
 112
 113     /* Now we've retrieved all the register information we can
 114      * set the feature bits based on the ID register fields.
 115      * We can assume any KVM supporting CPU is at least a v7
 116      * with VFPv3, virtualization extensions, and the generic
 117      * timers; this in turn implies most of the other feature
 118      * bits, but a few must be tested.
 119      */
 120     set_feature(&features, ARM_FEATURE_V7VE);
 121     set_feature(&features, ARM_FEATURE_VFP3);
 122     set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
 123
 124     if (extract32(id_pfr0, 12, 4) == 1) {
 125         set_feature(&features, ARM_FEATURE_THUMB2EE);
 126     }
 127     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
 128         set_feature(&features, ARM_FEATURE_NEON);
 129     }
 130     if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
 131         /* FMAC support implies VFPv4 */
 132         set_feature(&features, ARM_FEATURE_VFP4);
 133     }
 134
 135     ahcf->features = features;
 136
 137     return true;
 138 }
 139
 140 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
 141 {
 142     /* Return true if the regidx is a register we should synchronize
 143      * via the cpreg_tuples array (ie is not a core reg we sync by
 144      * hand in kvm_arch_get/put_registers())
 145      */
 146     switch (regidx & KVM_REG_ARM_COPROC_MASK) {
 147     case KVM_REG_ARM_CORE:
 148     case KVM_REG_ARM_VFP:
 149         return false;
 150     default:
 151         return true;
 152     }
 153 }
 154
 155 typedef struct CPRegStateLevel {
 156     uint64_t regidx;
 157     int level;
 158 } CPRegStateLevel;
 159
 160 /* All coprocessor registers not listed in the following table are assumed to
 161  * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
 162  * often, you must add it to this table with a state of either
 163  * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
 164  */
 165 static const CPRegStateLevel non_runtime_cpregs[] = {
 166     { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
 167 };
 168
 169 int kvm_arm_cpreg_level(uint64_t regidx)
 170 {
 171     int i;
 172
 173     for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
 174         const CPRegStateLevel *l = &non_runtime_cpregs[i];
 175         if (l->regidx == regidx) {
 176             return l->level;
 177         }
 178     }
 179
 180     return KVM_PUT_RUNTIME_STATE;
 181 }
 182
 183 #define ARM_CPU_ID_MPIDR       0, 0, 0, 5
 184
 185 int kvm_arch_init_vcpu(CPUState *cs)
 186 {
 187     int ret;
 188     uint64_t v;
 189     uint32_t mpidr;
 190     struct kvm_one_reg r;
 191     ARMCPU *cpu = ARM_CPU(cs);
 192
 193     if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
 194         fprintf(stderr, "KVM is not supported for this guest CPU type\n");
 195         return -EINVAL;
 196     }
 197
 198     /* Determine init features for this CPU */
 199     memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
 200     if (cpu->start_powered_off) {
 201         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
 202     }
 203     if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
 204         cpu->psci_version = 2;
 205         cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
 206     }
 207
 208     /* Do KVM_ARM_VCPU_INIT ioctl */
 209     ret = kvm_arm_vcpu_init(cs);
 210     if (ret) {
 211         return ret;
 212     }
 213
 214     /* Query the kernel to make sure it supports 32 VFP
 215      * registers: QEMU's "cortex-a15" CPU is always a
 216      * VFP-D32 core. The simplest way to do this is just
 217      * to attempt to read register d31.
 218      */
 219     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
 220     r.addr = (uintptr_t)(&v);
 221     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 222     if (ret == -ENOENT) {
 223         return -EINVAL;
 224     }
 225
 226     /*
 227      * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
 228      * Currently KVM has its own idea about MPIDR assignment, so we
 229      * override our defaults with what we get from KVM.
 230      */
 231     ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
 232     if (ret) {
 233         return ret;
 234     }
 235     cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
 236
 237     /* Check whether userspace can specify guest syndrome value */
 238     kvm_arm_init_serror_injection(cs);
 239
 240     return kvm_arm_init_cpreg_list(cpu);
 241 }
 242
 243 typedef struct Reg {
 244     uint64_t id;
 245     int offset;
 246 } Reg;
 247
 248 #define COREREG(KERNELNAME, QEMUFIELD)                       \
 249     {                                                        \
 250         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 251         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 252         offsetof(CPUARMState, QEMUFIELD)                     \
 253     }
 254
 255 #define VFPSYSREG(R)                                       \
 256     {                                                      \
 257         KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
 258         KVM_REG_ARM_VFP_##R,                               \
 259         offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R])      \
 260     }
 261
 262 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
 263 #define COREREG64(KERNELNAME, QEMUFIELD)                     \
 264     {                                                        \
 265         KVM_REG_ARM | KVM_REG_SIZE_U32 |                     \
 266         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
 267         offsetoflow32(CPUARMState, QEMUFIELD)                \
 268     }
 269
 270 static const Reg regs[] = {
 271     /* R0_usr .. R14_usr */
 272     COREREG(usr_regs.uregs[0], regs[0]),
 273     COREREG(usr_regs.uregs[1], regs[1]),
 274     COREREG(usr_regs.uregs[2], regs[2]),
 275     COREREG(usr_regs.uregs[3], regs[3]),
 276     COREREG(usr_regs.uregs[4], regs[4]),
 277     COREREG(usr_regs.uregs[5], regs[5]),
 278     COREREG(usr_regs.uregs[6], regs[6]),
 279     COREREG(usr_regs.uregs[7], regs[7]),
 280     COREREG(usr_regs.uregs[8], usr_regs[0]),
 281     COREREG(usr_regs.uregs[9], usr_regs[1]),
 282     COREREG(usr_regs.uregs[10], usr_regs[2]),
 283     COREREG(usr_regs.uregs[11], usr_regs[3]),
 284     COREREG(usr_regs.uregs[12], usr_regs[4]),
 285     COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
 286     COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
 287     /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
 288     COREREG(svc_regs[0], banked_r13[BANK_SVC]),
 289     COREREG(svc_regs[1], banked_r14[BANK_SVC]),
 290     COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
 291     COREREG(abt_regs[0], banked_r13[BANK_ABT]),
 292     COREREG(abt_regs[1], banked_r14[BANK_ABT]),
 293     COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
 294     COREREG(und_regs[0], banked_r13[BANK_UND]),
 295     COREREG(und_regs[1], banked_r14[BANK_UND]),
 296     COREREG64(und_regs[2], banked_spsr[BANK_UND]),
 297     COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
 298     COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
 299     COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
 300     /* R8_fiq .. R14_fiq and SPSR_fiq */
 301     COREREG(fiq_regs[0], fiq_regs[0]),
 302     COREREG(fiq_regs[1], fiq_regs[1]),
 303     COREREG(fiq_regs[2], fiq_regs[2]),
 304     COREREG(fiq_regs[3], fiq_regs[3]),
 305     COREREG(fiq_regs[4], fiq_regs[4]),
 306     COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
 307     COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
 308     COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
 309     /* R15 */
 310     COREREG(usr_regs.uregs[15], regs[15]),
 311     /* VFP system registers */
 312     VFPSYSREG(FPSID),
 313     VFPSYSREG(MVFR1),
 314     VFPSYSREG(MVFR0),
 315     VFPSYSREG(FPEXC),
 316     VFPSYSREG(FPINST),
 317     VFPSYSREG(FPINST2),
 318 };
 319
 320 int kvm_arch_put_registers(CPUState *cs, int level)
 321 {
 322     ARMCPU *cpu = ARM_CPU(cs);
 323     CPUARMState *env = &cpu->env;
 324     struct kvm_one_reg r;
 325     int mode, bn;
 326     int ret, i;
 327     uint32_t cpsr, fpscr;
 328
 329     /* Make sure the banked regs are properly set */
 330     mode = env->uncached_cpsr & CPSR_M;
 331     bn = bank_number(mode);
 332     if (mode == ARM_CPU_MODE_FIQ) {
 333         memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
 334     } else {
 335         memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
 336     }
 337     env->banked_r13[bn] = env->regs[13];
 338     env->banked_spsr[bn] = env->spsr;
 339     env->banked_r14[r14_bank_number(mode)] = env->regs[14];
 340
 341     /* Now we can safely copy stuff down to the kernel */
 342     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 343         r.id = regs[i].id;
 344         r.addr = (uintptr_t)(env) + regs[i].offset;
 345         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 346         if (ret) {
 347             return ret;
 348         }
 349     }
 350
 351     /* Special cases which aren't a single CPUARMState field */
 352     cpsr = cpsr_read(env);
 353     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 354         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 355     r.addr = (uintptr_t)(&cpsr);
 356     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 357     if (ret) {
 358         return ret;
 359     }
 360
 361     /* VFP registers */
 362     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 363     for (i = 0; i < 32; i++) {
 364         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 365         ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 366         if (ret) {
 367             return ret;
 368         }
 369         r.id++;
 370     }
 371
 372     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 373         KVM_REG_ARM_VFP_FPSCR;
 374     fpscr = vfp_get_fpscr(env);
 375     r.addr = (uintptr_t)&fpscr;
 376     ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
 377     if (ret) {
 378         return ret;
 379     }
 380
 381     ret = kvm_put_vcpu_events(cpu);
 382     if (ret) {
 383         return ret;
 384     }
 385
 386     write_cpustate_to_list(cpu, true);
 387
 388     if (!write_list_to_kvmstate(cpu, level)) {
 389         return EINVAL;
 390     }
 391
 392     kvm_arm_sync_mpstate_to_kvm(cpu);
 393
 394     return ret;
 395 }
 396
 397 int kvm_arch_get_registers(CPUState *cs)
 398 {
 399     ARMCPU *cpu = ARM_CPU(cs);
 400     CPUARMState *env = &cpu->env;
 401     struct kvm_one_reg r;
 402     int mode, bn;
 403     int ret, i;
 404     uint32_t cpsr, fpscr;
 405
 406     for (i = 0; i < ARRAY_SIZE(regs); i++) {
 407         r.id = regs[i].id;
 408         r.addr = (uintptr_t)(env) + regs[i].offset;
 409         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 410         if (ret) {
 411             return ret;
 412         }
 413     }
 414
 415     /* Special cases which aren't a single CPUARMState field */
 416     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
 417         KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
 418     r.addr = (uintptr_t)(&cpsr);
 419     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 420     if (ret) {
 421         return ret;
 422     }
 423     cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
 424
 425     /* Make sure the current mode regs are properly set */
 426     mode = env->uncached_cpsr & CPSR_M;
 427     bn = bank_number(mode);
 428     if (mode == ARM_CPU_MODE_FIQ) {
 429         memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
 430     } else {
 431         memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
 432     }
 433     env->regs[13] = env->banked_r13[bn];
 434     env->spsr = env->banked_spsr[bn];
 435     env->regs[14] = env->banked_r14[r14_bank_number(mode)];
 436
 437     /* VFP registers */
 438     r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
 439     for (i = 0; i < 32; i++) {
 440         r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
 441         ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 442         if (ret) {
 443             return ret;
 444         }
 445         r.id++;
 446     }
 447
 448     r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
 449         KVM_REG_ARM_VFP_FPSCR;
 450     r.addr = (uintptr_t)&fpscr;
 451     ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
 452     if (ret) {
 453         return ret;
 454     }
 455     vfp_set_fpscr(env, fpscr);
 456
 457     ret = kvm_get_vcpu_events(cpu);
 458     if (ret) {
 459         return ret;
 460     }
 461
 462     if (!write_kvmstate_to_list(cpu)) {
 463         return EINVAL;
 464     }
 465     /* Note that it's OK to have registers which aren't in CPUState,
 466      * so we can ignore a failure return here.
 467      */
 468     write_list_to_cpustate(cpu);
 469
 470     kvm_arm_sync_mpstate_to_qemu(cpu);
 471
 472     return 0;
 473 }
 474
 475 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 476 {
 477     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 478     return -EINVAL;
 479 }
 480
 481 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
 482 {
 483     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 484     return -EINVAL;
 485 }
 486
 487 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
 488 {
 489     qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
 490     return false;
 491 }
 492
 493 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 494                                   target_ulong len, int type)
 495 {
 496     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 497     return -EINVAL;
 498 }
 499
 500 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 501                                   target_ulong len, int type)
 502 {
 503     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 504     return -EINVAL;
 505 }
 506
 507 void kvm_arch_remove_all_hw_breakpoints(void)
 508 {
 509     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 510 }
 511
 512 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
 513 {
 514     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 515 }
 516
 517 bool kvm_arm_hw_debug_active(CPUState *cs)
 518 {
 519     return false;
 520 }
 521
 522 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
 523 {
 524     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 525 }
 526
 527 void kvm_arm_pmu_init(CPUState *cs)
 528 {
 529     qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
 530 }