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Update version for v7.0.0-rc4 release
[qemu/ar7.git] / hw / riscv / virt.c
blobda50cbed43ec54777992d40dbf158ec63fccef03
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/sysbus.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/riscv/riscv_hart.h"
32 #include "hw/riscv/virt.h"
33 #include "hw/riscv/boot.h"
34 #include "hw/riscv/numa.h"
35 #include "hw/intc/riscv_aclint.h"
36 #include "hw/intc/riscv_aplic.h"
37 #include "hw/intc/riscv_imsic.h"
38 #include "hw/intc/sifive_plic.h"
39 #include "hw/misc/sifive_test.h"
40 #include "chardev/char.h"
41 #include "sysemu/device_tree.h"
42 #include "sysemu/sysemu.h"
43 #include "sysemu/kvm.h"
44 #include "hw/pci/pci.h"
45 #include "hw/pci-host/gpex.h"
46 #include "hw/display/ramfb.h"
47
48 /*
49 * The virt machine physical address space used by some of the devices
50 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
51 * number of CPUs, and number of IMSIC guest files.
52 *
53 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
54 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
55 * of virt machine physical address space.
56 */
57
58 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
59 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
60 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
61 #error "Can't accomodate single IMSIC group in address space"
62 #endif
63
64 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \
65 VIRT_IMSIC_GROUP_MAX_SIZE)
66 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE
67 #error "Can't accomodate all IMSIC groups in address space"
68 #endif
69
70 static const MemMapEntry virt_memmap[] = {
71 [VIRT_DEBUG] = { 0x0, 0x100 },
72 [VIRT_MROM] = { 0x1000, 0xf000 },
73 [VIRT_TEST] = { 0x100000, 0x1000 },
74 [VIRT_RTC] = { 0x101000, 0x1000 },
75 [VIRT_CLINT] = { 0x2000000, 0x10000 },
76 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 },
77 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
78 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
79 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) },
80 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
81 [VIRT_UART0] = { 0x10000000, 0x100 },
82 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
83 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
84 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
85 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
86 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE },
87 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
88 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
89 [VIRT_DRAM] = { 0x80000000, 0x0 },
90 };
91
92 /* PCIe high mmio is fixed for RV32 */
93 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
94 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
95
96 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
97 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
98
99 static MemMapEntry virt_high_pcie_memmap;
100
101 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
102
103 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
104 const char *name,
105 const char *alias_prop_name)
106 {
107 /*
108 * Create a single flash device. We use the same parameters as
109 * the flash devices on the ARM virt board.
110 */
111 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
112
113 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
114 qdev_prop_set_uint8(dev, "width", 4);
115 qdev_prop_set_uint8(dev, "device-width", 2);
116 qdev_prop_set_bit(dev, "big-endian", false);
117 qdev_prop_set_uint16(dev, "id0", 0x89);
118 qdev_prop_set_uint16(dev, "id1", 0x18);
119 qdev_prop_set_uint16(dev, "id2", 0x00);
120 qdev_prop_set_uint16(dev, "id3", 0x00);
121 qdev_prop_set_string(dev, "name", name);
122
123 object_property_add_child(OBJECT(s), name, OBJECT(dev));
124 object_property_add_alias(OBJECT(s), alias_prop_name,
125 OBJECT(dev), "drive");
126
127 return PFLASH_CFI01(dev);
128 }
129
130 static void virt_flash_create(RISCVVirtState *s)
131 {
132 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
133 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
134 }
135
136 static void virt_flash_map1(PFlashCFI01 *flash,
137 hwaddr base, hwaddr size,
138 MemoryRegion *sysmem)
139 {
140 DeviceState *dev = DEVICE(flash);
141
142 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
143 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
144 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
145 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
146
147 memory_region_add_subregion(sysmem, base,
148 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
149 0));
150 }
151
152 static void virt_flash_map(RISCVVirtState *s,
153 MemoryRegion *sysmem)
154 {
155 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
156 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
157
158 virt_flash_map1(s->flash[0], flashbase, flashsize,
159 sysmem);
160 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
161 sysmem);
162 }
163
164 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename,
165 uint32_t irqchip_phandle)
166 {
167 int pin, dev;
168 uint32_t irq_map_stride = 0;
169 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS *
170 FDT_MAX_INT_MAP_WIDTH] = {};
171 uint32_t *irq_map = full_irq_map;
172
173 /* This code creates a standard swizzle of interrupts such that
174 * each device's first interrupt is based on it's PCI_SLOT number.
175 * (See pci_swizzle_map_irq_fn())
176 *
177 * We only need one entry per interrupt in the table (not one per
178 * possible slot) seeing the interrupt-map-mask will allow the table
179 * to wrap to any number of devices.
180 */
181 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
182 int devfn = dev * 0x8;
183
184 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
185 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
186 int i = 0;
187
188 /* Fill PCI address cells */
189 irq_map[i] = cpu_to_be32(devfn << 8);
190 i += FDT_PCI_ADDR_CELLS;
191
192 /* Fill PCI Interrupt cells */
193 irq_map[i] = cpu_to_be32(pin + 1);
194 i += FDT_PCI_INT_CELLS;
195
196 /* Fill interrupt controller phandle and cells */
197 irq_map[i++] = cpu_to_be32(irqchip_phandle);
198 irq_map[i++] = cpu_to_be32(irq_nr);
199 if (s->aia_type != VIRT_AIA_TYPE_NONE) {
200 irq_map[i++] = cpu_to_be32(0x4);
201 }
202
203 if (!irq_map_stride) {
204 irq_map_stride = i;
205 }
206 irq_map += irq_map_stride;
207 }
208 }
209
210 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
211 GPEX_NUM_IRQS * GPEX_NUM_IRQS *
212 irq_map_stride * sizeof(uint32_t));
213
214 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
215 0x1800, 0, 0, 0x7);
216 }
217
218 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
219 char *clust_name, uint32_t *phandle,
220 bool is_32_bit, uint32_t *intc_phandles)
221 {
222 int cpu;
223 uint32_t cpu_phandle;
224 MachineState *mc = MACHINE(s);
225 char *name, *cpu_name, *core_name, *intc_name;
226
227 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
228 cpu_phandle = (*phandle)++;
229
230 cpu_name = g_strdup_printf("/cpus/cpu@%d",
231 s->soc[socket].hartid_base + cpu);
232 qemu_fdt_add_subnode(mc->fdt, cpu_name);
233 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type",
234 (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
235 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
236 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name);
237 g_free(name);
238 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv");
239 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay");
240 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg",
241 s->soc[socket].hartid_base + cpu);
242 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu");
243 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket);
244 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle);
245
246 intc_phandles[cpu] = (*phandle)++;
247
248 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
249 qemu_fdt_add_subnode(mc->fdt, intc_name);
250 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
251 intc_phandles[cpu]);
252 if (riscv_feature(&s->soc[socket].harts[cpu].env,
253 RISCV_FEATURE_AIA)) {
254 static const char * const compat[2] = {
255 "riscv,cpu-intc-aia", "riscv,cpu-intc"
256 };
257 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible",
258 (char **)&compat, ARRAY_SIZE(compat));
259 } else {
260 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
261 "riscv,cpu-intc");
262 }
263 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
264 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
265
266 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
267 qemu_fdt_add_subnode(mc->fdt, core_name);
268 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle);
269
270 g_free(core_name);
271 g_free(intc_name);
272 g_free(cpu_name);
273 }
274 }
275
276 static void create_fdt_socket_memory(RISCVVirtState *s,
277 const MemMapEntry *memmap, int socket)
278 {
279 char *mem_name;
280 uint64_t addr, size;
281 MachineState *mc = MACHINE(s);
282
283 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
284 size = riscv_socket_mem_size(mc, socket);
285 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
286 qemu_fdt_add_subnode(mc->fdt, mem_name);
287 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg",
288 addr >> 32, addr, size >> 32, size);
289 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory");
290 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket);
291 g_free(mem_name);
292 }
293
294 static void create_fdt_socket_clint(RISCVVirtState *s,
295 const MemMapEntry *memmap, int socket,
296 uint32_t *intc_phandles)
297 {
298 int cpu;
299 char *clint_name;
300 uint32_t *clint_cells;
301 unsigned long clint_addr;
302 MachineState *mc = MACHINE(s);
303 static const char * const clint_compat[2] = {
304 "sifive,clint0", "riscv,clint0"
305 };
306
307 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
308
309 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
310 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
311 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
312 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
313 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
314 }
315
316 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
317 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
318 qemu_fdt_add_subnode(mc->fdt, clint_name);
319 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible",
320 (char **)&clint_compat,
321 ARRAY_SIZE(clint_compat));
322 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg",
323 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
324 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended",
325 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
326 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket);
327 g_free(clint_name);
328
329 g_free(clint_cells);
330 }
331
332 static void create_fdt_socket_aclint(RISCVVirtState *s,
333 const MemMapEntry *memmap, int socket,
334 uint32_t *intc_phandles)
335 {
336 int cpu;
337 char *name;
338 unsigned long addr, size;
339 uint32_t aclint_cells_size;
340 uint32_t *aclint_mswi_cells;
341 uint32_t *aclint_sswi_cells;
342 uint32_t *aclint_mtimer_cells;
343 MachineState *mc = MACHINE(s);
344
345 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
346 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
347 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
348
349 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
350 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
351 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT);
352 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
353 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER);
354 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
355 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT);
356 }
357 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2;
358
359 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
360 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket);
361 name = g_strdup_printf("/soc/mswi@%lx", addr);
362 qemu_fdt_add_subnode(mc->fdt, name);
363 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
364 "riscv,aclint-mswi");
365 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
366 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE);
367 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
368 aclint_mswi_cells, aclint_cells_size);
369 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
370 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
371 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
372 g_free(name);
373 }
374
375 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
376 addr = memmap[VIRT_CLINT].base +
377 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket);
378 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE;
379 } else {
380 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE +
381 (memmap[VIRT_CLINT].size * socket);
382 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE;
383 }
384 name = g_strdup_printf("/soc/mtimer@%lx", addr);
385 qemu_fdt_add_subnode(mc->fdt, name);
386 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
387 "riscv,aclint-mtimer");
388 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
389 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME,
390 0x0, size - RISCV_ACLINT_DEFAULT_MTIME,
391 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP,
392 0x0, RISCV_ACLINT_DEFAULT_MTIME);
393 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
394 aclint_mtimer_cells, aclint_cells_size);
395 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
396 g_free(name);
397
398 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) {
399 addr = memmap[VIRT_ACLINT_SSWI].base +
400 (memmap[VIRT_ACLINT_SSWI].size * socket);
401 name = g_strdup_printf("/soc/sswi@%lx", addr);
402 qemu_fdt_add_subnode(mc->fdt, name);
403 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
404 "riscv,aclint-sswi");
405 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
406 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size);
407 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended",
408 aclint_sswi_cells, aclint_cells_size);
409 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0);
410 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0);
411 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket);
412 g_free(name);
413 }
414
415 g_free(aclint_mswi_cells);
416 g_free(aclint_mtimer_cells);
417 g_free(aclint_sswi_cells);
418 }
419
420 static void create_fdt_socket_plic(RISCVVirtState *s,
421 const MemMapEntry *memmap, int socket,
422 uint32_t *phandle, uint32_t *intc_phandles,
423 uint32_t *plic_phandles)
424 {
425 int cpu;
426 char *plic_name;
427 uint32_t *plic_cells;
428 unsigned long plic_addr;
429 MachineState *mc = MACHINE(s);
430 static const char * const plic_compat[2] = {
431 "sifive,plic-1.0.0", "riscv,plic0"
432 };
433
434 if (kvm_enabled()) {
435 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
436 } else {
437 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
438 }
439
440 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
441 if (kvm_enabled()) {
442 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
443 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
444 } else {
445 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]);
446 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
447 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]);
448 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
449 }
450 }
451
452 plic_phandles[socket] = (*phandle)++;
453 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
454 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
455 qemu_fdt_add_subnode(mc->fdt, plic_name);
456 qemu_fdt_setprop_cell(mc->fdt, plic_name,
457 "#interrupt-cells", FDT_PLIC_INT_CELLS);
458 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible",
459 (char **)&plic_compat,
460 ARRAY_SIZE(plic_compat));
461 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0);
462 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended",
463 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
464 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg",
465 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
466 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
467 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket);
468 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle",
469 plic_phandles[socket]);
470 g_free(plic_name);
471
472 g_free(plic_cells);
473 }
474
475 static uint32_t imsic_num_bits(uint32_t count)
476 {
477 uint32_t ret = 0;
478
479 while (BIT(ret) < count) {
480 ret++;
481 }
482
483 return ret;
484 }
485
486 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap,
487 uint32_t *phandle, uint32_t *intc_phandles,
488 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle)
489 {
490 int cpu, socket;
491 char *imsic_name;
492 MachineState *mc = MACHINE(s);
493 uint32_t imsic_max_hart_per_socket, imsic_guest_bits;
494 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size;
495
496 *msi_m_phandle = (*phandle)++;
497 *msi_s_phandle = (*phandle)++;
498 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2);
499 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4);
500
501 /* M-level IMSIC node */
502 for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
503 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
504 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
505 }
506 imsic_max_hart_per_socket = 0;
507 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
508 imsic_addr = memmap[VIRT_IMSIC_M].base +
509 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
510 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts;
511 imsic_regs[socket * 4 + 0] = 0;
512 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
513 imsic_regs[socket * 4 + 2] = 0;
514 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
515 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
516 imsic_max_hart_per_socket = s->soc[socket].num_harts;
517 }
518 }
519 imsic_name = g_strdup_printf("/soc/imsics@%lx",
520 (unsigned long)memmap[VIRT_IMSIC_M].base);
521 qemu_fdt_add_subnode(mc->fdt, imsic_name);
522 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
523 "riscv,imsics");
524 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
525 FDT_IMSIC_INT_CELLS);
526 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
527 NULL, 0);
528 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
529 NULL, 0);
530 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
531 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
532 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
533 riscv_socket_count(mc) * sizeof(uint32_t) * 4);
534 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
535 VIRT_IRQCHIP_NUM_MSIS);
536 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
537 VIRT_IRQCHIP_IPI_MSI);
538 if (riscv_socket_count(mc) > 1) {
539 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
540 imsic_num_bits(imsic_max_hart_per_socket));
541 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
542 imsic_num_bits(riscv_socket_count(mc)));
543 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
544 IMSIC_MMIO_GROUP_MIN_SHIFT);
545 }
546 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle);
547 g_free(imsic_name);
548
549 /* S-level IMSIC node */
550 for (cpu = 0; cpu < mc->smp.cpus; cpu++) {
551 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
552 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
553 }
554 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1);
555 imsic_max_hart_per_socket = 0;
556 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
557 imsic_addr = memmap[VIRT_IMSIC_S].base +
558 socket * VIRT_IMSIC_GROUP_MAX_SIZE;
559 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) *
560 s->soc[socket].num_harts;
561 imsic_regs[socket * 4 + 0] = 0;
562 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr);
563 imsic_regs[socket * 4 + 2] = 0;
564 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size);
565 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) {
566 imsic_max_hart_per_socket = s->soc[socket].num_harts;
567 }
568 }
569 imsic_name = g_strdup_printf("/soc/imsics@%lx",
570 (unsigned long)memmap[VIRT_IMSIC_S].base);
571 qemu_fdt_add_subnode(mc->fdt, imsic_name);
572 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible",
573 "riscv,imsics");
574 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells",
575 FDT_IMSIC_INT_CELLS);
576 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller",
577 NULL, 0);
578 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller",
579 NULL, 0);
580 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended",
581 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2);
582 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs,
583 riscv_socket_count(mc) * sizeof(uint32_t) * 4);
584 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids",
585 VIRT_IRQCHIP_NUM_MSIS);
586 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id",
587 VIRT_IRQCHIP_IPI_MSI);
588 if (imsic_guest_bits) {
589 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits",
590 imsic_guest_bits);
591 }
592 if (riscv_socket_count(mc) > 1) {
593 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits",
594 imsic_num_bits(imsic_max_hart_per_socket));
595 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits",
596 imsic_num_bits(riscv_socket_count(mc)));
597 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift",
598 IMSIC_MMIO_GROUP_MIN_SHIFT);
599 }
600 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle);
601 g_free(imsic_name);
602
603 g_free(imsic_regs);
604 g_free(imsic_cells);
605 }
606
607 static void create_fdt_socket_aplic(RISCVVirtState *s,
608 const MemMapEntry *memmap, int socket,
609 uint32_t msi_m_phandle,
610 uint32_t msi_s_phandle,
611 uint32_t *phandle,
612 uint32_t *intc_phandles,
613 uint32_t *aplic_phandles)
614 {
615 int cpu;
616 char *aplic_name;
617 uint32_t *aplic_cells;
618 unsigned long aplic_addr;
619 MachineState *mc = MACHINE(s);
620 uint32_t aplic_m_phandle, aplic_s_phandle;
621
622 aplic_m_phandle = (*phandle)++;
623 aplic_s_phandle = (*phandle)++;
624 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2);
625
626 /* M-level APLIC node */
627 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
628 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
629 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT);
630 }
631 aplic_addr = memmap[VIRT_APLIC_M].base +
632 (memmap[VIRT_APLIC_M].size * socket);
633 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
634 qemu_fdt_add_subnode(mc->fdt, aplic_name);
635 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
636 qemu_fdt_setprop_cell(mc->fdt, aplic_name,
637 "#interrupt-cells", FDT_APLIC_INT_CELLS);
638 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
639 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
640 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
641 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
642 } else {
643 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
644 msi_m_phandle);
645 }
646 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
647 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size);
648 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
649 VIRT_IRQCHIP_NUM_SOURCES);
650 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children",
651 aplic_s_phandle);
652 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate",
653 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES);
654 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
655 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle);
656 g_free(aplic_name);
657
658 /* S-level APLIC node */
659 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) {
660 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]);
661 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT);
662 }
663 aplic_addr = memmap[VIRT_APLIC_S].base +
664 (memmap[VIRT_APLIC_S].size * socket);
665 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr);
666 qemu_fdt_add_subnode(mc->fdt, aplic_name);
667 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic");
668 qemu_fdt_setprop_cell(mc->fdt, aplic_name,
669 "#interrupt-cells", FDT_APLIC_INT_CELLS);
670 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0);
671 if (s->aia_type == VIRT_AIA_TYPE_APLIC) {
672 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended",
673 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2);
674 } else {
675 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent",
676 msi_s_phandle);
677 }
678 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg",
679 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size);
680 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources",
681 VIRT_IRQCHIP_NUM_SOURCES);
682 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket);
683 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle);
684 g_free(aplic_name);
685
686 g_free(aplic_cells);
687 aplic_phandles[socket] = aplic_s_phandle;
688 }
689
690 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap,
691 bool is_32_bit, uint32_t *phandle,
692 uint32_t *irq_mmio_phandle,
693 uint32_t *irq_pcie_phandle,
694 uint32_t *irq_virtio_phandle,
695 uint32_t *msi_pcie_phandle)
696 {
697 char *clust_name;
698 int socket, phandle_pos;
699 MachineState *mc = MACHINE(s);
700 uint32_t msi_m_phandle = 0, msi_s_phandle = 0;
701 uint32_t *intc_phandles, xplic_phandles[MAX_NODES];
702
703 qemu_fdt_add_subnode(mc->fdt, "/cpus");
704 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency",
705 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ);
706 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0);
707 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1);
708 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map");
709
710 intc_phandles = g_new0(uint32_t, mc->smp.cpus);
711
712 phandle_pos = mc->smp.cpus;
713 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
714 phandle_pos -= s->soc[socket].num_harts;
715
716 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
717 qemu_fdt_add_subnode(mc->fdt, clust_name);
718
719 create_fdt_socket_cpus(s, socket, clust_name, phandle,
720 is_32_bit, &intc_phandles[phandle_pos]);
721
722 create_fdt_socket_memory(s, memmap, socket);
723
724 g_free(clust_name);
725
726 if (!kvm_enabled()) {
727 if (s->have_aclint) {
728 create_fdt_socket_aclint(s, memmap, socket,
729 &intc_phandles[phandle_pos]);
730 } else {
731 create_fdt_socket_clint(s, memmap, socket,
732 &intc_phandles[phandle_pos]);
733 }
734 }
735 }
736
737 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
738 create_fdt_imsic(s, memmap, phandle, intc_phandles,
739 &msi_m_phandle, &msi_s_phandle);
740 *msi_pcie_phandle = msi_s_phandle;
741 }
742
743 phandle_pos = mc->smp.cpus;
744 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
745 phandle_pos -= s->soc[socket].num_harts;
746
747 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
748 create_fdt_socket_plic(s, memmap, socket, phandle,
749 &intc_phandles[phandle_pos], xplic_phandles);
750 } else {
751 create_fdt_socket_aplic(s, memmap, socket,
752 msi_m_phandle, msi_s_phandle, phandle,
753 &intc_phandles[phandle_pos], xplic_phandles);
754 }
755 }
756
757 g_free(intc_phandles);
758
759 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
760 if (socket == 0) {
761 *irq_mmio_phandle = xplic_phandles[socket];
762 *irq_virtio_phandle = xplic_phandles[socket];
763 *irq_pcie_phandle = xplic_phandles[socket];
764 }
765 if (socket == 1) {
766 *irq_virtio_phandle = xplic_phandles[socket];
767 *irq_pcie_phandle = xplic_phandles[socket];
768 }
769 if (socket == 2) {
770 *irq_pcie_phandle = xplic_phandles[socket];
771 }
772 }
773
774 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt);
775 }
776
777 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap,
778 uint32_t irq_virtio_phandle)
779 {
780 int i;
781 char *name;
782 MachineState *mc = MACHINE(s);
783
784 for (i = 0; i < VIRTIO_COUNT; i++) {
785 name = g_strdup_printf("/soc/virtio_mmio@%lx",
786 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
787 qemu_fdt_add_subnode(mc->fdt, name);
788 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio");
789 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
790 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
791 0x0, memmap[VIRT_VIRTIO].size);
792 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
793 irq_virtio_phandle);
794 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
795 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts",
796 VIRTIO_IRQ + i);
797 } else {
798 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts",
799 VIRTIO_IRQ + i, 0x4);
800 }
801 g_free(name);
802 }
803 }
804
805 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap,
806 uint32_t irq_pcie_phandle,
807 uint32_t msi_pcie_phandle)
808 {
809 char *name;
810 MachineState *mc = MACHINE(s);
811
812 name = g_strdup_printf("/soc/pci@%lx",
813 (long) memmap[VIRT_PCIE_ECAM].base);
814 qemu_fdt_add_subnode(mc->fdt, name);
815 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells",
816 FDT_PCI_ADDR_CELLS);
817 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells",
818 FDT_PCI_INT_CELLS);
819 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2);
820 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
821 "pci-host-ecam-generic");
822 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci");
823 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0);
824 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0,
825 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
826 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0);
827 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
828 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle);
829 }
830 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0,
831 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
832 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges",
833 1, FDT_PCI_RANGE_IOPORT, 2, 0,
834 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
835 1, FDT_PCI_RANGE_MMIO,
836 2, memmap[VIRT_PCIE_MMIO].base,
837 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
838 1, FDT_PCI_RANGE_MMIO_64BIT,
839 2, virt_high_pcie_memmap.base,
840 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
841
842 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle);
843 g_free(name);
844 }
845
846 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap,
847 uint32_t *phandle)
848 {
849 char *name;
850 uint32_t test_phandle;
851 MachineState *mc = MACHINE(s);
852
853 test_phandle = (*phandle)++;
854 name = g_strdup_printf("/soc/test@%lx",
855 (long)memmap[VIRT_TEST].base);
856 qemu_fdt_add_subnode(mc->fdt, name);
857 {
858 static const char * const compat[3] = {
859 "sifive,test1", "sifive,test0", "syscon"
860 };
861 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
862 (char **)&compat, ARRAY_SIZE(compat));
863 }
864 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
865 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size);
866 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle);
867 test_phandle = qemu_fdt_get_phandle(mc->fdt, name);
868 g_free(name);
869
870 name = g_strdup_printf("/soc/reboot");
871 qemu_fdt_add_subnode(mc->fdt, name);
872 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot");
873 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
874 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
875 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET);
876 g_free(name);
877
878 name = g_strdup_printf("/soc/poweroff");
879 qemu_fdt_add_subnode(mc->fdt, name);
880 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff");
881 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle);
882 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0);
883 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS);
884 g_free(name);
885 }
886
887 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap,
888 uint32_t irq_mmio_phandle)
889 {
890 char *name;
891 MachineState *mc = MACHINE(s);
892
893 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
894 qemu_fdt_add_subnode(mc->fdt, name);
895 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a");
896 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
897 0x0, memmap[VIRT_UART0].base,
898 0x0, memmap[VIRT_UART0].size);
899 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400);
900 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle);
901 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
902 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ);
903 } else {
904 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4);
905 }
906
907 qemu_fdt_add_subnode(mc->fdt, "/chosen");
908 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name);
909 g_free(name);
910 }
911
912 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap,
913 uint32_t irq_mmio_phandle)
914 {
915 char *name;
916 MachineState *mc = MACHINE(s);
917
918 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
919 qemu_fdt_add_subnode(mc->fdt, name);
920 qemu_fdt_setprop_string(mc->fdt, name, "compatible",
921 "google,goldfish-rtc");
922 qemu_fdt_setprop_cells(mc->fdt, name, "reg",
923 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size);
924 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent",
925 irq_mmio_phandle);
926 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
927 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ);
928 } else {
929 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4);
930 }
931 g_free(name);
932 }
933
934 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap)
935 {
936 char *name;
937 MachineState *mc = MACHINE(s);
938 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
939 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
940
941 name = g_strdup_printf("/flash@%" PRIx64, flashbase);
942 qemu_fdt_add_subnode(mc->fdt, name);
943 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
944 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
945 2, flashbase, 2, flashsize,
946 2, flashbase + flashsize, 2, flashsize);
947 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
948 g_free(name);
949 }
950
951 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
952 uint64_t mem_size, const char *cmdline, bool is_32_bit)
953 {
954 MachineState *mc = MACHINE(s);
955 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
956 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
957
958 if (mc->dtb) {
959 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
960 if (!mc->fdt) {
961 error_report("load_device_tree() failed");
962 exit(1);
963 }
964 goto update_bootargs;
965 } else {
966 mc->fdt = create_device_tree(&s->fdt_size);
967 if (!mc->fdt) {
968 error_report("create_device_tree() failed");
969 exit(1);
970 }
971 }
972
973 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu");
974 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio");
975 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2);
976 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2);
977
978 qemu_fdt_add_subnode(mc->fdt, "/soc");
979 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0);
980 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus");
981 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2);
982 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2);
983
984 create_fdt_sockets(s, memmap, is_32_bit, &phandle,
985 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle,
986 &msi_pcie_phandle);
987
988 create_fdt_virtio(s, memmap, irq_virtio_phandle);
989
990 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle);
991
992 create_fdt_reset(s, memmap, &phandle);
993
994 create_fdt_uart(s, memmap, irq_mmio_phandle);
995
996 create_fdt_rtc(s, memmap, irq_mmio_phandle);
997
998 create_fdt_flash(s, memmap);
999
1000 update_bootargs:
1001 if (cmdline) {
1002 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
1003 }
1004 }
1005
1006 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
1007 hwaddr ecam_base, hwaddr ecam_size,
1008 hwaddr mmio_base, hwaddr mmio_size,
1009 hwaddr high_mmio_base,
1010 hwaddr high_mmio_size,
1011 hwaddr pio_base,
1012 DeviceState *irqchip)
1013 {
1014 DeviceState *dev;
1015 MemoryRegion *ecam_alias, *ecam_reg;
1016 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
1017 qemu_irq irq;
1018 int i;
1019
1020 dev = qdev_new(TYPE_GPEX_HOST);
1021
1022 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1023
1024 ecam_alias = g_new0(MemoryRegion, 1);
1025 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1026 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1027 ecam_reg, 0, ecam_size);
1028 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
1029
1030 mmio_alias = g_new0(MemoryRegion, 1);
1031 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1032 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1033 mmio_reg, mmio_base, mmio_size);
1034 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
1035
1036 /* Map high MMIO space */
1037 high_mmio_alias = g_new0(MemoryRegion, 1);
1038 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1039 mmio_reg, high_mmio_base, high_mmio_size);
1040 memory_region_add_subregion(get_system_memory(), high_mmio_base,
1041 high_mmio_alias);
1042
1043 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
1044
1045 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1046 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i);
1047
1048 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
1049 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
1050 }
1051
1052 return dev;
1053 }
1054
1055 static FWCfgState *create_fw_cfg(const MachineState *mc)
1056 {
1057 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
1058 hwaddr size = virt_memmap[VIRT_FW_CFG].size;
1059 FWCfgState *fw_cfg;
1060 char *nodename;
1061
1062 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
1063 &address_space_memory);
1064 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
1065
1066 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1067 qemu_fdt_add_subnode(mc->fdt, nodename);
1068 qemu_fdt_setprop_string(mc->fdt, nodename,
1069 "compatible", "qemu,fw-cfg-mmio");
1070 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
1071 2, base, 2, size);
1072 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
1073 g_free(nodename);
1074 return fw_cfg;
1075 }
1076
1077 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket,
1078 int base_hartid, int hart_count)
1079 {
1080 DeviceState *ret;
1081 char *plic_hart_config;
1082
1083 /* Per-socket PLIC hart topology configuration string */
1084 plic_hart_config = riscv_plic_hart_config_string(hart_count);
1085
1086 /* Per-socket PLIC */
1087 ret = sifive_plic_create(
1088 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size,
1089 plic_hart_config, hart_count, base_hartid,
1090 VIRT_IRQCHIP_NUM_SOURCES,
1091 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1),
1092 VIRT_PLIC_PRIORITY_BASE,
1093 VIRT_PLIC_PENDING_BASE,
1094 VIRT_PLIC_ENABLE_BASE,
1095 VIRT_PLIC_ENABLE_STRIDE,
1096 VIRT_PLIC_CONTEXT_BASE,
1097 VIRT_PLIC_CONTEXT_STRIDE,
1098 memmap[VIRT_PLIC].size);
1099
1100 g_free(plic_hart_config);
1101
1102 return ret;
1103 }
1104
1105 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests,
1106 const MemMapEntry *memmap, int socket,
1107 int base_hartid, int hart_count)
1108 {
1109 int i;
1110 hwaddr addr;
1111 uint32_t guest_bits;
1112 DeviceState *aplic_m;
1113 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false;
1114
1115 if (msimode) {
1116 /* Per-socket M-level IMSICs */
1117 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1118 for (i = 0; i < hart_count; i++) {
1119 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0),
1120 base_hartid + i, true, 1,
1121 VIRT_IRQCHIP_NUM_MSIS);
1122 }
1123
1124 /* Per-socket S-level IMSICs */
1125 guest_bits = imsic_num_bits(aia_guests + 1);
1126 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE;
1127 for (i = 0; i < hart_count; i++) {
1128 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits),
1129 base_hartid + i, false, 1 + aia_guests,
1130 VIRT_IRQCHIP_NUM_MSIS);
1131 }
1132 }
1133
1134 /* Per-socket M-level APLIC */
1135 aplic_m = riscv_aplic_create(
1136 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size,
1137 memmap[VIRT_APLIC_M].size,
1138 (msimode) ? 0 : base_hartid,
1139 (msimode) ? 0 : hart_count,
1140 VIRT_IRQCHIP_NUM_SOURCES,
1141 VIRT_IRQCHIP_NUM_PRIO_BITS,
1142 msimode, true, NULL);
1143
1144 if (aplic_m) {
1145 /* Per-socket S-level APLIC */
1146 riscv_aplic_create(
1147 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size,
1148 memmap[VIRT_APLIC_S].size,
1149 (msimode) ? 0 : base_hartid,
1150 (msimode) ? 0 : hart_count,
1151 VIRT_IRQCHIP_NUM_SOURCES,
1152 VIRT_IRQCHIP_NUM_PRIO_BITS,
1153 msimode, false, aplic_m);
1154 }
1155
1156 return aplic_m;
1157 }
1158
1159 static void virt_machine_init(MachineState *machine)
1160 {
1161 const MemMapEntry *memmap = virt_memmap;
1162 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
1163 MemoryRegion *system_memory = get_system_memory();
1164 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
1165 char *soc_name;
1166 target_ulong start_addr = memmap[VIRT_DRAM].base;
1167 target_ulong firmware_end_addr, kernel_start_addr;
1168 uint32_t fdt_load_addr;
1169 uint64_t kernel_entry;
1170 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
1171 int i, base_hartid, hart_count;
1172
1173 /* Check socket count limit */
1174 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
1175 error_report("number of sockets/nodes should be less than %d",
1176 VIRT_SOCKETS_MAX);
1177 exit(1);
1178 }
1179
1180 /* Initialize sockets */
1181 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL;
1182 for (i = 0; i < riscv_socket_count(machine); i++) {
1183 if (!riscv_socket_check_hartids(machine, i)) {
1184 error_report("discontinuous hartids in socket%d", i);
1185 exit(1);
1186 }
1187
1188 base_hartid = riscv_socket_first_hartid(machine, i);
1189 if (base_hartid < 0) {
1190 error_report("can't find hartid base for socket%d", i);
1191 exit(1);
1192 }
1193
1194 hart_count = riscv_socket_hart_count(machine, i);
1195 if (hart_count < 0) {
1196 error_report("can't find hart count for socket%d", i);
1197 exit(1);
1198 }
1199
1200 soc_name = g_strdup_printf("soc%d", i);
1201 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
1202 TYPE_RISCV_HART_ARRAY);
1203 g_free(soc_name);
1204 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
1205 machine->cpu_type, &error_abort);
1206 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
1207 base_hartid, &error_abort);
1208 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
1209 hart_count, &error_abort);
1210 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
1211
1212 if (!kvm_enabled()) {
1213 if (s->have_aclint) {
1214 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) {
1215 /* Per-socket ACLINT MTIMER */
1216 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1217 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1218 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1219 base_hartid, hart_count,
1220 RISCV_ACLINT_DEFAULT_MTIMECMP,
1221 RISCV_ACLINT_DEFAULT_MTIME,
1222 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1223 } else {
1224 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */
1225 riscv_aclint_swi_create(memmap[VIRT_CLINT].base +
1226 i * memmap[VIRT_CLINT].size,
1227 base_hartid, hart_count, false);
1228 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1229 i * memmap[VIRT_CLINT].size +
1230 RISCV_ACLINT_SWI_SIZE,
1231 RISCV_ACLINT_DEFAULT_MTIMER_SIZE,
1232 base_hartid, hart_count,
1233 RISCV_ACLINT_DEFAULT_MTIMECMP,
1234 RISCV_ACLINT_DEFAULT_MTIME,
1235 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1236 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base +
1237 i * memmap[VIRT_ACLINT_SSWI].size,
1238 base_hartid, hart_count, true);
1239 }
1240 } else {
1241 /* Per-socket SiFive CLINT */
1242 riscv_aclint_swi_create(
1243 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
1244 base_hartid, hart_count, false);
1245 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base +
1246 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE,
1247 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count,
1248 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
1249 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true);
1250 }
1251 }
1252
1253 /* Per-socket interrupt controller */
1254 if (s->aia_type == VIRT_AIA_TYPE_NONE) {
1255 s->irqchip[i] = virt_create_plic(memmap, i,
1256 base_hartid, hart_count);
1257 } else {
1258 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests,
1259 memmap, i, base_hartid,
1260 hart_count);
1261 }
1262
1263 /* Try to use different IRQCHIP instance based device type */
1264 if (i == 0) {
1265 mmio_irqchip = s->irqchip[i];
1266 virtio_irqchip = s->irqchip[i];
1267 pcie_irqchip = s->irqchip[i];
1268 }
1269 if (i == 1) {
1270 virtio_irqchip = s->irqchip[i];
1271 pcie_irqchip = s->irqchip[i];
1272 }
1273 if (i == 2) {
1274 pcie_irqchip = s->irqchip[i];
1275 }
1276 }
1277
1278 if (riscv_is_32bit(&s->soc[0])) {
1279 #if HOST_LONG_BITS == 64
1280 /* limit RAM size in a 32-bit system */
1281 if (machine->ram_size > 10 * GiB) {
1282 machine->ram_size = 10 * GiB;
1283 error_report("Limiting RAM size to 10 GiB");
1284 }
1285 #endif
1286 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
1287 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
1288 } else {
1289 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
1290 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
1291 virt_high_pcie_memmap.base =
1292 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
1293 }
1294
1295 /* register system main memory (actual RAM) */
1296 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
1297 machine->ram);
1298
1299 /* create device tree */
1300 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
1301 riscv_is_32bit(&s->soc[0]));
1302
1303 /* boot rom */
1304 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
1305 memmap[VIRT_MROM].size, &error_fatal);
1306 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
1307 mask_rom);
1308
1309 /*
1310 * Only direct boot kernel is currently supported for KVM VM,
1311 * so the "-bios" parameter is ignored and treated like "-bios none"
1312 * when KVM is enabled.
1313 */
1314 if (kvm_enabled()) {
1315 g_free(machine->firmware);
1316 machine->firmware = g_strdup("none");
1317 }
1318
1319 if (riscv_is_32bit(&s->soc[0])) {
1320 firmware_end_addr = riscv_find_and_load_firmware(machine,
1321 RISCV32_BIOS_BIN, start_addr, NULL);
1322 } else {
1323 firmware_end_addr = riscv_find_and_load_firmware(machine,
1324 RISCV64_BIOS_BIN, start_addr, NULL);
1325 }
1326
1327 if (machine->kernel_filename) {
1328 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
1329 firmware_end_addr);
1330
1331 kernel_entry = riscv_load_kernel(machine->kernel_filename,
1332 kernel_start_addr, NULL);
1333
1334 if (machine->initrd_filename) {
1335 hwaddr start;
1336 hwaddr end = riscv_load_initrd(machine->initrd_filename,
1337 machine->ram_size, kernel_entry,
1338 &start);
1339 qemu_fdt_setprop_cell(machine->fdt, "/chosen",
1340 "linux,initrd-start", start);
1341 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
1342 end);
1343 }
1344 } else {
1345 /*
1346 * If dynamic firmware is used, it doesn't know where is the next mode
1347 * if kernel argument is not set.
1348 */
1349 kernel_entry = 0;
1350 }
1351
1352 if (drive_get(IF_PFLASH, 0, 0)) {
1353 /*
1354 * Pflash was supplied, let's overwrite the address we jump to after
1355 * reset to the base of the flash.
1356 */
1357 start_addr = virt_memmap[VIRT_FLASH].base;
1358 }
1359
1360 /*
1361 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
1362 * tree cannot be altered and we get FDT_ERR_NOSPACE.
1363 */
1364 s->fw_cfg = create_fw_cfg(machine);
1365 rom_set_fw(s->fw_cfg);
1366
1367 /* Compute the fdt load address in dram */
1368 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
1369 machine->ram_size, machine->fdt);
1370 /* load the reset vector */
1371 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
1372 virt_memmap[VIRT_MROM].base,
1373 virt_memmap[VIRT_MROM].size, kernel_entry,
1374 fdt_load_addr, machine->fdt);
1375
1376 /*
1377 * Only direct boot kernel is currently supported for KVM VM,
1378 * So here setup kernel start address and fdt address.
1379 * TODO:Support firmware loading and integrate to TCG start
1380 */
1381 if (kvm_enabled()) {
1382 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
1383 }
1384
1385 /* SiFive Test MMIO device */
1386 sifive_test_create(memmap[VIRT_TEST].base);
1387
1388 /* VirtIO MMIO devices */
1389 for (i = 0; i < VIRTIO_COUNT; i++) {
1390 sysbus_create_simple("virtio-mmio",
1391 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
1392 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i));
1393 }
1394
1395 gpex_pcie_init(system_memory,
1396 memmap[VIRT_PCIE_ECAM].base,
1397 memmap[VIRT_PCIE_ECAM].size,
1398 memmap[VIRT_PCIE_MMIO].base,
1399 memmap[VIRT_PCIE_MMIO].size,
1400 virt_high_pcie_memmap.base,
1401 virt_high_pcie_memmap.size,
1402 memmap[VIRT_PCIE_PIO].base,
1403 DEVICE(pcie_irqchip));
1404
1405 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
1406 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
1407 serial_hd(0), DEVICE_LITTLE_ENDIAN);
1408
1409 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
1410 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
1411
1412 virt_flash_create(s);
1413
1414 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
1415 /* Map legacy -drive if=pflash to machine properties */
1416 pflash_cfi01_legacy_drive(s->flash[i],
1417 drive_get(IF_PFLASH, 0, i));
1418 }
1419 virt_flash_map(s, system_memory);
1420 }
1421
1422 static void virt_machine_instance_init(Object *obj)
1423 {
1424 }
1425
1426 static char *virt_get_aia_guests(Object *obj, Error **errp)
1427 {
1428 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1429 char val[32];
1430
1431 sprintf(val, "%d", s->aia_guests);
1432 return g_strdup(val);
1433 }
1434
1435 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp)
1436 {
1437 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1438
1439 s->aia_guests = atoi(val);
1440 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) {
1441 error_setg(errp, "Invalid number of AIA IMSIC guests");
1442 error_append_hint(errp, "Valid values be between 0 and %d.\n",
1443 VIRT_IRQCHIP_MAX_GUESTS);
1444 }
1445 }
1446
1447 static char *virt_get_aia(Object *obj, Error **errp)
1448 {
1449 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1450 const char *val;
1451
1452 switch (s->aia_type) {
1453 case VIRT_AIA_TYPE_APLIC:
1454 val = "aplic";
1455 break;
1456 case VIRT_AIA_TYPE_APLIC_IMSIC:
1457 val = "aplic-imsic";
1458 break;
1459 default:
1460 val = "none";
1461 break;
1462 };
1463
1464 return g_strdup(val);
1465 }
1466
1467 static void virt_set_aia(Object *obj, const char *val, Error **errp)
1468 {
1469 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);
1470
1471 if (!strcmp(val, "none")) {
1472 s->aia_type = VIRT_AIA_TYPE_NONE;
1473 } else if (!strcmp(val, "aplic")) {
1474 s->aia_type = VIRT_AIA_TYPE_APLIC;
1475 } else if (!strcmp(val, "aplic-imsic")) {
1476 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC;
1477 } else {
1478 error_setg(errp, "Invalid AIA interrupt controller type");
1479 error_append_hint(errp, "Valid values are none, aplic, and "
1480 "aplic-imsic.\n");
1481 }
1482 }
1483
1484 static bool virt_get_aclint(Object *obj, Error **errp)
1485 {
1486 MachineState *ms = MACHINE(obj);
1487 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
1488
1489 return s->have_aclint;
1490 }
1491
1492 static void virt_set_aclint(Object *obj, bool value, Error **errp)
1493 {
1494 MachineState *ms = MACHINE(obj);
1495 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms);
1496
1497 s->have_aclint = value;
1498 }
1499
1500 static void virt_machine_class_init(ObjectClass *oc, void *data)
1501 {
1502 char str[128];
1503 MachineClass *mc = MACHINE_CLASS(oc);
1504
1505 mc->desc = "RISC-V VirtIO board";
1506 mc->init = virt_machine_init;
1507 mc->max_cpus = VIRT_CPUS_MAX;
1508 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
1509 mc->pci_allow_0_address = true;
1510 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
1511 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
1512 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
1513 mc->numa_mem_supported = true;
1514 mc->default_ram_id = "riscv_virt_board.ram";
1515
1516 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1517
1518 object_class_property_add_bool(oc, "aclint", virt_get_aclint,
1519 virt_set_aclint);
1520 object_class_property_set_description(oc, "aclint",
1521 "Set on/off to enable/disable "
1522 "emulating ACLINT devices");
1523
1524 object_class_property_add_str(oc, "aia", virt_get_aia,
1525 virt_set_aia);
1526 object_class_property_set_description(oc, "aia",
1527 "Set type of AIA interrupt "
1528 "conttoller. Valid values are "
1529 "none, aplic, and aplic-imsic.");
1530
1531 object_class_property_add_str(oc, "aia-guests",
1532 virt_get_aia_guests,
1533 virt_set_aia_guests);
1534 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value "
1535 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS);
1536 object_class_property_set_description(oc, "aia-guests", str);
1537 }
1538
1539 static const TypeInfo virt_machine_typeinfo = {
1540 .name = MACHINE_TYPE_NAME("virt"),
1541 .parent = TYPE_MACHINE,
1542 .class_init = virt_machine_class_init,
1543 .instance_init = virt_machine_instance_init,
1544 .instance_size = sizeof(RISCVVirtState),
1545 };
1546
1547 static void virt_machine_init_register_types(void)
1548 {
1549 type_register_static(&virt_machine_typeinfo);
1550 }
1551
1552 type_init(virt_machine_init_register_types)
AR7 emulation for QEMU