hw/bonito.c

   1 /*
   2  * bonito north bridge support
   3  *
   4  * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
   5  * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
   6  *
   7  * This code is licensed under the GNU GPL v2.
   8  */
   9
  10 /*
  11  * fulong 2e mini pc has a bonito north bridge.
  12  */
  13
  14 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
  15  *
  16  * devfn   pci_slot<<3  + funno
  17  * one pci bus can have 32 devices and each device can have 8 functions.
  18  *
  19  * In bonito north bridge, pci slot = IDSEL bit - 12.
  20  * For example, PCI_IDSEL_VIA686B = 17,
  21  * pci slot = 17-12=5
  22  *
  23  * so
  24  * VT686B_FUN0's devfn = (5<<3)+0
  25  * VT686B_FUN1's devfn = (5<<3)+1
  26  *
  27  * qemu also uses pci address for north bridge to access pci config register.
  28  * bus_no   [23:16]
  29  * dev_no   [15:11]
  30  * fun_no   [10:8]
  31  * reg_no   [7:2]
  32  *
  33  * so function bonito_sbridge_pciaddr for the translation from
  34  * north bridge address to pci address.
  35  */
  36
  37 #include <assert.h>
  38
  39 #include "hw.h"
  40 #include "pci.h"
  41 #include "pc.h"
  42 #include "mips.h"
  43 #include "pci_host.h"
  44 #include "sysemu.h"
  45 #include "exec-memory.h"
  46
  47 //#define DEBUG_BONITO
  48
  49 #ifdef DEBUG_BONITO
  50 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  51 #else
  52 #define DPRINTF(fmt, ...)
  53 #endif
  54
  55 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
  56 #define BONITO_BOOT_BASE        0x1fc00000
  57 #define BONITO_BOOT_SIZE        0x00100000
  58 #define BONITO_BOOT_TOP         (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
  59 #define BONITO_FLASH_BASE       0x1c000000
  60 #define BONITO_FLASH_SIZE       0x03000000
  61 #define BONITO_FLASH_TOP        (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
  62 #define BONITO_SOCKET_BASE      0x1f800000
  63 #define BONITO_SOCKET_SIZE      0x00400000
  64 #define BONITO_SOCKET_TOP       (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
  65 #define BONITO_REG_BASE         0x1fe00000
  66 #define BONITO_REG_SIZE         0x00040000
  67 #define BONITO_REG_TOP          (BONITO_REG_BASE+BONITO_REG_SIZE-1)
  68 #define BONITO_DEV_BASE         0x1ff00000
  69 #define BONITO_DEV_SIZE         0x00100000
  70 #define BONITO_DEV_TOP          (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
  71 #define BONITO_PCILO_BASE       0x10000000
  72 #define BONITO_PCILO_BASE_VA    0xb0000000
  73 #define BONITO_PCILO_SIZE       0x0c000000
  74 #define BONITO_PCILO_TOP        (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
  75 #define BONITO_PCILO0_BASE      0x10000000
  76 #define BONITO_PCILO1_BASE      0x14000000
  77 #define BONITO_PCILO2_BASE      0x18000000
  78 #define BONITO_PCIHI_BASE       0x20000000
  79 #define BONITO_PCIHI_SIZE       0x20000000
  80 #define BONITO_PCIHI_TOP        (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
  81 #define BONITO_PCIIO_BASE       0x1fd00000
  82 #define BONITO_PCIIO_BASE_VA    0xbfd00000
  83 #define BONITO_PCIIO_SIZE       0x00010000
  84 #define BONITO_PCIIO_TOP        (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
  85 #define BONITO_PCICFG_BASE      0x1fe80000
  86 #define BONITO_PCICFG_SIZE      0x00080000
  87 #define BONITO_PCICFG_TOP       (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
  88
  89
  90 #define BONITO_PCICONFIGBASE    0x00
  91 #define BONITO_REGBASE          0x100
  92
  93 #define BONITO_PCICONFIG_BASE   (BONITO_PCICONFIGBASE+BONITO_REG_BASE)
  94 #define BONITO_PCICONFIG_SIZE   (0x100)
  95
  96 #define BONITO_INTERNAL_REG_BASE  (BONITO_REGBASE+BONITO_REG_BASE)
  97 #define BONITO_INTERNAL_REG_SIZE  (0x70)
  98
  99 #define BONITO_SPCICONFIG_BASE  (BONITO_PCICFG_BASE)
 100 #define BONITO_SPCICONFIG_SIZE  (BONITO_PCICFG_SIZE)
 101
 102
 103
 104 /* 1. Bonito h/w Configuration */
 105 /* Power on register */
 106
 107 #define BONITO_BONPONCFG        (0x00 >> 2)      /* 0x100 */
 108 #define BONITO_BONGENCFG_OFFSET 0x4
 109 #define BONITO_BONGENCFG        (BONITO_BONGENCFG_OFFSET>>2)   /*0x104 */
 110
 111 /* 2. IO & IDE configuration */
 112 #define BONITO_IODEVCFG         (0x08 >> 2)      /* 0x108 */
 113
 114 /* 3. IO & IDE configuration */
 115 #define BONITO_SDCFG            (0x0c >> 2)      /* 0x10c */
 116
 117 /* 4. PCI address map control */
 118 #define BONITO_PCIMAP           (0x10 >> 2)      /* 0x110 */
 119 #define BONITO_PCIMEMBASECFG    (0x14 >> 2)      /* 0x114 */
 120 #define BONITO_PCIMAP_CFG       (0x18 >> 2)      /* 0x118 */
 121
 122 /* 5. ICU & GPIO regs */
 123 /* GPIO Regs - r/w */
 124 #define BONITO_GPIODATA_OFFSET  0x1c
 125 #define BONITO_GPIODATA         (BONITO_GPIODATA_OFFSET >> 2)   /* 0x11c */
 126 #define BONITO_GPIOIE           (0x20 >> 2)      /* 0x120 */
 127
 128 /* ICU Configuration Regs - r/w */
 129 #define BONITO_INTEDGE          (0x24 >> 2)      /* 0x124 */
 130 #define BONITO_INTSTEER         (0x28 >> 2)      /* 0x128 */
 131 #define BONITO_INTPOL           (0x2c >> 2)      /* 0x12c */
 132
 133 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 134 #define BONITO_INTENSET         (0x30 >> 2)      /* 0x130 */
 135 #define BONITO_INTENCLR         (0x34 >> 2)      /* 0x134 */
 136 #define BONITO_INTEN            (0x38 >> 2)      /* 0x138 */
 137 #define BONITO_INTISR           (0x3c >> 2)      /* 0x13c */
 138
 139 /* PCI mail boxes */
 140 #define BONITO_PCIMAIL0_OFFSET    0x40
 141 #define BONITO_PCIMAIL1_OFFSET    0x44
 142 #define BONITO_PCIMAIL2_OFFSET    0x48
 143 #define BONITO_PCIMAIL3_OFFSET    0x4c
 144 #define BONITO_PCIMAIL0         (0x40 >> 2)      /* 0x140 */
 145 #define BONITO_PCIMAIL1         (0x44 >> 2)      /* 0x144 */
 146 #define BONITO_PCIMAIL2         (0x48 >> 2)      /* 0x148 */
 147 #define BONITO_PCIMAIL3         (0x4c >> 2)      /* 0x14c */
 148
 149 /* 6. PCI cache */
 150 #define BONITO_PCICACHECTRL     (0x50 >> 2)      /* 0x150 */
 151 #define BONITO_PCICACHETAG      (0x54 >> 2)      /* 0x154 */
 152 #define BONITO_PCIBADADDR       (0x58 >> 2)      /* 0x158 */
 153 #define BONITO_PCIMSTAT         (0x5c >> 2)      /* 0x15c */
 154
 155 /* 7. other*/
 156 #define BONITO_TIMECFG          (0x60 >> 2)      /* 0x160 */
 157 #define BONITO_CPUCFG           (0x64 >> 2)      /* 0x164 */
 158 #define BONITO_DQCFG            (0x68 >> 2)      /* 0x168 */
 159 #define BONITO_MEMSIZE          (0x6C >> 2)      /* 0x16c */
 160
 161 #define BONITO_REGS             (0x70 >> 2)
 162
 163 /* PCI config for south bridge. type 0 */
 164 #define BONITO_PCICONF_IDSEL_MASK      0xfffff800     /* [31:11] */
 165 #define BONITO_PCICONF_IDSEL_OFFSET    11
 166 #define BONITO_PCICONF_FUN_MASK        0x700    /* [10:8] */
 167 #define BONITO_PCICONF_FUN_OFFSET      8
 168 #define BONITO_PCICONF_REG_MASK        0xFC
 169 #define BONITO_PCICONF_REG_OFFSET      0
 170
 171
 172 /* idsel BIT = pci slot number +12 */
 173 #define PCI_SLOT_BASE              12
 174 #define PCI_IDSEL_VIA686B_BIT      (17)
 175 #define PCI_IDSEL_VIA686B          (1<<PCI_IDSEL_VIA686B_BIT)
 176
 177 #define PCI_ADDR(busno,devno,funno,regno)  \
 178     ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
 179
 180 typedef PCIHostState BonitoState;
 181
 182 typedef struct PCIBonitoState
 183 {
 184     PCIDevice dev;
 185     BonitoState *pcihost;
 186     uint32_t regs[BONITO_REGS];
 187
 188     struct bonldma {
 189         uint32_t ldmactrl;
 190         uint32_t ldmastat;
 191         uint32_t ldmaaddr;
 192         uint32_t ldmago;
 193     } bonldma;
 194
 195     /* Based at 1fe00300, bonito Copier */
 196     struct boncop {
 197         uint32_t copctrl;
 198         uint32_t copstat;
 199         uint32_t coppaddr;
 200         uint32_t copgo;
 201     } boncop;
 202
 203     /* Bonito registers */
 204     target_phys_addr_t bonito_reg_start;
 205     target_phys_addr_t bonito_reg_length;
 206     int bonito_reg_handle;
 207
 208     target_phys_addr_t bonito_pciconf_start;
 209     target_phys_addr_t bonito_pciconf_length;
 210     int bonito_pciconf_handle;
 211
 212     target_phys_addr_t bonito_spciconf_start;
 213     target_phys_addr_t bonito_spciconf_length;
 214     int bonito_spciconf_handle;
 215
 216     target_phys_addr_t bonito_pciio_start;
 217     target_phys_addr_t bonito_pciio_length;
 218     int bonito_pciio_handle;
 219
 220     target_phys_addr_t bonito_localio_start;
 221     target_phys_addr_t bonito_localio_length;
 222     int bonito_localio_handle;
 223
 224     target_phys_addr_t bonito_ldma_start;
 225     target_phys_addr_t bonito_ldma_length;
 226     int bonito_ldma_handle;
 227
 228     target_phys_addr_t bonito_cop_start;
 229     target_phys_addr_t bonito_cop_length;
 230     int bonito_cop_handle;
 231
 232 } PCIBonitoState;
 233
 234 PCIBonitoState * bonito_state;
 235
 236 static void bonito_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 237 {
 238     PCIBonitoState *s = opaque;
 239     uint32_t saddr;
 240     int reset = 0;
 241
 242     saddr = (addr - BONITO_REGBASE) >> 2;
 243
 244     DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
 245     switch (saddr) {
 246     case BONITO_BONPONCFG:
 247     case BONITO_IODEVCFG:
 248     case BONITO_SDCFG:
 249     case BONITO_PCIMAP:
 250     case BONITO_PCIMEMBASECFG:
 251     case BONITO_PCIMAP_CFG:
 252     case BONITO_GPIODATA:
 253     case BONITO_GPIOIE:
 254     case BONITO_INTEDGE:
 255     case BONITO_INTSTEER:
 256     case BONITO_INTPOL:
 257     case BONITO_PCIMAIL0:
 258     case BONITO_PCIMAIL1:
 259     case BONITO_PCIMAIL2:
 260     case BONITO_PCIMAIL3:
 261     case BONITO_PCICACHECTRL:
 262     case BONITO_PCICACHETAG:
 263     case BONITO_PCIBADADDR:
 264     case BONITO_PCIMSTAT:
 265     case BONITO_TIMECFG:
 266     case BONITO_CPUCFG:
 267     case BONITO_DQCFG:
 268     case BONITO_MEMSIZE:
 269         s->regs[saddr] = val;
 270         break;
 271     case BONITO_BONGENCFG:
 272         if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
 273             reset = 1; /* bit 2 jump from 0 to 1 cause reset */
 274         }
 275         s->regs[saddr] = val;
 276         if (reset) {
 277             qemu_system_reset_request();
 278         }
 279         break;
 280     case BONITO_INTENSET:
 281         s->regs[BONITO_INTENSET] = val;
 282         s->regs[BONITO_INTEN] |= val;
 283         break;
 284     case BONITO_INTENCLR:
 285         s->regs[BONITO_INTENCLR] = val;
 286         s->regs[BONITO_INTEN] &= ~val;
 287         break;
 288     case BONITO_INTEN:
 289     case BONITO_INTISR:
 290         DPRINTF("write to readonly bonito register %x\n", saddr);
 291         break;
 292     default:
 293         DPRINTF("write to unknown bonito register %x\n", saddr);
 294         break;
 295     }
 296 }
 297
 298 static uint32_t bonito_readl(void *opaque, target_phys_addr_t addr)
 299 {
 300     PCIBonitoState *s = opaque;
 301     uint32_t saddr;
 302
 303     saddr = (addr - BONITO_REGBASE) >> 2;
 304
 305     DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
 306     switch (saddr) {
 307     case BONITO_INTISR:
 308         return s->regs[saddr];
 309     default:
 310         return s->regs[saddr];
 311     }
 312 }
 313
 314 static CPUWriteMemoryFunc * const bonito_write[] = {
 315     NULL,
 316     NULL,
 317     bonito_writel,
 318 };
 319
 320 static CPUReadMemoryFunc * const bonito_read[] = {
 321     NULL,
 322     NULL,
 323     bonito_readl,
 324 };
 325
 326 static void bonito_pciconf_writel(void *opaque, target_phys_addr_t addr,
 327                                   uint32_t val)
 328 {
 329     PCIBonitoState *s = opaque;
 330
 331     DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
 332     s->dev.config_write(&s->dev, addr, val, 4);
 333 }
 334
 335 static uint32_t bonito_pciconf_readl(void *opaque, target_phys_addr_t addr)
 336 {
 337
 338     PCIBonitoState *s = opaque;
 339
 340     DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
 341     return s->dev.config_read(&s->dev, addr, 4);
 342 }
 343
 344 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
 345 static CPUWriteMemoryFunc * const bonito_pciconf_write[] = {
 346     NULL,
 347     NULL,
 348     bonito_pciconf_writel,
 349 };
 350
 351 static CPUReadMemoryFunc * const bonito_pciconf_read[] = {
 352     NULL,
 353     NULL,
 354     bonito_pciconf_readl,
 355 };
 356
 357 static uint32_t bonito_ldma_readl(void *opaque, target_phys_addr_t addr)
 358 {
 359     uint32_t val;
 360     PCIBonitoState *s = opaque;
 361
 362     val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)];
 363
 364     return val;
 365 }
 366
 367 static void bonito_ldma_writel(void *opaque, target_phys_addr_t addr,
 368                                uint32_t val)
 369 {
 370     PCIBonitoState *s = opaque;
 371
 372     ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff;
 373 }
 374
 375 static CPUWriteMemoryFunc * const bonito_ldma_write[] = {
 376     NULL,
 377     NULL,
 378     bonito_ldma_writel,
 379 };
 380
 381 static CPUReadMemoryFunc * const bonito_ldma_read[] = {
 382     NULL,
 383     NULL,
 384     bonito_ldma_readl,
 385 };
 386
 387 static uint32_t bonito_cop_readl(void *opaque, target_phys_addr_t addr)
 388 {
 389     uint32_t val;
 390     PCIBonitoState *s = opaque;
 391
 392     val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)];
 393
 394     return val;
 395 }
 396
 397 static void bonito_cop_writel(void *opaque, target_phys_addr_t addr,
 398                               uint32_t val)
 399 {
 400     PCIBonitoState *s = opaque;
 401
 402     ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff;
 403 }
 404
 405 static CPUWriteMemoryFunc * const bonito_cop_write[] = {
 406     NULL,
 407     NULL,
 408     bonito_cop_writel,
 409 };
 410
 411 static CPUReadMemoryFunc * const bonito_cop_read[] = {
 412     NULL,
 413     NULL,
 414     bonito_cop_readl,
 415 };
 416
 417 static uint32_t bonito_sbridge_pciaddr(void *opaque, target_phys_addr_t addr)
 418 {
 419     PCIBonitoState *s = opaque;
 420     uint32_t cfgaddr;
 421     uint32_t idsel;
 422     uint32_t devno;
 423     uint32_t funno;
 424     uint32_t regno;
 425     uint32_t pciaddr;
 426
 427     /* support type0 pci config */
 428     if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
 429         return 0xffffffff;
 430     }
 431
 432     cfgaddr = addr & 0xffff;
 433     cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
 434
 435     idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
 436     devno = ffs(idsel) - 1;
 437     funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
 438     regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
 439
 440     if (idsel == 0) {
 441         fprintf(stderr, "error in bonito pci config address" TARGET_FMT_plx
 442             ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]);
 443         exit(1);
 444     }
 445     pciaddr = PCI_ADDR(pci_bus_num(s->pcihost->bus), devno, funno, regno);
 446     DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
 447         cfgaddr, pciaddr, pci_bus_num(s->pcihost->bus), devno, funno, regno);
 448
 449     return pciaddr;
 450 }
 451
 452 static void bonito_spciconf_writeb(void *opaque, target_phys_addr_t addr,
 453                                    uint32_t val)
 454 {
 455     PCIBonitoState *s = opaque;
 456     uint32_t pciaddr;
 457     uint16_t status;
 458
 459     DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val);
 460     pciaddr = bonito_sbridge_pciaddr(s, addr);
 461
 462     if (pciaddr == 0xffffffff) {
 463         return;
 464     }
 465
 466     /* set the pci address in s->config_reg */
 467     s->pcihost->config_reg = (pciaddr) | (1u << 31);
 468     pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val & 0xff, 1);
 469
 470     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 471     status = pci_get_word(s->dev.config + PCI_STATUS);
 472     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 473     pci_set_word(s->dev.config + PCI_STATUS, status);
 474 }
 475
 476 static void bonito_spciconf_writew(void *opaque, target_phys_addr_t addr,
 477                                    uint32_t val)
 478 {
 479     PCIBonitoState *s = opaque;
 480     uint32_t pciaddr;
 481     uint16_t status;
 482
 483     DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val);
 484     assert((addr&0x1)==0);
 485
 486     pciaddr = bonito_sbridge_pciaddr(s, addr);
 487
 488     if (pciaddr == 0xffffffff) {
 489         return;
 490     }
 491
 492     /* set the pci address in s->config_reg */
 493     s->pcihost->config_reg = (pciaddr) | (1u << 31);
 494     pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 2);
 495
 496     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 497     status = pci_get_word(s->dev.config + PCI_STATUS);
 498     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 499     pci_set_word(s->dev.config + PCI_STATUS, status);
 500 }
 501
 502 static void bonito_spciconf_writel(void *opaque, target_phys_addr_t addr,
 503                                    uint32_t val)
 504 {
 505     PCIBonitoState *s = opaque;
 506     uint32_t pciaddr;
 507     uint16_t status;
 508
 509     DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
 510     assert((addr&0x3)==0);
 511
 512     pciaddr = bonito_sbridge_pciaddr(s, addr);
 513
 514     if (pciaddr == 0xffffffff) {
 515         return;
 516     }
 517
 518     /* set the pci address in s->config_reg */
 519     s->pcihost->config_reg = (pciaddr) | (1u << 31);
 520     pci_data_write(s->pcihost->bus, s->pcihost->config_reg, val, 4);
 521
 522     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 523     status = pci_get_word(s->dev.config + PCI_STATUS);
 524     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 525     pci_set_word(s->dev.config + PCI_STATUS, status);
 526 }
 527
 528 static uint32_t bonito_spciconf_readb(void *opaque, target_phys_addr_t addr)
 529 {
 530     PCIBonitoState *s = opaque;
 531     uint32_t pciaddr;
 532     uint16_t status;
 533
 534     DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr);
 535     pciaddr = bonito_sbridge_pciaddr(s, addr);
 536
 537     if (pciaddr == 0xffffffff) {
 538         return 0xff;
 539     }
 540
 541     /* set the pci address in s->config_reg */
 542     s->pcihost->config_reg = (pciaddr) | (1u << 31);
 543
 544     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 545     status = pci_get_word(s->dev.config + PCI_STATUS);
 546     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 547     pci_set_word(s->dev.config + PCI_STATUS, status);
 548
 549     return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 1);
 550 }
 551
 552 static uint32_t bonito_spciconf_readw(void *opaque, target_phys_addr_t addr)
 553 {
 554     PCIBonitoState *s = opaque;
 555     uint32_t pciaddr;
 556     uint16_t status;
 557
 558     DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr);
 559     assert((addr&0x1)==0);
 560
 561     pciaddr = bonito_sbridge_pciaddr(s, addr);
 562
 563     if (pciaddr == 0xffffffff) {
 564         return 0xffff;
 565     }
 566
 567     /* set the pci address in s->config_reg */
 568     s->pcihost->config_reg = (pciaddr) | (1u << 31);
 569
 570     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 571     status = pci_get_word(s->dev.config + PCI_STATUS);
 572     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 573     pci_set_word(s->dev.config + PCI_STATUS, status);
 574
 575     return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 2);
 576 }
 577
 578 static uint32_t bonito_spciconf_readl(void *opaque, target_phys_addr_t addr)
 579 {
 580     PCIBonitoState *s = opaque;
 581     uint32_t pciaddr;
 582     uint16_t status;
 583
 584     DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr);
 585     assert((addr&0x3) == 0);
 586
 587     pciaddr = bonito_sbridge_pciaddr(s, addr);
 588
 589     if (pciaddr == 0xffffffff) {
 590         return 0xffffffff;
 591     }
 592
 593     /* set the pci address in s->config_reg */
 594     s->pcihost->config_reg = (pciaddr) | (1u << 31);
 595
 596     /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
 597     status = pci_get_word(s->dev.config + PCI_STATUS);
 598     status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
 599     pci_set_word(s->dev.config + PCI_STATUS, status);
 600
 601     return pci_data_read(s->pcihost->bus, s->pcihost->config_reg, 4);
 602 }
 603
 604 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
 605 static CPUWriteMemoryFunc * const bonito_spciconf_write[] = {
 606     bonito_spciconf_writeb,
 607     bonito_spciconf_writew,
 608     bonito_spciconf_writel,
 609 };
 610
 611 static CPUReadMemoryFunc * const bonito_spciconf_read[] = {
 612     bonito_spciconf_readb,
 613     bonito_spciconf_readw,
 614     bonito_spciconf_readl,
 615 };
 616
 617 #define BONITO_IRQ_BASE 32
 618
 619 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
 620 {
 621     qemu_irq *pic = opaque;
 622     int internal_irq = irq_num - BONITO_IRQ_BASE;
 623
 624     if (bonito_state->regs[BONITO_INTEDGE] & (1<<internal_irq)) {
 625         qemu_irq_pulse(*pic);
 626     } else {   /* level triggered */
 627         if (bonito_state->regs[BONITO_INTPOL] & (1<<internal_irq)) {
 628             qemu_irq_raise(*pic);
 629         } else {
 630             qemu_irq_lower(*pic);
 631         }
 632     }
 633 }
 634
 635 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
 636 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
 637 {
 638     int slot;
 639
 640     slot = (pci_dev->devfn >> 3);
 641
 642     switch (slot) {
 643     case 5:   /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
 644         return irq_num % 4 + BONITO_IRQ_BASE;
 645     case 6:   /* FULONG2E_ATI_SLOT, VGA */
 646         return 4 + BONITO_IRQ_BASE;
 647     case 7:   /* FULONG2E_RTL_SLOT, RTL8139 */
 648         return 5 + BONITO_IRQ_BASE;
 649     case 8 ... 12: /* PCI slot 1 to 4 */
 650         return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
 651     default:  /* Unknown device, don't do any translation */
 652         return irq_num;
 653     }
 654 }
 655
 656 static void bonito_reset(void *opaque)
 657 {
 658     PCIBonitoState *s = opaque;
 659
 660     /* set the default value of north bridge registers */
 661
 662     s->regs[BONITO_BONPONCFG] = 0xc40;
 663     s->regs[BONITO_BONGENCFG] = 0x1384;
 664     s->regs[BONITO_IODEVCFG] = 0x2bff8010;
 665     s->regs[BONITO_SDCFG] = 0x255e0091;
 666
 667     s->regs[BONITO_GPIODATA] = 0x1ff;
 668     s->regs[BONITO_GPIOIE] = 0x1ff;
 669     s->regs[BONITO_DQCFG] = 0x8;
 670     s->regs[BONITO_MEMSIZE] = 0x10000000;
 671     s->regs[BONITO_PCIMAP] = 0x6140;
 672 }
 673
 674 static const VMStateDescription vmstate_bonito = {
 675     .name = "Bonito",
 676     .version_id = 1,
 677     .minimum_version_id = 1,
 678     .minimum_version_id_old = 1,
 679     .fields      = (VMStateField []) {
 680         VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
 681         VMSTATE_END_OF_LIST()
 682     }
 683 };
 684
 685 static int bonito_pcihost_initfn(SysBusDevice *dev)
 686 {
 687     return 0;
 688 }
 689
 690 static int bonito_initfn(PCIDevice *dev)
 691 {
 692     PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev);
 693
 694     /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
 695     pci_config_set_prog_interface(dev->config, 0x00);
 696
 697     /* set the north bridge register mapping */
 698     s->bonito_reg_handle = cpu_register_io_memory(bonito_read, bonito_write, s,
 699                                                   DEVICE_NATIVE_ENDIAN);
 700     s->bonito_reg_start = BONITO_INTERNAL_REG_BASE;
 701     s->bonito_reg_length = BONITO_INTERNAL_REG_SIZE;
 702     cpu_register_physical_memory(s->bonito_reg_start, s->bonito_reg_length,
 703                                  s->bonito_reg_handle);
 704
 705     /* set the north bridge pci configure  mapping */
 706     s->bonito_pciconf_handle = cpu_register_io_memory(bonito_pciconf_read,
 707                                                       bonito_pciconf_write, s,
 708                                                       DEVICE_NATIVE_ENDIAN);
 709     s->bonito_pciconf_start = BONITO_PCICONFIG_BASE;
 710     s->bonito_pciconf_length = BONITO_PCICONFIG_SIZE;
 711     cpu_register_physical_memory(s->bonito_pciconf_start, s->bonito_pciconf_length,
 712                                  s->bonito_pciconf_handle);
 713
 714     /* set the south bridge pci configure  mapping */
 715     s->bonito_spciconf_handle = cpu_register_io_memory(bonito_spciconf_read,
 716                                                        bonito_spciconf_write, s,
 717                                                        DEVICE_NATIVE_ENDIAN);
 718     s->bonito_spciconf_start = BONITO_SPCICONFIG_BASE;
 719     s->bonito_spciconf_length = BONITO_SPCICONFIG_SIZE;
 720     cpu_register_physical_memory(s->bonito_spciconf_start, s->bonito_spciconf_length,
 721                                  s->bonito_spciconf_handle);
 722
 723     s->bonito_ldma_handle = cpu_register_io_memory(bonito_ldma_read,
 724                                                    bonito_ldma_write, s,
 725                                                    DEVICE_NATIVE_ENDIAN);
 726     s->bonito_ldma_start = 0xbfe00200;
 727     s->bonito_ldma_length = 0x100;
 728     cpu_register_physical_memory(s->bonito_ldma_start, s->bonito_ldma_length,
 729                                  s->bonito_ldma_handle);
 730
 731     s->bonito_cop_handle = cpu_register_io_memory(bonito_cop_read,
 732                                                   bonito_cop_write, s,
 733                                                   DEVICE_NATIVE_ENDIAN);
 734     s->bonito_cop_start = 0xbfe00300;
 735     s->bonito_cop_length = 0x100;
 736     cpu_register_physical_memory(s->bonito_cop_start, s->bonito_cop_length,
 737                                  s->bonito_cop_handle);
 738
 739     /* Map PCI IO Space  0x1fd0 0000 - 0x1fd1 0000 */
 740     s->bonito_pciio_start = BONITO_PCIIO_BASE;
 741     s->bonito_pciio_length = BONITO_PCIIO_SIZE;
 742     isa_mem_base = s->bonito_pciio_start;
 743     isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length);
 744
 745     /* add pci local io mapping */
 746     s->bonito_localio_start = BONITO_DEV_BASE;
 747     s->bonito_localio_length = BONITO_DEV_SIZE;
 748     isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length);
 749
 750     /* set the default value of north bridge pci config */
 751     pci_set_word(dev->config + PCI_COMMAND, 0x0000);
 752     pci_set_word(dev->config + PCI_STATUS, 0x0000);
 753     pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
 754     pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
 755
 756     pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
 757     pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
 758     pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
 759     pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
 760
 761     qemu_register_reset(bonito_reset, s);
 762
 763     return 0;
 764 }
 765
 766 PCIBus *bonito_init(qemu_irq *pic)
 767 {
 768     DeviceState *dev;
 769     PCIBus *b;
 770     BonitoState *pcihost;
 771     PCIBonitoState *s;
 772     PCIDevice *d;
 773
 774     dev = qdev_create(NULL, "Bonito-pcihost");
 775     pcihost = FROM_SYSBUS(BonitoState, sysbus_from_qdev(dev));
 776     b = pci_register_bus(&pcihost->busdev.qdev, "pci", pci_bonito_set_irq,
 777                          pci_bonito_map_irq, pic, get_system_memory(),
 778                          get_system_io(),
 779                          0x28, 32);
 780     pcihost->bus = b;
 781     qdev_init_nofail(dev);
 782
 783     d = pci_create_simple(b, PCI_DEVFN(0, 0), "Bonito");
 784     s = DO_UPCAST(PCIBonitoState, dev, d);
 785     s->pcihost = pcihost;
 786     bonito_state = s;
 787
 788     return b;
 789 }
 790
 791 static PCIDeviceInfo bonito_info = {
 792     .qdev.name    = "Bonito",
 793     .qdev.desc    = "Host bridge",
 794     .qdev.size    = sizeof(PCIBonitoState),
 795     .qdev.vmsd    = &vmstate_bonito,
 796     .qdev.no_user = 1,
 797     .init         = bonito_initfn,
 798     /*Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined"*/
 799     .vendor_id    = 0xdf53,
 800     .device_id    = 0x00d5,
 801     .revision     = 0x01,
 802     .class_id     = PCI_CLASS_BRIDGE_HOST,
 803 };
 804
 805 static SysBusDeviceInfo bonito_pcihost_info = {
 806     .init         = bonito_pcihost_initfn,
 807     .qdev.name    = "Bonito-pcihost",
 808     .qdev.size    = sizeof(BonitoState),
 809     .qdev.no_user = 1,
 810 };
 811
 812 static void bonito_register(void)
 813 {
 814     sysbus_register_withprop(&bonito_pcihost_info);
 815     pci_qdev_register(&bonito_info);
 816 }
 817 device_init(bonito_register);