spapr: Abort if XICS interrupt controller cannot be initialized
[qemu/ar7.git] / hw / core / cpu.c
blobdb1a03c6bbb3fc027cb17c991aa51dbe1489f04c
1 /*
2 * QEMU CPU model
4 * Copyright (c) 2012-2014 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "hw/core/cpu.h"
24 #include "sysemu/hw_accel.h"
25 #include "qemu/notify.h"
26 #include "qemu/log.h"
27 #include "qemu/main-loop.h"
28 #include "exec/log.h"
29 #include "qemu/error-report.h"
30 #include "qemu/qemu-print.h"
31 #include "sysemu/tcg.h"
32 #include "hw/boards.h"
33 #include "hw/qdev-properties.h"
34 #include "trace-root.h"
35 #include "qemu/plugin.h"
37 CPUInterruptHandler cpu_interrupt_handler;
39 CPUState *cpu_by_arch_id(int64_t id)
41 CPUState *cpu;
43 CPU_FOREACH(cpu) {
44 CPUClass *cc = CPU_GET_CLASS(cpu);
46 if (cc->get_arch_id(cpu) == id) {
47 return cpu;
50 return NULL;
53 bool cpu_exists(int64_t id)
55 return !!cpu_by_arch_id(id);
58 CPUState *cpu_create(const char *typename)
60 Error *err = NULL;
61 CPUState *cpu = CPU(object_new(typename));
62 object_property_set_bool(OBJECT(cpu), true, "realized", &err);
63 if (err != NULL) {
64 error_report_err(err);
65 object_unref(OBJECT(cpu));
66 exit(EXIT_FAILURE);
68 return cpu;
71 bool cpu_paging_enabled(const CPUState *cpu)
73 CPUClass *cc = CPU_GET_CLASS(cpu);
75 return cc->get_paging_enabled(cpu);
78 static bool cpu_common_get_paging_enabled(const CPUState *cpu)
80 return false;
83 void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
84 Error **errp)
86 CPUClass *cc = CPU_GET_CLASS(cpu);
88 cc->get_memory_mapping(cpu, list, errp);
91 static void cpu_common_get_memory_mapping(CPUState *cpu,
92 MemoryMappingList *list,
93 Error **errp)
95 error_setg(errp, "Obtaining memory mappings is unsupported on this CPU.");
98 /* Resetting the IRQ comes from across the code base so we take the
99 * BQL here if we need to. cpu_interrupt assumes it is held.*/
100 void cpu_reset_interrupt(CPUState *cpu, int mask)
102 bool need_lock = !qemu_mutex_iothread_locked();
104 if (need_lock) {
105 qemu_mutex_lock_iothread();
107 cpu->interrupt_request &= ~mask;
108 if (need_lock) {
109 qemu_mutex_unlock_iothread();
113 void cpu_exit(CPUState *cpu)
115 atomic_set(&cpu->exit_request, 1);
116 /* Ensure cpu_exec will see the exit request after TCG has exited. */
117 smp_wmb();
118 atomic_set(&cpu->icount_decr_ptr->u16.high, -1);
121 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
122 void *opaque)
124 CPUClass *cc = CPU_GET_CLASS(cpu);
126 return (*cc->write_elf32_qemunote)(f, cpu, opaque);
129 static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f,
130 CPUState *cpu, void *opaque)
132 return 0;
135 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
136 int cpuid, void *opaque)
138 CPUClass *cc = CPU_GET_CLASS(cpu);
140 return (*cc->write_elf32_note)(f, cpu, cpuid, opaque);
143 static int cpu_common_write_elf32_note(WriteCoreDumpFunction f,
144 CPUState *cpu, int cpuid,
145 void *opaque)
147 return -1;
150 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
151 void *opaque)
153 CPUClass *cc = CPU_GET_CLASS(cpu);
155 return (*cc->write_elf64_qemunote)(f, cpu, opaque);
158 static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f,
159 CPUState *cpu, void *opaque)
161 return 0;
164 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
165 int cpuid, void *opaque)
167 CPUClass *cc = CPU_GET_CLASS(cpu);
169 return (*cc->write_elf64_note)(f, cpu, cpuid, opaque);
172 static int cpu_common_write_elf64_note(WriteCoreDumpFunction f,
173 CPUState *cpu, int cpuid,
174 void *opaque)
176 return -1;
180 static int cpu_common_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg)
182 return 0;
185 static int cpu_common_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg)
187 return 0;
190 static bool cpu_common_debug_check_watchpoint(CPUState *cpu, CPUWatchpoint *wp)
192 /* If no extra check is required, QEMU watchpoint match can be considered
193 * as an architectural match.
195 return true;
198 static bool cpu_common_virtio_is_big_endian(CPUState *cpu)
200 return target_words_bigendian();
203 static void cpu_common_noop(CPUState *cpu)
207 static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req)
209 return false;
212 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
214 CPUClass *cc = CPU_GET_CLASS(cpu);
215 GuestPanicInformation *res = NULL;
217 if (cc->get_crash_info) {
218 res = cc->get_crash_info(cpu);
220 return res;
223 void cpu_dump_state(CPUState *cpu, FILE *f, int flags)
225 CPUClass *cc = CPU_GET_CLASS(cpu);
227 if (cc->dump_state) {
228 cpu_synchronize_state(cpu);
229 cc->dump_state(cpu, f, flags);
233 void cpu_dump_statistics(CPUState *cpu, int flags)
235 CPUClass *cc = CPU_GET_CLASS(cpu);
237 if (cc->dump_statistics) {
238 cc->dump_statistics(cpu, flags);
242 void cpu_reset(CPUState *cpu)
244 CPUClass *klass = CPU_GET_CLASS(cpu);
246 if (klass->reset != NULL) {
247 (*klass->reset)(cpu);
250 trace_guest_cpu_reset(cpu);
253 static void cpu_common_reset(CPUState *cpu)
255 CPUClass *cc = CPU_GET_CLASS(cpu);
257 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
258 qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
259 log_cpu_state(cpu, cc->reset_dump_flags);
262 cpu->interrupt_request = 0;
263 cpu->halted = 0;
264 cpu->mem_io_pc = 0;
265 cpu->icount_extra = 0;
266 atomic_set(&cpu->icount_decr_ptr->u32, 0);
267 cpu->can_do_io = 1;
268 cpu->exception_index = -1;
269 cpu->crash_occurred = false;
270 cpu->cflags_next_tb = -1;
272 if (tcg_enabled()) {
273 cpu_tb_jmp_cache_clear(cpu);
275 tcg_flush_softmmu_tlb(cpu);
279 static bool cpu_common_has_work(CPUState *cs)
281 return false;
284 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
286 CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
288 assert(cpu_model && cc->class_by_name);
289 return cc->class_by_name(cpu_model);
292 static void cpu_common_parse_features(const char *typename, char *features,
293 Error **errp)
295 char *val;
296 static bool cpu_globals_initialized;
297 /* Single "key=value" string being parsed */
298 char *featurestr = features ? strtok(features, ",") : NULL;
300 /* should be called only once, catch invalid users */
301 assert(!cpu_globals_initialized);
302 cpu_globals_initialized = true;
304 while (featurestr) {
305 val = strchr(featurestr, '=');
306 if (val) {
307 GlobalProperty *prop = g_new0(typeof(*prop), 1);
308 *val = 0;
309 val++;
310 prop->driver = typename;
311 prop->property = g_strdup(featurestr);
312 prop->value = g_strdup(val);
313 qdev_prop_register_global(prop);
314 } else {
315 error_setg(errp, "Expected key=value format, found %s.",
316 featurestr);
317 return;
319 featurestr = strtok(NULL, ",");
323 static void cpu_common_realizefn(DeviceState *dev, Error **errp)
325 CPUState *cpu = CPU(dev);
326 Object *machine = qdev_get_machine();
328 /* qdev_get_machine() can return something that's not TYPE_MACHINE
329 * if this is one of the user-only emulators; in that case there's
330 * no need to check the ignore_memory_transaction_failures board flag.
332 if (object_dynamic_cast(machine, TYPE_MACHINE)) {
333 ObjectClass *oc = object_get_class(machine);
334 MachineClass *mc = MACHINE_CLASS(oc);
336 if (mc) {
337 cpu->ignore_memory_transaction_failures =
338 mc->ignore_memory_transaction_failures;
342 if (dev->hotplugged) {
343 cpu_synchronize_post_init(cpu);
344 cpu_resume(cpu);
347 /* NOTE: latest generic point where the cpu is fully realized */
348 trace_init_vcpu(cpu);
351 static void cpu_common_unrealizefn(DeviceState *dev, Error **errp)
353 CPUState *cpu = CPU(dev);
354 /* NOTE: latest generic point before the cpu is fully unrealized */
355 trace_fini_vcpu(cpu);
356 qemu_plugin_vcpu_exit_hook(cpu);
357 cpu_exec_unrealizefn(cpu);
360 static void cpu_common_initfn(Object *obj)
362 CPUState *cpu = CPU(obj);
363 CPUClass *cc = CPU_GET_CLASS(obj);
365 cpu->cpu_index = UNASSIGNED_CPU_INDEX;
366 cpu->cluster_index = UNASSIGNED_CLUSTER_INDEX;
367 cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;
368 /* *-user doesn't have configurable SMP topology */
369 /* the default value is changed by qemu_init_vcpu() for softmmu */
370 cpu->nr_cores = 1;
371 cpu->nr_threads = 1;
373 qemu_mutex_init(&cpu->work_mutex);
374 QTAILQ_INIT(&cpu->breakpoints);
375 QTAILQ_INIT(&cpu->watchpoints);
377 cpu_exec_initfn(cpu);
380 static void cpu_common_finalize(Object *obj)
382 CPUState *cpu = CPU(obj);
384 qemu_mutex_destroy(&cpu->work_mutex);
387 static int64_t cpu_common_get_arch_id(CPUState *cpu)
389 return cpu->cpu_index;
392 static vaddr cpu_adjust_watchpoint_address(CPUState *cpu, vaddr addr, int len)
394 return addr;
397 static void generic_handle_interrupt(CPUState *cpu, int mask)
399 cpu->interrupt_request |= mask;
401 if (!qemu_cpu_is_self(cpu)) {
402 qemu_cpu_kick(cpu);
406 CPUInterruptHandler cpu_interrupt_handler = generic_handle_interrupt;
408 static void cpu_class_init(ObjectClass *klass, void *data)
410 DeviceClass *dc = DEVICE_CLASS(klass);
411 CPUClass *k = CPU_CLASS(klass);
413 k->parse_features = cpu_common_parse_features;
414 k->reset = cpu_common_reset;
415 k->get_arch_id = cpu_common_get_arch_id;
416 k->has_work = cpu_common_has_work;
417 k->get_paging_enabled = cpu_common_get_paging_enabled;
418 k->get_memory_mapping = cpu_common_get_memory_mapping;
419 k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
420 k->write_elf32_note = cpu_common_write_elf32_note;
421 k->write_elf64_qemunote = cpu_common_write_elf64_qemunote;
422 k->write_elf64_note = cpu_common_write_elf64_note;
423 k->gdb_read_register = cpu_common_gdb_read_register;
424 k->gdb_write_register = cpu_common_gdb_write_register;
425 k->virtio_is_big_endian = cpu_common_virtio_is_big_endian;
426 k->debug_excp_handler = cpu_common_noop;
427 k->debug_check_watchpoint = cpu_common_debug_check_watchpoint;
428 k->cpu_exec_enter = cpu_common_noop;
429 k->cpu_exec_exit = cpu_common_noop;
430 k->cpu_exec_interrupt = cpu_common_exec_interrupt;
431 k->adjust_watchpoint_address = cpu_adjust_watchpoint_address;
432 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
433 dc->realize = cpu_common_realizefn;
434 dc->unrealize = cpu_common_unrealizefn;
435 dc->props = cpu_common_props;
437 * Reason: CPUs still need special care by board code: wiring up
438 * IRQs, adding reset handlers, halting non-first CPUs, ...
440 dc->user_creatable = false;
443 static const TypeInfo cpu_type_info = {
444 .name = TYPE_CPU,
445 .parent = TYPE_DEVICE,
446 .instance_size = sizeof(CPUState),
447 .instance_init = cpu_common_initfn,
448 .instance_finalize = cpu_common_finalize,
449 .abstract = true,
450 .class_size = sizeof(CPUClass),
451 .class_init = cpu_class_init,
454 static void cpu_register_types(void)
456 type_register_static(&cpu_type_info);
459 type_init(cpu_register_types)