target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts
[qemu/ar7.git] / tcg / ppc / tcg-target.h
blobe3395e301cac4c01973c86cdeca42bb73f15b607
1 /*
2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2008 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #ifndef TCG_TARGET_PPC
25 #define TCG_TARGET_PPC 1
27 #define TCG_TARGET_WORDS_BIGENDIAN
28 #define TCG_TARGET_NB_REGS 32
30 typedef enum {
31 TCG_REG_R0 = 0,
32 TCG_REG_R1,
33 TCG_REG_R2,
34 TCG_REG_R3,
35 TCG_REG_R4,
36 TCG_REG_R5,
37 TCG_REG_R6,
38 TCG_REG_R7,
39 TCG_REG_R8,
40 TCG_REG_R9,
41 TCG_REG_R10,
42 TCG_REG_R11,
43 TCG_REG_R12,
44 TCG_REG_R13,
45 TCG_REG_R14,
46 TCG_REG_R15,
47 TCG_REG_R16,
48 TCG_REG_R17,
49 TCG_REG_R18,
50 TCG_REG_R19,
51 TCG_REG_R20,
52 TCG_REG_R21,
53 TCG_REG_R22,
54 TCG_REG_R23,
55 TCG_REG_R24,
56 TCG_REG_R25,
57 TCG_REG_R26,
58 TCG_REG_R27,
59 TCG_REG_R28,
60 TCG_REG_R29,
61 TCG_REG_R30,
62 TCG_REG_R31
63 } TCGReg;
65 /* used for function call generation */
66 #define TCG_REG_CALL_STACK TCG_REG_R1
67 #define TCG_TARGET_STACK_ALIGN 16
68 #if defined _CALL_DARWIN || defined __APPLE__
69 #define TCG_TARGET_CALL_STACK_OFFSET 24
70 #elif defined _CALL_AIX
71 #define TCG_TARGET_CALL_STACK_OFFSET 52
72 #elif defined _CALL_SYSV
73 #define TCG_TARGET_CALL_ALIGN_ARGS 1
74 #define TCG_TARGET_CALL_STACK_OFFSET 8
75 #else
76 #error Unsupported system
77 #endif
79 /* optional instructions */
80 #define TCG_TARGET_HAS_div_i32 1
81 #define TCG_TARGET_HAS_rem_i32 0
82 #define TCG_TARGET_HAS_rot_i32 1
83 #define TCG_TARGET_HAS_ext8s_i32 1
84 #define TCG_TARGET_HAS_ext16s_i32 1
85 #define TCG_TARGET_HAS_ext8u_i32 1
86 #define TCG_TARGET_HAS_ext16u_i32 1
87 #define TCG_TARGET_HAS_bswap16_i32 1
88 #define TCG_TARGET_HAS_bswap32_i32 1
89 #define TCG_TARGET_HAS_not_i32 1
90 #define TCG_TARGET_HAS_neg_i32 1
91 #define TCG_TARGET_HAS_andc_i32 1
92 #define TCG_TARGET_HAS_orc_i32 1
93 #define TCG_TARGET_HAS_eqv_i32 1
94 #define TCG_TARGET_HAS_nand_i32 1
95 #define TCG_TARGET_HAS_nor_i32 1
96 #define TCG_TARGET_HAS_deposit_i32 1
97 #define TCG_TARGET_HAS_movcond_i32 1
98 #define TCG_TARGET_HAS_muls2_i32 0
99 #define TCG_TARGET_HAS_muluh_i32 0
100 #define TCG_TARGET_HAS_mulsh_i32 0
102 #define TCG_TARGET_HAS_new_ldst 1
104 #define TCG_AREG0 TCG_REG_R27
106 #define tcg_qemu_tb_exec(env, tb_ptr) \
107 ((uintptr_t __attribute__ ((longcall)) \
108 (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
110 #endif