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microblaze/ml605: Define macros for irq/memory maps
[qemu/ar7.git] / linux-user / main.c
blob919297736c807f9b098771f732a35324913dc236
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "qemu/cache-utils.h"
32 #include "cpu.h"
33 #include "tcg.h"
34 #include "qemu/timer.h"
35 #include "qemu/envlist.h"
36 #include "elf.h"
37
38 char *exec_path;
39
40 int singlestep;
41 const char *filename;
42 const char *argv0;
43 int gdbstub_port;
44 envlist_t *envlist;
45 static const char *cpu_model;
46 unsigned long mmap_min_addr;
47 #if defined(CONFIG_USE_GUEST_BASE)
48 unsigned long guest_base;
49 int have_guest_base;
50 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
51 /*
52 * When running 32-on-64 we should make sure we can fit all of the possible
53 * guest address space into a contiguous chunk of virtual host memory.
54 *
55 * This way we will never overlap with our own libraries or binaries or stack
56 * or anything else that QEMU maps.
57 */
58 # ifdef TARGET_MIPS
59 /* MIPS only supports 31 bits of virtual address space for user space */
60 unsigned long reserved_va = 0x77000000;
61 # else
62 unsigned long reserved_va = 0xf7000000;
63 # endif
64 #else
65 unsigned long reserved_va;
66 #endif
67 #endif
68
69 static void usage(void);
70
71 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
72 const char *qemu_uname_release = CONFIG_UNAME_RELEASE;
73
74 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
75 we allocate a bigger stack. Need a better solution, for example
76 by remapping the process stack directly at the right place */
77 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
78
79 void gemu_log(const char *fmt, ...)
80 {
81 va_list ap;
82
83 va_start(ap, fmt);
84 vfprintf(stderr, fmt, ap);
85 va_end(ap);
86 }
87
88 #if defined(TARGET_I386)
89 int cpu_get_pic_interrupt(CPUX86State *env)
90 {
91 return -1;
92 }
93 #endif
94
95 /***********************************************************/
96 /* Helper routines for implementing atomic operations. */
97
98 /* To implement exclusive operations we force all cpus to syncronise.
99 We don't require a full sync, only that no cpus are executing guest code.
100 The alternative is to map target atomic ops onto host equivalents,
101 which requires quite a lot of per host/target work. */
102 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
103 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
104 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
105 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
106 static int pending_cpus;
107
108 /* Make sure everything is in a consistent state for calling fork(). */
109 void fork_start(void)
110 {
111 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
112 pthread_mutex_lock(&exclusive_lock);
113 mmap_fork_start();
114 }
115
116 void fork_end(int child)
117 {
118 mmap_fork_end(child);
119 if (child) {
120 CPUState *cpu, *next_cpu;
121 /* Child processes created by fork() only have a single thread.
122 Discard information about the parent threads. */
123 CPU_FOREACH_SAFE(cpu, next_cpu) {
124 if (cpu != thread_cpu) {
125 QTAILQ_REMOVE(&cpus, thread_cpu, node);
126 }
127 }
128 pending_cpus = 0;
129 pthread_mutex_init(&exclusive_lock, NULL);
130 pthread_mutex_init(&cpu_list_mutex, NULL);
131 pthread_cond_init(&exclusive_cond, NULL);
132 pthread_cond_init(&exclusive_resume, NULL);
133 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
134 gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);
135 } else {
136 pthread_mutex_unlock(&exclusive_lock);
137 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
138 }
139 }
140
141 /* Wait for pending exclusive operations to complete. The exclusive lock
142 must be held. */
143 static inline void exclusive_idle(void)
144 {
145 while (pending_cpus) {
146 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
147 }
148 }
149
150 /* Start an exclusive operation.
151 Must only be called from outside cpu_arm_exec. */
152 static inline void start_exclusive(void)
153 {
154 CPUState *other_cpu;
155
156 pthread_mutex_lock(&exclusive_lock);
157 exclusive_idle();
158
159 pending_cpus = 1;
160 /* Make all other cpus stop executing. */
161 CPU_FOREACH(other_cpu) {
162 if (other_cpu->running) {
163 pending_cpus++;
164 cpu_exit(other_cpu);
165 }
166 }
167 if (pending_cpus > 1) {
168 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
169 }
170 }
171
172 /* Finish an exclusive operation. */
173 static inline void end_exclusive(void)
174 {
175 pending_cpus = 0;
176 pthread_cond_broadcast(&exclusive_resume);
177 pthread_mutex_unlock(&exclusive_lock);
178 }
179
180 /* Wait for exclusive ops to finish, and begin cpu execution. */
181 static inline void cpu_exec_start(CPUState *cpu)
182 {
183 pthread_mutex_lock(&exclusive_lock);
184 exclusive_idle();
185 cpu->running = true;
186 pthread_mutex_unlock(&exclusive_lock);
187 }
188
189 /* Mark cpu as not executing, and release pending exclusive ops. */
190 static inline void cpu_exec_end(CPUState *cpu)
191 {
192 pthread_mutex_lock(&exclusive_lock);
193 cpu->running = false;
194 if (pending_cpus > 1) {
195 pending_cpus--;
196 if (pending_cpus == 1) {
197 pthread_cond_signal(&exclusive_cond);
198 }
199 }
200 exclusive_idle();
201 pthread_mutex_unlock(&exclusive_lock);
202 }
203
204 void cpu_list_lock(void)
205 {
206 pthread_mutex_lock(&cpu_list_mutex);
207 }
208
209 void cpu_list_unlock(void)
210 {
211 pthread_mutex_unlock(&cpu_list_mutex);
212 }
213
214
215 #ifdef TARGET_I386
216 /***********************************************************/
217 /* CPUX86 core interface */
218
219 void cpu_smm_update(CPUX86State *env)
220 {
221 }
222
223 uint64_t cpu_get_tsc(CPUX86State *env)
224 {
225 return cpu_get_real_ticks();
226 }
227
228 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
229 int flags)
230 {
231 unsigned int e1, e2;
232 uint32_t *p;
233 e1 = (addr << 16) | (limit & 0xffff);
234 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
235 e2 |= flags;
236 p = ptr;
237 p[0] = tswap32(e1);
238 p[1] = tswap32(e2);
239 }
240
241 static uint64_t *idt_table;
242 #ifdef TARGET_X86_64
243 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
244 uint64_t addr, unsigned int sel)
245 {
246 uint32_t *p, e1, e2;
247 e1 = (addr & 0xffff) | (sel << 16);
248 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
249 p = ptr;
250 p[0] = tswap32(e1);
251 p[1] = tswap32(e2);
252 p[2] = tswap32(addr >> 32);
253 p[3] = 0;
254 }
255 /* only dpl matters as we do only user space emulation */
256 static void set_idt(int n, unsigned int dpl)
257 {
258 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
259 }
260 #else
261 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
262 uint32_t addr, unsigned int sel)
263 {
264 uint32_t *p, e1, e2;
265 e1 = (addr & 0xffff) | (sel << 16);
266 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
267 p = ptr;
268 p[0] = tswap32(e1);
269 p[1] = tswap32(e2);
270 }
271
272 /* only dpl matters as we do only user space emulation */
273 static void set_idt(int n, unsigned int dpl)
274 {
275 set_gate(idt_table + n, 0, dpl, 0, 0);
276 }
277 #endif
278
279 void cpu_loop(CPUX86State *env)
280 {
281 CPUState *cs = CPU(x86_env_get_cpu(env));
282 int trapnr;
283 abi_ulong pc;
284 target_siginfo_t info;
285
286 for(;;) {
287 trapnr = cpu_x86_exec(env);
288 switch(trapnr) {
289 case 0x80:
290 /* linux syscall from int $0x80 */
291 env->regs[R_EAX] = do_syscall(env,
292 env->regs[R_EAX],
293 env->regs[R_EBX],
294 env->regs[R_ECX],
295 env->regs[R_EDX],
296 env->regs[R_ESI],
297 env->regs[R_EDI],
298 env->regs[R_EBP],
299 0, 0);
300 break;
301 #ifndef TARGET_ABI32
302 case EXCP_SYSCALL:
303 /* linux syscall from syscall instruction */
304 env->regs[R_EAX] = do_syscall(env,
305 env->regs[R_EAX],
306 env->regs[R_EDI],
307 env->regs[R_ESI],
308 env->regs[R_EDX],
309 env->regs[10],
310 env->regs[8],
311 env->regs[9],
312 0, 0);
313 env->eip = env->exception_next_eip;
314 break;
315 #endif
316 case EXCP0B_NOSEG:
317 case EXCP0C_STACK:
318 info.si_signo = SIGBUS;
319 info.si_errno = 0;
320 info.si_code = TARGET_SI_KERNEL;
321 info._sifields._sigfault._addr = 0;
322 queue_signal(env, info.si_signo, &info);
323 break;
324 case EXCP0D_GPF:
325 /* XXX: potential problem if ABI32 */
326 #ifndef TARGET_X86_64
327 if (env->eflags & VM_MASK) {
328 handle_vm86_fault(env);
329 } else
330 #endif
331 {
332 info.si_signo = SIGSEGV;
333 info.si_errno = 0;
334 info.si_code = TARGET_SI_KERNEL;
335 info._sifields._sigfault._addr = 0;
336 queue_signal(env, info.si_signo, &info);
337 }
338 break;
339 case EXCP0E_PAGE:
340 info.si_signo = SIGSEGV;
341 info.si_errno = 0;
342 if (!(env->error_code & 1))
343 info.si_code = TARGET_SEGV_MAPERR;
344 else
345 info.si_code = TARGET_SEGV_ACCERR;
346 info._sifields._sigfault._addr = env->cr[2];
347 queue_signal(env, info.si_signo, &info);
348 break;
349 case EXCP00_DIVZ:
350 #ifndef TARGET_X86_64
351 if (env->eflags & VM_MASK) {
352 handle_vm86_trap(env, trapnr);
353 } else
354 #endif
355 {
356 /* division by zero */
357 info.si_signo = SIGFPE;
358 info.si_errno = 0;
359 info.si_code = TARGET_FPE_INTDIV;
360 info._sifields._sigfault._addr = env->eip;
361 queue_signal(env, info.si_signo, &info);
362 }
363 break;
364 case EXCP01_DB:
365 case EXCP03_INT3:
366 #ifndef TARGET_X86_64
367 if (env->eflags & VM_MASK) {
368 handle_vm86_trap(env, trapnr);
369 } else
370 #endif
371 {
372 info.si_signo = SIGTRAP;
373 info.si_errno = 0;
374 if (trapnr == EXCP01_DB) {
375 info.si_code = TARGET_TRAP_BRKPT;
376 info._sifields._sigfault._addr = env->eip;
377 } else {
378 info.si_code = TARGET_SI_KERNEL;
379 info._sifields._sigfault._addr = 0;
380 }
381 queue_signal(env, info.si_signo, &info);
382 }
383 break;
384 case EXCP04_INTO:
385 case EXCP05_BOUND:
386 #ifndef TARGET_X86_64
387 if (env->eflags & VM_MASK) {
388 handle_vm86_trap(env, trapnr);
389 } else
390 #endif
391 {
392 info.si_signo = SIGSEGV;
393 info.si_errno = 0;
394 info.si_code = TARGET_SI_KERNEL;
395 info._sifields._sigfault._addr = 0;
396 queue_signal(env, info.si_signo, &info);
397 }
398 break;
399 case EXCP06_ILLOP:
400 info.si_signo = SIGILL;
401 info.si_errno = 0;
402 info.si_code = TARGET_ILL_ILLOPN;
403 info._sifields._sigfault._addr = env->eip;
404 queue_signal(env, info.si_signo, &info);
405 break;
406 case EXCP_INTERRUPT:
407 /* just indicate that signals should be handled asap */
408 break;
409 case EXCP_DEBUG:
410 {
411 int sig;
412
413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
414 if (sig)
415 {
416 info.si_signo = sig;
417 info.si_errno = 0;
418 info.si_code = TARGET_TRAP_BRKPT;
419 queue_signal(env, info.si_signo, &info);
420 }
421 }
422 break;
423 default:
424 pc = env->segs[R_CS].base + env->eip;
425 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
426 (long)pc, trapnr);
427 abort();
428 }
429 process_pending_signals(env);
430 }
431 }
432 #endif
433
434 #ifdef TARGET_ARM
435
436 #define get_user_code_u32(x, gaddr, doswap) \
437 ({ abi_long __r = get_user_u32((x), (gaddr)); \
438 if (!__r && (doswap)) { \
439 (x) = bswap32(x); \
440 } \
441 __r; \
442 })
443
444 #define get_user_code_u16(x, gaddr, doswap) \
445 ({ abi_long __r = get_user_u16((x), (gaddr)); \
446 if (!__r && (doswap)) { \
447 (x) = bswap16(x); \
448 } \
449 __r; \
450 })
451
452 #ifdef TARGET_ABI32
453 /* Commpage handling -- there is no commpage for AArch64 */
454
455 /*
456 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
457 * Input:
458 * r0 = pointer to oldval
459 * r1 = pointer to newval
460 * r2 = pointer to target value
461 *
462 * Output:
463 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
464 * C set if *ptr was changed, clear if no exchange happened
465 *
466 * Note segv's in kernel helpers are a bit tricky, we can set the
467 * data address sensibly but the PC address is just the entry point.
468 */
469 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
470 {
471 uint64_t oldval, newval, val;
472 uint32_t addr, cpsr;
473 target_siginfo_t info;
474
475 /* Based on the 32 bit code in do_kernel_trap */
476
477 /* XXX: This only works between threads, not between processes.
478 It's probably possible to implement this with native host
479 operations. However things like ldrex/strex are much harder so
480 there's not much point trying. */
481 start_exclusive();
482 cpsr = cpsr_read(env);
483 addr = env->regs[2];
484
485 if (get_user_u64(oldval, env->regs[0])) {
486 env->cp15.c6_data = env->regs[0];
487 goto segv;
488 };
489
490 if (get_user_u64(newval, env->regs[1])) {
491 env->cp15.c6_data = env->regs[1];
492 goto segv;
493 };
494
495 if (get_user_u64(val, addr)) {
496 env->cp15.c6_data = addr;
497 goto segv;
498 }
499
500 if (val == oldval) {
501 val = newval;
502
503 if (put_user_u64(val, addr)) {
504 env->cp15.c6_data = addr;
505 goto segv;
506 };
507
508 env->regs[0] = 0;
509 cpsr |= CPSR_C;
510 } else {
511 env->regs[0] = -1;
512 cpsr &= ~CPSR_C;
513 }
514 cpsr_write(env, cpsr, CPSR_C);
515 end_exclusive();
516 return;
517
518 segv:
519 end_exclusive();
520 /* We get the PC of the entry address - which is as good as anything,
521 on a real kernel what you get depends on which mode it uses. */
522 info.si_signo = SIGSEGV;
523 info.si_errno = 0;
524 /* XXX: check env->error_code */
525 info.si_code = TARGET_SEGV_MAPERR;
526 info._sifields._sigfault._addr = env->cp15.c6_data;
527 queue_signal(env, info.si_signo, &info);
528
529 end_exclusive();
530 }
531
532 /* Handle a jump to the kernel code page. */
533 static int
534 do_kernel_trap(CPUARMState *env)
535 {
536 uint32_t addr;
537 uint32_t cpsr;
538 uint32_t val;
539
540 switch (env->regs[15]) {
541 case 0xffff0fa0: /* __kernel_memory_barrier */
542 /* ??? No-op. Will need to do better for SMP. */
543 break;
544 case 0xffff0fc0: /* __kernel_cmpxchg */
545 /* XXX: This only works between threads, not between processes.
546 It's probably possible to implement this with native host
547 operations. However things like ldrex/strex are much harder so
548 there's not much point trying. */
549 start_exclusive();
550 cpsr = cpsr_read(env);
551 addr = env->regs[2];
552 /* FIXME: This should SEGV if the access fails. */
553 if (get_user_u32(val, addr))
554 val = ~env->regs[0];
555 if (val == env->regs[0]) {
556 val = env->regs[1];
557 /* FIXME: Check for segfaults. */
558 put_user_u32(val, addr);
559 env->regs[0] = 0;
560 cpsr |= CPSR_C;
561 } else {
562 env->regs[0] = -1;
563 cpsr &= ~CPSR_C;
564 }
565 cpsr_write(env, cpsr, CPSR_C);
566 end_exclusive();
567 break;
568 case 0xffff0fe0: /* __kernel_get_tls */
569 env->regs[0] = env->cp15.tpidrro_el0;
570 break;
571 case 0xffff0f60: /* __kernel_cmpxchg64 */
572 arm_kernel_cmpxchg64_helper(env);
573 break;
574
575 default:
576 return 1;
577 }
578 /* Jump back to the caller. */
579 addr = env->regs[14];
580 if (addr & 1) {
581 env->thumb = 1;
582 addr &= ~1;
583 }
584 env->regs[15] = addr;
585
586 return 0;
587 }
588
589 /* Store exclusive handling for AArch32 */
590 static int do_strex(CPUARMState *env)
591 {
592 uint64_t val;
593 int size;
594 int rc = 1;
595 int segv = 0;
596 uint32_t addr;
597 start_exclusive();
598 if (env->exclusive_addr != env->exclusive_test) {
599 goto fail;
600 }
601 /* We know we're always AArch32 so the address is in uint32_t range
602 * unless it was the -1 exclusive-monitor-lost value (which won't
603 * match exclusive_test above).
604 */
605 assert(extract64(env->exclusive_addr, 32, 32) == 0);
606 addr = env->exclusive_addr;
607 size = env->exclusive_info & 0xf;
608 switch (size) {
609 case 0:
610 segv = get_user_u8(val, addr);
611 break;
612 case 1:
613 segv = get_user_u16(val, addr);
614 break;
615 case 2:
616 case 3:
617 segv = get_user_u32(val, addr);
618 break;
619 default:
620 abort();
621 }
622 if (segv) {
623 env->cp15.c6_data = addr;
624 goto done;
625 }
626 if (size == 3) {
627 uint32_t valhi;
628 segv = get_user_u32(valhi, addr + 4);
629 if (segv) {
630 env->cp15.c6_data = addr + 4;
631 goto done;
632 }
633 val = deposit64(val, 32, 32, valhi);
634 }
635 if (val != env->exclusive_val) {
636 goto fail;
637 }
638
639 val = env->regs[(env->exclusive_info >> 8) & 0xf];
640 switch (size) {
641 case 0:
642 segv = put_user_u8(val, addr);
643 break;
644 case 1:
645 segv = put_user_u16(val, addr);
646 break;
647 case 2:
648 case 3:
649 segv = put_user_u32(val, addr);
650 break;
651 }
652 if (segv) {
653 env->cp15.c6_data = addr;
654 goto done;
655 }
656 if (size == 3) {
657 val = env->regs[(env->exclusive_info >> 12) & 0xf];
658 segv = put_user_u32(val, addr + 4);
659 if (segv) {
660 env->cp15.c6_data = addr + 4;
661 goto done;
662 }
663 }
664 rc = 0;
665 fail:
666 env->regs[15] += 4;
667 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
668 done:
669 end_exclusive();
670 return segv;
671 }
672
673 void cpu_loop(CPUARMState *env)
674 {
675 CPUState *cs = CPU(arm_env_get_cpu(env));
676 int trapnr;
677 unsigned int n, insn;
678 target_siginfo_t info;
679 uint32_t addr;
680
681 for(;;) {
682 cpu_exec_start(cs);
683 trapnr = cpu_arm_exec(env);
684 cpu_exec_end(cs);
685 switch(trapnr) {
686 case EXCP_UDEF:
687 {
688 TaskState *ts = env->opaque;
689 uint32_t opcode;
690 int rc;
691
692 /* we handle the FPU emulation here, as Linux */
693 /* we get the opcode */
694 /* FIXME - what to do if get_user() fails? */
695 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
696
697 rc = EmulateAll(opcode, &ts->fpa, env);
698 if (rc == 0) { /* illegal instruction */
699 info.si_signo = SIGILL;
700 info.si_errno = 0;
701 info.si_code = TARGET_ILL_ILLOPN;
702 info._sifields._sigfault._addr = env->regs[15];
703 queue_signal(env, info.si_signo, &info);
704 } else if (rc < 0) { /* FP exception */
705 int arm_fpe=0;
706
707 /* translate softfloat flags to FPSR flags */
708 if (-rc & float_flag_invalid)
709 arm_fpe |= BIT_IOC;
710 if (-rc & float_flag_divbyzero)
711 arm_fpe |= BIT_DZC;
712 if (-rc & float_flag_overflow)
713 arm_fpe |= BIT_OFC;
714 if (-rc & float_flag_underflow)
715 arm_fpe |= BIT_UFC;
716 if (-rc & float_flag_inexact)
717 arm_fpe |= BIT_IXC;
718
719 FPSR fpsr = ts->fpa.fpsr;
720 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
721
722 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
723 info.si_signo = SIGFPE;
724 info.si_errno = 0;
725
726 /* ordered by priority, least first */
727 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
728 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
729 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
730 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
731 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
732
733 info._sifields._sigfault._addr = env->regs[15];
734 queue_signal(env, info.si_signo, &info);
735 } else {
736 env->regs[15] += 4;
737 }
738
739 /* accumulate unenabled exceptions */
740 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
741 fpsr |= BIT_IXC;
742 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
743 fpsr |= BIT_UFC;
744 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
745 fpsr |= BIT_OFC;
746 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
747 fpsr |= BIT_DZC;
748 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
749 fpsr |= BIT_IOC;
750 ts->fpa.fpsr=fpsr;
751 } else { /* everything OK */
752 /* increment PC */
753 env->regs[15] += 4;
754 }
755 }
756 break;
757 case EXCP_SWI:
758 case EXCP_BKPT:
759 {
760 env->eabi = 1;
761 /* system call */
762 if (trapnr == EXCP_BKPT) {
763 if (env->thumb) {
764 /* FIXME - what to do if get_user() fails? */
765 get_user_code_u16(insn, env->regs[15], env->bswap_code);
766 n = insn & 0xff;
767 env->regs[15] += 2;
768 } else {
769 /* FIXME - what to do if get_user() fails? */
770 get_user_code_u32(insn, env->regs[15], env->bswap_code);
771 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
772 env->regs[15] += 4;
773 }
774 } else {
775 if (env->thumb) {
776 /* FIXME - what to do if get_user() fails? */
777 get_user_code_u16(insn, env->regs[15] - 2,
778 env->bswap_code);
779 n = insn & 0xff;
780 } else {
781 /* FIXME - what to do if get_user() fails? */
782 get_user_code_u32(insn, env->regs[15] - 4,
783 env->bswap_code);
784 n = insn & 0xffffff;
785 }
786 }
787
788 if (n == ARM_NR_cacheflush) {
789 /* nop */
790 } else if (n == ARM_NR_semihosting
791 || n == ARM_NR_thumb_semihosting) {
792 env->regs[0] = do_arm_semihosting (env);
793 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
794 /* linux syscall */
795 if (env->thumb || n == 0) {
796 n = env->regs[7];
797 } else {
798 n -= ARM_SYSCALL_BASE;
799 env->eabi = 0;
800 }
801 if ( n > ARM_NR_BASE) {
802 switch (n) {
803 case ARM_NR_cacheflush:
804 /* nop */
805 break;
806 case ARM_NR_set_tls:
807 cpu_set_tls(env, env->regs[0]);
808 env->regs[0] = 0;
809 break;
810 default:
811 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
812 n);
813 env->regs[0] = -TARGET_ENOSYS;
814 break;
815 }
816 } else {
817 env->regs[0] = do_syscall(env,
818 n,
819 env->regs[0],
820 env->regs[1],
821 env->regs[2],
822 env->regs[3],
823 env->regs[4],
824 env->regs[5],
825 0, 0);
826 }
827 } else {
828 goto error;
829 }
830 }
831 break;
832 case EXCP_INTERRUPT:
833 /* just indicate that signals should be handled asap */
834 break;
835 case EXCP_PREFETCH_ABORT:
836 addr = env->cp15.c6_insn;
837 goto do_segv;
838 case EXCP_DATA_ABORT:
839 addr = env->cp15.c6_data;
840 do_segv:
841 {
842 info.si_signo = SIGSEGV;
843 info.si_errno = 0;
844 /* XXX: check env->error_code */
845 info.si_code = TARGET_SEGV_MAPERR;
846 info._sifields._sigfault._addr = addr;
847 queue_signal(env, info.si_signo, &info);
848 }
849 break;
850 case EXCP_DEBUG:
851 {
852 int sig;
853
854 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
855 if (sig)
856 {
857 info.si_signo = sig;
858 info.si_errno = 0;
859 info.si_code = TARGET_TRAP_BRKPT;
860 queue_signal(env, info.si_signo, &info);
861 }
862 }
863 break;
864 case EXCP_KERNEL_TRAP:
865 if (do_kernel_trap(env))
866 goto error;
867 break;
868 case EXCP_STREX:
869 if (do_strex(env)) {
870 addr = env->cp15.c6_data;
871 goto do_segv;
872 }
873 break;
874 default:
875 error:
876 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
877 trapnr);
878 cpu_dump_state(cs, stderr, fprintf, 0);
879 abort();
880 }
881 process_pending_signals(env);
882 }
883 }
884
885 #else
886
887 /*
888 * Handle AArch64 store-release exclusive
889 *
890 * rs = gets the status result of store exclusive
891 * rt = is the register that is stored
892 * rt2 = is the second register store (in STP)
893 *
894 */
895 static int do_strex_a64(CPUARMState *env)
896 {
897 uint64_t val;
898 int size;
899 bool is_pair;
900 int rc = 1;
901 int segv = 0;
902 uint64_t addr;
903 int rs, rt, rt2;
904
905 start_exclusive();
906 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
907 size = extract32(env->exclusive_info, 0, 2);
908 is_pair = extract32(env->exclusive_info, 2, 1);
909 rs = extract32(env->exclusive_info, 4, 5);
910 rt = extract32(env->exclusive_info, 9, 5);
911 rt2 = extract32(env->exclusive_info, 14, 5);
912
913 addr = env->exclusive_addr;
914
915 if (addr != env->exclusive_test) {
916 goto finish;
917 }
918
919 switch (size) {
920 case 0:
921 segv = get_user_u8(val, addr);
922 break;
923 case 1:
924 segv = get_user_u16(val, addr);
925 break;
926 case 2:
927 segv = get_user_u32(val, addr);
928 break;
929 case 3:
930 segv = get_user_u64(val, addr);
931 break;
932 default:
933 abort();
934 }
935 if (segv) {
936 env->cp15.c6_data = addr;
937 goto error;
938 }
939 if (val != env->exclusive_val) {
940 goto finish;
941 }
942 if (is_pair) {
943 if (size == 2) {
944 segv = get_user_u32(val, addr + 4);
945 } else {
946 segv = get_user_u64(val, addr + 8);
947 }
948 if (segv) {
949 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
950 goto error;
951 }
952 if (val != env->exclusive_high) {
953 goto finish;
954 }
955 }
956 /* handle the zero register */
957 val = rt == 31 ? 0 : env->xregs[rt];
958 switch (size) {
959 case 0:
960 segv = put_user_u8(val, addr);
961 break;
962 case 1:
963 segv = put_user_u16(val, addr);
964 break;
965 case 2:
966 segv = put_user_u32(val, addr);
967 break;
968 case 3:
969 segv = put_user_u64(val, addr);
970 break;
971 }
972 if (segv) {
973 goto error;
974 }
975 if (is_pair) {
976 /* handle the zero register */
977 val = rt2 == 31 ? 0 : env->xregs[rt2];
978 if (size == 2) {
979 segv = put_user_u32(val, addr + 4);
980 } else {
981 segv = put_user_u64(val, addr + 8);
982 }
983 if (segv) {
984 env->cp15.c6_data = addr + (size == 2 ? 4 : 8);
985 goto error;
986 }
987 }
988 rc = 0;
989 finish:
990 env->pc += 4;
991 /* rs == 31 encodes a write to the ZR, thus throwing away
992 * the status return. This is rather silly but valid.
993 */
994 if (rs < 31) {
995 env->xregs[rs] = rc;
996 }
997 error:
998 /* instruction faulted, PC does not advance */
999 /* either way a strex releases any exclusive lock we have */
1000 env->exclusive_addr = -1;
1001 end_exclusive();
1002 return segv;
1003 }
1004
1005 /* AArch64 main loop */
1006 void cpu_loop(CPUARMState *env)
1007 {
1008 CPUState *cs = CPU(arm_env_get_cpu(env));
1009 int trapnr, sig;
1010 target_siginfo_t info;
1011 uint32_t addr;
1012
1013 for (;;) {
1014 cpu_exec_start(cs);
1015 trapnr = cpu_arm_exec(env);
1016 cpu_exec_end(cs);
1017
1018 switch (trapnr) {
1019 case EXCP_SWI:
1020 env->xregs[0] = do_syscall(env,
1021 env->xregs[8],
1022 env->xregs[0],
1023 env->xregs[1],
1024 env->xregs[2],
1025 env->xregs[3],
1026 env->xregs[4],
1027 env->xregs[5],
1028 0, 0);
1029 break;
1030 case EXCP_INTERRUPT:
1031 /* just indicate that signals should be handled asap */
1032 break;
1033 case EXCP_UDEF:
1034 info.si_signo = SIGILL;
1035 info.si_errno = 0;
1036 info.si_code = TARGET_ILL_ILLOPN;
1037 info._sifields._sigfault._addr = env->pc;
1038 queue_signal(env, info.si_signo, &info);
1039 break;
1040 case EXCP_PREFETCH_ABORT:
1041 addr = env->cp15.c6_insn;
1042 goto do_segv;
1043 case EXCP_DATA_ABORT:
1044 addr = env->cp15.c6_data;
1045 do_segv:
1046 info.si_signo = SIGSEGV;
1047 info.si_errno = 0;
1048 /* XXX: check env->error_code */
1049 info.si_code = TARGET_SEGV_MAPERR;
1050 info._sifields._sigfault._addr = addr;
1051 queue_signal(env, info.si_signo, &info);
1052 break;
1053 case EXCP_DEBUG:
1054 case EXCP_BKPT:
1055 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1056 if (sig) {
1057 info.si_signo = sig;
1058 info.si_errno = 0;
1059 info.si_code = TARGET_TRAP_BRKPT;
1060 queue_signal(env, info.si_signo, &info);
1061 }
1062 break;
1063 case EXCP_STREX:
1064 if (do_strex_a64(env)) {
1065 addr = env->cp15.c6_data;
1066 goto do_segv;
1067 }
1068 break;
1069 default:
1070 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1071 trapnr);
1072 cpu_dump_state(cs, stderr, fprintf, 0);
1073 abort();
1074 }
1075 process_pending_signals(env);
1076 /* Exception return on AArch64 always clears the exclusive monitor,
1077 * so any return to running guest code implies this.
1078 * A strex (successful or otherwise) also clears the monitor, so
1079 * we don't need to specialcase EXCP_STREX.
1080 */
1081 env->exclusive_addr = -1;
1082 }
1083 }
1084 #endif /* ndef TARGET_ABI32 */
1085
1086 #endif
1087
1088 #ifdef TARGET_UNICORE32
1089
1090 void cpu_loop(CPUUniCore32State *env)
1091 {
1092 CPUState *cs = CPU(uc32_env_get_cpu(env));
1093 int trapnr;
1094 unsigned int n, insn;
1095 target_siginfo_t info;
1096
1097 for (;;) {
1098 cpu_exec_start(cs);
1099 trapnr = uc32_cpu_exec(env);
1100 cpu_exec_end(cs);
1101 switch (trapnr) {
1102 case UC32_EXCP_PRIV:
1103 {
1104 /* system call */
1105 get_user_u32(insn, env->regs[31] - 4);
1106 n = insn & 0xffffff;
1107
1108 if (n >= UC32_SYSCALL_BASE) {
1109 /* linux syscall */
1110 n -= UC32_SYSCALL_BASE;
1111 if (n == UC32_SYSCALL_NR_set_tls) {
1112 cpu_set_tls(env, env->regs[0]);
1113 env->regs[0] = 0;
1114 } else {
1115 env->regs[0] = do_syscall(env,
1116 n,
1117 env->regs[0],
1118 env->regs[1],
1119 env->regs[2],
1120 env->regs[3],
1121 env->regs[4],
1122 env->regs[5],
1123 0, 0);
1124 }
1125 } else {
1126 goto error;
1127 }
1128 }
1129 break;
1130 case UC32_EXCP_DTRAP:
1131 case UC32_EXCP_ITRAP:
1132 info.si_signo = SIGSEGV;
1133 info.si_errno = 0;
1134 /* XXX: check env->error_code */
1135 info.si_code = TARGET_SEGV_MAPERR;
1136 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1137 queue_signal(env, info.si_signo, &info);
1138 break;
1139 case EXCP_INTERRUPT:
1140 /* just indicate that signals should be handled asap */
1141 break;
1142 case EXCP_DEBUG:
1143 {
1144 int sig;
1145
1146 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1147 if (sig) {
1148 info.si_signo = sig;
1149 info.si_errno = 0;
1150 info.si_code = TARGET_TRAP_BRKPT;
1151 queue_signal(env, info.si_signo, &info);
1152 }
1153 }
1154 break;
1155 default:
1156 goto error;
1157 }
1158 process_pending_signals(env);
1159 }
1160
1161 error:
1162 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1163 cpu_dump_state(cs, stderr, fprintf, 0);
1164 abort();
1165 }
1166 #endif
1167
1168 #ifdef TARGET_SPARC
1169 #define SPARC64_STACK_BIAS 2047
1170
1171 //#define DEBUG_WIN
1172
1173 /* WARNING: dealing with register windows _is_ complicated. More info
1174 can be found at http://www.sics.se/~psm/sparcstack.html */
1175 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1176 {
1177 index = (index + cwp * 16) % (16 * env->nwindows);
1178 /* wrap handling : if cwp is on the last window, then we use the
1179 registers 'after' the end */
1180 if (index < 8 && env->cwp == env->nwindows - 1)
1181 index += 16 * env->nwindows;
1182 return index;
1183 }
1184
1185 /* save the register window 'cwp1' */
1186 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1187 {
1188 unsigned int i;
1189 abi_ulong sp_ptr;
1190
1191 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1192 #ifdef TARGET_SPARC64
1193 if (sp_ptr & 3)
1194 sp_ptr += SPARC64_STACK_BIAS;
1195 #endif
1196 #if defined(DEBUG_WIN)
1197 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1198 sp_ptr, cwp1);
1199 #endif
1200 for(i = 0; i < 16; i++) {
1201 /* FIXME - what to do if put_user() fails? */
1202 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1203 sp_ptr += sizeof(abi_ulong);
1204 }
1205 }
1206
1207 static void save_window(CPUSPARCState *env)
1208 {
1209 #ifndef TARGET_SPARC64
1210 unsigned int new_wim;
1211 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1212 ((1LL << env->nwindows) - 1);
1213 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1214 env->wim = new_wim;
1215 #else
1216 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1217 env->cansave++;
1218 env->canrestore--;
1219 #endif
1220 }
1221
1222 static void restore_window(CPUSPARCState *env)
1223 {
1224 #ifndef TARGET_SPARC64
1225 unsigned int new_wim;
1226 #endif
1227 unsigned int i, cwp1;
1228 abi_ulong sp_ptr;
1229
1230 #ifndef TARGET_SPARC64
1231 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1232 ((1LL << env->nwindows) - 1);
1233 #endif
1234
1235 /* restore the invalid window */
1236 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1237 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1238 #ifdef TARGET_SPARC64
1239 if (sp_ptr & 3)
1240 sp_ptr += SPARC64_STACK_BIAS;
1241 #endif
1242 #if defined(DEBUG_WIN)
1243 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1244 sp_ptr, cwp1);
1245 #endif
1246 for(i = 0; i < 16; i++) {
1247 /* FIXME - what to do if get_user() fails? */
1248 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1249 sp_ptr += sizeof(abi_ulong);
1250 }
1251 #ifdef TARGET_SPARC64
1252 env->canrestore++;
1253 if (env->cleanwin < env->nwindows - 1)
1254 env->cleanwin++;
1255 env->cansave--;
1256 #else
1257 env->wim = new_wim;
1258 #endif
1259 }
1260
1261 static void flush_windows(CPUSPARCState *env)
1262 {
1263 int offset, cwp1;
1264
1265 offset = 1;
1266 for(;;) {
1267 /* if restore would invoke restore_window(), then we can stop */
1268 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1269 #ifndef TARGET_SPARC64
1270 if (env->wim & (1 << cwp1))
1271 break;
1272 #else
1273 if (env->canrestore == 0)
1274 break;
1275 env->cansave++;
1276 env->canrestore--;
1277 #endif
1278 save_window_offset(env, cwp1);
1279 offset++;
1280 }
1281 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1282 #ifndef TARGET_SPARC64
1283 /* set wim so that restore will reload the registers */
1284 env->wim = 1 << cwp1;
1285 #endif
1286 #if defined(DEBUG_WIN)
1287 printf("flush_windows: nb=%d\n", offset - 1);
1288 #endif
1289 }
1290
1291 void cpu_loop (CPUSPARCState *env)
1292 {
1293 CPUState *cs = CPU(sparc_env_get_cpu(env));
1294 int trapnr;
1295 abi_long ret;
1296 target_siginfo_t info;
1297
1298 while (1) {
1299 trapnr = cpu_sparc_exec (env);
1300
1301 /* Compute PSR before exposing state. */
1302 if (env->cc_op != CC_OP_FLAGS) {
1303 cpu_get_psr(env);
1304 }
1305
1306 switch (trapnr) {
1307 #ifndef TARGET_SPARC64
1308 case 0x88:
1309 case 0x90:
1310 #else
1311 case 0x110:
1312 case 0x16d:
1313 #endif
1314 ret = do_syscall (env, env->gregs[1],
1315 env->regwptr[0], env->regwptr[1],
1316 env->regwptr[2], env->regwptr[3],
1317 env->regwptr[4], env->regwptr[5],
1318 0, 0);
1319 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1320 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1321 env->xcc |= PSR_CARRY;
1322 #else
1323 env->psr |= PSR_CARRY;
1324 #endif
1325 ret = -ret;
1326 } else {
1327 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1328 env->xcc &= ~PSR_CARRY;
1329 #else
1330 env->psr &= ~PSR_CARRY;
1331 #endif
1332 }
1333 env->regwptr[0] = ret;
1334 /* next instruction */
1335 env->pc = env->npc;
1336 env->npc = env->npc + 4;
1337 break;
1338 case 0x83: /* flush windows */
1339 #ifdef TARGET_ABI32
1340 case 0x103:
1341 #endif
1342 flush_windows(env);
1343 /* next instruction */
1344 env->pc = env->npc;
1345 env->npc = env->npc + 4;
1346 break;
1347 #ifndef TARGET_SPARC64
1348 case TT_WIN_OVF: /* window overflow */
1349 save_window(env);
1350 break;
1351 case TT_WIN_UNF: /* window underflow */
1352 restore_window(env);
1353 break;
1354 case TT_TFAULT:
1355 case TT_DFAULT:
1356 {
1357 info.si_signo = TARGET_SIGSEGV;
1358 info.si_errno = 0;
1359 /* XXX: check env->error_code */
1360 info.si_code = TARGET_SEGV_MAPERR;
1361 info._sifields._sigfault._addr = env->mmuregs[4];
1362 queue_signal(env, info.si_signo, &info);
1363 }
1364 break;
1365 #else
1366 case TT_SPILL: /* window overflow */
1367 save_window(env);
1368 break;
1369 case TT_FILL: /* window underflow */
1370 restore_window(env);
1371 break;
1372 case TT_TFAULT:
1373 case TT_DFAULT:
1374 {
1375 info.si_signo = TARGET_SIGSEGV;
1376 info.si_errno = 0;
1377 /* XXX: check env->error_code */
1378 info.si_code = TARGET_SEGV_MAPERR;
1379 if (trapnr == TT_DFAULT)
1380 info._sifields._sigfault._addr = env->dmmuregs[4];
1381 else
1382 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1383 queue_signal(env, info.si_signo, &info);
1384 }
1385 break;
1386 #ifndef TARGET_ABI32
1387 case 0x16e:
1388 flush_windows(env);
1389 sparc64_get_context(env);
1390 break;
1391 case 0x16f:
1392 flush_windows(env);
1393 sparc64_set_context(env);
1394 break;
1395 #endif
1396 #endif
1397 case EXCP_INTERRUPT:
1398 /* just indicate that signals should be handled asap */
1399 break;
1400 case TT_ILL_INSN:
1401 {
1402 info.si_signo = TARGET_SIGILL;
1403 info.si_errno = 0;
1404 info.si_code = TARGET_ILL_ILLOPC;
1405 info._sifields._sigfault._addr = env->pc;
1406 queue_signal(env, info.si_signo, &info);
1407 }
1408 break;
1409 case EXCP_DEBUG:
1410 {
1411 int sig;
1412
1413 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1414 if (sig)
1415 {
1416 info.si_signo = sig;
1417 info.si_errno = 0;
1418 info.si_code = TARGET_TRAP_BRKPT;
1419 queue_signal(env, info.si_signo, &info);
1420 }
1421 }
1422 break;
1423 default:
1424 printf ("Unhandled trap: 0x%x\n", trapnr);
1425 cpu_dump_state(cs, stderr, fprintf, 0);
1426 exit (1);
1427 }
1428 process_pending_signals (env);
1429 }
1430 }
1431
1432 #endif
1433
1434 #ifdef TARGET_PPC
1435 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1436 {
1437 /* TO FIX */
1438 return 0;
1439 }
1440
1441 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1442 {
1443 return cpu_ppc_get_tb(env);
1444 }
1445
1446 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1447 {
1448 return cpu_ppc_get_tb(env) >> 32;
1449 }
1450
1451 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1452 {
1453 return cpu_ppc_get_tb(env);
1454 }
1455
1456 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1457 {
1458 return cpu_ppc_get_tb(env) >> 32;
1459 }
1460
1461 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1462 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1463
1464 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1465 {
1466 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1467 }
1468
1469 /* XXX: to be fixed */
1470 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1471 {
1472 return -1;
1473 }
1474
1475 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1476 {
1477 return -1;
1478 }
1479
1480 #define EXCP_DUMP(env, fmt, ...) \
1481 do { \
1482 CPUState *cs = ENV_GET_CPU(env); \
1483 fprintf(stderr, fmt , ## __VA_ARGS__); \
1484 cpu_dump_state(cs, stderr, fprintf, 0); \
1485 qemu_log(fmt, ## __VA_ARGS__); \
1486 if (qemu_log_enabled()) { \
1487 log_cpu_state(cs, 0); \
1488 } \
1489 } while (0)
1490
1491 static int do_store_exclusive(CPUPPCState *env)
1492 {
1493 target_ulong addr;
1494 target_ulong page_addr;
1495 target_ulong val;
1496 int flags;
1497 int segv = 0;
1498
1499 addr = env->reserve_ea;
1500 page_addr = addr & TARGET_PAGE_MASK;
1501 start_exclusive();
1502 mmap_lock();
1503 flags = page_get_flags(page_addr);
1504 if ((flags & PAGE_READ) == 0) {
1505 segv = 1;
1506 } else {
1507 int reg = env->reserve_info & 0x1f;
1508 int size = (env->reserve_info >> 5) & 0xf;
1509 int stored = 0;
1510
1511 if (addr == env->reserve_addr) {
1512 switch (size) {
1513 case 1: segv = get_user_u8(val, addr); break;
1514 case 2: segv = get_user_u16(val, addr); break;
1515 case 4: segv = get_user_u32(val, addr); break;
1516 #if defined(TARGET_PPC64)
1517 case 8: segv = get_user_u64(val, addr); break;
1518 #endif
1519 default: abort();
1520 }
1521 if (!segv && val == env->reserve_val) {
1522 val = env->gpr[reg];
1523 switch (size) {
1524 case 1: segv = put_user_u8(val, addr); break;
1525 case 2: segv = put_user_u16(val, addr); break;
1526 case 4: segv = put_user_u32(val, addr); break;
1527 #if defined(TARGET_PPC64)
1528 case 8: segv = put_user_u64(val, addr); break;
1529 #endif
1530 default: abort();
1531 }
1532 if (!segv) {
1533 stored = 1;
1534 }
1535 }
1536 }
1537 env->crf[0] = (stored << 1) | xer_so;
1538 env->reserve_addr = (target_ulong)-1;
1539 }
1540 if (!segv) {
1541 env->nip += 4;
1542 }
1543 mmap_unlock();
1544 end_exclusive();
1545 return segv;
1546 }
1547
1548 void cpu_loop(CPUPPCState *env)
1549 {
1550 CPUState *cs = CPU(ppc_env_get_cpu(env));
1551 target_siginfo_t info;
1552 int trapnr;
1553 target_ulong ret;
1554
1555 for(;;) {
1556 cpu_exec_start(cs);
1557 trapnr = cpu_ppc_exec(env);
1558 cpu_exec_end(cs);
1559 switch(trapnr) {
1560 case POWERPC_EXCP_NONE:
1561 /* Just go on */
1562 break;
1563 case POWERPC_EXCP_CRITICAL: /* Critical input */
1564 cpu_abort(env, "Critical interrupt while in user mode. "
1565 "Aborting\n");
1566 break;
1567 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1568 cpu_abort(env, "Machine check exception while in user mode. "
1569 "Aborting\n");
1570 break;
1571 case POWERPC_EXCP_DSI: /* Data storage exception */
1572 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1573 env->spr[SPR_DAR]);
1574 /* XXX: check this. Seems bugged */
1575 switch (env->error_code & 0xFF000000) {
1576 case 0x40000000:
1577 info.si_signo = TARGET_SIGSEGV;
1578 info.si_errno = 0;
1579 info.si_code = TARGET_SEGV_MAPERR;
1580 break;
1581 case 0x04000000:
1582 info.si_signo = TARGET_SIGILL;
1583 info.si_errno = 0;
1584 info.si_code = TARGET_ILL_ILLADR;
1585 break;
1586 case 0x08000000:
1587 info.si_signo = TARGET_SIGSEGV;
1588 info.si_errno = 0;
1589 info.si_code = TARGET_SEGV_ACCERR;
1590 break;
1591 default:
1592 /* Let's send a regular segfault... */
1593 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1594 env->error_code);
1595 info.si_signo = TARGET_SIGSEGV;
1596 info.si_errno = 0;
1597 info.si_code = TARGET_SEGV_MAPERR;
1598 break;
1599 }
1600 info._sifields._sigfault._addr = env->nip;
1601 queue_signal(env, info.si_signo, &info);
1602 break;
1603 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1604 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1605 "\n", env->spr[SPR_SRR0]);
1606 /* XXX: check this */
1607 switch (env->error_code & 0xFF000000) {
1608 case 0x40000000:
1609 info.si_signo = TARGET_SIGSEGV;
1610 info.si_errno = 0;
1611 info.si_code = TARGET_SEGV_MAPERR;
1612 break;
1613 case 0x10000000:
1614 case 0x08000000:
1615 info.si_signo = TARGET_SIGSEGV;
1616 info.si_errno = 0;
1617 info.si_code = TARGET_SEGV_ACCERR;
1618 break;
1619 default:
1620 /* Let's send a regular segfault... */
1621 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1622 env->error_code);
1623 info.si_signo = TARGET_SIGSEGV;
1624 info.si_errno = 0;
1625 info.si_code = TARGET_SEGV_MAPERR;
1626 break;
1627 }
1628 info._sifields._sigfault._addr = env->nip - 4;
1629 queue_signal(env, info.si_signo, &info);
1630 break;
1631 case POWERPC_EXCP_EXTERNAL: /* External input */
1632 cpu_abort(env, "External interrupt while in user mode. "
1633 "Aborting\n");
1634 break;
1635 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1636 EXCP_DUMP(env, "Unaligned memory access\n");
1637 /* XXX: check this */
1638 info.si_signo = TARGET_SIGBUS;
1639 info.si_errno = 0;
1640 info.si_code = TARGET_BUS_ADRALN;
1641 info._sifields._sigfault._addr = env->nip - 4;
1642 queue_signal(env, info.si_signo, &info);
1643 break;
1644 case POWERPC_EXCP_PROGRAM: /* Program exception */
1645 /* XXX: check this */
1646 switch (env->error_code & ~0xF) {
1647 case POWERPC_EXCP_FP:
1648 EXCP_DUMP(env, "Floating point program exception\n");
1649 info.si_signo = TARGET_SIGFPE;
1650 info.si_errno = 0;
1651 switch (env->error_code & 0xF) {
1652 case POWERPC_EXCP_FP_OX:
1653 info.si_code = TARGET_FPE_FLTOVF;
1654 break;
1655 case POWERPC_EXCP_FP_UX:
1656 info.si_code = TARGET_FPE_FLTUND;
1657 break;
1658 case POWERPC_EXCP_FP_ZX:
1659 case POWERPC_EXCP_FP_VXZDZ:
1660 info.si_code = TARGET_FPE_FLTDIV;
1661 break;
1662 case POWERPC_EXCP_FP_XX:
1663 info.si_code = TARGET_FPE_FLTRES;
1664 break;
1665 case POWERPC_EXCP_FP_VXSOFT:
1666 info.si_code = TARGET_FPE_FLTINV;
1667 break;
1668 case POWERPC_EXCP_FP_VXSNAN:
1669 case POWERPC_EXCP_FP_VXISI:
1670 case POWERPC_EXCP_FP_VXIDI:
1671 case POWERPC_EXCP_FP_VXIMZ:
1672 case POWERPC_EXCP_FP_VXVC:
1673 case POWERPC_EXCP_FP_VXSQRT:
1674 case POWERPC_EXCP_FP_VXCVI:
1675 info.si_code = TARGET_FPE_FLTSUB;
1676 break;
1677 default:
1678 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1679 env->error_code);
1680 break;
1681 }
1682 break;
1683 case POWERPC_EXCP_INVAL:
1684 EXCP_DUMP(env, "Invalid instruction\n");
1685 info.si_signo = TARGET_SIGILL;
1686 info.si_errno = 0;
1687 switch (env->error_code & 0xF) {
1688 case POWERPC_EXCP_INVAL_INVAL:
1689 info.si_code = TARGET_ILL_ILLOPC;
1690 break;
1691 case POWERPC_EXCP_INVAL_LSWX:
1692 info.si_code = TARGET_ILL_ILLOPN;
1693 break;
1694 case POWERPC_EXCP_INVAL_SPR:
1695 info.si_code = TARGET_ILL_PRVREG;
1696 break;
1697 case POWERPC_EXCP_INVAL_FP:
1698 info.si_code = TARGET_ILL_COPROC;
1699 break;
1700 default:
1701 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1702 env->error_code & 0xF);
1703 info.si_code = TARGET_ILL_ILLADR;
1704 break;
1705 }
1706 break;
1707 case POWERPC_EXCP_PRIV:
1708 EXCP_DUMP(env, "Privilege violation\n");
1709 info.si_signo = TARGET_SIGILL;
1710 info.si_errno = 0;
1711 switch (env->error_code & 0xF) {
1712 case POWERPC_EXCP_PRIV_OPC:
1713 info.si_code = TARGET_ILL_PRVOPC;
1714 break;
1715 case POWERPC_EXCP_PRIV_REG:
1716 info.si_code = TARGET_ILL_PRVREG;
1717 break;
1718 default:
1719 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1720 env->error_code & 0xF);
1721 info.si_code = TARGET_ILL_PRVOPC;
1722 break;
1723 }
1724 break;
1725 case POWERPC_EXCP_TRAP:
1726 cpu_abort(env, "Tried to call a TRAP\n");
1727 break;
1728 default:
1729 /* Should not happen ! */
1730 cpu_abort(env, "Unknown program exception (%02x)\n",
1731 env->error_code);
1732 break;
1733 }
1734 info._sifields._sigfault._addr = env->nip - 4;
1735 queue_signal(env, info.si_signo, &info);
1736 break;
1737 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1738 EXCP_DUMP(env, "No floating point allowed\n");
1739 info.si_signo = TARGET_SIGILL;
1740 info.si_errno = 0;
1741 info.si_code = TARGET_ILL_COPROC;
1742 info._sifields._sigfault._addr = env->nip - 4;
1743 queue_signal(env, info.si_signo, &info);
1744 break;
1745 case POWERPC_EXCP_SYSCALL: /* System call exception */
1746 cpu_abort(env, "Syscall exception while in user mode. "
1747 "Aborting\n");
1748 break;
1749 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1750 EXCP_DUMP(env, "No APU instruction allowed\n");
1751 info.si_signo = TARGET_SIGILL;
1752 info.si_errno = 0;
1753 info.si_code = TARGET_ILL_COPROC;
1754 info._sifields._sigfault._addr = env->nip - 4;
1755 queue_signal(env, info.si_signo, &info);
1756 break;
1757 case POWERPC_EXCP_DECR: /* Decrementer exception */
1758 cpu_abort(env, "Decrementer interrupt while in user mode. "
1759 "Aborting\n");
1760 break;
1761 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1762 cpu_abort(env, "Fix interval timer interrupt while in user mode. "
1763 "Aborting\n");
1764 break;
1765 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1766 cpu_abort(env, "Watchdog timer interrupt while in user mode. "
1767 "Aborting\n");
1768 break;
1769 case POWERPC_EXCP_DTLB: /* Data TLB error */
1770 cpu_abort(env, "Data TLB exception while in user mode. "
1771 "Aborting\n");
1772 break;
1773 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1774 cpu_abort(env, "Instruction TLB exception while in user mode. "
1775 "Aborting\n");
1776 break;
1777 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1778 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1779 info.si_signo = TARGET_SIGILL;
1780 info.si_errno = 0;
1781 info.si_code = TARGET_ILL_COPROC;
1782 info._sifields._sigfault._addr = env->nip - 4;
1783 queue_signal(env, info.si_signo, &info);
1784 break;
1785 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1786 cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
1787 break;
1788 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1789 cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
1790 break;
1791 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1792 cpu_abort(env, "Performance monitor exception not handled\n");
1793 break;
1794 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1795 cpu_abort(env, "Doorbell interrupt while in user mode. "
1796 "Aborting\n");
1797 break;
1798 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1799 cpu_abort(env, "Doorbell critical interrupt while in user mode. "
1800 "Aborting\n");
1801 break;
1802 case POWERPC_EXCP_RESET: /* System reset exception */
1803 cpu_abort(env, "Reset interrupt while in user mode. "
1804 "Aborting\n");
1805 break;
1806 case POWERPC_EXCP_DSEG: /* Data segment exception */
1807 cpu_abort(env, "Data segment exception while in user mode. "
1808 "Aborting\n");
1809 break;
1810 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1811 cpu_abort(env, "Instruction segment exception "
1812 "while in user mode. Aborting\n");
1813 break;
1814 /* PowerPC 64 with hypervisor mode support */
1815 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1816 cpu_abort(env, "Hypervisor decrementer interrupt "
1817 "while in user mode. Aborting\n");
1818 break;
1819 case POWERPC_EXCP_TRACE: /* Trace exception */
1820 /* Nothing to do:
1821 * we use this exception to emulate step-by-step execution mode.
1822 */
1823 break;
1824 /* PowerPC 64 with hypervisor mode support */
1825 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1826 cpu_abort(env, "Hypervisor data storage exception "
1827 "while in user mode. Aborting\n");
1828 break;
1829 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1830 cpu_abort(env, "Hypervisor instruction storage exception "
1831 "while in user mode. Aborting\n");
1832 break;
1833 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1834 cpu_abort(env, "Hypervisor data segment exception "
1835 "while in user mode. Aborting\n");
1836 break;
1837 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1838 cpu_abort(env, "Hypervisor instruction segment exception "
1839 "while in user mode. Aborting\n");
1840 break;
1841 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1842 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1843 info.si_signo = TARGET_SIGILL;
1844 info.si_errno = 0;
1845 info.si_code = TARGET_ILL_COPROC;
1846 info._sifields._sigfault._addr = env->nip - 4;
1847 queue_signal(env, info.si_signo, &info);
1848 break;
1849 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1850 cpu_abort(env, "Programmable interval timer interrupt "
1851 "while in user mode. Aborting\n");
1852 break;
1853 case POWERPC_EXCP_IO: /* IO error exception */
1854 cpu_abort(env, "IO error exception while in user mode. "
1855 "Aborting\n");
1856 break;
1857 case POWERPC_EXCP_RUNM: /* Run mode exception */
1858 cpu_abort(env, "Run mode exception while in user mode. "
1859 "Aborting\n");
1860 break;
1861 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1862 cpu_abort(env, "Emulation trap exception not handled\n");
1863 break;
1864 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1865 cpu_abort(env, "Instruction fetch TLB exception "
1866 "while in user-mode. Aborting");
1867 break;
1868 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1869 cpu_abort(env, "Data load TLB exception while in user-mode. "
1870 "Aborting");
1871 break;
1872 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1873 cpu_abort(env, "Data store TLB exception while in user-mode. "
1874 "Aborting");
1875 break;
1876 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1877 cpu_abort(env, "Floating-point assist exception not handled\n");
1878 break;
1879 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1880 cpu_abort(env, "Instruction address breakpoint exception "
1881 "not handled\n");
1882 break;
1883 case POWERPC_EXCP_SMI: /* System management interrupt */
1884 cpu_abort(env, "System management interrupt while in user mode. "
1885 "Aborting\n");
1886 break;
1887 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1888 cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
1889 "Aborting\n");
1890 break;
1891 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1892 cpu_abort(env, "Performance monitor exception not handled\n");
1893 break;
1894 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1895 cpu_abort(env, "Vector assist exception not handled\n");
1896 break;
1897 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1898 cpu_abort(env, "Soft patch exception not handled\n");
1899 break;
1900 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1901 cpu_abort(env, "Maintenance exception while in user mode. "
1902 "Aborting\n");
1903 break;
1904 case POWERPC_EXCP_STOP: /* stop translation */
1905 /* We did invalidate the instruction cache. Go on */
1906 break;
1907 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1908 /* We just stopped because of a branch. Go on */
1909 break;
1910 case POWERPC_EXCP_SYSCALL_USER:
1911 /* system call in user-mode emulation */
1912 /* WARNING:
1913 * PPC ABI uses overflow flag in cr0 to signal an error
1914 * in syscalls.
1915 */
1916 env->crf[0] &= ~0x1;
1917 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1918 env->gpr[5], env->gpr[6], env->gpr[7],
1919 env->gpr[8], 0, 0);
1920 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1921 /* Returning from a successful sigreturn syscall.
1922 Avoid corrupting register state. */
1923 break;
1924 }
1925 if (ret > (target_ulong)(-515)) {
1926 env->crf[0] |= 0x1;
1927 ret = -ret;
1928 }
1929 env->gpr[3] = ret;
1930 break;
1931 case POWERPC_EXCP_STCX:
1932 if (do_store_exclusive(env)) {
1933 info.si_signo = TARGET_SIGSEGV;
1934 info.si_errno = 0;
1935 info.si_code = TARGET_SEGV_MAPERR;
1936 info._sifields._sigfault._addr = env->nip;
1937 queue_signal(env, info.si_signo, &info);
1938 }
1939 break;
1940 case EXCP_DEBUG:
1941 {
1942 int sig;
1943
1944 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1945 if (sig) {
1946 info.si_signo = sig;
1947 info.si_errno = 0;
1948 info.si_code = TARGET_TRAP_BRKPT;
1949 queue_signal(env, info.si_signo, &info);
1950 }
1951 }
1952 break;
1953 case EXCP_INTERRUPT:
1954 /* just indicate that signals should be handled asap */
1955 break;
1956 default:
1957 cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
1958 break;
1959 }
1960 process_pending_signals(env);
1961 }
1962 }
1963 #endif
1964
1965 #ifdef TARGET_MIPS
1966
1967 # ifdef TARGET_ABI_MIPSO32
1968 # define MIPS_SYS(name, args) args,
1969 static const uint8_t mips_syscall_args[] = {
1970 MIPS_SYS(sys_syscall , 8) /* 4000 */
1971 MIPS_SYS(sys_exit , 1)
1972 MIPS_SYS(sys_fork , 0)
1973 MIPS_SYS(sys_read , 3)
1974 MIPS_SYS(sys_write , 3)
1975 MIPS_SYS(sys_open , 3) /* 4005 */
1976 MIPS_SYS(sys_close , 1)
1977 MIPS_SYS(sys_waitpid , 3)
1978 MIPS_SYS(sys_creat , 2)
1979 MIPS_SYS(sys_link , 2)
1980 MIPS_SYS(sys_unlink , 1) /* 4010 */
1981 MIPS_SYS(sys_execve , 0)
1982 MIPS_SYS(sys_chdir , 1)
1983 MIPS_SYS(sys_time , 1)
1984 MIPS_SYS(sys_mknod , 3)
1985 MIPS_SYS(sys_chmod , 2) /* 4015 */
1986 MIPS_SYS(sys_lchown , 3)
1987 MIPS_SYS(sys_ni_syscall , 0)
1988 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1989 MIPS_SYS(sys_lseek , 3)
1990 MIPS_SYS(sys_getpid , 0) /* 4020 */
1991 MIPS_SYS(sys_mount , 5)
1992 MIPS_SYS(sys_umount , 1)
1993 MIPS_SYS(sys_setuid , 1)
1994 MIPS_SYS(sys_getuid , 0)
1995 MIPS_SYS(sys_stime , 1) /* 4025 */
1996 MIPS_SYS(sys_ptrace , 4)
1997 MIPS_SYS(sys_alarm , 1)
1998 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
1999 MIPS_SYS(sys_pause , 0)
2000 MIPS_SYS(sys_utime , 2) /* 4030 */
2001 MIPS_SYS(sys_ni_syscall , 0)
2002 MIPS_SYS(sys_ni_syscall , 0)
2003 MIPS_SYS(sys_access , 2)
2004 MIPS_SYS(sys_nice , 1)
2005 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2006 MIPS_SYS(sys_sync , 0)
2007 MIPS_SYS(sys_kill , 2)
2008 MIPS_SYS(sys_rename , 2)
2009 MIPS_SYS(sys_mkdir , 2)
2010 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2011 MIPS_SYS(sys_dup , 1)
2012 MIPS_SYS(sys_pipe , 0)
2013 MIPS_SYS(sys_times , 1)
2014 MIPS_SYS(sys_ni_syscall , 0)
2015 MIPS_SYS(sys_brk , 1) /* 4045 */
2016 MIPS_SYS(sys_setgid , 1)
2017 MIPS_SYS(sys_getgid , 0)
2018 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2019 MIPS_SYS(sys_geteuid , 0)
2020 MIPS_SYS(sys_getegid , 0) /* 4050 */
2021 MIPS_SYS(sys_acct , 0)
2022 MIPS_SYS(sys_umount2 , 2)
2023 MIPS_SYS(sys_ni_syscall , 0)
2024 MIPS_SYS(sys_ioctl , 3)
2025 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2026 MIPS_SYS(sys_ni_syscall , 2)
2027 MIPS_SYS(sys_setpgid , 2)
2028 MIPS_SYS(sys_ni_syscall , 0)
2029 MIPS_SYS(sys_olduname , 1)
2030 MIPS_SYS(sys_umask , 1) /* 4060 */
2031 MIPS_SYS(sys_chroot , 1)
2032 MIPS_SYS(sys_ustat , 2)
2033 MIPS_SYS(sys_dup2 , 2)
2034 MIPS_SYS(sys_getppid , 0)
2035 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2036 MIPS_SYS(sys_setsid , 0)
2037 MIPS_SYS(sys_sigaction , 3)
2038 MIPS_SYS(sys_sgetmask , 0)
2039 MIPS_SYS(sys_ssetmask , 1)
2040 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2041 MIPS_SYS(sys_setregid , 2)
2042 MIPS_SYS(sys_sigsuspend , 0)
2043 MIPS_SYS(sys_sigpending , 1)
2044 MIPS_SYS(sys_sethostname , 2)
2045 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2046 MIPS_SYS(sys_getrlimit , 2)
2047 MIPS_SYS(sys_getrusage , 2)
2048 MIPS_SYS(sys_gettimeofday, 2)
2049 MIPS_SYS(sys_settimeofday, 2)
2050 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2051 MIPS_SYS(sys_setgroups , 2)
2052 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2053 MIPS_SYS(sys_symlink , 2)
2054 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2055 MIPS_SYS(sys_readlink , 3) /* 4085 */
2056 MIPS_SYS(sys_uselib , 1)
2057 MIPS_SYS(sys_swapon , 2)
2058 MIPS_SYS(sys_reboot , 3)
2059 MIPS_SYS(old_readdir , 3)
2060 MIPS_SYS(old_mmap , 6) /* 4090 */
2061 MIPS_SYS(sys_munmap , 2)
2062 MIPS_SYS(sys_truncate , 2)
2063 MIPS_SYS(sys_ftruncate , 2)
2064 MIPS_SYS(sys_fchmod , 2)
2065 MIPS_SYS(sys_fchown , 3) /* 4095 */
2066 MIPS_SYS(sys_getpriority , 2)
2067 MIPS_SYS(sys_setpriority , 3)
2068 MIPS_SYS(sys_ni_syscall , 0)
2069 MIPS_SYS(sys_statfs , 2)
2070 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2071 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2072 MIPS_SYS(sys_socketcall , 2)
2073 MIPS_SYS(sys_syslog , 3)
2074 MIPS_SYS(sys_setitimer , 3)
2075 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2076 MIPS_SYS(sys_newstat , 2)
2077 MIPS_SYS(sys_newlstat , 2)
2078 MIPS_SYS(sys_newfstat , 2)
2079 MIPS_SYS(sys_uname , 1)
2080 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2081 MIPS_SYS(sys_vhangup , 0)
2082 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2083 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2084 MIPS_SYS(sys_wait4 , 4)
2085 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2086 MIPS_SYS(sys_sysinfo , 1)
2087 MIPS_SYS(sys_ipc , 6)
2088 MIPS_SYS(sys_fsync , 1)
2089 MIPS_SYS(sys_sigreturn , 0)
2090 MIPS_SYS(sys_clone , 6) /* 4120 */
2091 MIPS_SYS(sys_setdomainname, 2)
2092 MIPS_SYS(sys_newuname , 1)
2093 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2094 MIPS_SYS(sys_adjtimex , 1)
2095 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2096 MIPS_SYS(sys_sigprocmask , 3)
2097 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2098 MIPS_SYS(sys_init_module , 5)
2099 MIPS_SYS(sys_delete_module, 1)
2100 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2101 MIPS_SYS(sys_quotactl , 0)
2102 MIPS_SYS(sys_getpgid , 1)
2103 MIPS_SYS(sys_fchdir , 1)
2104 MIPS_SYS(sys_bdflush , 2)
2105 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2106 MIPS_SYS(sys_personality , 1)
2107 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2108 MIPS_SYS(sys_setfsuid , 1)
2109 MIPS_SYS(sys_setfsgid , 1)
2110 MIPS_SYS(sys_llseek , 5) /* 4140 */
2111 MIPS_SYS(sys_getdents , 3)
2112 MIPS_SYS(sys_select , 5)
2113 MIPS_SYS(sys_flock , 2)
2114 MIPS_SYS(sys_msync , 3)
2115 MIPS_SYS(sys_readv , 3) /* 4145 */
2116 MIPS_SYS(sys_writev , 3)
2117 MIPS_SYS(sys_cacheflush , 3)
2118 MIPS_SYS(sys_cachectl , 3)
2119 MIPS_SYS(sys_sysmips , 4)
2120 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2121 MIPS_SYS(sys_getsid , 1)
2122 MIPS_SYS(sys_fdatasync , 0)
2123 MIPS_SYS(sys_sysctl , 1)
2124 MIPS_SYS(sys_mlock , 2)
2125 MIPS_SYS(sys_munlock , 2) /* 4155 */
2126 MIPS_SYS(sys_mlockall , 1)
2127 MIPS_SYS(sys_munlockall , 0)
2128 MIPS_SYS(sys_sched_setparam, 2)
2129 MIPS_SYS(sys_sched_getparam, 2)
2130 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2131 MIPS_SYS(sys_sched_getscheduler, 1)
2132 MIPS_SYS(sys_sched_yield , 0)
2133 MIPS_SYS(sys_sched_get_priority_max, 1)
2134 MIPS_SYS(sys_sched_get_priority_min, 1)
2135 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2136 MIPS_SYS(sys_nanosleep, 2)
2137 MIPS_SYS(sys_mremap , 5)
2138 MIPS_SYS(sys_accept , 3)
2139 MIPS_SYS(sys_bind , 3)
2140 MIPS_SYS(sys_connect , 3) /* 4170 */
2141 MIPS_SYS(sys_getpeername , 3)
2142 MIPS_SYS(sys_getsockname , 3)
2143 MIPS_SYS(sys_getsockopt , 5)
2144 MIPS_SYS(sys_listen , 2)
2145 MIPS_SYS(sys_recv , 4) /* 4175 */
2146 MIPS_SYS(sys_recvfrom , 6)
2147 MIPS_SYS(sys_recvmsg , 3)
2148 MIPS_SYS(sys_send , 4)
2149 MIPS_SYS(sys_sendmsg , 3)
2150 MIPS_SYS(sys_sendto , 6) /* 4180 */
2151 MIPS_SYS(sys_setsockopt , 5)
2152 MIPS_SYS(sys_shutdown , 2)
2153 MIPS_SYS(sys_socket , 3)
2154 MIPS_SYS(sys_socketpair , 4)
2155 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2156 MIPS_SYS(sys_getresuid , 3)
2157 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2158 MIPS_SYS(sys_poll , 3)
2159 MIPS_SYS(sys_nfsservctl , 3)
2160 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2161 MIPS_SYS(sys_getresgid , 3)
2162 MIPS_SYS(sys_prctl , 5)
2163 MIPS_SYS(sys_rt_sigreturn, 0)
2164 MIPS_SYS(sys_rt_sigaction, 4)
2165 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2166 MIPS_SYS(sys_rt_sigpending, 2)
2167 MIPS_SYS(sys_rt_sigtimedwait, 4)
2168 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2169 MIPS_SYS(sys_rt_sigsuspend, 0)
2170 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2171 MIPS_SYS(sys_pwrite64 , 6)
2172 MIPS_SYS(sys_chown , 3)
2173 MIPS_SYS(sys_getcwd , 2)
2174 MIPS_SYS(sys_capget , 2)
2175 MIPS_SYS(sys_capset , 2) /* 4205 */
2176 MIPS_SYS(sys_sigaltstack , 2)
2177 MIPS_SYS(sys_sendfile , 4)
2178 MIPS_SYS(sys_ni_syscall , 0)
2179 MIPS_SYS(sys_ni_syscall , 0)
2180 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2181 MIPS_SYS(sys_truncate64 , 4)
2182 MIPS_SYS(sys_ftruncate64 , 4)
2183 MIPS_SYS(sys_stat64 , 2)
2184 MIPS_SYS(sys_lstat64 , 2)
2185 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2186 MIPS_SYS(sys_pivot_root , 2)
2187 MIPS_SYS(sys_mincore , 3)
2188 MIPS_SYS(sys_madvise , 3)
2189 MIPS_SYS(sys_getdents64 , 3)
2190 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2191 MIPS_SYS(sys_ni_syscall , 0)
2192 MIPS_SYS(sys_gettid , 0)
2193 MIPS_SYS(sys_readahead , 5)
2194 MIPS_SYS(sys_setxattr , 5)
2195 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2196 MIPS_SYS(sys_fsetxattr , 5)
2197 MIPS_SYS(sys_getxattr , 4)
2198 MIPS_SYS(sys_lgetxattr , 4)
2199 MIPS_SYS(sys_fgetxattr , 4)
2200 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2201 MIPS_SYS(sys_llistxattr , 3)
2202 MIPS_SYS(sys_flistxattr , 3)
2203 MIPS_SYS(sys_removexattr , 2)
2204 MIPS_SYS(sys_lremovexattr, 2)
2205 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2206 MIPS_SYS(sys_tkill , 2)
2207 MIPS_SYS(sys_sendfile64 , 5)
2208 MIPS_SYS(sys_futex , 6)
2209 MIPS_SYS(sys_sched_setaffinity, 3)
2210 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2211 MIPS_SYS(sys_io_setup , 2)
2212 MIPS_SYS(sys_io_destroy , 1)
2213 MIPS_SYS(sys_io_getevents, 5)
2214 MIPS_SYS(sys_io_submit , 3)
2215 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2216 MIPS_SYS(sys_exit_group , 1)
2217 MIPS_SYS(sys_lookup_dcookie, 3)
2218 MIPS_SYS(sys_epoll_create, 1)
2219 MIPS_SYS(sys_epoll_ctl , 4)
2220 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2221 MIPS_SYS(sys_remap_file_pages, 5)
2222 MIPS_SYS(sys_set_tid_address, 1)
2223 MIPS_SYS(sys_restart_syscall, 0)
2224 MIPS_SYS(sys_fadvise64_64, 7)
2225 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2226 MIPS_SYS(sys_fstatfs64 , 2)
2227 MIPS_SYS(sys_timer_create, 3)
2228 MIPS_SYS(sys_timer_settime, 4)
2229 MIPS_SYS(sys_timer_gettime, 2)
2230 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2231 MIPS_SYS(sys_timer_delete, 1)
2232 MIPS_SYS(sys_clock_settime, 2)
2233 MIPS_SYS(sys_clock_gettime, 2)
2234 MIPS_SYS(sys_clock_getres, 2)
2235 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2236 MIPS_SYS(sys_tgkill , 3)
2237 MIPS_SYS(sys_utimes , 2)
2238 MIPS_SYS(sys_mbind , 4)
2239 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2240 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2241 MIPS_SYS(sys_mq_open , 4)
2242 MIPS_SYS(sys_mq_unlink , 1)
2243 MIPS_SYS(sys_mq_timedsend, 5)
2244 MIPS_SYS(sys_mq_timedreceive, 5)
2245 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2246 MIPS_SYS(sys_mq_getsetattr, 3)
2247 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2248 MIPS_SYS(sys_waitid , 4)
2249 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2250 MIPS_SYS(sys_add_key , 5)
2251 MIPS_SYS(sys_request_key, 4)
2252 MIPS_SYS(sys_keyctl , 5)
2253 MIPS_SYS(sys_set_thread_area, 1)
2254 MIPS_SYS(sys_inotify_init, 0)
2255 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2256 MIPS_SYS(sys_inotify_rm_watch, 2)
2257 MIPS_SYS(sys_migrate_pages, 4)
2258 MIPS_SYS(sys_openat, 4)
2259 MIPS_SYS(sys_mkdirat, 3)
2260 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2261 MIPS_SYS(sys_fchownat, 5)
2262 MIPS_SYS(sys_futimesat, 3)
2263 MIPS_SYS(sys_fstatat64, 4)
2264 MIPS_SYS(sys_unlinkat, 3)
2265 MIPS_SYS(sys_renameat, 4) /* 4295 */
2266 MIPS_SYS(sys_linkat, 5)
2267 MIPS_SYS(sys_symlinkat, 3)
2268 MIPS_SYS(sys_readlinkat, 4)
2269 MIPS_SYS(sys_fchmodat, 3)
2270 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2271 MIPS_SYS(sys_pselect6, 6)
2272 MIPS_SYS(sys_ppoll, 5)
2273 MIPS_SYS(sys_unshare, 1)
2274 MIPS_SYS(sys_splice, 6)
2275 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2276 MIPS_SYS(sys_tee, 4)
2277 MIPS_SYS(sys_vmsplice, 4)
2278 MIPS_SYS(sys_move_pages, 6)
2279 MIPS_SYS(sys_set_robust_list, 2)
2280 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2281 MIPS_SYS(sys_kexec_load, 4)
2282 MIPS_SYS(sys_getcpu, 3)
2283 MIPS_SYS(sys_epoll_pwait, 6)
2284 MIPS_SYS(sys_ioprio_set, 3)
2285 MIPS_SYS(sys_ioprio_get, 2)
2286 MIPS_SYS(sys_utimensat, 4)
2287 MIPS_SYS(sys_signalfd, 3)
2288 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2289 MIPS_SYS(sys_eventfd, 1)
2290 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2291 MIPS_SYS(sys_timerfd_create, 2)
2292 MIPS_SYS(sys_timerfd_gettime, 2)
2293 MIPS_SYS(sys_timerfd_settime, 4)
2294 MIPS_SYS(sys_signalfd4, 4)
2295 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2296 MIPS_SYS(sys_epoll_create1, 1)
2297 MIPS_SYS(sys_dup3, 3)
2298 MIPS_SYS(sys_pipe2, 2)
2299 MIPS_SYS(sys_inotify_init1, 1)
2300 MIPS_SYS(sys_preadv, 6) /* 4330 */
2301 MIPS_SYS(sys_pwritev, 6)
2302 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2303 MIPS_SYS(sys_perf_event_open, 5)
2304 MIPS_SYS(sys_accept4, 4)
2305 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2306 MIPS_SYS(sys_fanotify_init, 2)
2307 MIPS_SYS(sys_fanotify_mark, 6)
2308 MIPS_SYS(sys_prlimit64, 4)
2309 MIPS_SYS(sys_name_to_handle_at, 5)
2310 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2311 MIPS_SYS(sys_clock_adjtime, 2)
2312 MIPS_SYS(sys_syncfs, 1)
2313 };
2314 # undef MIPS_SYS
2315 # endif /* O32 */
2316
2317 static int do_store_exclusive(CPUMIPSState *env)
2318 {
2319 target_ulong addr;
2320 target_ulong page_addr;
2321 target_ulong val;
2322 int flags;
2323 int segv = 0;
2324 int reg;
2325 int d;
2326
2327 addr = env->lladdr;
2328 page_addr = addr & TARGET_PAGE_MASK;
2329 start_exclusive();
2330 mmap_lock();
2331 flags = page_get_flags(page_addr);
2332 if ((flags & PAGE_READ) == 0) {
2333 segv = 1;
2334 } else {
2335 reg = env->llreg & 0x1f;
2336 d = (env->llreg & 0x20) != 0;
2337 if (d) {
2338 segv = get_user_s64(val, addr);
2339 } else {
2340 segv = get_user_s32(val, addr);
2341 }
2342 if (!segv) {
2343 if (val != env->llval) {
2344 env->active_tc.gpr[reg] = 0;
2345 } else {
2346 if (d) {
2347 segv = put_user_u64(env->llnewval, addr);
2348 } else {
2349 segv = put_user_u32(env->llnewval, addr);
2350 }
2351 if (!segv) {
2352 env->active_tc.gpr[reg] = 1;
2353 }
2354 }
2355 }
2356 }
2357 env->lladdr = -1;
2358 if (!segv) {
2359 env->active_tc.PC += 4;
2360 }
2361 mmap_unlock();
2362 end_exclusive();
2363 return segv;
2364 }
2365
2366 /* Break codes */
2367 enum {
2368 BRK_OVERFLOW = 6,
2369 BRK_DIVZERO = 7
2370 };
2371
2372 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2373 unsigned int code)
2374 {
2375 int ret = -1;
2376
2377 switch (code) {
2378 case BRK_OVERFLOW:
2379 case BRK_DIVZERO:
2380 info->si_signo = TARGET_SIGFPE;
2381 info->si_errno = 0;
2382 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2383 queue_signal(env, info->si_signo, &*info);
2384 ret = 0;
2385 break;
2386 default:
2387 break;
2388 }
2389
2390 return ret;
2391 }
2392
2393 void cpu_loop(CPUMIPSState *env)
2394 {
2395 CPUState *cs = CPU(mips_env_get_cpu(env));
2396 target_siginfo_t info;
2397 int trapnr;
2398 abi_long ret;
2399 # ifdef TARGET_ABI_MIPSO32
2400 unsigned int syscall_num;
2401 # endif
2402
2403 for(;;) {
2404 cpu_exec_start(cs);
2405 trapnr = cpu_mips_exec(env);
2406 cpu_exec_end(cs);
2407 switch(trapnr) {
2408 case EXCP_SYSCALL:
2409 env->active_tc.PC += 4;
2410 # ifdef TARGET_ABI_MIPSO32
2411 syscall_num = env->active_tc.gpr[2] - 4000;
2412 if (syscall_num >= sizeof(mips_syscall_args)) {
2413 ret = -TARGET_ENOSYS;
2414 } else {
2415 int nb_args;
2416 abi_ulong sp_reg;
2417 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2418
2419 nb_args = mips_syscall_args[syscall_num];
2420 sp_reg = env->active_tc.gpr[29];
2421 switch (nb_args) {
2422 /* these arguments are taken from the stack */
2423 case 8:
2424 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2425 goto done_syscall;
2426 }
2427 case 7:
2428 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2429 goto done_syscall;
2430 }
2431 case 6:
2432 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2433 goto done_syscall;
2434 }
2435 case 5:
2436 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2437 goto done_syscall;
2438 }
2439 default:
2440 break;
2441 }
2442 ret = do_syscall(env, env->active_tc.gpr[2],
2443 env->active_tc.gpr[4],
2444 env->active_tc.gpr[5],
2445 env->active_tc.gpr[6],
2446 env->active_tc.gpr[7],
2447 arg5, arg6, arg7, arg8);
2448 }
2449 done_syscall:
2450 # else
2451 ret = do_syscall(env, env->active_tc.gpr[2],
2452 env->active_tc.gpr[4], env->active_tc.gpr[5],
2453 env->active_tc.gpr[6], env->active_tc.gpr[7],
2454 env->active_tc.gpr[8], env->active_tc.gpr[9],
2455 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2456 # endif /* O32 */
2457 if (ret == -TARGET_QEMU_ESIGRETURN) {
2458 /* Returning from a successful sigreturn syscall.
2459 Avoid clobbering register state. */
2460 break;
2461 }
2462 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2463 env->active_tc.gpr[7] = 1; /* error flag */
2464 ret = -ret;
2465 } else {
2466 env->active_tc.gpr[7] = 0; /* error flag */
2467 }
2468 env->active_tc.gpr[2] = ret;
2469 break;
2470 case EXCP_TLBL:
2471 case EXCP_TLBS:
2472 case EXCP_AdEL:
2473 case EXCP_AdES:
2474 info.si_signo = TARGET_SIGSEGV;
2475 info.si_errno = 0;
2476 /* XXX: check env->error_code */
2477 info.si_code = TARGET_SEGV_MAPERR;
2478 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2479 queue_signal(env, info.si_signo, &info);
2480 break;
2481 case EXCP_CpU:
2482 case EXCP_RI:
2483 info.si_signo = TARGET_SIGILL;
2484 info.si_errno = 0;
2485 info.si_code = 0;
2486 queue_signal(env, info.si_signo, &info);
2487 break;
2488 case EXCP_INTERRUPT:
2489 /* just indicate that signals should be handled asap */
2490 break;
2491 case EXCP_DEBUG:
2492 {
2493 int sig;
2494
2495 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2496 if (sig)
2497 {
2498 info.si_signo = sig;
2499 info.si_errno = 0;
2500 info.si_code = TARGET_TRAP_BRKPT;
2501 queue_signal(env, info.si_signo, &info);
2502 }
2503 }
2504 break;
2505 case EXCP_SC:
2506 if (do_store_exclusive(env)) {
2507 info.si_signo = TARGET_SIGSEGV;
2508 info.si_errno = 0;
2509 info.si_code = TARGET_SEGV_MAPERR;
2510 info._sifields._sigfault._addr = env->active_tc.PC;
2511 queue_signal(env, info.si_signo, &info);
2512 }
2513 break;
2514 case EXCP_DSPDIS:
2515 info.si_signo = TARGET_SIGILL;
2516 info.si_errno = 0;
2517 info.si_code = TARGET_ILL_ILLOPC;
2518 queue_signal(env, info.si_signo, &info);
2519 break;
2520 /* The code below was inspired by the MIPS Linux kernel trap
2521 * handling code in arch/mips/kernel/traps.c.
2522 */
2523 case EXCP_BREAK:
2524 {
2525 abi_ulong trap_instr;
2526 unsigned int code;
2527
2528 if (env->hflags & MIPS_HFLAG_M16) {
2529 if (env->insn_flags & ASE_MICROMIPS) {
2530 /* microMIPS mode */
2531 ret = get_user_u16(trap_instr, env->active_tc.PC);
2532 if (ret != 0) {
2533 goto error;
2534 }
2535
2536 if ((trap_instr >> 10) == 0x11) {
2537 /* 16-bit instruction */
2538 code = trap_instr & 0xf;
2539 } else {
2540 /* 32-bit instruction */
2541 abi_ulong instr_lo;
2542
2543 ret = get_user_u16(instr_lo,
2544 env->active_tc.PC + 2);
2545 if (ret != 0) {
2546 goto error;
2547 }
2548 trap_instr = (trap_instr << 16) | instr_lo;
2549 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2550 /* Unfortunately, microMIPS also suffers from
2551 the old assembler bug... */
2552 if (code >= (1 << 10)) {
2553 code >>= 10;
2554 }
2555 }
2556 } else {
2557 /* MIPS16e mode */
2558 ret = get_user_u16(trap_instr, env->active_tc.PC);
2559 if (ret != 0) {
2560 goto error;
2561 }
2562 code = (trap_instr >> 6) & 0x3f;
2563 }
2564 } else {
2565 ret = get_user_ual(trap_instr, env->active_tc.PC);
2566 if (ret != 0) {
2567 goto error;
2568 }
2569
2570 /* As described in the original Linux kernel code, the
2571 * below checks on 'code' are to work around an old
2572 * assembly bug.
2573 */
2574 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2575 if (code >= (1 << 10)) {
2576 code >>= 10;
2577 }
2578 }
2579
2580 if (do_break(env, &info, code) != 0) {
2581 goto error;
2582 }
2583 }
2584 break;
2585 case EXCP_TRAP:
2586 {
2587 abi_ulong trap_instr;
2588 unsigned int code = 0;
2589
2590 if (env->hflags & MIPS_HFLAG_M16) {
2591 /* microMIPS mode */
2592 abi_ulong instr[2];
2593
2594 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2595 get_user_u16(instr[1], env->active_tc.PC + 2);
2596
2597 trap_instr = (instr[0] << 16) | instr[1];
2598 } else {
2599 ret = get_user_ual(trap_instr, env->active_tc.PC);
2600 }
2601
2602 if (ret != 0) {
2603 goto error;
2604 }
2605
2606 /* The immediate versions don't provide a code. */
2607 if (!(trap_instr & 0xFC000000)) {
2608 if (env->hflags & MIPS_HFLAG_M16) {
2609 /* microMIPS mode */
2610 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2611 } else {
2612 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2613 }
2614 }
2615
2616 if (do_break(env, &info, code) != 0) {
2617 goto error;
2618 }
2619 }
2620 break;
2621 default:
2622 error:
2623 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2624 trapnr);
2625 cpu_dump_state(cs, stderr, fprintf, 0);
2626 abort();
2627 }
2628 process_pending_signals(env);
2629 }
2630 }
2631 #endif
2632
2633 #ifdef TARGET_OPENRISC
2634
2635 void cpu_loop(CPUOpenRISCState *env)
2636 {
2637 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2638 int trapnr, gdbsig;
2639
2640 for (;;) {
2641 trapnr = cpu_exec(env);
2642 gdbsig = 0;
2643
2644 switch (trapnr) {
2645 case EXCP_RESET:
2646 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2647 exit(1);
2648 break;
2649 case EXCP_BUSERR:
2650 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2651 gdbsig = SIGBUS;
2652 break;
2653 case EXCP_DPF:
2654 case EXCP_IPF:
2655 cpu_dump_state(cs, stderr, fprintf, 0);
2656 gdbsig = TARGET_SIGSEGV;
2657 break;
2658 case EXCP_TICK:
2659 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2660 break;
2661 case EXCP_ALIGN:
2662 qemu_log("\nAlignment pc is %#x\n", env->pc);
2663 gdbsig = SIGBUS;
2664 break;
2665 case EXCP_ILLEGAL:
2666 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2667 gdbsig = SIGILL;
2668 break;
2669 case EXCP_INT:
2670 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2671 break;
2672 case EXCP_DTLBMISS:
2673 case EXCP_ITLBMISS:
2674 qemu_log("\nTLB miss\n");
2675 break;
2676 case EXCP_RANGE:
2677 qemu_log("\nRange\n");
2678 gdbsig = SIGSEGV;
2679 break;
2680 case EXCP_SYSCALL:
2681 env->pc += 4; /* 0xc00; */
2682 env->gpr[11] = do_syscall(env,
2683 env->gpr[11], /* return value */
2684 env->gpr[3], /* r3 - r7 are params */
2685 env->gpr[4],
2686 env->gpr[5],
2687 env->gpr[6],
2688 env->gpr[7],
2689 env->gpr[8], 0, 0);
2690 break;
2691 case EXCP_FPE:
2692 qemu_log("\nFloating point error\n");
2693 break;
2694 case EXCP_TRAP:
2695 qemu_log("\nTrap\n");
2696 gdbsig = SIGTRAP;
2697 break;
2698 case EXCP_NR:
2699 qemu_log("\nNR\n");
2700 break;
2701 default:
2702 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2703 trapnr);
2704 cpu_dump_state(cs, stderr, fprintf, 0);
2705 gdbsig = TARGET_SIGILL;
2706 break;
2707 }
2708 if (gdbsig) {
2709 gdb_handlesig(cs, gdbsig);
2710 if (gdbsig != TARGET_SIGTRAP) {
2711 exit(1);
2712 }
2713 }
2714
2715 process_pending_signals(env);
2716 }
2717 }
2718
2719 #endif /* TARGET_OPENRISC */
2720
2721 #ifdef TARGET_SH4
2722 void cpu_loop(CPUSH4State *env)
2723 {
2724 CPUState *cs = CPU(sh_env_get_cpu(env));
2725 int trapnr, ret;
2726 target_siginfo_t info;
2727
2728 while (1) {
2729 trapnr = cpu_sh4_exec (env);
2730
2731 switch (trapnr) {
2732 case 0x160:
2733 env->pc += 2;
2734 ret = do_syscall(env,
2735 env->gregs[3],
2736 env->gregs[4],
2737 env->gregs[5],
2738 env->gregs[6],
2739 env->gregs[7],
2740 env->gregs[0],
2741 env->gregs[1],
2742 0, 0);
2743 env->gregs[0] = ret;
2744 break;
2745 case EXCP_INTERRUPT:
2746 /* just indicate that signals should be handled asap */
2747 break;
2748 case EXCP_DEBUG:
2749 {
2750 int sig;
2751
2752 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2753 if (sig)
2754 {
2755 info.si_signo = sig;
2756 info.si_errno = 0;
2757 info.si_code = TARGET_TRAP_BRKPT;
2758 queue_signal(env, info.si_signo, &info);
2759 }
2760 }
2761 break;
2762 case 0xa0:
2763 case 0xc0:
2764 info.si_signo = SIGSEGV;
2765 info.si_errno = 0;
2766 info.si_code = TARGET_SEGV_MAPERR;
2767 info._sifields._sigfault._addr = env->tea;
2768 queue_signal(env, info.si_signo, &info);
2769 break;
2770
2771 default:
2772 printf ("Unhandled trap: 0x%x\n", trapnr);
2773 cpu_dump_state(cs, stderr, fprintf, 0);
2774 exit (1);
2775 }
2776 process_pending_signals (env);
2777 }
2778 }
2779 #endif
2780
2781 #ifdef TARGET_CRIS
2782 void cpu_loop(CPUCRISState *env)
2783 {
2784 CPUState *cs = CPU(cris_env_get_cpu(env));
2785 int trapnr, ret;
2786 target_siginfo_t info;
2787
2788 while (1) {
2789 trapnr = cpu_cris_exec (env);
2790 switch (trapnr) {
2791 case 0xaa:
2792 {
2793 info.si_signo = SIGSEGV;
2794 info.si_errno = 0;
2795 /* XXX: check env->error_code */
2796 info.si_code = TARGET_SEGV_MAPERR;
2797 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2798 queue_signal(env, info.si_signo, &info);
2799 }
2800 break;
2801 case EXCP_INTERRUPT:
2802 /* just indicate that signals should be handled asap */
2803 break;
2804 case EXCP_BREAK:
2805 ret = do_syscall(env,
2806 env->regs[9],
2807 env->regs[10],
2808 env->regs[11],
2809 env->regs[12],
2810 env->regs[13],
2811 env->pregs[7],
2812 env->pregs[11],
2813 0, 0);
2814 env->regs[10] = ret;
2815 break;
2816 case EXCP_DEBUG:
2817 {
2818 int sig;
2819
2820 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2821 if (sig)
2822 {
2823 info.si_signo = sig;
2824 info.si_errno = 0;
2825 info.si_code = TARGET_TRAP_BRKPT;
2826 queue_signal(env, info.si_signo, &info);
2827 }
2828 }
2829 break;
2830 default:
2831 printf ("Unhandled trap: 0x%x\n", trapnr);
2832 cpu_dump_state(cs, stderr, fprintf, 0);
2833 exit (1);
2834 }
2835 process_pending_signals (env);
2836 }
2837 }
2838 #endif
2839
2840 #ifdef TARGET_MICROBLAZE
2841 void cpu_loop(CPUMBState *env)
2842 {
2843 CPUState *cs = CPU(mb_env_get_cpu(env));
2844 int trapnr, ret;
2845 target_siginfo_t info;
2846
2847 while (1) {
2848 trapnr = cpu_mb_exec (env);
2849 switch (trapnr) {
2850 case 0xaa:
2851 {
2852 info.si_signo = SIGSEGV;
2853 info.si_errno = 0;
2854 /* XXX: check env->error_code */
2855 info.si_code = TARGET_SEGV_MAPERR;
2856 info._sifields._sigfault._addr = 0;
2857 queue_signal(env, info.si_signo, &info);
2858 }
2859 break;
2860 case EXCP_INTERRUPT:
2861 /* just indicate that signals should be handled asap */
2862 break;
2863 case EXCP_BREAK:
2864 /* Return address is 4 bytes after the call. */
2865 env->regs[14] += 4;
2866 env->sregs[SR_PC] = env->regs[14];
2867 ret = do_syscall(env,
2868 env->regs[12],
2869 env->regs[5],
2870 env->regs[6],
2871 env->regs[7],
2872 env->regs[8],
2873 env->regs[9],
2874 env->regs[10],
2875 0, 0);
2876 env->regs[3] = ret;
2877 break;
2878 case EXCP_HW_EXCP:
2879 env->regs[17] = env->sregs[SR_PC] + 4;
2880 if (env->iflags & D_FLAG) {
2881 env->sregs[SR_ESR] |= 1 << 12;
2882 env->sregs[SR_PC] -= 4;
2883 /* FIXME: if branch was immed, replay the imm as well. */
2884 }
2885
2886 env->iflags &= ~(IMM_FLAG | D_FLAG);
2887
2888 switch (env->sregs[SR_ESR] & 31) {
2889 case ESR_EC_DIVZERO:
2890 info.si_signo = SIGFPE;
2891 info.si_errno = 0;
2892 info.si_code = TARGET_FPE_FLTDIV;
2893 info._sifields._sigfault._addr = 0;
2894 queue_signal(env, info.si_signo, &info);
2895 break;
2896 case ESR_EC_FPU:
2897 info.si_signo = SIGFPE;
2898 info.si_errno = 0;
2899 if (env->sregs[SR_FSR] & FSR_IO) {
2900 info.si_code = TARGET_FPE_FLTINV;
2901 }
2902 if (env->sregs[SR_FSR] & FSR_DZ) {
2903 info.si_code = TARGET_FPE_FLTDIV;
2904 }
2905 info._sifields._sigfault._addr = 0;
2906 queue_signal(env, info.si_signo, &info);
2907 break;
2908 default:
2909 printf ("Unhandled hw-exception: 0x%x\n",
2910 env->sregs[SR_ESR] & ESR_EC_MASK);
2911 cpu_dump_state(cs, stderr, fprintf, 0);
2912 exit (1);
2913 break;
2914 }
2915 break;
2916 case EXCP_DEBUG:
2917 {
2918 int sig;
2919
2920 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2921 if (sig)
2922 {
2923 info.si_signo = sig;
2924 info.si_errno = 0;
2925 info.si_code = TARGET_TRAP_BRKPT;
2926 queue_signal(env, info.si_signo, &info);
2927 }
2928 }
2929 break;
2930 default:
2931 printf ("Unhandled trap: 0x%x\n", trapnr);
2932 cpu_dump_state(cs, stderr, fprintf, 0);
2933 exit (1);
2934 }
2935 process_pending_signals (env);
2936 }
2937 }
2938 #endif
2939
2940 #ifdef TARGET_M68K
2941
2942 void cpu_loop(CPUM68KState *env)
2943 {
2944 CPUState *cs = CPU(m68k_env_get_cpu(env));
2945 int trapnr;
2946 unsigned int n;
2947 target_siginfo_t info;
2948 TaskState *ts = env->opaque;
2949
2950 for(;;) {
2951 trapnr = cpu_m68k_exec(env);
2952 switch(trapnr) {
2953 case EXCP_ILLEGAL:
2954 {
2955 if (ts->sim_syscalls) {
2956 uint16_t nr;
2957 nr = lduw(env->pc + 2);
2958 env->pc += 4;
2959 do_m68k_simcall(env, nr);
2960 } else {
2961 goto do_sigill;
2962 }
2963 }
2964 break;
2965 case EXCP_HALT_INSN:
2966 /* Semihosing syscall. */
2967 env->pc += 4;
2968 do_m68k_semihosting(env, env->dregs[0]);
2969 break;
2970 case EXCP_LINEA:
2971 case EXCP_LINEF:
2972 case EXCP_UNSUPPORTED:
2973 do_sigill:
2974 info.si_signo = SIGILL;
2975 info.si_errno = 0;
2976 info.si_code = TARGET_ILL_ILLOPN;
2977 info._sifields._sigfault._addr = env->pc;
2978 queue_signal(env, info.si_signo, &info);
2979 break;
2980 case EXCP_TRAP0:
2981 {
2982 ts->sim_syscalls = 0;
2983 n = env->dregs[0];
2984 env->pc += 2;
2985 env->dregs[0] = do_syscall(env,
2986 n,
2987 env->dregs[1],
2988 env->dregs[2],
2989 env->dregs[3],
2990 env->dregs[4],
2991 env->dregs[5],
2992 env->aregs[0],
2993 0, 0);
2994 }
2995 break;
2996 case EXCP_INTERRUPT:
2997 /* just indicate that signals should be handled asap */
2998 break;
2999 case EXCP_ACCESS:
3000 {
3001 info.si_signo = SIGSEGV;
3002 info.si_errno = 0;
3003 /* XXX: check env->error_code */
3004 info.si_code = TARGET_SEGV_MAPERR;
3005 info._sifields._sigfault._addr = env->mmu.ar;
3006 queue_signal(env, info.si_signo, &info);
3007 }
3008 break;
3009 case EXCP_DEBUG:
3010 {
3011 int sig;
3012
3013 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3014 if (sig)
3015 {
3016 info.si_signo = sig;
3017 info.si_errno = 0;
3018 info.si_code = TARGET_TRAP_BRKPT;
3019 queue_signal(env, info.si_signo, &info);
3020 }
3021 }
3022 break;
3023 default:
3024 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3025 trapnr);
3026 cpu_dump_state(cs, stderr, fprintf, 0);
3027 abort();
3028 }
3029 process_pending_signals(env);
3030 }
3031 }
3032 #endif /* TARGET_M68K */
3033
3034 #ifdef TARGET_ALPHA
3035 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3036 {
3037 target_ulong addr, val, tmp;
3038 target_siginfo_t info;
3039 int ret = 0;
3040
3041 addr = env->lock_addr;
3042 tmp = env->lock_st_addr;
3043 env->lock_addr = -1;
3044 env->lock_st_addr = 0;
3045
3046 start_exclusive();
3047 mmap_lock();
3048
3049 if (addr == tmp) {
3050 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3051 goto do_sigsegv;
3052 }
3053
3054 if (val == env->lock_value) {
3055 tmp = env->ir[reg];
3056 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3057 goto do_sigsegv;
3058 }
3059 ret = 1;
3060 }
3061 }
3062 env->ir[reg] = ret;
3063 env->pc += 4;
3064
3065 mmap_unlock();
3066 end_exclusive();
3067 return;
3068
3069 do_sigsegv:
3070 mmap_unlock();
3071 end_exclusive();
3072
3073 info.si_signo = TARGET_SIGSEGV;
3074 info.si_errno = 0;
3075 info.si_code = TARGET_SEGV_MAPERR;
3076 info._sifields._sigfault._addr = addr;
3077 queue_signal(env, TARGET_SIGSEGV, &info);
3078 }
3079
3080 void cpu_loop(CPUAlphaState *env)
3081 {
3082 CPUState *cs = CPU(alpha_env_get_cpu(env));
3083 int trapnr;
3084 target_siginfo_t info;
3085 abi_long sysret;
3086
3087 while (1) {
3088 trapnr = cpu_alpha_exec (env);
3089
3090 /* All of the traps imply a transition through PALcode, which
3091 implies an REI instruction has been executed. Which means
3092 that the intr_flag should be cleared. */
3093 env->intr_flag = 0;
3094
3095 switch (trapnr) {
3096 case EXCP_RESET:
3097 fprintf(stderr, "Reset requested. Exit\n");
3098 exit(1);
3099 break;
3100 case EXCP_MCHK:
3101 fprintf(stderr, "Machine check exception. Exit\n");
3102 exit(1);
3103 break;
3104 case EXCP_SMP_INTERRUPT:
3105 case EXCP_CLK_INTERRUPT:
3106 case EXCP_DEV_INTERRUPT:
3107 fprintf(stderr, "External interrupt. Exit\n");
3108 exit(1);
3109 break;
3110 case EXCP_MMFAULT:
3111 env->lock_addr = -1;
3112 info.si_signo = TARGET_SIGSEGV;
3113 info.si_errno = 0;
3114 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3115 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3116 info._sifields._sigfault._addr = env->trap_arg0;
3117 queue_signal(env, info.si_signo, &info);
3118 break;
3119 case EXCP_UNALIGN:
3120 env->lock_addr = -1;
3121 info.si_signo = TARGET_SIGBUS;
3122 info.si_errno = 0;
3123 info.si_code = TARGET_BUS_ADRALN;
3124 info._sifields._sigfault._addr = env->trap_arg0;
3125 queue_signal(env, info.si_signo, &info);
3126 break;
3127 case EXCP_OPCDEC:
3128 do_sigill:
3129 env->lock_addr = -1;
3130 info.si_signo = TARGET_SIGILL;
3131 info.si_errno = 0;
3132 info.si_code = TARGET_ILL_ILLOPC;
3133 info._sifields._sigfault._addr = env->pc;
3134 queue_signal(env, info.si_signo, &info);
3135 break;
3136 case EXCP_ARITH:
3137 env->lock_addr = -1;
3138 info.si_signo = TARGET_SIGFPE;
3139 info.si_errno = 0;
3140 info.si_code = TARGET_FPE_FLTINV;
3141 info._sifields._sigfault._addr = env->pc;
3142 queue_signal(env, info.si_signo, &info);
3143 break;
3144 case EXCP_FEN:
3145 /* No-op. Linux simply re-enables the FPU. */
3146 break;
3147 case EXCP_CALL_PAL:
3148 env->lock_addr = -1;
3149 switch (env->error_code) {
3150 case 0x80:
3151 /* BPT */
3152 info.si_signo = TARGET_SIGTRAP;
3153 info.si_errno = 0;
3154 info.si_code = TARGET_TRAP_BRKPT;
3155 info._sifields._sigfault._addr = env->pc;
3156 queue_signal(env, info.si_signo, &info);
3157 break;
3158 case 0x81:
3159 /* BUGCHK */
3160 info.si_signo = TARGET_SIGTRAP;
3161 info.si_errno = 0;
3162 info.si_code = 0;
3163 info._sifields._sigfault._addr = env->pc;
3164 queue_signal(env, info.si_signo, &info);
3165 break;
3166 case 0x83:
3167 /* CALLSYS */
3168 trapnr = env->ir[IR_V0];
3169 sysret = do_syscall(env, trapnr,
3170 env->ir[IR_A0], env->ir[IR_A1],
3171 env->ir[IR_A2], env->ir[IR_A3],
3172 env->ir[IR_A4], env->ir[IR_A5],
3173 0, 0);
3174 if (trapnr == TARGET_NR_sigreturn
3175 || trapnr == TARGET_NR_rt_sigreturn) {
3176 break;
3177 }
3178 /* Syscall writes 0 to V0 to bypass error check, similar
3179 to how this is handled internal to Linux kernel.
3180 (Ab)use trapnr temporarily as boolean indicating error. */
3181 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3182 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3183 env->ir[IR_A3] = trapnr;
3184 break;
3185 case 0x86:
3186 /* IMB */
3187 /* ??? We can probably elide the code using page_unprotect
3188 that is checking for self-modifying code. Instead we
3189 could simply call tb_flush here. Until we work out the
3190 changes required to turn off the extra write protection,
3191 this can be a no-op. */
3192 break;
3193 case 0x9E:
3194 /* RDUNIQUE */
3195 /* Handled in the translator for usermode. */
3196 abort();
3197 case 0x9F:
3198 /* WRUNIQUE */
3199 /* Handled in the translator for usermode. */
3200 abort();
3201 case 0xAA:
3202 /* GENTRAP */
3203 info.si_signo = TARGET_SIGFPE;
3204 switch (env->ir[IR_A0]) {
3205 case TARGET_GEN_INTOVF:
3206 info.si_code = TARGET_FPE_INTOVF;
3207 break;
3208 case TARGET_GEN_INTDIV:
3209 info.si_code = TARGET_FPE_INTDIV;
3210 break;
3211 case TARGET_GEN_FLTOVF:
3212 info.si_code = TARGET_FPE_FLTOVF;
3213 break;
3214 case TARGET_GEN_FLTUND:
3215 info.si_code = TARGET_FPE_FLTUND;
3216 break;
3217 case TARGET_GEN_FLTINV:
3218 info.si_code = TARGET_FPE_FLTINV;
3219 break;
3220 case TARGET_GEN_FLTINE:
3221 info.si_code = TARGET_FPE_FLTRES;
3222 break;
3223 case TARGET_GEN_ROPRAND:
3224 info.si_code = 0;
3225 break;
3226 default:
3227 info.si_signo = TARGET_SIGTRAP;
3228 info.si_code = 0;
3229 break;
3230 }
3231 info.si_errno = 0;
3232 info._sifields._sigfault._addr = env->pc;
3233 queue_signal(env, info.si_signo, &info);
3234 break;
3235 default:
3236 goto do_sigill;
3237 }
3238 break;
3239 case EXCP_DEBUG:
3240 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3241 if (info.si_signo) {
3242 env->lock_addr = -1;
3243 info.si_errno = 0;
3244 info.si_code = TARGET_TRAP_BRKPT;
3245 queue_signal(env, info.si_signo, &info);
3246 }
3247 break;
3248 case EXCP_STL_C:
3249 case EXCP_STQ_C:
3250 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3251 break;
3252 case EXCP_INTERRUPT:
3253 /* Just indicate that signals should be handled asap. */
3254 break;
3255 default:
3256 printf ("Unhandled trap: 0x%x\n", trapnr);
3257 cpu_dump_state(cs, stderr, fprintf, 0);
3258 exit (1);
3259 }
3260 process_pending_signals (env);
3261 }
3262 }
3263 #endif /* TARGET_ALPHA */
3264
3265 #ifdef TARGET_S390X
3266 void cpu_loop(CPUS390XState *env)
3267 {
3268 CPUState *cs = CPU(s390_env_get_cpu(env));
3269 int trapnr, n, sig;
3270 target_siginfo_t info;
3271 target_ulong addr;
3272
3273 while (1) {
3274 trapnr = cpu_s390x_exec(env);
3275 switch (trapnr) {
3276 case EXCP_INTERRUPT:
3277 /* Just indicate that signals should be handled asap. */
3278 break;
3279
3280 case EXCP_SVC:
3281 n = env->int_svc_code;
3282 if (!n) {
3283 /* syscalls > 255 */
3284 n = env->regs[1];
3285 }
3286 env->psw.addr += env->int_svc_ilen;
3287 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3288 env->regs[4], env->regs[5],
3289 env->regs[6], env->regs[7], 0, 0);
3290 break;
3291
3292 case EXCP_DEBUG:
3293 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3294 if (sig) {
3295 n = TARGET_TRAP_BRKPT;
3296 goto do_signal_pc;
3297 }
3298 break;
3299 case EXCP_PGM:
3300 n = env->int_pgm_code;
3301 switch (n) {
3302 case PGM_OPERATION:
3303 case PGM_PRIVILEGED:
3304 sig = SIGILL;
3305 n = TARGET_ILL_ILLOPC;
3306 goto do_signal_pc;
3307 case PGM_PROTECTION:
3308 case PGM_ADDRESSING:
3309 sig = SIGSEGV;
3310 /* XXX: check env->error_code */
3311 n = TARGET_SEGV_MAPERR;
3312 addr = env->__excp_addr;
3313 goto do_signal;
3314 case PGM_EXECUTE:
3315 case PGM_SPECIFICATION:
3316 case PGM_SPECIAL_OP:
3317 case PGM_OPERAND:
3318 do_sigill_opn:
3319 sig = SIGILL;
3320 n = TARGET_ILL_ILLOPN;
3321 goto do_signal_pc;
3322
3323 case PGM_FIXPT_OVERFLOW:
3324 sig = SIGFPE;
3325 n = TARGET_FPE_INTOVF;
3326 goto do_signal_pc;
3327 case PGM_FIXPT_DIVIDE:
3328 sig = SIGFPE;
3329 n = TARGET_FPE_INTDIV;
3330 goto do_signal_pc;
3331
3332 case PGM_DATA:
3333 n = (env->fpc >> 8) & 0xff;
3334 if (n == 0xff) {
3335 /* compare-and-trap */
3336 goto do_sigill_opn;
3337 } else {
3338 /* An IEEE exception, simulated or otherwise. */
3339 if (n & 0x80) {
3340 n = TARGET_FPE_FLTINV;
3341 } else if (n & 0x40) {
3342 n = TARGET_FPE_FLTDIV;
3343 } else if (n & 0x20) {
3344 n = TARGET_FPE_FLTOVF;
3345 } else if (n & 0x10) {
3346 n = TARGET_FPE_FLTUND;
3347 } else if (n & 0x08) {
3348 n = TARGET_FPE_FLTRES;
3349 } else {
3350 /* ??? Quantum exception; BFP, DFP error. */
3351 goto do_sigill_opn;
3352 }
3353 sig = SIGFPE;
3354 goto do_signal_pc;
3355 }
3356
3357 default:
3358 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3359 cpu_dump_state(cs, stderr, fprintf, 0);
3360 exit(1);
3361 }
3362 break;
3363
3364 do_signal_pc:
3365 addr = env->psw.addr;
3366 do_signal:
3367 info.si_signo = sig;
3368 info.si_errno = 0;
3369 info.si_code = n;
3370 info._sifields._sigfault._addr = addr;
3371 queue_signal(env, info.si_signo, &info);
3372 break;
3373
3374 default:
3375 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3376 cpu_dump_state(cs, stderr, fprintf, 0);
3377 exit(1);
3378 }
3379 process_pending_signals (env);
3380 }
3381 }
3382
3383 #endif /* TARGET_S390X */
3384
3385 THREAD CPUState *thread_cpu;
3386
3387 void task_settid(TaskState *ts)
3388 {
3389 if (ts->ts_tid == 0) {
3390 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3391 }
3392 }
3393
3394 void stop_all_tasks(void)
3395 {
3396 /*
3397 * We trust that when using NPTL, start_exclusive()
3398 * handles thread stopping correctly.
3399 */
3400 start_exclusive();
3401 }
3402
3403 /* Assumes contents are already zeroed. */
3404 void init_task_state(TaskState *ts)
3405 {
3406 int i;
3407
3408 ts->used = 1;
3409 ts->first_free = ts->sigqueue_table;
3410 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3411 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3412 }
3413 ts->sigqueue_table[i].next = NULL;
3414 }
3415
3416 CPUArchState *cpu_copy(CPUArchState *env)
3417 {
3418 CPUArchState *new_env = cpu_init(cpu_model);
3419 #if defined(TARGET_HAS_ICE)
3420 CPUBreakpoint *bp;
3421 CPUWatchpoint *wp;
3422 #endif
3423
3424 /* Reset non arch specific state */
3425 cpu_reset(ENV_GET_CPU(new_env));
3426
3427 memcpy(new_env, env, sizeof(CPUArchState));
3428
3429 /* Clone all break/watchpoints.
3430 Note: Once we support ptrace with hw-debug register access, make sure
3431 BP_CPU break/watchpoints are handled correctly on clone. */
3432 QTAILQ_INIT(&env->breakpoints);
3433 QTAILQ_INIT(&env->watchpoints);
3434 #if defined(TARGET_HAS_ICE)
3435 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3436 cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
3437 }
3438 QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
3439 cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
3440 wp->flags, NULL);
3441 }
3442 #endif
3443
3444 return new_env;
3445 }
3446
3447 static void handle_arg_help(const char *arg)
3448 {
3449 usage();
3450 }
3451
3452 static void handle_arg_log(const char *arg)
3453 {
3454 int mask;
3455
3456 mask = qemu_str_to_log_mask(arg);
3457 if (!mask) {
3458 qemu_print_log_usage(stdout);
3459 exit(1);
3460 }
3461 qemu_set_log(mask);
3462 }
3463
3464 static void handle_arg_log_filename(const char *arg)
3465 {
3466 qemu_set_log_filename(arg);
3467 }
3468
3469 static void handle_arg_set_env(const char *arg)
3470 {
3471 char *r, *p, *token;
3472 r = p = strdup(arg);
3473 while ((token = strsep(&p, ",")) != NULL) {
3474 if (envlist_setenv(envlist, token) != 0) {
3475 usage();
3476 }
3477 }
3478 free(r);
3479 }
3480
3481 static void handle_arg_unset_env(const char *arg)
3482 {
3483 char *r, *p, *token;
3484 r = p = strdup(arg);
3485 while ((token = strsep(&p, ",")) != NULL) {
3486 if (envlist_unsetenv(envlist, token) != 0) {
3487 usage();
3488 }
3489 }
3490 free(r);
3491 }
3492
3493 static void handle_arg_argv0(const char *arg)
3494 {
3495 argv0 = strdup(arg);
3496 }
3497
3498 static void handle_arg_stack_size(const char *arg)
3499 {
3500 char *p;
3501 guest_stack_size = strtoul(arg, &p, 0);
3502 if (guest_stack_size == 0) {
3503 usage();
3504 }
3505
3506 if (*p == 'M') {
3507 guest_stack_size *= 1024 * 1024;
3508 } else if (*p == 'k' || *p == 'K') {
3509 guest_stack_size *= 1024;
3510 }
3511 }
3512
3513 static void handle_arg_ld_prefix(const char *arg)
3514 {
3515 interp_prefix = strdup(arg);
3516 }
3517
3518 static void handle_arg_pagesize(const char *arg)
3519 {
3520 qemu_host_page_size = atoi(arg);
3521 if (qemu_host_page_size == 0 ||
3522 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3523 fprintf(stderr, "page size must be a power of two\n");
3524 exit(1);
3525 }
3526 }
3527
3528 static void handle_arg_gdb(const char *arg)
3529 {
3530 gdbstub_port = atoi(arg);
3531 }
3532
3533 static void handle_arg_uname(const char *arg)
3534 {
3535 qemu_uname_release = strdup(arg);
3536 }
3537
3538 static void handle_arg_cpu(const char *arg)
3539 {
3540 cpu_model = strdup(arg);
3541 if (cpu_model == NULL || is_help_option(cpu_model)) {
3542 /* XXX: implement xxx_cpu_list for targets that still miss it */
3543 #if defined(cpu_list)
3544 cpu_list(stdout, &fprintf);
3545 #endif
3546 exit(1);
3547 }
3548 }
3549
3550 #if defined(CONFIG_USE_GUEST_BASE)
3551 static void handle_arg_guest_base(const char *arg)
3552 {
3553 guest_base = strtol(arg, NULL, 0);
3554 have_guest_base = 1;
3555 }
3556
3557 static void handle_arg_reserved_va(const char *arg)
3558 {
3559 char *p;
3560 int shift = 0;
3561 reserved_va = strtoul(arg, &p, 0);
3562 switch (*p) {
3563 case 'k':
3564 case 'K':
3565 shift = 10;
3566 break;
3567 case 'M':
3568 shift = 20;
3569 break;
3570 case 'G':
3571 shift = 30;
3572 break;
3573 }
3574 if (shift) {
3575 unsigned long unshifted = reserved_va;
3576 p++;
3577 reserved_va <<= shift;
3578 if (((reserved_va >> shift) != unshifted)
3579 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3580 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3581 #endif
3582 ) {
3583 fprintf(stderr, "Reserved virtual address too big\n");
3584 exit(1);
3585 }
3586 }
3587 if (*p) {
3588 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3589 exit(1);
3590 }
3591 }
3592 #endif
3593
3594 static void handle_arg_singlestep(const char *arg)
3595 {
3596 singlestep = 1;
3597 }
3598
3599 static void handle_arg_strace(const char *arg)
3600 {
3601 do_strace = 1;
3602 }
3603
3604 static void handle_arg_version(const char *arg)
3605 {
3606 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3607 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3608 exit(0);
3609 }
3610
3611 struct qemu_argument {
3612 const char *argv;
3613 const char *env;
3614 bool has_arg;
3615 void (*handle_opt)(const char *arg);
3616 const char *example;
3617 const char *help;
3618 };
3619
3620 static const struct qemu_argument arg_table[] = {
3621 {"h", "", false, handle_arg_help,
3622 "", "print this help"},
3623 {"g", "QEMU_GDB", true, handle_arg_gdb,
3624 "port", "wait gdb connection to 'port'"},
3625 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3626 "path", "set the elf interpreter prefix to 'path'"},
3627 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3628 "size", "set the stack size to 'size' bytes"},
3629 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3630 "model", "select CPU (-cpu help for list)"},
3631 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3632 "var=value", "sets targets environment variable (see below)"},
3633 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3634 "var", "unsets targets environment variable (see below)"},
3635 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3636 "argv0", "forces target process argv[0] to be 'argv0'"},
3637 {"r", "QEMU_UNAME", true, handle_arg_uname,
3638 "uname", "set qemu uname release string to 'uname'"},
3639 #if defined(CONFIG_USE_GUEST_BASE)
3640 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3641 "address", "set guest_base address to 'address'"},
3642 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3643 "size", "reserve 'size' bytes for guest virtual address space"},
3644 #endif
3645 {"d", "QEMU_LOG", true, handle_arg_log,
3646 "item[,...]", "enable logging of specified items "
3647 "(use '-d help' for a list of items)"},
3648 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3649 "logfile", "write logs to 'logfile' (default stderr)"},
3650 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3651 "pagesize", "set the host page size to 'pagesize'"},
3652 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3653 "", "run in singlestep mode"},
3654 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3655 "", "log system calls"},
3656 {"version", "QEMU_VERSION", false, handle_arg_version,
3657 "", "display version information and exit"},
3658 {NULL, NULL, false, NULL, NULL, NULL}
3659 };
3660
3661 static void usage(void)
3662 {
3663 const struct qemu_argument *arginfo;
3664 int maxarglen;
3665 int maxenvlen;
3666
3667 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3668 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3669 "\n"
3670 "Options and associated environment variables:\n"
3671 "\n");
3672
3673 /* Calculate column widths. We must always have at least enough space
3674 * for the column header.
3675 */
3676 maxarglen = strlen("Argument");
3677 maxenvlen = strlen("Env-variable");
3678
3679 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3680 int arglen = strlen(arginfo->argv);
3681 if (arginfo->has_arg) {
3682 arglen += strlen(arginfo->example) + 1;
3683 }
3684 if (strlen(arginfo->env) > maxenvlen) {
3685 maxenvlen = strlen(arginfo->env);
3686 }
3687 if (arglen > maxarglen) {
3688 maxarglen = arglen;
3689 }
3690 }
3691
3692 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3693 maxenvlen, "Env-variable");
3694
3695 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3696 if (arginfo->has_arg) {
3697 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3698 (int)(maxarglen - strlen(arginfo->argv) - 1),
3699 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3700 } else {
3701 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3702 maxenvlen, arginfo->env,
3703 arginfo->help);
3704 }
3705 }
3706
3707 printf("\n"
3708 "Defaults:\n"
3709 "QEMU_LD_PREFIX = %s\n"
3710 "QEMU_STACK_SIZE = %ld byte\n",
3711 interp_prefix,
3712 guest_stack_size);
3713
3714 printf("\n"
3715 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3716 "QEMU_UNSET_ENV environment variables to set and unset\n"
3717 "environment variables for the target process.\n"
3718 "It is possible to provide several variables by separating them\n"
3719 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3720 "provide the -E and -U options multiple times.\n"
3721 "The following lines are equivalent:\n"
3722 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3723 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3724 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3725 "Note that if you provide several changes to a single variable\n"
3726 "the last change will stay in effect.\n");
3727
3728 exit(1);
3729 }
3730
3731 static int parse_args(int argc, char **argv)
3732 {
3733 const char *r;
3734 int optind;
3735 const struct qemu_argument *arginfo;
3736
3737 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3738 if (arginfo->env == NULL) {
3739 continue;
3740 }
3741
3742 r = getenv(arginfo->env);
3743 if (r != NULL) {
3744 arginfo->handle_opt(r);
3745 }
3746 }
3747
3748 optind = 1;
3749 for (;;) {
3750 if (optind >= argc) {
3751 break;
3752 }
3753 r = argv[optind];
3754 if (r[0] != '-') {
3755 break;
3756 }
3757 optind++;
3758 r++;
3759 if (!strcmp(r, "-")) {
3760 break;
3761 }
3762
3763 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3764 if (!strcmp(r, arginfo->argv)) {
3765 if (arginfo->has_arg) {
3766 if (optind >= argc) {
3767 usage();
3768 }
3769 arginfo->handle_opt(argv[optind]);
3770 optind++;
3771 } else {
3772 arginfo->handle_opt(NULL);
3773 }
3774 break;
3775 }
3776 }
3777
3778 /* no option matched the current argv */
3779 if (arginfo->handle_opt == NULL) {
3780 usage();
3781 }
3782 }
3783
3784 if (optind >= argc) {
3785 usage();
3786 }
3787
3788 filename = argv[optind];
3789 exec_path = argv[optind];
3790
3791 return optind;
3792 }
3793
3794 int main(int argc, char **argv, char **envp)
3795 {
3796 struct target_pt_regs regs1, *regs = &regs1;
3797 struct image_info info1, *info = &info1;
3798 struct linux_binprm bprm;
3799 TaskState *ts;
3800 CPUArchState *env;
3801 CPUState *cpu;
3802 int optind;
3803 char **target_environ, **wrk;
3804 char **target_argv;
3805 int target_argc;
3806 int i;
3807 int ret;
3808 int execfd;
3809
3810 module_call_init(MODULE_INIT_QOM);
3811
3812 qemu_init_auxval(envp);
3813 qemu_cache_utils_init();
3814
3815 if ((envlist = envlist_create()) == NULL) {
3816 (void) fprintf(stderr, "Unable to allocate envlist\n");
3817 exit(1);
3818 }
3819
3820 /* add current environment into the list */
3821 for (wrk = environ; *wrk != NULL; wrk++) {
3822 (void) envlist_setenv(envlist, *wrk);
3823 }
3824
3825 /* Read the stack limit from the kernel. If it's "unlimited",
3826 then we can do little else besides use the default. */
3827 {
3828 struct rlimit lim;
3829 if (getrlimit(RLIMIT_STACK, &lim) == 0
3830 && lim.rlim_cur != RLIM_INFINITY
3831 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3832 guest_stack_size = lim.rlim_cur;
3833 }
3834 }
3835
3836 cpu_model = NULL;
3837 #if defined(cpudef_setup)
3838 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3839 #endif
3840
3841 optind = parse_args(argc, argv);
3842
3843 /* Zero out regs */
3844 memset(regs, 0, sizeof(struct target_pt_regs));
3845
3846 /* Zero out image_info */
3847 memset(info, 0, sizeof(struct image_info));
3848
3849 memset(&bprm, 0, sizeof (bprm));
3850
3851 /* Scan interp_prefix dir for replacement files. */
3852 init_paths(interp_prefix);
3853
3854 init_qemu_uname_release();
3855
3856 if (cpu_model == NULL) {
3857 #if defined(TARGET_I386)
3858 #ifdef TARGET_X86_64
3859 cpu_model = "qemu64";
3860 #else
3861 cpu_model = "qemu32";
3862 #endif
3863 #elif defined(TARGET_ARM)
3864 cpu_model = "any";
3865 #elif defined(TARGET_UNICORE32)
3866 cpu_model = "any";
3867 #elif defined(TARGET_M68K)
3868 cpu_model = "any";
3869 #elif defined(TARGET_SPARC)
3870 #ifdef TARGET_SPARC64
3871 cpu_model = "TI UltraSparc II";
3872 #else
3873 cpu_model = "Fujitsu MB86904";
3874 #endif
3875 #elif defined(TARGET_MIPS)
3876 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3877 cpu_model = "20Kc";
3878 #else
3879 cpu_model = "24Kf";
3880 #endif
3881 #elif defined TARGET_OPENRISC
3882 cpu_model = "or1200";
3883 #elif defined(TARGET_PPC)
3884 #ifdef TARGET_PPC64
3885 cpu_model = "970fx";
3886 #else
3887 cpu_model = "750";
3888 #endif
3889 #else
3890 cpu_model = "any";
3891 #endif
3892 }
3893 tcg_exec_init(0);
3894 cpu_exec_init_all();
3895 /* NOTE: we need to init the CPU at this stage to get
3896 qemu_host_page_size */
3897 env = cpu_init(cpu_model);
3898 if (!env) {
3899 fprintf(stderr, "Unable to find CPU definition\n");
3900 exit(1);
3901 }
3902 cpu = ENV_GET_CPU(env);
3903 cpu_reset(cpu);
3904
3905 thread_cpu = cpu;
3906
3907 if (getenv("QEMU_STRACE")) {
3908 do_strace = 1;
3909 }
3910
3911 target_environ = envlist_to_environ(envlist, NULL);
3912 envlist_free(envlist);
3913
3914 #if defined(CONFIG_USE_GUEST_BASE)
3915 /*
3916 * Now that page sizes are configured in cpu_init() we can do
3917 * proper page alignment for guest_base.
3918 */
3919 guest_base = HOST_PAGE_ALIGN(guest_base);
3920
3921 if (reserved_va || have_guest_base) {
3922 guest_base = init_guest_space(guest_base, reserved_va, 0,
3923 have_guest_base);
3924 if (guest_base == (unsigned long)-1) {
3925 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3926 "space for use as guest address space (check your virtual "
3927 "memory ulimit setting or reserve less using -R option)\n",
3928 reserved_va);
3929 exit(1);
3930 }
3931
3932 if (reserved_va) {
3933 mmap_next_start = reserved_va;
3934 }
3935 }
3936 #endif /* CONFIG_USE_GUEST_BASE */
3937
3938 /*
3939 * Read in mmap_min_addr kernel parameter. This value is used
3940 * When loading the ELF image to determine whether guest_base
3941 * is needed. It is also used in mmap_find_vma.
3942 */
3943 {
3944 FILE *fp;
3945
3946 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3947 unsigned long tmp;
3948 if (fscanf(fp, "%lu", &tmp) == 1) {
3949 mmap_min_addr = tmp;
3950 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3951 }
3952 fclose(fp);
3953 }
3954 }
3955
3956 /*
3957 * Prepare copy of argv vector for target.
3958 */
3959 target_argc = argc - optind;
3960 target_argv = calloc(target_argc + 1, sizeof (char *));
3961 if (target_argv == NULL) {
3962 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3963 exit(1);
3964 }
3965
3966 /*
3967 * If argv0 is specified (using '-0' switch) we replace
3968 * argv[0] pointer with the given one.
3969 */
3970 i = 0;
3971 if (argv0 != NULL) {
3972 target_argv[i++] = strdup(argv0);
3973 }
3974 for (; i < target_argc; i++) {
3975 target_argv[i] = strdup(argv[optind + i]);
3976 }
3977 target_argv[target_argc] = NULL;
3978
3979 ts = g_malloc0 (sizeof(TaskState));
3980 init_task_state(ts);
3981 /* build Task State */
3982 ts->info = info;
3983 ts->bprm = &bprm;
3984 env->opaque = ts;
3985 task_settid(ts);
3986
3987 execfd = qemu_getauxval(AT_EXECFD);
3988 if (execfd == 0) {
3989 execfd = open(filename, O_RDONLY);
3990 if (execfd < 0) {
3991 printf("Error while loading %s: %s\n", filename, strerror(errno));
3992 _exit(1);
3993 }
3994 }
3995
3996 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
3997 info, &bprm);
3998 if (ret != 0) {
3999 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4000 _exit(1);
4001 }
4002
4003 for (wrk = target_environ; *wrk; wrk++) {
4004 free(*wrk);
4005 }
4006
4007 free(target_environ);
4008
4009 if (qemu_log_enabled()) {
4010 #if defined(CONFIG_USE_GUEST_BASE)
4011 qemu_log("guest_base 0x%lx\n", guest_base);
4012 #endif
4013 log_page_dump();
4014
4015 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4016 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4017 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4018 info->start_code);
4019 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4020 info->start_data);
4021 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4022 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4023 info->start_stack);
4024 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4025 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4026 }
4027
4028 target_set_brk(info->brk);
4029 syscall_init();
4030 signal_init();
4031
4032 #if defined(CONFIG_USE_GUEST_BASE)
4033 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4034 generating the prologue until now so that the prologue can take
4035 the real value of GUEST_BASE into account. */
4036 tcg_prologue_init(&tcg_ctx);
4037 #endif
4038
4039 #if defined(TARGET_I386)
4040 cpu_x86_set_cpl(env, 3);
4041
4042 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4043 env->hflags |= HF_PE_MASK;
4044 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4045 env->cr[4] |= CR4_OSFXSR_MASK;
4046 env->hflags |= HF_OSFXSR_MASK;
4047 }
4048 #ifndef TARGET_ABI32
4049 /* enable 64 bit mode if possible */
4050 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4051 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4052 exit(1);
4053 }
4054 env->cr[4] |= CR4_PAE_MASK;
4055 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4056 env->hflags |= HF_LMA_MASK;
4057 #endif
4058
4059 /* flags setup : we activate the IRQs by default as in user mode */
4060 env->eflags |= IF_MASK;
4061
4062 /* linux register setup */
4063 #ifndef TARGET_ABI32
4064 env->regs[R_EAX] = regs->rax;
4065 env->regs[R_EBX] = regs->rbx;
4066 env->regs[R_ECX] = regs->rcx;
4067 env->regs[R_EDX] = regs->rdx;
4068 env->regs[R_ESI] = regs->rsi;
4069 env->regs[R_EDI] = regs->rdi;
4070 env->regs[R_EBP] = regs->rbp;
4071 env->regs[R_ESP] = regs->rsp;
4072 env->eip = regs->rip;
4073 #else
4074 env->regs[R_EAX] = regs->eax;
4075 env->regs[R_EBX] = regs->ebx;
4076 env->regs[R_ECX] = regs->ecx;
4077 env->regs[R_EDX] = regs->edx;
4078 env->regs[R_ESI] = regs->esi;
4079 env->regs[R_EDI] = regs->edi;
4080 env->regs[R_EBP] = regs->ebp;
4081 env->regs[R_ESP] = regs->esp;
4082 env->eip = regs->eip;
4083 #endif
4084
4085 /* linux interrupt setup */
4086 #ifndef TARGET_ABI32
4087 env->idt.limit = 511;
4088 #else
4089 env->idt.limit = 255;
4090 #endif
4091 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4092 PROT_READ|PROT_WRITE,
4093 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4094 idt_table = g2h(env->idt.base);
4095 set_idt(0, 0);
4096 set_idt(1, 0);
4097 set_idt(2, 0);
4098 set_idt(3, 3);
4099 set_idt(4, 3);
4100 set_idt(5, 0);
4101 set_idt(6, 0);
4102 set_idt(7, 0);
4103 set_idt(8, 0);
4104 set_idt(9, 0);
4105 set_idt(10, 0);
4106 set_idt(11, 0);
4107 set_idt(12, 0);
4108 set_idt(13, 0);
4109 set_idt(14, 0);
4110 set_idt(15, 0);
4111 set_idt(16, 0);
4112 set_idt(17, 0);
4113 set_idt(18, 0);
4114 set_idt(19, 0);
4115 set_idt(0x80, 3);
4116
4117 /* linux segment setup */
4118 {
4119 uint64_t *gdt_table;
4120 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4121 PROT_READ|PROT_WRITE,
4122 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4123 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4124 gdt_table = g2h(env->gdt.base);
4125 #ifdef TARGET_ABI32
4126 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4127 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4128 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4129 #else
4130 /* 64 bit code segment */
4131 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4132 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4133 DESC_L_MASK |
4134 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4135 #endif
4136 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4137 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4138 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4139 }
4140 cpu_x86_load_seg(env, R_CS, __USER_CS);
4141 cpu_x86_load_seg(env, R_SS, __USER_DS);
4142 #ifdef TARGET_ABI32
4143 cpu_x86_load_seg(env, R_DS, __USER_DS);
4144 cpu_x86_load_seg(env, R_ES, __USER_DS);
4145 cpu_x86_load_seg(env, R_FS, __USER_DS);
4146 cpu_x86_load_seg(env, R_GS, __USER_DS);
4147 /* This hack makes Wine work... */
4148 env->segs[R_FS].selector = 0;
4149 #else
4150 cpu_x86_load_seg(env, R_DS, 0);
4151 cpu_x86_load_seg(env, R_ES, 0);
4152 cpu_x86_load_seg(env, R_FS, 0);
4153 cpu_x86_load_seg(env, R_GS, 0);
4154 #endif
4155 #elif defined(TARGET_AARCH64)
4156 {
4157 int i;
4158
4159 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4160 fprintf(stderr,
4161 "The selected ARM CPU does not support 64 bit mode\n");
4162 exit(1);
4163 }
4164
4165 for (i = 0; i < 31; i++) {
4166 env->xregs[i] = regs->regs[i];
4167 }
4168 env->pc = regs->pc;
4169 env->xregs[31] = regs->sp;
4170 }
4171 #elif defined(TARGET_ARM)
4172 {
4173 int i;
4174 cpsr_write(env, regs->uregs[16], 0xffffffff);
4175 for(i = 0; i < 16; i++) {
4176 env->regs[i] = regs->uregs[i];
4177 }
4178 /* Enable BE8. */
4179 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4180 && (info->elf_flags & EF_ARM_BE8)) {
4181 env->bswap_code = 1;
4182 }
4183 }
4184 #elif defined(TARGET_UNICORE32)
4185 {
4186 int i;
4187 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4188 for (i = 0; i < 32; i++) {
4189 env->regs[i] = regs->uregs[i];
4190 }
4191 }
4192 #elif defined(TARGET_SPARC)
4193 {
4194 int i;
4195 env->pc = regs->pc;
4196 env->npc = regs->npc;
4197 env->y = regs->y;
4198 for(i = 0; i < 8; i++)
4199 env->gregs[i] = regs->u_regs[i];
4200 for(i = 0; i < 8; i++)
4201 env->regwptr[i] = regs->u_regs[i + 8];
4202 }
4203 #elif defined(TARGET_PPC)
4204 {
4205 int i;
4206
4207 #if defined(TARGET_PPC64)
4208 #if defined(TARGET_ABI32)
4209 env->msr &= ~((target_ulong)1 << MSR_SF);
4210 #else
4211 env->msr |= (target_ulong)1 << MSR_SF;
4212 #endif
4213 #endif
4214 env->nip = regs->nip;
4215 for(i = 0; i < 32; i++) {
4216 env->gpr[i] = regs->gpr[i];
4217 }
4218 }
4219 #elif defined(TARGET_M68K)
4220 {
4221 env->pc = regs->pc;
4222 env->dregs[0] = regs->d0;
4223 env->dregs[1] = regs->d1;
4224 env->dregs[2] = regs->d2;
4225 env->dregs[3] = regs->d3;
4226 env->dregs[4] = regs->d4;
4227 env->dregs[5] = regs->d5;
4228 env->dregs[6] = regs->d6;
4229 env->dregs[7] = regs->d7;
4230 env->aregs[0] = regs->a0;
4231 env->aregs[1] = regs->a1;
4232 env->aregs[2] = regs->a2;
4233 env->aregs[3] = regs->a3;
4234 env->aregs[4] = regs->a4;
4235 env->aregs[5] = regs->a5;
4236 env->aregs[6] = regs->a6;
4237 env->aregs[7] = regs->usp;
4238 env->sr = regs->sr;
4239 ts->sim_syscalls = 1;
4240 }
4241 #elif defined(TARGET_MICROBLAZE)
4242 {
4243 env->regs[0] = regs->r0;
4244 env->regs[1] = regs->r1;
4245 env->regs[2] = regs->r2;
4246 env->regs[3] = regs->r3;
4247 env->regs[4] = regs->r4;
4248 env->regs[5] = regs->r5;
4249 env->regs[6] = regs->r6;
4250 env->regs[7] = regs->r7;
4251 env->regs[8] = regs->r8;
4252 env->regs[9] = regs->r9;
4253 env->regs[10] = regs->r10;
4254 env->regs[11] = regs->r11;
4255 env->regs[12] = regs->r12;
4256 env->regs[13] = regs->r13;
4257 env->regs[14] = regs->r14;
4258 env->regs[15] = regs->r15;
4259 env->regs[16] = regs->r16;
4260 env->regs[17] = regs->r17;
4261 env->regs[18] = regs->r18;
4262 env->regs[19] = regs->r19;
4263 env->regs[20] = regs->r20;
4264 env->regs[21] = regs->r21;
4265 env->regs[22] = regs->r22;
4266 env->regs[23] = regs->r23;
4267 env->regs[24] = regs->r24;
4268 env->regs[25] = regs->r25;
4269 env->regs[26] = regs->r26;
4270 env->regs[27] = regs->r27;
4271 env->regs[28] = regs->r28;
4272 env->regs[29] = regs->r29;
4273 env->regs[30] = regs->r30;
4274 env->regs[31] = regs->r31;
4275 env->sregs[SR_PC] = regs->pc;
4276 }
4277 #elif defined(TARGET_MIPS)
4278 {
4279 int i;
4280
4281 for(i = 0; i < 32; i++) {
4282 env->active_tc.gpr[i] = regs->regs[i];
4283 }
4284 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4285 if (regs->cp0_epc & 1) {
4286 env->hflags |= MIPS_HFLAG_M16;
4287 }
4288 }
4289 #elif defined(TARGET_OPENRISC)
4290 {
4291 int i;
4292
4293 for (i = 0; i < 32; i++) {
4294 env->gpr[i] = regs->gpr[i];
4295 }
4296
4297 env->sr = regs->sr;
4298 env->pc = regs->pc;
4299 }
4300 #elif defined(TARGET_SH4)
4301 {
4302 int i;
4303
4304 for(i = 0; i < 16; i++) {
4305 env->gregs[i] = regs->regs[i];
4306 }
4307 env->pc = regs->pc;
4308 }
4309 #elif defined(TARGET_ALPHA)
4310 {
4311 int i;
4312
4313 for(i = 0; i < 28; i++) {
4314 env->ir[i] = ((abi_ulong *)regs)[i];
4315 }
4316 env->ir[IR_SP] = regs->usp;
4317 env->pc = regs->pc;
4318 }
4319 #elif defined(TARGET_CRIS)
4320 {
4321 env->regs[0] = regs->r0;
4322 env->regs[1] = regs->r1;
4323 env->regs[2] = regs->r2;
4324 env->regs[3] = regs->r3;
4325 env->regs[4] = regs->r4;
4326 env->regs[5] = regs->r5;
4327 env->regs[6] = regs->r6;
4328 env->regs[7] = regs->r7;
4329 env->regs[8] = regs->r8;
4330 env->regs[9] = regs->r9;
4331 env->regs[10] = regs->r10;
4332 env->regs[11] = regs->r11;
4333 env->regs[12] = regs->r12;
4334 env->regs[13] = regs->r13;
4335 env->regs[14] = info->start_stack;
4336 env->regs[15] = regs->acr;
4337 env->pc = regs->erp;
4338 }
4339 #elif defined(TARGET_S390X)
4340 {
4341 int i;
4342 for (i = 0; i < 16; i++) {
4343 env->regs[i] = regs->gprs[i];
4344 }
4345 env->psw.mask = regs->psw.mask;
4346 env->psw.addr = regs->psw.addr;
4347 }
4348 #else
4349 #error unsupported target CPU
4350 #endif
4351
4352 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4353 ts->stack_base = info->start_stack;
4354 ts->heap_base = info->brk;
4355 /* This will be filled in on the first SYS_HEAPINFO call. */
4356 ts->heap_limit = 0;
4357 #endif
4358
4359 if (gdbstub_port) {
4360 if (gdbserver_start(gdbstub_port) < 0) {
4361 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4362 gdbstub_port);
4363 exit(1);
4364 }
4365 gdb_handlesig(cpu, 0);
4366 }
4367 cpu_loop(env);
4368 /* never exits */
4369 return 0;
4370 }
AR7 emulation for QEMU