hw/pci-host/uninorth.c

   1 /*
   2  * QEMU Uninorth PCI host (for all Mac99 and newer machines)
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/ppc/mac.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/pci-host/uninorth.h"
  30 #include "trace.h"
  31
  32 static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
  33
  34 static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
  35 {
  36     return (irq_num + (pci_dev->devfn >> 3)) & 3;
  37 }
  38
  39 static void pci_unin_set_irq(void *opaque, int irq_num, int level)
  40 {
  41     UNINHostState *s = opaque;
  42
  43     trace_unin_set_irq(unin_irq_line[irq_num], level);
  44     qemu_set_irq(s->irqs[irq_num], level);
  45 }
  46
  47 static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
  48 {
  49     uint32_t retval;
  50
  51     if (reg & (1u << 31)) {
  52         /* XXX OpenBIOS compatibility hack */
  53         retval = reg | (addr & 3);
  54     } else if (reg & 1) {
  55         /* CFA1 style */
  56         retval = (reg & ~7u) | (addr & 7);
  57     } else {
  58         uint32_t slot, func;
  59
  60         /* Grab CFA0 style values */
  61         slot = ctz32(reg & 0xfffff800);
  62         if (slot == 32) {
  63             slot = -1; /* XXX: should this be 0? */
  64         }
  65         func = (reg >> 8) & 7;
  66
  67         /* ... and then convert them to x86 format */
  68         /* config pointer */
  69         retval = (reg & (0xff - 7)) | (addr & 7);
  70         /* slot */
  71         retval |= slot << 11;
  72         /* fn */
  73         retval |= func << 8;
  74     }
  75
  76     trace_unin_get_config_reg(reg, addr, retval);
  77
  78     return retval;
  79 }
  80
  81 static void unin_data_write(void *opaque, hwaddr addr,
  82                             uint64_t val, unsigned len)
  83 {
  84     UNINHostState *s = opaque;
  85     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  86     trace_unin_data_write(addr, len, val);
  87     pci_data_write(phb->bus,
  88                    unin_get_config_reg(phb->config_reg, addr),
  89                    val, len);
  90 }
  91
  92 static uint64_t unin_data_read(void *opaque, hwaddr addr,
  93                                unsigned len)
  94 {
  95     UNINHostState *s = opaque;
  96     PCIHostState *phb = PCI_HOST_BRIDGE(s);
  97     uint32_t val;
  98
  99     val = pci_data_read(phb->bus,
 100                         unin_get_config_reg(phb->config_reg, addr),
 101                         len);
 102     trace_unin_data_read(addr, len, val);
 103     return val;
 104 }
 105
 106 static const MemoryRegionOps unin_data_ops = {
 107     .read = unin_data_read,
 108     .write = unin_data_write,
 109     .endianness = DEVICE_LITTLE_ENDIAN,
 110 };
 111
 112 static void pci_unin_init_irqs(UNINHostState *s)
 113 {
 114     int i;
 115
 116     for (i = 0; i < ARRAY_SIZE(s->irqs); i++) {
 117         s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), unin_irq_line[i]);
 118     }
 119 }
 120
 121 static char *pci_unin_main_ofw_unit_address(const SysBusDevice *dev)
 122 {
 123     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
 124
 125     return g_strdup_printf("%x", s->ofw_addr);
 126 }
 127
 128 static void pci_unin_main_realize(DeviceState *dev, Error **errp)
 129 {
 130     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(dev);
 131     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 132
 133     h->bus = pci_register_root_bus(dev, NULL,
 134                                    pci_unin_set_irq, pci_unin_map_irq,
 135                                    s,
 136                                    &s->pci_mmio,
 137                                    &s->pci_io,
 138                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 139
 140     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-pci");
 141     pci_unin_init_irqs(s);
 142
 143     /* DEC 21154 bridge */
 144 #if 0
 145     /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
 146     pci_create_simple(h->bus, PCI_DEVFN(12, 0), "dec-21154");
 147 #endif
 148 }
 149
 150 static void pci_unin_main_init(Object *obj)
 151 {
 152     UNINHostState *s = UNI_NORTH_PCI_HOST_BRIDGE(obj);
 153     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 154     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 155
 156     /* Use values found on a real PowerMac */
 157     /* Uninorth main bus */
 158     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 159                           obj, "unin-pci-conf-idx", 0x1000);
 160     memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
 161                           "unin-pci-conf-data", 0x1000);
 162
 163     memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
 164                        0x100000000ULL);
 165     memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
 166                           "unin-pci-isa-mmio", 0x00800000);
 167
 168     memory_region_init_alias(&s->pci_hole, OBJECT(s),
 169                              "unin-pci-hole", &s->pci_mmio,
 170                              0x80000000ULL, 0x10000000ULL);
 171
 172     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 173                              (Object **) &s->pic,
 174                              qdev_prop_allow_set_link_before_realize,
 175                              0, NULL);
 176
 177     sysbus_init_mmio(sbd, &h->conf_mem);
 178     sysbus_init_mmio(sbd, &h->data_mem);
 179     sysbus_init_mmio(sbd, &s->pci_hole);
 180     sysbus_init_mmio(sbd, &s->pci_io);
 181 }
 182
 183 static void pci_u3_agp_realize(DeviceState *dev, Error **errp)
 184 {
 185     UNINHostState *s = U3_AGP_HOST_BRIDGE(dev);
 186     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 187
 188     h->bus = pci_register_root_bus(dev, NULL,
 189                                    pci_unin_set_irq, pci_unin_map_irq,
 190                                    s,
 191                                    &s->pci_mmio,
 192                                    &s->pci_io,
 193                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 194
 195     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "u3-agp");
 196     pci_unin_init_irqs(s);
 197 }
 198
 199 static void pci_u3_agp_init(Object *obj)
 200 {
 201     UNINHostState *s = U3_AGP_HOST_BRIDGE(obj);
 202     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 203     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 204
 205     /* Uninorth U3 AGP bus */
 206     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 207                           obj, "unin-pci-conf-idx", 0x1000);
 208     memory_region_init_io(&h->data_mem, OBJECT(h), &unin_data_ops, obj,
 209                           "unin-pci-conf-data", 0x1000);
 210
 211     memory_region_init(&s->pci_mmio, OBJECT(s), "unin-pci-mmio",
 212                        0x100000000ULL);
 213     memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
 214                           "unin-pci-isa-mmio", 0x00800000);
 215
 216     memory_region_init_alias(&s->pci_hole, OBJECT(s),
 217                              "unin-pci-hole", &s->pci_mmio,
 218                              0x80000000ULL, 0x70000000ULL);
 219
 220     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 221                              (Object **) &s->pic,
 222                              qdev_prop_allow_set_link_before_realize,
 223                              0, NULL);
 224
 225     sysbus_init_mmio(sbd, &h->conf_mem);
 226     sysbus_init_mmio(sbd, &h->data_mem);
 227     sysbus_init_mmio(sbd, &s->pci_hole);
 228     sysbus_init_mmio(sbd, &s->pci_io);
 229 }
 230
 231 static void pci_unin_agp_realize(DeviceState *dev, Error **errp)
 232 {
 233     UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(dev);
 234     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 235
 236     h->bus = pci_register_root_bus(dev, NULL,
 237                                    pci_unin_set_irq, pci_unin_map_irq,
 238                                    s,
 239                                    &s->pci_mmio,
 240                                    &s->pci_io,
 241                                    PCI_DEVFN(11, 0), 4, TYPE_PCI_BUS);
 242
 243     pci_create_simple(h->bus, PCI_DEVFN(11, 0), "uni-north-agp");
 244     pci_unin_init_irqs(s);
 245 }
 246
 247 static void pci_unin_agp_init(Object *obj)
 248 {
 249     UNINHostState *s = UNI_NORTH_AGP_HOST_BRIDGE(obj);
 250     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 251     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 252
 253     /* Uninorth AGP bus */
 254     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 255                           obj, "unin-agp-conf-idx", 0x1000);
 256     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
 257                           obj, "unin-agp-conf-data", 0x1000);
 258
 259     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 260                              (Object **) &s->pic,
 261                              qdev_prop_allow_set_link_before_realize,
 262                              0, NULL);
 263
 264     sysbus_init_mmio(sbd, &h->conf_mem);
 265     sysbus_init_mmio(sbd, &h->data_mem);
 266 }
 267
 268 static void pci_unin_internal_realize(DeviceState *dev, Error **errp)
 269 {
 270     UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(dev);
 271     PCIHostState *h = PCI_HOST_BRIDGE(dev);
 272
 273     h->bus = pci_register_root_bus(dev, NULL,
 274                                    pci_unin_set_irq, pci_unin_map_irq,
 275                                    s,
 276                                    &s->pci_mmio,
 277                                    &s->pci_io,
 278                                    PCI_DEVFN(14, 0), 4, TYPE_PCI_BUS);
 279
 280     pci_create_simple(h->bus, PCI_DEVFN(14, 0), "uni-north-internal-pci");
 281     pci_unin_init_irqs(s);
 282 }
 283
 284 static void pci_unin_internal_init(Object *obj)
 285 {
 286     UNINHostState *s = UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE(obj);
 287     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 288     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 289
 290     /* Uninorth internal bus */
 291     memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops,
 292                           obj, "unin-pci-conf-idx", 0x1000);
 293     memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops,
 294                           obj, "unin-pci-conf-data", 0x1000);
 295
 296     object_property_add_link(obj, "pic", TYPE_OPENPIC,
 297                              (Object **) &s->pic,
 298                              qdev_prop_allow_set_link_before_realize,
 299                              0, NULL);
 300
 301     sysbus_init_mmio(sbd, &h->conf_mem);
 302     sysbus_init_mmio(sbd, &h->data_mem);
 303 }
 304
 305 static void unin_main_pci_host_realize(PCIDevice *d, Error **errp)
 306 {
 307     /* cache_line_size */
 308     d->config[0x0C] = 0x08;
 309     /* latency_timer */
 310     d->config[0x0D] = 0x10;
 311     /* capabilities_pointer */
 312     d->config[0x34] = 0x00;
 313
 314     /*
 315      * Set kMacRISCPCIAddressSelect (0x48) register to indicate PCI
 316      * memory space with base 0x80000000, size 0x10000000 for Apple's
 317      * AppleMacRiscPCI driver
 318      */
 319     d->config[0x48] = 0x0;
 320     d->config[0x49] = 0x0;
 321     d->config[0x4a] = 0x0;
 322     d->config[0x4b] = 0x1;
 323 }
 324
 325 static void unin_agp_pci_host_realize(PCIDevice *d, Error **errp)
 326 {
 327     /* cache_line_size */
 328     d->config[0x0C] = 0x08;
 329     /* latency_timer */
 330     d->config[0x0D] = 0x10;
 331     /* capabilities_pointer
 332     d->config[0x34] = 0x80; */
 333 }
 334
 335 static void u3_agp_pci_host_realize(PCIDevice *d, Error **errp)
 336 {
 337     /* cache line size */
 338     d->config[0x0C] = 0x08;
 339     /* latency timer */
 340     d->config[0x0D] = 0x10;
 341 }
 342
 343 static void unin_internal_pci_host_realize(PCIDevice *d, Error **errp)
 344 {
 345     /* cache_line_size */
 346     d->config[0x0C] = 0x08;
 347     /* latency_timer */
 348     d->config[0x0D] = 0x10;
 349     /* capabilities_pointer */
 350     d->config[0x34] = 0x00;
 351 }
 352
 353 static void unin_main_pci_host_class_init(ObjectClass *klass, void *data)
 354 {
 355     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 356     DeviceClass *dc = DEVICE_CLASS(klass);
 357
 358     k->realize   = unin_main_pci_host_realize;
 359     k->vendor_id = PCI_VENDOR_ID_APPLE;
 360     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI;
 361     k->revision  = 0x00;
 362     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 363     /*
 364      * PCI-facing part of the host bridge, not usable without the
 365      * host-facing part, which can't be device_add'ed, yet.
 366      */
 367     dc->user_creatable = false;
 368 }
 369
 370 static const TypeInfo unin_main_pci_host_info = {
 371     .name = "uni-north-pci",
 372     .parent = TYPE_PCI_DEVICE,
 373     .instance_size = sizeof(PCIDevice),
 374     .class_init = unin_main_pci_host_class_init,
 375     .interfaces = (InterfaceInfo[]) {
 376         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 377         { },
 378     },
 379 };
 380
 381 static void u3_agp_pci_host_class_init(ObjectClass *klass, void *data)
 382 {
 383     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 384     DeviceClass *dc = DEVICE_CLASS(klass);
 385
 386     k->realize   = u3_agp_pci_host_realize;
 387     k->vendor_id = PCI_VENDOR_ID_APPLE;
 388     k->device_id = PCI_DEVICE_ID_APPLE_U3_AGP;
 389     k->revision  = 0x00;
 390     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 391     /*
 392      * PCI-facing part of the host bridge, not usable without the
 393      * host-facing part, which can't be device_add'ed, yet.
 394      */
 395     dc->user_creatable = false;
 396 }
 397
 398 static const TypeInfo u3_agp_pci_host_info = {
 399     .name = "u3-agp",
 400     .parent = TYPE_PCI_DEVICE,
 401     .instance_size = sizeof(PCIDevice),
 402     .class_init = u3_agp_pci_host_class_init,
 403     .interfaces = (InterfaceInfo[]) {
 404         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 405         { },
 406     },
 407 };
 408
 409 static void unin_agp_pci_host_class_init(ObjectClass *klass, void *data)
 410 {
 411     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 412     DeviceClass *dc = DEVICE_CLASS(klass);
 413
 414     k->realize   = unin_agp_pci_host_realize;
 415     k->vendor_id = PCI_VENDOR_ID_APPLE;
 416     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP;
 417     k->revision  = 0x00;
 418     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 419     /*
 420      * PCI-facing part of the host bridge, not usable without the
 421      * host-facing part, which can't be device_add'ed, yet.
 422      */
 423     dc->user_creatable = false;
 424 }
 425
 426 static const TypeInfo unin_agp_pci_host_info = {
 427     .name = "uni-north-agp",
 428     .parent = TYPE_PCI_DEVICE,
 429     .instance_size = sizeof(PCIDevice),
 430     .class_init = unin_agp_pci_host_class_init,
 431     .interfaces = (InterfaceInfo[]) {
 432         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 433         { },
 434     },
 435 };
 436
 437 static void unin_internal_pci_host_class_init(ObjectClass *klass, void *data)
 438 {
 439     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 440     DeviceClass *dc = DEVICE_CLASS(klass);
 441
 442     k->realize   = unin_internal_pci_host_realize;
 443     k->vendor_id = PCI_VENDOR_ID_APPLE;
 444     k->device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI;
 445     k->revision  = 0x00;
 446     k->class_id  = PCI_CLASS_BRIDGE_HOST;
 447     /*
 448      * PCI-facing part of the host bridge, not usable without the
 449      * host-facing part, which can't be device_add'ed, yet.
 450      */
 451     dc->user_creatable = false;
 452 }
 453
 454 static const TypeInfo unin_internal_pci_host_info = {
 455     .name = "uni-north-internal-pci",
 456     .parent = TYPE_PCI_DEVICE,
 457     .instance_size = sizeof(PCIDevice),
 458     .class_init = unin_internal_pci_host_class_init,
 459     .interfaces = (InterfaceInfo[]) {
 460         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 461         { },
 462     },
 463 };
 464
 465 static Property pci_unin_main_pci_host_props[] = {
 466     DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1),
 467     DEFINE_PROP_END_OF_LIST()
 468 };
 469
 470 static void pci_unin_main_class_init(ObjectClass *klass, void *data)
 471 {
 472     DeviceClass *dc = DEVICE_CLASS(klass);
 473     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 474
 475     dc->realize = pci_unin_main_realize;
 476     dc->props = pci_unin_main_pci_host_props;
 477     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 478     dc->fw_name = "pci";
 479     sbc->explicit_ofw_unit_address = pci_unin_main_ofw_unit_address;
 480 }
 481
 482 static const TypeInfo pci_unin_main_info = {
 483     .name          = TYPE_UNI_NORTH_PCI_HOST_BRIDGE,
 484     .parent        = TYPE_PCI_HOST_BRIDGE,
 485     .instance_size = sizeof(UNINHostState),
 486     .instance_init = pci_unin_main_init,
 487     .class_init    = pci_unin_main_class_init,
 488 };
 489
 490 static void pci_u3_agp_class_init(ObjectClass *klass, void *data)
 491 {
 492     DeviceClass *dc = DEVICE_CLASS(klass);
 493
 494     dc->realize = pci_u3_agp_realize;
 495     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 496 }
 497
 498 static const TypeInfo pci_u3_agp_info = {
 499     .name          = TYPE_U3_AGP_HOST_BRIDGE,
 500     .parent        = TYPE_PCI_HOST_BRIDGE,
 501     .instance_size = sizeof(UNINHostState),
 502     .instance_init = pci_u3_agp_init,
 503     .class_init    = pci_u3_agp_class_init,
 504 };
 505
 506 static void pci_unin_agp_class_init(ObjectClass *klass, void *data)
 507 {
 508     DeviceClass *dc = DEVICE_CLASS(klass);
 509
 510     dc->realize = pci_unin_agp_realize;
 511     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 512 }
 513
 514 static const TypeInfo pci_unin_agp_info = {
 515     .name          = TYPE_UNI_NORTH_AGP_HOST_BRIDGE,
 516     .parent        = TYPE_PCI_HOST_BRIDGE,
 517     .instance_size = sizeof(UNINHostState),
 518     .instance_init = pci_unin_agp_init,
 519     .class_init    = pci_unin_agp_class_init,
 520 };
 521
 522 static void pci_unin_internal_class_init(ObjectClass *klass, void *data)
 523 {
 524     DeviceClass *dc = DEVICE_CLASS(klass);
 525
 526     dc->realize = pci_unin_internal_realize;
 527     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 528 }
 529
 530 static const TypeInfo pci_unin_internal_info = {
 531     .name          = TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE,
 532     .parent        = TYPE_PCI_HOST_BRIDGE,
 533     .instance_size = sizeof(UNINHostState),
 534     .instance_init = pci_unin_internal_init,
 535     .class_init    = pci_unin_internal_class_init,
 536 };
 537
 538 /* UniN device */
 539 static void unin_write(void *opaque, hwaddr addr, uint64_t value,
 540                        unsigned size)
 541 {
 542     trace_unin_write(addr, value);
 543 }
 544
 545 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size)
 546 {
 547     uint32_t value;
 548
 549     switch (addr) {
 550     case 0:
 551         value = UNINORTH_VERSION_10A;
 552         break;
 553     default:
 554         value = 0;
 555     }
 556
 557     trace_unin_read(addr, value);
 558
 559     return value;
 560 }
 561
 562 static const MemoryRegionOps unin_ops = {
 563     .read = unin_read,
 564     .write = unin_write,
 565     .endianness = DEVICE_BIG_ENDIAN,
 566 };
 567
 568 static void unin_init(Object *obj)
 569 {
 570     UNINState *s = UNI_NORTH(obj);
 571     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 572
 573     memory_region_init_io(&s->mem, obj, &unin_ops, s, "unin", 0x1000);
 574
 575     sysbus_init_mmio(sbd, &s->mem);
 576 }
 577
 578 static void unin_class_init(ObjectClass *klass, void *data)
 579 {
 580     DeviceClass *dc = DEVICE_CLASS(klass);
 581
 582     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 583 }
 584
 585 static const TypeInfo unin_info = {
 586     .name          = TYPE_UNI_NORTH,
 587     .parent        = TYPE_SYS_BUS_DEVICE,
 588     .instance_size = sizeof(UNINState),
 589     .instance_init = unin_init,
 590     .class_init    = unin_class_init,
 591 };
 592
 593 static void unin_register_types(void)
 594 {
 595     type_register_static(&unin_main_pci_host_info);
 596     type_register_static(&u3_agp_pci_host_info);
 597     type_register_static(&unin_agp_pci_host_info);
 598     type_register_static(&unin_internal_pci_host_info);
 599
 600     type_register_static(&pci_unin_main_info);
 601     type_register_static(&pci_u3_agp_info);
 602     type_register_static(&pci_unin_agp_info);
 603     type_register_static(&pci_unin_internal_info);
 604
 605     type_register_static(&unin_info);
 606 }
 607
 608 type_init(unin_register_types)