2 * PowerPC exception emulation helpers for QEMU.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/main-loop.h"
23 #include "exec/exec-all.h"
25 #include "helper_regs.h"
26 #include "hw/ppc/ppc.h"
31 #include "sysemu/tcg.h"
32 #include "exec/helper-proto.h"
33 #include "exec/cpu_ldst.h"
36 /*****************************************************************************/
37 /* Exception processing */
38 #if !defined(CONFIG_USER_ONLY)
40 static const char *powerpc_excp_name(int excp
)
43 case POWERPC_EXCP_CRITICAL
: return "CRITICAL";
44 case POWERPC_EXCP_MCHECK
: return "MCHECK";
45 case POWERPC_EXCP_DSI
: return "DSI";
46 case POWERPC_EXCP_ISI
: return "ISI";
47 case POWERPC_EXCP_EXTERNAL
: return "EXTERNAL";
48 case POWERPC_EXCP_ALIGN
: return "ALIGN";
49 case POWERPC_EXCP_PROGRAM
: return "PROGRAM";
50 case POWERPC_EXCP_FPU
: return "FPU";
51 case POWERPC_EXCP_SYSCALL
: return "SYSCALL";
52 case POWERPC_EXCP_APU
: return "APU";
53 case POWERPC_EXCP_DECR
: return "DECR";
54 case POWERPC_EXCP_FIT
: return "FIT";
55 case POWERPC_EXCP_WDT
: return "WDT";
56 case POWERPC_EXCP_DTLB
: return "DTLB";
57 case POWERPC_EXCP_ITLB
: return "ITLB";
58 case POWERPC_EXCP_DEBUG
: return "DEBUG";
59 case POWERPC_EXCP_SPEU
: return "SPEU";
60 case POWERPC_EXCP_EFPDI
: return "EFPDI";
61 case POWERPC_EXCP_EFPRI
: return "EFPRI";
62 case POWERPC_EXCP_EPERFM
: return "EPERFM";
63 case POWERPC_EXCP_DOORI
: return "DOORI";
64 case POWERPC_EXCP_DOORCI
: return "DOORCI";
65 case POWERPC_EXCP_GDOORI
: return "GDOORI";
66 case POWERPC_EXCP_GDOORCI
: return "GDOORCI";
67 case POWERPC_EXCP_HYPPRIV
: return "HYPPRIV";
68 case POWERPC_EXCP_RESET
: return "RESET";
69 case POWERPC_EXCP_DSEG
: return "DSEG";
70 case POWERPC_EXCP_ISEG
: return "ISEG";
71 case POWERPC_EXCP_HDECR
: return "HDECR";
72 case POWERPC_EXCP_TRACE
: return "TRACE";
73 case POWERPC_EXCP_HDSI
: return "HDSI";
74 case POWERPC_EXCP_HISI
: return "HISI";
75 case POWERPC_EXCP_HDSEG
: return "HDSEG";
76 case POWERPC_EXCP_HISEG
: return "HISEG";
77 case POWERPC_EXCP_VPU
: return "VPU";
78 case POWERPC_EXCP_PIT
: return "PIT";
79 case POWERPC_EXCP_EMUL
: return "EMUL";
80 case POWERPC_EXCP_IFTLB
: return "IFTLB";
81 case POWERPC_EXCP_DLTLB
: return "DLTLB";
82 case POWERPC_EXCP_DSTLB
: return "DSTLB";
83 case POWERPC_EXCP_FPA
: return "FPA";
84 case POWERPC_EXCP_DABR
: return "DABR";
85 case POWERPC_EXCP_IABR
: return "IABR";
86 case POWERPC_EXCP_SMI
: return "SMI";
87 case POWERPC_EXCP_PERFM
: return "PERFM";
88 case POWERPC_EXCP_THERM
: return "THERM";
89 case POWERPC_EXCP_VPUA
: return "VPUA";
90 case POWERPC_EXCP_SOFTP
: return "SOFTP";
91 case POWERPC_EXCP_MAINT
: return "MAINT";
92 case POWERPC_EXCP_MEXTBR
: return "MEXTBR";
93 case POWERPC_EXCP_NMEXTBR
: return "NMEXTBR";
94 case POWERPC_EXCP_ITLBE
: return "ITLBE";
95 case POWERPC_EXCP_DTLBE
: return "DTLBE";
96 case POWERPC_EXCP_VSXU
: return "VSXU";
97 case POWERPC_EXCP_FU
: return "FU";
98 case POWERPC_EXCP_HV_EMU
: return "HV_EMU";
99 case POWERPC_EXCP_HV_MAINT
: return "HV_MAINT";
100 case POWERPC_EXCP_HV_FU
: return "HV_FU";
101 case POWERPC_EXCP_SDOOR
: return "SDOOR";
102 case POWERPC_EXCP_SDOOR_HV
: return "SDOOR_HV";
103 case POWERPC_EXCP_HVIRT
: return "HVIRT";
104 case POWERPC_EXCP_SYSCALL_VECTORED
: return "SYSCALL_VECTORED";
106 g_assert_not_reached();
110 static void dump_syscall(CPUPPCState
*env
)
112 qemu_log_mask(CPU_LOG_INT
, "syscall r0=%016" PRIx64
113 " r3=%016" PRIx64
" r4=%016" PRIx64
" r5=%016" PRIx64
114 " r6=%016" PRIx64
" r7=%016" PRIx64
" r8=%016" PRIx64
115 " nip=" TARGET_FMT_lx
"\n",
116 ppc_dump_gpr(env
, 0), ppc_dump_gpr(env
, 3),
117 ppc_dump_gpr(env
, 4), ppc_dump_gpr(env
, 5),
118 ppc_dump_gpr(env
, 6), ppc_dump_gpr(env
, 7),
119 ppc_dump_gpr(env
, 8), env
->nip
);
122 static void dump_hcall(CPUPPCState
*env
)
124 qemu_log_mask(CPU_LOG_INT
, "hypercall r3=%016" PRIx64
125 " r4=%016" PRIx64
" r5=%016" PRIx64
" r6=%016" PRIx64
126 " r7=%016" PRIx64
" r8=%016" PRIx64
" r9=%016" PRIx64
127 " r10=%016" PRIx64
" r11=%016" PRIx64
" r12=%016" PRIx64
128 " nip=" TARGET_FMT_lx
"\n",
129 ppc_dump_gpr(env
, 3), ppc_dump_gpr(env
, 4),
130 ppc_dump_gpr(env
, 5), ppc_dump_gpr(env
, 6),
131 ppc_dump_gpr(env
, 7), ppc_dump_gpr(env
, 8),
132 ppc_dump_gpr(env
, 9), ppc_dump_gpr(env
, 10),
133 ppc_dump_gpr(env
, 11), ppc_dump_gpr(env
, 12),
138 /* Return true iff byteswap is needed to load instruction */
139 static inline bool insn_need_byteswap(CPUArchState
*env
)
141 /* SYSTEM builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
142 return !!(env
->msr
& ((target_ulong
)1 << MSR_LE
));
145 static uint32_t ppc_ldl_code(CPUArchState
*env
, abi_ptr addr
)
147 uint32_t insn
= cpu_ldl_code(env
, addr
);
149 if (insn_need_byteswap(env
)) {
150 insn
= bswap32(insn
);
157 static void ppc_excp_debug_sw_tlb(CPUPPCState
*env
, int excp
)
160 target_ulong
*miss
, *cmp
;
163 if (!qemu_loglevel_mask(CPU_LOG_MMU
)) {
167 if (excp
== POWERPC_EXCP_IFTLB
) {
170 miss
= &env
->spr
[SPR_IMISS
];
171 cmp
= &env
->spr
[SPR_ICMP
];
173 if (excp
== POWERPC_EXCP_DLTLB
) {
179 miss
= &env
->spr
[SPR_DMISS
];
180 cmp
= &env
->spr
[SPR_DCMP
];
182 qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx
" %cC "
183 TARGET_FMT_lx
" H1 " TARGET_FMT_lx
" H2 "
184 TARGET_FMT_lx
" %08x\n", es
, en
, *miss
, en
, *cmp
,
185 env
->spr
[SPR_HASH1
], env
->spr
[SPR_HASH2
],
189 #if defined(TARGET_PPC64)
190 static int powerpc_reset_wakeup(CPUPPCState
*env
, int excp
, target_ulong
*msr
)
192 /* We no longer are in a PM state */
193 env
->resume_as_sreset
= false;
195 /* Pretend to be returning from doze always as we don't lose state */
196 *msr
|= SRR1_WS_NOLOSS
;
198 /* Machine checks are sent normally */
199 if (excp
== POWERPC_EXCP_MCHECK
) {
203 case POWERPC_EXCP_RESET
:
204 *msr
|= SRR1_WAKERESET
;
206 case POWERPC_EXCP_EXTERNAL
:
209 case POWERPC_EXCP_DECR
:
210 *msr
|= SRR1_WAKEDEC
;
212 case POWERPC_EXCP_SDOOR
:
213 *msr
|= SRR1_WAKEDBELL
;
215 case POWERPC_EXCP_SDOOR_HV
:
216 *msr
|= SRR1_WAKEHDBELL
;
218 case POWERPC_EXCP_HV_MAINT
:
219 *msr
|= SRR1_WAKEHMI
;
221 case POWERPC_EXCP_HVIRT
:
222 *msr
|= SRR1_WAKEHVI
;
225 cpu_abort(env_cpu(env
),
226 "Unsupported exception %d in Power Save mode\n", excp
);
228 return POWERPC_EXCP_RESET
;
232 * AIL - Alternate Interrupt Location, a mode that allows interrupts to be
233 * taken with the MMU on, and which uses an alternate location (e.g., so the
234 * kernel/hv can map the vectors there with an effective address).
236 * An interrupt is considered to be taken "with AIL" or "AIL applies" if they
237 * are delivered in this way. AIL requires the LPCR to be set to enable this
238 * mode, and then a number of conditions have to be true for AIL to apply.
240 * First of all, SRESET, MCE, and HMI are always delivered without AIL, because
241 * they specifically want to be in real mode (e.g., the MCE might be signaling
242 * a SLB multi-hit which requires SLB flush before the MMU can be enabled).
244 * After that, behaviour depends on the current MSR[IR], MSR[DR], MSR[HV],
245 * whether or not the interrupt changes MSR[HV] from 0 to 1, and the current
246 * radix mode (LPCR[HR]).
248 * POWER8, POWER9 with LPCR[HR]=0
249 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
250 * +-----------+-------------+---------+-------------+-----+
251 * | a | 00/01/10 | x | x | 0 |
252 * | a | 11 | 0 | 1 | 0 |
253 * | a | 11 | 1 | 1 | a |
254 * | a | 11 | 0 | 0 | a |
255 * +-------------------------------------------------------+
257 * POWER9 with LPCR[HR]=1
258 * | LPCR[AIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
259 * +-----------+-------------+---------+-------------+-----+
260 * | a | 00/01/10 | x | x | 0 |
261 * | a | 11 | x | x | a |
262 * +-------------------------------------------------------+
264 * The difference with POWER9 being that MSR[HV] 0->1 interrupts can be sent to
265 * the hypervisor in AIL mode if the guest is radix. This is good for
266 * performance but allows the guest to influence the AIL of hypervisor
267 * interrupts using its MSR, and also the hypervisor must disallow guest
268 * interrupts (MSR[HV] 0->0) from using AIL if the hypervisor does not want to
269 * use AIL for its MSR[HV] 0->1 interrupts.
271 * POWER10 addresses those issues with a new LPCR[HAIL] bit that is applied to
272 * interrupts that begin execution with MSR[HV]=1 (so both MSR[HV] 0->1 and
275 * HAIL=1 is equivalent to AIL=3, for interrupts delivered with MSR[HV]=1.
277 * POWER10 behaviour is
278 * | LPCR[AIL] | LPCR[HAIL] | MSR[IR||DR] | MSR[HV] | new MSR[HV] | AIL |
279 * +-----------+------------+-------------+---------+-------------+-----+
280 * | a | h | 00/01/10 | 0 | 0 | 0 |
281 * | a | h | 11 | 0 | 0 | a |
282 * | a | h | x | 0 | 1 | h |
283 * | a | h | 00/01/10 | 1 | 1 | 0 |
284 * | a | h | 11 | 1 | 1 | h |
285 * +--------------------------------------------------------------------+
287 static void ppc_excp_apply_ail(PowerPCCPU
*cpu
, int excp
, target_ulong msr
,
288 target_ulong
*new_msr
, target_ulong
*vector
)
290 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cpu
);
291 CPUPPCState
*env
= &cpu
->env
;
292 bool mmu_all_on
= ((msr
>> MSR_IR
) & 1) && ((msr
>> MSR_DR
) & 1);
293 bool hv_escalation
= !(msr
& MSR_HVB
) && (*new_msr
& MSR_HVB
);
296 if (excp
== POWERPC_EXCP_MCHECK
||
297 excp
== POWERPC_EXCP_RESET
||
298 excp
== POWERPC_EXCP_HV_MAINT
) {
299 /* SRESET, MCE, HMI never apply AIL */
303 if (!(pcc
->lpcr_mask
& LPCR_AIL
)) {
304 /* This CPU does not have AIL */
309 if (!(pcc
->lpcr_mask
& LPCR_HAIL
)) {
311 /* AIL only works if MSR[IR] and MSR[DR] are both enabled. */
314 if (hv_escalation
&& !(env
->spr
[SPR_LPCR
] & LPCR_HR
)) {
316 * AIL does not work if there is a MSR[HV] 0->1 transition and the
317 * partition is in HPT mode. For radix guests, such interrupts are
318 * allowed to be delivered to the hypervisor in ail mode.
323 ail
= (env
->spr
[SPR_LPCR
] & LPCR_AIL
) >> LPCR_AIL_SHIFT
;
328 /* AIL=1 is reserved, treat it like AIL=0 */
334 if (!mmu_all_on
&& !hv_escalation
) {
336 * AIL works for HV interrupts even with guest MSR[IR/DR] disabled.
337 * Guest->guest and HV->HV interrupts do require MMU on.
342 if (*new_msr
& MSR_HVB
) {
343 if (!(env
->spr
[SPR_LPCR
] & LPCR_HAIL
)) {
344 /* HV interrupts depend on LPCR[HAIL] */
347 ail
= 3; /* HAIL=1 gives AIL=3 behaviour for HV interrupts */
349 ail
= (env
->spr
[SPR_LPCR
] & LPCR_AIL
) >> LPCR_AIL_SHIFT
;
354 if (ail
== 1 || ail
== 2) {
355 /* AIL=1 and AIL=2 are reserved, treat them like AIL=0 */
361 * AIL applies, so the new MSR gets IR and DR set, and an offset applied
364 *new_msr
|= (1 << MSR_IR
) | (1 << MSR_DR
);
366 if (excp
!= POWERPC_EXCP_SYSCALL_VECTORED
) {
368 *vector
|= 0x0000000000018000ull
;
369 } else if (ail
== 3) {
370 *vector
|= 0xc000000000004000ull
;
374 * scv AIL is a little different. AIL=2 does not change the address,
375 * only the MSR. AIL=3 replaces the 0x17000 base with 0xc...3000.
378 *vector
&= ~0x0000000000017000ull
; /* Un-apply the base offset */
379 *vector
|= 0xc000000000003000ull
; /* Apply scv's AIL=3 offset */
385 static void powerpc_reset_excp_state(PowerPCCPU
*cpu
)
387 CPUState
*cs
= CPU(cpu
);
388 CPUPPCState
*env
= &cpu
->env
;
390 /* Reset exception state */
391 cs
->exception_index
= POWERPC_EXCP_NONE
;
395 static void powerpc_set_excp_state(PowerPCCPU
*cpu
, target_ulong vector
,
398 CPUPPCState
*env
= &cpu
->env
;
400 assert((msr
& env
->msr_mask
) == msr
);
403 * We don't use hreg_store_msr here as already have treated any
404 * special case that could occur. Just store MSR and update hflags
406 * Note: We *MUST* not use hreg_store_msr() as-is anyway because it
407 * will prevent setting of the HV bit which some exceptions might need
412 hreg_compute_hflags(env
);
413 ppc_maybe_interrupt(env
);
415 powerpc_reset_excp_state(cpu
);
418 * Any interrupt is context synchronizing, check if TCG TLB needs
419 * a delayed flush on ppc64
421 check_tlb_flush(env
, false);
423 /* Reset the reservation */
424 env
->reserve_addr
= -1;
427 static void powerpc_mcheck_checkstop(CPUPPCState
*env
)
429 CPUState
*cs
= env_cpu(env
);
431 if (FIELD_EX64(env
->msr
, MSR
, ME
)) {
435 /* Machine check exception is not enabled. Enter checkstop state. */
436 fprintf(stderr
, "Machine check while not allowed. "
437 "Entering checkstop state\n");
438 if (qemu_log_separate()) {
439 qemu_log("Machine check while not allowed. "
440 "Entering checkstop state\n");
443 cpu_interrupt_exittb(cs
);
446 static void powerpc_excp_40x(PowerPCCPU
*cpu
, int excp
)
448 CPUState
*cs
= CPU(cpu
);
449 CPUPPCState
*env
= &cpu
->env
;
450 target_ulong msr
, new_msr
, vector
;
453 /* new srr1 value excluding must-be-zero bits */
454 msr
= env
->msr
& ~0x783f0000ULL
;
457 * new interrupt handler msr preserves existing ME unless
458 * explicitly overridden.
460 new_msr
= env
->msr
& (((target_ulong
)1 << MSR_ME
));
462 /* target registers */
467 * Hypervisor emulation assistance interrupt only exists on server
468 * arch 2.05 server or later.
470 if (excp
== POWERPC_EXCP_HV_EMU
) {
471 excp
= POWERPC_EXCP_PROGRAM
;
474 vector
= env
->excp_vectors
[excp
];
475 if (vector
== (target_ulong
)-1ULL) {
476 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
480 vector
|= env
->excp_prefix
;
483 case POWERPC_EXCP_CRITICAL
: /* Critical input */
487 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
488 powerpc_mcheck_checkstop(env
);
489 /* machine check exceptions don't have ME set */
490 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
495 case POWERPC_EXCP_DSI
: /* Data storage exception */
496 trace_ppc_excp_dsi(env
->spr
[SPR_40x_ESR
], env
->spr
[SPR_40x_DEAR
]);
498 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
499 trace_ppc_excp_isi(msr
, env
->nip
);
501 case POWERPC_EXCP_EXTERNAL
: /* External input */
503 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
505 case POWERPC_EXCP_PROGRAM
: /* Program exception */
506 switch (env
->error_code
& ~0xF) {
507 case POWERPC_EXCP_FP
:
508 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
509 trace_ppc_excp_fp_ignore();
510 powerpc_reset_excp_state(cpu
);
513 env
->spr
[SPR_40x_ESR
] = ESR_FP
;
515 case POWERPC_EXCP_INVAL
:
516 trace_ppc_excp_inval(env
->nip
);
517 env
->spr
[SPR_40x_ESR
] = ESR_PIL
;
519 case POWERPC_EXCP_PRIV
:
520 env
->spr
[SPR_40x_ESR
] = ESR_PPR
;
522 case POWERPC_EXCP_TRAP
:
523 env
->spr
[SPR_40x_ESR
] = ESR_PTR
;
526 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
531 case POWERPC_EXCP_SYSCALL
: /* System call exception */
535 * We need to correct the NIP which in this case is supposed
536 * to point to the next instruction
540 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
541 trace_ppc_excp_print("FIT");
543 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
544 trace_ppc_excp_print("WDT");
546 case POWERPC_EXCP_DTLB
: /* Data TLB error */
547 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
549 case POWERPC_EXCP_PIT
: /* Programmable interval timer interrupt */
550 trace_ppc_excp_print("PIT");
552 case POWERPC_EXCP_DEBUG
: /* Debug interrupt */
553 cpu_abort(cs
, "%s exception not implemented\n",
554 powerpc_excp_name(excp
));
557 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
562 env
->spr
[srr0
] = env
->nip
;
565 env
->spr
[srr1
] = msr
;
567 powerpc_set_excp_state(cpu
, vector
, new_msr
);
570 static void powerpc_excp_6xx(PowerPCCPU
*cpu
, int excp
)
572 CPUState
*cs
= CPU(cpu
);
573 CPUPPCState
*env
= &cpu
->env
;
574 target_ulong msr
, new_msr
, vector
;
576 /* new srr1 value excluding must-be-zero bits */
577 msr
= env
->msr
& ~0x783f0000ULL
;
580 * new interrupt handler msr preserves existing ME unless
581 * explicitly overridden
583 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
586 * Hypervisor emulation assistance interrupt only exists on server
587 * arch 2.05 server or later.
589 if (excp
== POWERPC_EXCP_HV_EMU
) {
590 excp
= POWERPC_EXCP_PROGRAM
;
593 vector
= env
->excp_vectors
[excp
];
594 if (vector
== (target_ulong
)-1ULL) {
595 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
599 vector
|= env
->excp_prefix
;
602 case POWERPC_EXCP_CRITICAL
: /* Critical input */
604 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
605 powerpc_mcheck_checkstop(env
);
606 /* machine check exceptions don't have ME set */
607 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
610 case POWERPC_EXCP_DSI
: /* Data storage exception */
611 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
613 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
614 trace_ppc_excp_isi(msr
, env
->nip
);
615 msr
|= env
->error_code
;
617 case POWERPC_EXCP_EXTERNAL
: /* External input */
619 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
620 /* Get rS/rD and rA from faulting opcode */
622 * Note: the opcode fields will not be set properly for a
623 * direct store load/store, but nobody cares as nobody
624 * actually uses direct store segments.
626 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
628 case POWERPC_EXCP_PROGRAM
: /* Program exception */
629 switch (env
->error_code
& ~0xF) {
630 case POWERPC_EXCP_FP
:
631 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
632 trace_ppc_excp_fp_ignore();
633 powerpc_reset_excp_state(cpu
);
638 * FP exceptions always have NIP pointing to the faulting
639 * instruction, so always use store_next and claim we are
640 * precise in the MSR.
644 case POWERPC_EXCP_INVAL
:
645 trace_ppc_excp_inval(env
->nip
);
648 case POWERPC_EXCP_PRIV
:
651 case POWERPC_EXCP_TRAP
:
655 /* Should never occur */
656 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
661 case POWERPC_EXCP_SYSCALL
: /* System call exception */
665 * We need to correct the NIP which in this case is supposed
666 * to point to the next instruction
670 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
671 case POWERPC_EXCP_DECR
: /* Decrementer exception */
673 case POWERPC_EXCP_DTLB
: /* Data TLB error */
674 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
676 case POWERPC_EXCP_RESET
: /* System reset exception */
677 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
678 cpu_abort(cs
, "Trying to deliver power-saving system reset "
679 "exception %d with no HV support\n", excp
);
682 case POWERPC_EXCP_TRACE
: /* Trace exception */
684 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
685 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
686 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
687 /* Swap temporary saved registers with GPRs */
688 if (!(new_msr
& ((target_ulong
)1 << MSR_TGPR
))) {
689 new_msr
|= (target_ulong
)1 << MSR_TGPR
;
690 hreg_swap_gpr_tgpr(env
);
693 ppc_excp_debug_sw_tlb(env
, excp
);
695 msr
|= env
->crf
[0] << 28;
696 msr
|= env
->error_code
; /* key, D/I, S/L bits */
697 /* Set way using a LRU mechanism */
698 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
700 case POWERPC_EXCP_FPA
: /* Floating-point assist exception */
701 case POWERPC_EXCP_DABR
: /* Data address breakpoint */
702 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
703 case POWERPC_EXCP_SMI
: /* System management interrupt */
704 case POWERPC_EXCP_MEXTBR
: /* Maskable external breakpoint */
705 case POWERPC_EXCP_NMEXTBR
: /* Non maskable external breakpoint */
706 cpu_abort(cs
, "%s exception not implemented\n",
707 powerpc_excp_name(excp
));
710 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
715 * Sort out endianness of interrupt, this differs depending on the
716 * CPU, the HV mode, etc...
718 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
719 new_msr
|= (target_ulong
)1 << MSR_LE
;
723 env
->spr
[SPR_SRR0
] = env
->nip
;
726 env
->spr
[SPR_SRR1
] = msr
;
728 powerpc_set_excp_state(cpu
, vector
, new_msr
);
731 static void powerpc_excp_7xx(PowerPCCPU
*cpu
, int excp
)
733 CPUState
*cs
= CPU(cpu
);
734 CPUPPCState
*env
= &cpu
->env
;
735 target_ulong msr
, new_msr
, vector
;
737 /* new srr1 value excluding must-be-zero bits */
738 msr
= env
->msr
& ~0x783f0000ULL
;
741 * new interrupt handler msr preserves existing ME unless
742 * explicitly overridden
744 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
747 * Hypervisor emulation assistance interrupt only exists on server
748 * arch 2.05 server or later.
750 if (excp
== POWERPC_EXCP_HV_EMU
) {
751 excp
= POWERPC_EXCP_PROGRAM
;
754 vector
= env
->excp_vectors
[excp
];
755 if (vector
== (target_ulong
)-1ULL) {
756 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
760 vector
|= env
->excp_prefix
;
763 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
764 powerpc_mcheck_checkstop(env
);
765 /* machine check exceptions don't have ME set */
766 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
769 case POWERPC_EXCP_DSI
: /* Data storage exception */
770 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
772 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
773 trace_ppc_excp_isi(msr
, env
->nip
);
774 msr
|= env
->error_code
;
776 case POWERPC_EXCP_EXTERNAL
: /* External input */
778 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
779 /* Get rS/rD and rA from faulting opcode */
781 * Note: the opcode fields will not be set properly for a
782 * direct store load/store, but nobody cares as nobody
783 * actually uses direct store segments.
785 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
787 case POWERPC_EXCP_PROGRAM
: /* Program exception */
788 switch (env
->error_code
& ~0xF) {
789 case POWERPC_EXCP_FP
:
790 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
791 trace_ppc_excp_fp_ignore();
792 powerpc_reset_excp_state(cpu
);
797 * FP exceptions always have NIP pointing to the faulting
798 * instruction, so always use store_next and claim we are
799 * precise in the MSR.
803 case POWERPC_EXCP_INVAL
:
804 trace_ppc_excp_inval(env
->nip
);
807 case POWERPC_EXCP_PRIV
:
810 case POWERPC_EXCP_TRAP
:
814 /* Should never occur */
815 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
820 case POWERPC_EXCP_SYSCALL
: /* System call exception */
822 int lev
= env
->error_code
;
824 if (lev
== 1 && cpu
->vhyp
) {
831 * We need to correct the NIP which in this case is supposed
832 * to point to the next instruction
837 * The Virtual Open Firmware (VOF) relies on the 'sc 1'
838 * instruction to communicate with QEMU. The pegasos2 machine
839 * uses VOF and the 7xx CPUs, so although the 7xx don't have
840 * HV mode, we need to keep hypercall support.
842 if (lev
== 1 && cpu
->vhyp
) {
843 PPCVirtualHypervisorClass
*vhc
=
844 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
845 vhc
->hypercall(cpu
->vhyp
, cpu
);
846 powerpc_reset_excp_state(cpu
);
852 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
853 case POWERPC_EXCP_DECR
: /* Decrementer exception */
855 case POWERPC_EXCP_RESET
: /* System reset exception */
856 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
857 cpu_abort(cs
, "Trying to deliver power-saving system reset "
858 "exception %d with no HV support\n", excp
);
861 case POWERPC_EXCP_TRACE
: /* Trace exception */
863 case POWERPC_EXCP_IFTLB
: /* Instruction fetch TLB error */
864 case POWERPC_EXCP_DLTLB
: /* Data load TLB miss */
865 case POWERPC_EXCP_DSTLB
: /* Data store TLB miss */
866 ppc_excp_debug_sw_tlb(env
, excp
);
868 msr
|= env
->crf
[0] << 28;
869 msr
|= env
->error_code
; /* key, D/I, S/L bits */
870 /* Set way using a LRU mechanism */
871 msr
|= ((env
->last_way
+ 1) & (env
->nb_ways
- 1)) << 17;
874 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
875 case POWERPC_EXCP_SMI
: /* System management interrupt */
876 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
877 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor interrupt */
878 cpu_abort(cs
, "%s exception not implemented\n",
879 powerpc_excp_name(excp
));
882 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
887 * Sort out endianness of interrupt, this differs depending on the
888 * CPU, the HV mode, etc...
890 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
891 new_msr
|= (target_ulong
)1 << MSR_LE
;
895 env
->spr
[SPR_SRR0
] = env
->nip
;
898 env
->spr
[SPR_SRR1
] = msr
;
900 powerpc_set_excp_state(cpu
, vector
, new_msr
);
903 static void powerpc_excp_74xx(PowerPCCPU
*cpu
, int excp
)
905 CPUState
*cs
= CPU(cpu
);
906 CPUPPCState
*env
= &cpu
->env
;
907 target_ulong msr
, new_msr
, vector
;
909 /* new srr1 value excluding must-be-zero bits */
910 msr
= env
->msr
& ~0x783f0000ULL
;
913 * new interrupt handler msr preserves existing ME unless
914 * explicitly overridden
916 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
919 * Hypervisor emulation assistance interrupt only exists on server
920 * arch 2.05 server or later.
922 if (excp
== POWERPC_EXCP_HV_EMU
) {
923 excp
= POWERPC_EXCP_PROGRAM
;
926 vector
= env
->excp_vectors
[excp
];
927 if (vector
== (target_ulong
)-1ULL) {
928 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
932 vector
|= env
->excp_prefix
;
935 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
936 powerpc_mcheck_checkstop(env
);
937 /* machine check exceptions don't have ME set */
938 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
941 case POWERPC_EXCP_DSI
: /* Data storage exception */
942 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
944 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
945 trace_ppc_excp_isi(msr
, env
->nip
);
946 msr
|= env
->error_code
;
948 case POWERPC_EXCP_EXTERNAL
: /* External input */
950 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
951 /* Get rS/rD and rA from faulting opcode */
953 * Note: the opcode fields will not be set properly for a
954 * direct store load/store, but nobody cares as nobody
955 * actually uses direct store segments.
957 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
959 case POWERPC_EXCP_PROGRAM
: /* Program exception */
960 switch (env
->error_code
& ~0xF) {
961 case POWERPC_EXCP_FP
:
962 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
963 trace_ppc_excp_fp_ignore();
964 powerpc_reset_excp_state(cpu
);
969 * FP exceptions always have NIP pointing to the faulting
970 * instruction, so always use store_next and claim we are
971 * precise in the MSR.
975 case POWERPC_EXCP_INVAL
:
976 trace_ppc_excp_inval(env
->nip
);
979 case POWERPC_EXCP_PRIV
:
982 case POWERPC_EXCP_TRAP
:
986 /* Should never occur */
987 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
992 case POWERPC_EXCP_SYSCALL
: /* System call exception */
994 int lev
= env
->error_code
;
996 if (lev
== 1 && cpu
->vhyp
) {
1003 * We need to correct the NIP which in this case is supposed
1004 * to point to the next instruction
1009 * The Virtual Open Firmware (VOF) relies on the 'sc 1'
1010 * instruction to communicate with QEMU. The pegasos2 machine
1011 * uses VOF and the 74xx CPUs, so although the 74xx don't have
1012 * HV mode, we need to keep hypercall support.
1014 if (lev
== 1 && cpu
->vhyp
) {
1015 PPCVirtualHypervisorClass
*vhc
=
1016 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
1017 vhc
->hypercall(cpu
->vhyp
, cpu
);
1018 powerpc_reset_excp_state(cpu
);
1024 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1025 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1027 case POWERPC_EXCP_RESET
: /* System reset exception */
1028 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1029 cpu_abort(cs
, "Trying to deliver power-saving system reset "
1030 "exception %d with no HV support\n", excp
);
1033 case POWERPC_EXCP_TRACE
: /* Trace exception */
1035 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
1037 case POWERPC_EXCP_IABR
: /* Instruction address breakpoint */
1038 case POWERPC_EXCP_SMI
: /* System management interrupt */
1039 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
1040 case POWERPC_EXCP_PERFM
: /* Embedded performance monitor interrupt */
1041 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
1042 cpu_abort(cs
, "%s exception not implemented\n",
1043 powerpc_excp_name(excp
));
1046 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
1051 * Sort out endianness of interrupt, this differs depending on the
1052 * CPU, the HV mode, etc...
1054 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
1055 new_msr
|= (target_ulong
)1 << MSR_LE
;
1059 env
->spr
[SPR_SRR0
] = env
->nip
;
1062 env
->spr
[SPR_SRR1
] = msr
;
1064 powerpc_set_excp_state(cpu
, vector
, new_msr
);
1067 static void powerpc_excp_booke(PowerPCCPU
*cpu
, int excp
)
1069 CPUState
*cs
= CPU(cpu
);
1070 CPUPPCState
*env
= &cpu
->env
;
1071 target_ulong msr
, new_msr
, vector
;
1077 * new interrupt handler msr preserves existing ME unless
1078 * explicitly overridden
1080 new_msr
= env
->msr
& ((target_ulong
)1 << MSR_ME
);
1082 /* target registers */
1087 * Hypervisor emulation assistance interrupt only exists on server
1088 * arch 2.05 server or later.
1090 if (excp
== POWERPC_EXCP_HV_EMU
) {
1091 excp
= POWERPC_EXCP_PROGRAM
;
1096 * SPEU and VPU share the same IVOR but they exist in different
1097 * processors. SPEU is e500v1/2 only and VPU is e6500 only.
1099 if (excp
== POWERPC_EXCP_VPU
) {
1100 excp
= POWERPC_EXCP_SPEU
;
1104 vector
= env
->excp_vectors
[excp
];
1105 if (vector
== (target_ulong
)-1ULL) {
1106 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
1110 vector
|= env
->excp_prefix
;
1113 case POWERPC_EXCP_CRITICAL
: /* Critical input */
1114 srr0
= SPR_BOOKE_CSRR0
;
1115 srr1
= SPR_BOOKE_CSRR1
;
1117 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1118 powerpc_mcheck_checkstop(env
);
1119 /* machine check exceptions don't have ME set */
1120 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
1122 /* FIXME: choose one or the other based on CPU type */
1123 srr0
= SPR_BOOKE_MCSRR0
;
1124 srr1
= SPR_BOOKE_MCSRR1
;
1126 env
->spr
[SPR_BOOKE_CSRR0
] = env
->nip
;
1127 env
->spr
[SPR_BOOKE_CSRR1
] = msr
;
1130 case POWERPC_EXCP_DSI
: /* Data storage exception */
1131 trace_ppc_excp_dsi(env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
1133 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1134 trace_ppc_excp_isi(msr
, env
->nip
);
1136 case POWERPC_EXCP_EXTERNAL
: /* External input */
1137 if (env
->mpic_proxy
) {
1138 /* IACK the IRQ on delivery */
1139 env
->spr
[SPR_BOOKE_EPR
] = ldl_phys(cs
->as
, env
->mpic_iack
);
1142 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1144 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1145 switch (env
->error_code
& ~0xF) {
1146 case POWERPC_EXCP_FP
:
1147 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
1148 trace_ppc_excp_fp_ignore();
1149 powerpc_reset_excp_state(cpu
);
1154 * FP exceptions always have NIP pointing to the faulting
1155 * instruction, so always use store_next and claim we are
1156 * precise in the MSR.
1159 env
->spr
[SPR_BOOKE_ESR
] = ESR_FP
;
1161 case POWERPC_EXCP_INVAL
:
1162 trace_ppc_excp_inval(env
->nip
);
1164 env
->spr
[SPR_BOOKE_ESR
] = ESR_PIL
;
1166 case POWERPC_EXCP_PRIV
:
1168 env
->spr
[SPR_BOOKE_ESR
] = ESR_PPR
;
1170 case POWERPC_EXCP_TRAP
:
1172 env
->spr
[SPR_BOOKE_ESR
] = ESR_PTR
;
1175 /* Should never occur */
1176 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
1181 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1185 * We need to correct the NIP which in this case is supposed
1186 * to point to the next instruction
1190 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1191 case POWERPC_EXCP_APU
: /* Auxiliary processor unavailable */
1192 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1194 case POWERPC_EXCP_FIT
: /* Fixed-interval timer interrupt */
1196 trace_ppc_excp_print("FIT");
1198 case POWERPC_EXCP_WDT
: /* Watchdog timer interrupt */
1199 trace_ppc_excp_print("WDT");
1200 srr0
= SPR_BOOKE_CSRR0
;
1201 srr1
= SPR_BOOKE_CSRR1
;
1203 case POWERPC_EXCP_DTLB
: /* Data TLB error */
1204 case POWERPC_EXCP_ITLB
: /* Instruction TLB error */
1206 case POWERPC_EXCP_DEBUG
: /* Debug interrupt */
1207 if (env
->flags
& POWERPC_FLAG_DE
) {
1208 /* FIXME: choose one or the other based on CPU type */
1209 srr0
= SPR_BOOKE_DSRR0
;
1210 srr1
= SPR_BOOKE_DSRR1
;
1212 env
->spr
[SPR_BOOKE_CSRR0
] = env
->nip
;
1213 env
->spr
[SPR_BOOKE_CSRR1
] = msr
;
1215 /* DBSR already modified by caller */
1217 cpu_abort(cs
, "Debug exception triggered on unsupported model\n");
1220 case POWERPC_EXCP_SPEU
: /* SPE/embedded floating-point unavailable/VPU */
1221 env
->spr
[SPR_BOOKE_ESR
] = ESR_SPV
;
1223 case POWERPC_EXCP_DOORI
: /* Embedded doorbell interrupt */
1225 case POWERPC_EXCP_DOORCI
: /* Embedded doorbell critical interrupt */
1226 srr0
= SPR_BOOKE_CSRR0
;
1227 srr1
= SPR_BOOKE_CSRR1
;
1229 case POWERPC_EXCP_RESET
: /* System reset exception */
1230 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1231 cpu_abort(cs
, "Trying to deliver power-saving system reset "
1232 "exception %d with no HV support\n", excp
);
1235 case POWERPC_EXCP_EFPDI
: /* Embedded floating-point data interrupt */
1236 case POWERPC_EXCP_EFPRI
: /* Embedded floating-point round interrupt */
1237 cpu_abort(cs
, "%s exception not implemented\n",
1238 powerpc_excp_name(excp
));
1241 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
1245 #if defined(TARGET_PPC64)
1246 if (env
->spr
[SPR_BOOKE_EPCR
] & EPCR_ICM
) {
1247 /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
1248 new_msr
|= (target_ulong
)1 << MSR_CM
;
1250 vector
= (uint32_t)vector
;
1255 env
->spr
[srr0
] = env
->nip
;
1258 env
->spr
[srr1
] = msr
;
1260 powerpc_set_excp_state(cpu
, vector
, new_msr
);
1264 * When running a nested HV guest under vhyp, external interrupts are
1265 * delivered as HVIRT.
1267 static bool books_vhyp_promotes_external_to_hvirt(PowerPCCPU
*cpu
)
1270 return vhyp_cpu_in_nested(cpu
);
1277 * When running under vhyp, hcalls are always intercepted and sent to the
1278 * vhc->hypercall handler.
1280 static bool books_vhyp_handles_hcall(PowerPCCPU
*cpu
)
1283 return !vhyp_cpu_in_nested(cpu
);
1289 * When running a nested KVM HV guest under vhyp, HV exceptions are not
1290 * delivered to the guest (because there is no concept of HV support), but
1291 * rather they are sent to the vhyp to exit from the L2 back to the L1 and
1292 * return from the H_ENTER_NESTED hypercall.
1294 static bool books_vhyp_handles_hv_excp(PowerPCCPU
*cpu
)
1297 return vhyp_cpu_in_nested(cpu
);
1303 static bool is_prefix_insn(CPUPPCState
*env
, uint32_t insn
)
1305 if (!(env
->insns_flags2
& PPC2_ISA310
)) {
1308 return ((insn
& 0xfc000000) == 0x04000000);
1311 static bool is_prefix_insn_excp(PowerPCCPU
*cpu
, int excp
)
1313 CPUPPCState
*env
= &cpu
->env
;
1315 if (!tcg_enabled()) {
1317 * This does not load instructions and set the prefix bit correctly
1318 * for injected interrupts with KVM. That may have to be discovered
1319 * and set by the KVM layer before injecting.
1325 case POWERPC_EXCP_HDSI
:
1326 /* HDSI PRTABLE_FAULT has the originating access type in error_code */
1327 if ((env
->spr
[SPR_HDSISR
] & DSISR_PRTABLE_FAULT
) &&
1328 (env
->error_code
== MMU_INST_FETCH
)) {
1330 * Fetch failed due to partition scope translation, so prefix
1331 * indication is not relevant (and attempting to load the
1332 * instruction at NIP would cause recursive faults with the same
1338 case POWERPC_EXCP_MCHECK
:
1339 case POWERPC_EXCP_DSI
:
1340 case POWERPC_EXCP_DSEG
:
1341 case POWERPC_EXCP_ALIGN
:
1342 case POWERPC_EXCP_PROGRAM
:
1343 case POWERPC_EXCP_FPU
:
1344 case POWERPC_EXCP_TRACE
:
1345 case POWERPC_EXCP_HV_EMU
:
1346 case POWERPC_EXCP_VPU
:
1347 case POWERPC_EXCP_VSXU
:
1348 case POWERPC_EXCP_FU
:
1349 case POWERPC_EXCP_HV_FU
: {
1350 uint32_t insn
= ppc_ldl_code(env
, env
->nip
);
1351 if (is_prefix_insn(env
, insn
)) {
1362 static bool is_prefix_insn_excp(PowerPCCPU
*cpu
, int excp
)
1368 static void powerpc_excp_books(PowerPCCPU
*cpu
, int excp
)
1370 CPUState
*cs
= CPU(cpu
);
1371 CPUPPCState
*env
= &cpu
->env
;
1372 target_ulong msr
, new_msr
, vector
;
1373 int srr0
, srr1
, lev
= -1;
1375 /* new srr1 value excluding must-be-zero bits */
1376 msr
= env
->msr
& ~0x783f0000ULL
;
1379 * new interrupt handler msr preserves existing HV and ME unless
1380 * explicitly overridden
1382 new_msr
= env
->msr
& (((target_ulong
)1 << MSR_ME
) | MSR_HVB
);
1384 /* target registers */
1389 * check for special resume at 0x100 from doze/nap/sleep/winkle on
1392 if (env
->resume_as_sreset
) {
1393 excp
= powerpc_reset_wakeup(env
, excp
, &msr
);
1397 * We don't want to generate a Hypervisor Emulation Assistance
1398 * Interrupt if we don't have HVB in msr_mask (PAPR mode),
1399 * unless running a nested-hv guest, in which case the L1
1400 * kernel wants the interrupt.
1402 if (excp
== POWERPC_EXCP_HV_EMU
&& !(env
->msr_mask
& MSR_HVB
) &&
1403 !books_vhyp_handles_hv_excp(cpu
)) {
1404 excp
= POWERPC_EXCP_PROGRAM
;
1407 vector
= env
->excp_vectors
[excp
];
1408 if (vector
== (target_ulong
)-1ULL) {
1409 cpu_abort(cs
, "Raised an exception without defined vector %d\n",
1413 vector
|= env
->excp_prefix
;
1415 if (is_prefix_insn_excp(cpu
, excp
)) {
1420 case POWERPC_EXCP_MCHECK
: /* Machine check exception */
1421 powerpc_mcheck_checkstop(env
);
1422 if (env
->msr_mask
& MSR_HVB
) {
1424 * ISA specifies HV, but can be delivered to guest with HV
1425 * clear (e.g., see FWNMI in PAPR).
1427 new_msr
|= (target_ulong
)MSR_HVB
;
1430 /* machine check exceptions don't have ME set */
1431 new_msr
&= ~((target_ulong
)1 << MSR_ME
);
1433 msr
|= env
->error_code
;
1436 case POWERPC_EXCP_DSI
: /* Data storage exception */
1437 trace_ppc_excp_dsi(env
->spr
[SPR_DSISR
], env
->spr
[SPR_DAR
]);
1439 case POWERPC_EXCP_ISI
: /* Instruction storage exception */
1440 trace_ppc_excp_isi(msr
, env
->nip
);
1441 msr
|= env
->error_code
;
1443 case POWERPC_EXCP_EXTERNAL
: /* External input */
1448 * LPES0 is only taken into consideration if we support HV
1449 * mode for this CPU.
1451 if (!env
->has_hv_mode
) {
1455 lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1458 new_msr
|= (target_ulong
)MSR_HVB
;
1459 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1466 case POWERPC_EXCP_ALIGN
: /* Alignment exception */
1467 /* Optional DSISR update was removed from ISA v3.0 */
1468 if (!(env
->insns_flags2
& PPC2_ISA300
)) {
1469 /* Get rS/rD and rA from faulting opcode */
1471 * Note: the opcode fields will not be set properly for a
1472 * direct store load/store, but nobody cares as nobody
1473 * actually uses direct store segments.
1475 env
->spr
[SPR_DSISR
] |= (env
->error_code
& 0x03FF0000) >> 16;
1478 case POWERPC_EXCP_PROGRAM
: /* Program exception */
1479 switch (env
->error_code
& ~0xF) {
1480 case POWERPC_EXCP_FP
:
1481 if (!FIELD_EX64_FE(env
->msr
) || !FIELD_EX64(env
->msr
, MSR
, FP
)) {
1482 trace_ppc_excp_fp_ignore();
1483 powerpc_reset_excp_state(cpu
);
1488 * FP exceptions always have NIP pointing to the faulting
1489 * instruction, so always use store_next and claim we are
1490 * precise in the MSR.
1494 case POWERPC_EXCP_INVAL
:
1495 trace_ppc_excp_inval(env
->nip
);
1498 case POWERPC_EXCP_PRIV
:
1501 case POWERPC_EXCP_TRAP
:
1505 /* Should never occur */
1506 cpu_abort(cs
, "Invalid program exception %d. Aborting\n",
1511 case POWERPC_EXCP_SYSCALL
: /* System call exception */
1512 lev
= env
->error_code
;
1514 if (lev
== 1 && cpu
->vhyp
) {
1521 * We need to correct the NIP which in this case is supposed
1522 * to point to the next instruction
1526 /* "PAPR mode" built-in hypercall emulation */
1527 if (lev
== 1 && books_vhyp_handles_hcall(cpu
)) {
1528 PPCVirtualHypervisorClass
*vhc
=
1529 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
1530 vhc
->hypercall(cpu
->vhyp
, cpu
);
1531 powerpc_reset_excp_state(cpu
);
1534 if (env
->insns_flags2
& PPC2_ISA310
) {
1535 /* ISAv3.1 puts LEV into SRR1 */
1539 new_msr
|= (target_ulong
)MSR_HVB
;
1542 case POWERPC_EXCP_SYSCALL_VECTORED
: /* scv exception */
1543 lev
= env
->error_code
;
1546 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_EE
);
1547 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1549 vector
+= lev
* 0x20;
1554 case POWERPC_EXCP_FPU
: /* Floating-point unavailable exception */
1555 case POWERPC_EXCP_DECR
: /* Decrementer exception */
1557 case POWERPC_EXCP_RESET
: /* System reset exception */
1558 /* A power-saving exception sets ME, otherwise it is unchanged */
1559 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1560 /* indicate that we resumed from power save mode */
1562 new_msr
|= ((target_ulong
)1 << MSR_ME
);
1564 if (env
->msr_mask
& MSR_HVB
) {
1566 * ISA specifies HV, but can be delivered to guest with HV
1567 * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
1569 new_msr
|= (target_ulong
)MSR_HVB
;
1571 if (FIELD_EX64(env
->msr
, MSR
, POW
)) {
1572 cpu_abort(cs
, "Trying to deliver power-saving system reset "
1573 "exception %d with no HV support\n", excp
);
1577 case POWERPC_EXCP_TRACE
: /* Trace exception */
1578 msr
|= env
->error_code
;
1580 case POWERPC_EXCP_DSEG
: /* Data segment exception */
1581 case POWERPC_EXCP_ISEG
: /* Instruction segment exception */
1582 case POWERPC_EXCP_SDOOR
: /* Doorbell interrupt */
1583 case POWERPC_EXCP_PERFM
: /* Performance monitor interrupt */
1585 case POWERPC_EXCP_HISI
: /* Hypervisor instruction storage exception */
1586 msr
|= env
->error_code
;
1588 case POWERPC_EXCP_HDECR
: /* Hypervisor decrementer exception */
1589 case POWERPC_EXCP_HDSI
: /* Hypervisor data storage exception */
1590 case POWERPC_EXCP_SDOOR_HV
: /* Hypervisor Doorbell interrupt */
1591 case POWERPC_EXCP_HVIRT
: /* Hypervisor virtualization */
1594 new_msr
|= (target_ulong
)MSR_HVB
;
1595 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1598 case POWERPC_EXCP_HV_EMU
: {
1599 uint32_t insn
= ppc_ldl_code(env
, env
->nip
);
1600 env
->spr
[SPR_HEIR
] = insn
;
1601 if (is_prefix_insn(env
, insn
)) {
1602 uint32_t insn2
= ppc_ldl_code(env
, env
->nip
+ 4);
1603 env
->spr
[SPR_HEIR
] <<= 32;
1604 env
->spr
[SPR_HEIR
] |= insn2
;
1608 new_msr
|= (target_ulong
)MSR_HVB
;
1609 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1613 case POWERPC_EXCP_VPU
: /* Vector unavailable exception */
1614 case POWERPC_EXCP_VSXU
: /* VSX unavailable exception */
1615 case POWERPC_EXCP_FU
: /* Facility unavailable exception */
1616 env
->spr
[SPR_FSCR
] |= ((target_ulong
)env
->error_code
<< 56);
1618 case POWERPC_EXCP_HV_FU
: /* Hypervisor Facility Unavailable Exception */
1619 env
->spr
[SPR_HFSCR
] |= ((target_ulong
)env
->error_code
<< FSCR_IC_POS
);
1622 new_msr
|= (target_ulong
)MSR_HVB
;
1623 new_msr
|= env
->msr
& ((target_ulong
)1 << MSR_RI
);
1625 case POWERPC_EXCP_PERFM_EBB
: /* Performance Monitor EBB Exception */
1626 case POWERPC_EXCP_EXTERNAL_EBB
: /* External EBB Exception */
1627 env
->spr
[SPR_BESCR
] &= ~BESCR_GE
;
1630 * Save NIP for rfebb insn in SPR_EBBRR. Next nip is
1631 * stored in the EBB Handler SPR_EBBHR.
1633 env
->spr
[SPR_EBBRR
] = env
->nip
;
1634 powerpc_set_excp_state(cpu
, env
->spr
[SPR_EBBHR
], env
->msr
);
1637 * This exception is handled in userspace. No need to proceed.
1640 case POWERPC_EXCP_THERM
: /* Thermal interrupt */
1641 case POWERPC_EXCP_VPUA
: /* Vector assist exception */
1642 case POWERPC_EXCP_MAINT
: /* Maintenance exception */
1643 case POWERPC_EXCP_HV_MAINT
: /* Hypervisor Maintenance exception */
1644 cpu_abort(cs
, "%s exception not implemented\n",
1645 powerpc_excp_name(excp
));
1648 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
1653 * Sort out endianness of interrupt, this differs depending on the
1654 * CPU, the HV mode, etc...
1656 if (ppc_interrupts_little_endian(cpu
, !!(new_msr
& MSR_HVB
))) {
1657 new_msr
|= (target_ulong
)1 << MSR_LE
;
1660 new_msr
|= (target_ulong
)1 << MSR_SF
;
1662 if (excp
!= POWERPC_EXCP_SYSCALL_VECTORED
) {
1664 env
->spr
[srr0
] = env
->nip
;
1667 env
->spr
[srr1
] = msr
;
1670 if ((new_msr
& MSR_HVB
) && books_vhyp_handles_hv_excp(cpu
)) {
1671 PPCVirtualHypervisorClass
*vhc
=
1672 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu
->vhyp
);
1673 /* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
1674 vhc
->deliver_hv_excp(cpu
, excp
);
1676 powerpc_reset_excp_state(cpu
);
1680 if (!(env
->msr_mask
& MSR_HVB
) && srr0
== SPR_HSRR0
) {
1681 cpu_abort(cs
, "Trying to deliver HV exception (HSRR) %d with "
1682 "no HV support\n", excp
);
1685 /* This can update new_msr and vector if AIL applies */
1686 ppc_excp_apply_ail(cpu
, excp
, msr
, &new_msr
, &vector
);
1688 powerpc_set_excp_state(cpu
, vector
, new_msr
);
1692 static inline void powerpc_excp_books(PowerPCCPU
*cpu
, int excp
)
1694 g_assert_not_reached();
1698 static void powerpc_excp(PowerPCCPU
*cpu
, int excp
)
1700 CPUState
*cs
= CPU(cpu
);
1701 CPUPPCState
*env
= &cpu
->env
;
1703 if (excp
<= POWERPC_EXCP_NONE
|| excp
>= POWERPC_EXCP_NB
) {
1704 cpu_abort(cs
, "Invalid PowerPC exception %d. Aborting\n", excp
);
1707 qemu_log_mask(CPU_LOG_INT
, "Raise exception at " TARGET_FMT_lx
1708 " => %s (%d) error=%02x\n", env
->nip
, powerpc_excp_name(excp
),
1709 excp
, env
->error_code
);
1710 env
->excp_stats
[excp
]++;
1712 switch (env
->excp_model
) {
1713 case POWERPC_EXCP_40x
:
1714 powerpc_excp_40x(cpu
, excp
);
1716 case POWERPC_EXCP_6xx
:
1717 powerpc_excp_6xx(cpu
, excp
);
1719 case POWERPC_EXCP_7xx
:
1720 powerpc_excp_7xx(cpu
, excp
);
1722 case POWERPC_EXCP_74xx
:
1723 powerpc_excp_74xx(cpu
, excp
);
1725 case POWERPC_EXCP_BOOKE
:
1726 powerpc_excp_booke(cpu
, excp
);
1728 case POWERPC_EXCP_970
:
1729 case POWERPC_EXCP_POWER7
:
1730 case POWERPC_EXCP_POWER8
:
1731 case POWERPC_EXCP_POWER9
:
1732 case POWERPC_EXCP_POWER10
:
1733 powerpc_excp_books(cpu
, excp
);
1736 g_assert_not_reached();
1740 void ppc_cpu_do_interrupt(CPUState
*cs
)
1742 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1744 powerpc_excp(cpu
, cs
->exception_index
);
1747 #if defined(TARGET_PPC64)
1748 #define P7_UNUSED_INTERRUPTS \
1749 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_HVIRT | PPC_INTERRUPT_CEXT | \
1750 PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
1751 PPC_INTERRUPT_PIT | PPC_INTERRUPT_DOORBELL | PPC_INTERRUPT_HDOORBELL | \
1752 PPC_INTERRUPT_THERM | PPC_INTERRUPT_EBB)
1754 static int p7_interrupt_powersave(CPUPPCState
*env
)
1756 if ((env
->pending_interrupts
& PPC_INTERRUPT_EXT
) &&
1757 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE0
)) {
1758 return PPC_INTERRUPT_EXT
;
1760 if ((env
->pending_interrupts
& PPC_INTERRUPT_DECR
) &&
1761 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE1
)) {
1762 return PPC_INTERRUPT_DECR
;
1764 if ((env
->pending_interrupts
& PPC_INTERRUPT_MCK
) &&
1765 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE2
)) {
1766 return PPC_INTERRUPT_MCK
;
1768 if ((env
->pending_interrupts
& PPC_INTERRUPT_HMI
) &&
1769 (env
->spr
[SPR_LPCR
] & LPCR_P7_PECE2
)) {
1770 return PPC_INTERRUPT_HMI
;
1772 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
1773 return PPC_INTERRUPT_RESET
;
1778 static int p7_next_unmasked_interrupt(CPUPPCState
*env
)
1780 CPUState
*cs
= env_cpu(env
);
1782 /* Ignore MSR[EE] when coming out of some power management states */
1783 bool msr_ee
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
1785 assert((env
->pending_interrupts
& P7_UNUSED_INTERRUPTS
) == 0);
1788 /* LPCR[PECE] controls which interrupts can exit power-saving mode */
1789 return p7_interrupt_powersave(env
);
1792 /* Machine check exception */
1793 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1794 return PPC_INTERRUPT_MCK
;
1797 /* Hypervisor decrementer exception */
1798 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
1799 /* LPCR will be clear when not supported so this will work */
1800 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
1801 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
1802 /* HDEC clears on delivery */
1803 return PPC_INTERRUPT_HDECR
;
1807 /* External interrupt can ignore MSR:EE under some circumstances */
1808 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
1809 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1810 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1811 /* HEIC blocks delivery to the hypervisor */
1812 if ((msr_ee
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
1813 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
1814 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
1815 return PPC_INTERRUPT_EXT
;
1819 /* Decrementer exception */
1820 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
1821 return PPC_INTERRUPT_DECR
;
1823 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
1824 return PPC_INTERRUPT_PERFM
;
1831 #define P8_UNUSED_INTERRUPTS \
1832 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_HVIRT | \
1833 PPC_INTERRUPT_CEXT | PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | \
1834 PPC_INTERRUPT_FIT | PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM)
1836 static int p8_interrupt_powersave(CPUPPCState
*env
)
1838 if ((env
->pending_interrupts
& PPC_INTERRUPT_EXT
) &&
1839 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE2
)) {
1840 return PPC_INTERRUPT_EXT
;
1842 if ((env
->pending_interrupts
& PPC_INTERRUPT_DECR
) &&
1843 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE3
)) {
1844 return PPC_INTERRUPT_DECR
;
1846 if ((env
->pending_interrupts
& PPC_INTERRUPT_MCK
) &&
1847 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE4
)) {
1848 return PPC_INTERRUPT_MCK
;
1850 if ((env
->pending_interrupts
& PPC_INTERRUPT_HMI
) &&
1851 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE4
)) {
1852 return PPC_INTERRUPT_HMI
;
1854 if ((env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) &&
1855 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE0
)) {
1856 return PPC_INTERRUPT_DOORBELL
;
1858 if ((env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) &&
1859 (env
->spr
[SPR_LPCR
] & LPCR_P8_PECE1
)) {
1860 return PPC_INTERRUPT_HDOORBELL
;
1862 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
1863 return PPC_INTERRUPT_RESET
;
1868 static int p8_next_unmasked_interrupt(CPUPPCState
*env
)
1870 CPUState
*cs
= env_cpu(env
);
1872 /* Ignore MSR[EE] when coming out of some power management states */
1873 bool msr_ee
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
1875 assert((env
->pending_interrupts
& P8_UNUSED_INTERRUPTS
) == 0);
1878 /* LPCR[PECE] controls which interrupts can exit power-saving mode */
1879 return p8_interrupt_powersave(env
);
1882 /* Machine check exception */
1883 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1884 return PPC_INTERRUPT_MCK
;
1887 /* Hypervisor decrementer exception */
1888 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
1889 /* LPCR will be clear when not supported so this will work */
1890 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
1891 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
1892 /* HDEC clears on delivery */
1893 return PPC_INTERRUPT_HDECR
;
1897 /* External interrupt can ignore MSR:EE under some circumstances */
1898 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
1899 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
1900 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1901 /* HEIC blocks delivery to the hypervisor */
1902 if ((msr_ee
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
1903 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
1904 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
1905 return PPC_INTERRUPT_EXT
;
1909 /* Decrementer exception */
1910 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
1911 return PPC_INTERRUPT_DECR
;
1913 if (env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) {
1914 return PPC_INTERRUPT_DOORBELL
;
1916 if (env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) {
1917 return PPC_INTERRUPT_HDOORBELL
;
1919 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
1920 return PPC_INTERRUPT_PERFM
;
1923 if (env
->pending_interrupts
& PPC_INTERRUPT_EBB
) {
1925 * EBB exception must be taken in problem state and
1926 * with BESCR_GE set.
1928 if (FIELD_EX64(env
->msr
, MSR
, PR
) &&
1929 (env
->spr
[SPR_BESCR
] & BESCR_GE
)) {
1930 return PPC_INTERRUPT_EBB
;
1938 #define P9_UNUSED_INTERRUPTS \
1939 (PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_CEXT | \
1940 PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | PPC_INTERRUPT_FIT | \
1941 PPC_INTERRUPT_PIT | PPC_INTERRUPT_THERM)
1943 static int p9_interrupt_powersave(CPUPPCState
*env
)
1945 /* External Exception */
1946 if ((env
->pending_interrupts
& PPC_INTERRUPT_EXT
) &&
1947 (env
->spr
[SPR_LPCR
] & LPCR_EEE
)) {
1948 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
1949 if (!heic
|| !FIELD_EX64_HV(env
->msr
) ||
1950 FIELD_EX64(env
->msr
, MSR
, PR
)) {
1951 return PPC_INTERRUPT_EXT
;
1954 /* Decrementer Exception */
1955 if ((env
->pending_interrupts
& PPC_INTERRUPT_DECR
) &&
1956 (env
->spr
[SPR_LPCR
] & LPCR_DEE
)) {
1957 return PPC_INTERRUPT_DECR
;
1959 /* Machine Check or Hypervisor Maintenance Exception */
1960 if (env
->spr
[SPR_LPCR
] & LPCR_OEE
) {
1961 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
1962 return PPC_INTERRUPT_MCK
;
1964 if (env
->pending_interrupts
& PPC_INTERRUPT_HMI
) {
1965 return PPC_INTERRUPT_HMI
;
1968 /* Privileged Doorbell Exception */
1969 if ((env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) &&
1970 (env
->spr
[SPR_LPCR
] & LPCR_PDEE
)) {
1971 return PPC_INTERRUPT_DOORBELL
;
1973 /* Hypervisor Doorbell Exception */
1974 if ((env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) &&
1975 (env
->spr
[SPR_LPCR
] & LPCR_HDEE
)) {
1976 return PPC_INTERRUPT_HDOORBELL
;
1978 /* Hypervisor virtualization exception */
1979 if ((env
->pending_interrupts
& PPC_INTERRUPT_HVIRT
) &&
1980 (env
->spr
[SPR_LPCR
] & LPCR_HVEE
)) {
1981 return PPC_INTERRUPT_HVIRT
;
1983 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
1984 return PPC_INTERRUPT_RESET
;
1989 static int p9_next_unmasked_interrupt(CPUPPCState
*env
)
1991 CPUState
*cs
= env_cpu(env
);
1993 /* Ignore MSR[EE] when coming out of some power management states */
1994 bool msr_ee
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
1996 assert((env
->pending_interrupts
& P9_UNUSED_INTERRUPTS
) == 0);
1999 if (env
->spr
[SPR_PSSCR
] & PSSCR_EC
) {
2001 * When PSSCR[EC] is set, LPCR[PECE] controls which interrupts can
2002 * wakeup the processor
2004 return p9_interrupt_powersave(env
);
2007 * When it's clear, any system-caused exception exits power-saving
2008 * mode, even the ones that gate on MSR[EE].
2014 /* Machine check exception */
2015 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
2016 return PPC_INTERRUPT_MCK
;
2019 /* Hypervisor decrementer exception */
2020 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
2021 /* LPCR will be clear when not supported so this will work */
2022 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
2023 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
2024 /* HDEC clears on delivery */
2025 return PPC_INTERRUPT_HDECR
;
2029 /* Hypervisor virtualization interrupt */
2030 if (env
->pending_interrupts
& PPC_INTERRUPT_HVIRT
) {
2031 /* LPCR will be clear when not supported so this will work */
2032 bool hvice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HVICE
);
2033 if ((msr_ee
|| !FIELD_EX64_HV(env
->msr
)) && hvice
) {
2034 return PPC_INTERRUPT_HVIRT
;
2038 /* External interrupt can ignore MSR:EE under some circumstances */
2039 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
2040 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
2041 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
2042 /* HEIC blocks delivery to the hypervisor */
2043 if ((msr_ee
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
2044 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
2045 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
2046 return PPC_INTERRUPT_EXT
;
2050 /* Decrementer exception */
2051 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
2052 return PPC_INTERRUPT_DECR
;
2054 if (env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) {
2055 return PPC_INTERRUPT_DOORBELL
;
2057 if (env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) {
2058 return PPC_INTERRUPT_HDOORBELL
;
2060 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
2061 return PPC_INTERRUPT_PERFM
;
2064 if (env
->pending_interrupts
& PPC_INTERRUPT_EBB
) {
2066 * EBB exception must be taken in problem state and
2067 * with BESCR_GE set.
2069 if (FIELD_EX64(env
->msr
, MSR
, PR
) &&
2070 (env
->spr
[SPR_BESCR
] & BESCR_GE
)) {
2071 return PPC_INTERRUPT_EBB
;
2080 static int ppc_next_unmasked_interrupt_generic(CPUPPCState
*env
)
2084 /* External reset */
2085 if (env
->pending_interrupts
& PPC_INTERRUPT_RESET
) {
2086 return PPC_INTERRUPT_RESET
;
2088 /* Machine check exception */
2089 if (env
->pending_interrupts
& PPC_INTERRUPT_MCK
) {
2090 return PPC_INTERRUPT_MCK
;
2093 /* External debug exception */
2094 if (env
->pending_interrupts
& PPC_INTERRUPT_DEBUG
) {
2095 return PPC_INTERRUPT_DEBUG
;
2100 * For interrupts that gate on MSR:EE, we need to do something a
2101 * bit more subtle, as we need to let them through even when EE is
2102 * clear when coming out of some power management states (in order
2103 * for them to become a 0x100).
2105 async_deliver
= FIELD_EX64(env
->msr
, MSR
, EE
) || env
->resume_as_sreset
;
2107 /* Hypervisor decrementer exception */
2108 if (env
->pending_interrupts
& PPC_INTERRUPT_HDECR
) {
2109 /* LPCR will be clear when not supported so this will work */
2110 bool hdice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HDICE
);
2111 if ((async_deliver
|| !FIELD_EX64_HV(env
->msr
)) && hdice
) {
2112 /* HDEC clears on delivery */
2113 return PPC_INTERRUPT_HDECR
;
2117 /* Hypervisor virtualization interrupt */
2118 if (env
->pending_interrupts
& PPC_INTERRUPT_HVIRT
) {
2119 /* LPCR will be clear when not supported so this will work */
2120 bool hvice
= !!(env
->spr
[SPR_LPCR
] & LPCR_HVICE
);
2121 if ((async_deliver
|| !FIELD_EX64_HV(env
->msr
)) && hvice
) {
2122 return PPC_INTERRUPT_HVIRT
;
2126 /* External interrupt can ignore MSR:EE under some circumstances */
2127 if (env
->pending_interrupts
& PPC_INTERRUPT_EXT
) {
2128 bool lpes0
= !!(env
->spr
[SPR_LPCR
] & LPCR_LPES0
);
2129 bool heic
= !!(env
->spr
[SPR_LPCR
] & LPCR_HEIC
);
2130 /* HEIC blocks delivery to the hypervisor */
2131 if ((async_deliver
&& !(heic
&& FIELD_EX64_HV(env
->msr
) &&
2132 !FIELD_EX64(env
->msr
, MSR
, PR
))) ||
2133 (env
->has_hv_mode
&& !FIELD_EX64_HV(env
->msr
) && !lpes0
)) {
2134 return PPC_INTERRUPT_EXT
;
2137 if (FIELD_EX64(env
->msr
, MSR
, CE
)) {
2138 /* External critical interrupt */
2139 if (env
->pending_interrupts
& PPC_INTERRUPT_CEXT
) {
2140 return PPC_INTERRUPT_CEXT
;
2143 if (async_deliver
!= 0) {
2144 /* Watchdog timer on embedded PowerPC */
2145 if (env
->pending_interrupts
& PPC_INTERRUPT_WDT
) {
2146 return PPC_INTERRUPT_WDT
;
2148 if (env
->pending_interrupts
& PPC_INTERRUPT_CDOORBELL
) {
2149 return PPC_INTERRUPT_CDOORBELL
;
2151 /* Fixed interval timer on embedded PowerPC */
2152 if (env
->pending_interrupts
& PPC_INTERRUPT_FIT
) {
2153 return PPC_INTERRUPT_FIT
;
2155 /* Programmable interval timer on embedded PowerPC */
2156 if (env
->pending_interrupts
& PPC_INTERRUPT_PIT
) {
2157 return PPC_INTERRUPT_PIT
;
2159 /* Decrementer exception */
2160 if (env
->pending_interrupts
& PPC_INTERRUPT_DECR
) {
2161 return PPC_INTERRUPT_DECR
;
2163 if (env
->pending_interrupts
& PPC_INTERRUPT_DOORBELL
) {
2164 return PPC_INTERRUPT_DOORBELL
;
2166 if (env
->pending_interrupts
& PPC_INTERRUPT_HDOORBELL
) {
2167 return PPC_INTERRUPT_HDOORBELL
;
2169 if (env
->pending_interrupts
& PPC_INTERRUPT_PERFM
) {
2170 return PPC_INTERRUPT_PERFM
;
2172 /* Thermal interrupt */
2173 if (env
->pending_interrupts
& PPC_INTERRUPT_THERM
) {
2174 return PPC_INTERRUPT_THERM
;
2177 if (env
->pending_interrupts
& PPC_INTERRUPT_EBB
) {
2179 * EBB exception must be taken in problem state and
2180 * with BESCR_GE set.
2182 if (FIELD_EX64(env
->msr
, MSR
, PR
) &&
2183 (env
->spr
[SPR_BESCR
] & BESCR_GE
)) {
2184 return PPC_INTERRUPT_EBB
;
2192 static int ppc_next_unmasked_interrupt(CPUPPCState
*env
)
2194 switch (env
->excp_model
) {
2195 #if defined(TARGET_PPC64)
2196 case POWERPC_EXCP_POWER7
:
2197 return p7_next_unmasked_interrupt(env
);
2198 case POWERPC_EXCP_POWER8
:
2199 return p8_next_unmasked_interrupt(env
);
2200 case POWERPC_EXCP_POWER9
:
2201 case POWERPC_EXCP_POWER10
:
2202 return p9_next_unmasked_interrupt(env
);
2205 return ppc_next_unmasked_interrupt_generic(env
);
2210 * Sets CPU_INTERRUPT_HARD if there is at least one unmasked interrupt to be
2211 * delivered and clears CPU_INTERRUPT_HARD otherwise.
2213 * This method is called by ppc_set_interrupt when an interrupt is raised or
2214 * lowered, and should also be called whenever an interrupt masking condition
2216 * - When relevant bits of MSR are altered, like EE, HV, PR, etc.;
2217 * - When relevant bits of LPCR are altered, like PECE, HDICE, HVICE, etc.;
2218 * - When PSSCR[EC] or env->resume_as_sreset are changed;
2219 * - When cs->halted is changed and the CPU has a different interrupt masking
2220 * logic in power-saving mode (e.g., POWER7/8/9/10);
2222 void ppc_maybe_interrupt(CPUPPCState
*env
)
2224 CPUState
*cs
= env_cpu(env
);
2225 QEMU_IOTHREAD_LOCK_GUARD();
2227 if (ppc_next_unmasked_interrupt(env
)) {
2228 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
2230 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
2234 #if defined(TARGET_PPC64)
2235 static void p7_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2237 PowerPCCPU
*cpu
= env_archcpu(env
);
2238 CPUState
*cs
= env_cpu(env
);
2240 switch (interrupt
) {
2241 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2242 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2243 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2246 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2247 /* HDEC clears on delivery */
2248 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2249 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2252 case PPC_INTERRUPT_EXT
:
2253 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2254 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2256 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2260 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2261 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2263 case PPC_INTERRUPT_PERFM
:
2264 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2265 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2269 * This is a bug ! It means that has_work took us out of halt without
2270 * anything to deliver while in a PM state that requires getting
2273 * This means we will incorrectly execute past the power management
2274 * instruction instead of triggering a reset.
2276 * It generally means a discrepancy between the wakeup conditions in the
2277 * processor has_work implementation and the logic in this function.
2279 assert(!env
->resume_as_sreset
);
2282 cpu_abort(cs
, "Invalid PowerPC interrupt %d. Aborting\n", interrupt
);
2286 static void p8_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2288 PowerPCCPU
*cpu
= env_archcpu(env
);
2289 CPUState
*cs
= env_cpu(env
);
2291 switch (interrupt
) {
2292 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2293 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2294 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2297 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2298 /* HDEC clears on delivery */
2299 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2300 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2303 case PPC_INTERRUPT_EXT
:
2304 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2305 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2307 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2311 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2312 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2314 case PPC_INTERRUPT_DOORBELL
:
2315 env
->pending_interrupts
&= ~PPC_INTERRUPT_DOORBELL
;
2316 if (is_book3s_arch2x(env
)) {
2317 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR
);
2319 powerpc_excp(cpu
, POWERPC_EXCP_DOORI
);
2322 case PPC_INTERRUPT_HDOORBELL
:
2323 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDOORBELL
;
2324 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR_HV
);
2326 case PPC_INTERRUPT_PERFM
:
2327 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2328 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2330 case PPC_INTERRUPT_EBB
: /* EBB exception */
2331 env
->pending_interrupts
&= ~PPC_INTERRUPT_EBB
;
2332 if (env
->spr
[SPR_BESCR
] & BESCR_PMEO
) {
2333 powerpc_excp(cpu
, POWERPC_EXCP_PERFM_EBB
);
2334 } else if (env
->spr
[SPR_BESCR
] & BESCR_EEO
) {
2335 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL_EBB
);
2340 * This is a bug ! It means that has_work took us out of halt without
2341 * anything to deliver while in a PM state that requires getting
2344 * This means we will incorrectly execute past the power management
2345 * instruction instead of triggering a reset.
2347 * It generally means a discrepancy between the wakeup conditions in the
2348 * processor has_work implementation and the logic in this function.
2350 assert(!env
->resume_as_sreset
);
2353 cpu_abort(cs
, "Invalid PowerPC interrupt %d. Aborting\n", interrupt
);
2357 static void p9_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2359 PowerPCCPU
*cpu
= env_archcpu(env
);
2360 CPUState
*cs
= env_cpu(env
);
2362 if (cs
->halted
&& !(env
->spr
[SPR_PSSCR
] & PSSCR_EC
) &&
2363 !FIELD_EX64(env
->msr
, MSR
, EE
)) {
2365 * A pending interrupt took us out of power-saving, but MSR[EE] says
2366 * that we should return to NIP+4 instead of delivering it.
2371 switch (interrupt
) {
2372 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2373 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2374 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2377 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2378 /* HDEC clears on delivery */
2379 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2380 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2382 case PPC_INTERRUPT_HVIRT
: /* Hypervisor virtualization interrupt */
2383 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2386 case PPC_INTERRUPT_EXT
:
2387 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2388 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2390 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2394 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2395 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2397 case PPC_INTERRUPT_DOORBELL
:
2398 env
->pending_interrupts
&= ~PPC_INTERRUPT_DOORBELL
;
2399 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR
);
2401 case PPC_INTERRUPT_HDOORBELL
:
2402 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDOORBELL
;
2403 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR_HV
);
2405 case PPC_INTERRUPT_PERFM
:
2406 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2407 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2409 case PPC_INTERRUPT_EBB
: /* EBB exception */
2410 env
->pending_interrupts
&= ~PPC_INTERRUPT_EBB
;
2411 if (env
->spr
[SPR_BESCR
] & BESCR_PMEO
) {
2412 powerpc_excp(cpu
, POWERPC_EXCP_PERFM_EBB
);
2413 } else if (env
->spr
[SPR_BESCR
] & BESCR_EEO
) {
2414 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL_EBB
);
2419 * This is a bug ! It means that has_work took us out of halt without
2420 * anything to deliver while in a PM state that requires getting
2423 * This means we will incorrectly execute past the power management
2424 * instruction instead of triggering a reset.
2426 * It generally means a discrepancy between the wakeup conditions in the
2427 * processor has_work implementation and the logic in this function.
2429 assert(!env
->resume_as_sreset
);
2432 cpu_abort(cs
, "Invalid PowerPC interrupt %d. Aborting\n", interrupt
);
2437 static void ppc_deliver_interrupt_generic(CPUPPCState
*env
, int interrupt
)
2439 PowerPCCPU
*cpu
= env_archcpu(env
);
2440 CPUState
*cs
= env_cpu(env
);
2442 switch (interrupt
) {
2443 case PPC_INTERRUPT_RESET
: /* External reset */
2444 env
->pending_interrupts
&= ~PPC_INTERRUPT_RESET
;
2445 powerpc_excp(cpu
, POWERPC_EXCP_RESET
);
2447 case PPC_INTERRUPT_MCK
: /* Machine check exception */
2448 env
->pending_interrupts
&= ~PPC_INTERRUPT_MCK
;
2449 powerpc_excp(cpu
, POWERPC_EXCP_MCHECK
);
2452 case PPC_INTERRUPT_HDECR
: /* Hypervisor decrementer exception */
2453 /* HDEC clears on delivery */
2454 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDECR
;
2455 powerpc_excp(cpu
, POWERPC_EXCP_HDECR
);
2457 case PPC_INTERRUPT_HVIRT
: /* Hypervisor virtualization interrupt */
2458 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2461 case PPC_INTERRUPT_EXT
:
2462 if (books_vhyp_promotes_external_to_hvirt(cpu
)) {
2463 powerpc_excp(cpu
, POWERPC_EXCP_HVIRT
);
2465 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL
);
2468 case PPC_INTERRUPT_CEXT
: /* External critical interrupt */
2469 powerpc_excp(cpu
, POWERPC_EXCP_CRITICAL
);
2472 case PPC_INTERRUPT_WDT
: /* Watchdog timer on embedded PowerPC */
2473 env
->pending_interrupts
&= ~PPC_INTERRUPT_WDT
;
2474 powerpc_excp(cpu
, POWERPC_EXCP_WDT
);
2476 case PPC_INTERRUPT_CDOORBELL
:
2477 env
->pending_interrupts
&= ~PPC_INTERRUPT_CDOORBELL
;
2478 powerpc_excp(cpu
, POWERPC_EXCP_DOORCI
);
2480 case PPC_INTERRUPT_FIT
: /* Fixed interval timer on embedded PowerPC */
2481 env
->pending_interrupts
&= ~PPC_INTERRUPT_FIT
;
2482 powerpc_excp(cpu
, POWERPC_EXCP_FIT
);
2484 case PPC_INTERRUPT_PIT
: /* Programmable interval timer on embedded ppc */
2485 env
->pending_interrupts
&= ~PPC_INTERRUPT_PIT
;
2486 powerpc_excp(cpu
, POWERPC_EXCP_PIT
);
2488 case PPC_INTERRUPT_DECR
: /* Decrementer exception */
2489 if (ppc_decr_clear_on_delivery(env
)) {
2490 env
->pending_interrupts
&= ~PPC_INTERRUPT_DECR
;
2492 powerpc_excp(cpu
, POWERPC_EXCP_DECR
);
2494 case PPC_INTERRUPT_DOORBELL
:
2495 env
->pending_interrupts
&= ~PPC_INTERRUPT_DOORBELL
;
2496 if (is_book3s_arch2x(env
)) {
2497 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR
);
2499 powerpc_excp(cpu
, POWERPC_EXCP_DOORI
);
2502 case PPC_INTERRUPT_HDOORBELL
:
2503 env
->pending_interrupts
&= ~PPC_INTERRUPT_HDOORBELL
;
2504 powerpc_excp(cpu
, POWERPC_EXCP_SDOOR_HV
);
2506 case PPC_INTERRUPT_PERFM
:
2507 env
->pending_interrupts
&= ~PPC_INTERRUPT_PERFM
;
2508 powerpc_excp(cpu
, POWERPC_EXCP_PERFM
);
2510 case PPC_INTERRUPT_THERM
: /* Thermal interrupt */
2511 env
->pending_interrupts
&= ~PPC_INTERRUPT_THERM
;
2512 powerpc_excp(cpu
, POWERPC_EXCP_THERM
);
2514 case PPC_INTERRUPT_EBB
: /* EBB exception */
2515 env
->pending_interrupts
&= ~PPC_INTERRUPT_EBB
;
2516 if (env
->spr
[SPR_BESCR
] & BESCR_PMEO
) {
2517 powerpc_excp(cpu
, POWERPC_EXCP_PERFM_EBB
);
2518 } else if (env
->spr
[SPR_BESCR
] & BESCR_EEO
) {
2519 powerpc_excp(cpu
, POWERPC_EXCP_EXTERNAL_EBB
);
2524 * This is a bug ! It means that has_work took us out of halt without
2525 * anything to deliver while in a PM state that requires getting
2528 * This means we will incorrectly execute past the power management
2529 * instruction instead of triggering a reset.
2531 * It generally means a discrepancy between the wakeup conditions in the
2532 * processor has_work implementation and the logic in this function.
2534 assert(!env
->resume_as_sreset
);
2537 cpu_abort(cs
, "Invalid PowerPC interrupt %d. Aborting\n", interrupt
);
2541 static void ppc_deliver_interrupt(CPUPPCState
*env
, int interrupt
)
2543 switch (env
->excp_model
) {
2544 #if defined(TARGET_PPC64)
2545 case POWERPC_EXCP_POWER7
:
2546 p7_deliver_interrupt(env
, interrupt
);
2548 case POWERPC_EXCP_POWER8
:
2549 p8_deliver_interrupt(env
, interrupt
);
2551 case POWERPC_EXCP_POWER9
:
2552 case POWERPC_EXCP_POWER10
:
2553 p9_deliver_interrupt(env
, interrupt
);
2557 ppc_deliver_interrupt_generic(env
, interrupt
);
2561 void ppc_cpu_do_system_reset(CPUState
*cs
)
2563 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2565 powerpc_excp(cpu
, POWERPC_EXCP_RESET
);
2568 void ppc_cpu_do_fwnmi_machine_check(CPUState
*cs
, target_ulong vector
)
2570 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2571 CPUPPCState
*env
= &cpu
->env
;
2572 target_ulong msr
= 0;
2575 * Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already
2578 msr
= (1ULL << MSR_ME
);
2579 msr
|= env
->msr
& (1ULL << MSR_SF
);
2580 if (ppc_interrupts_little_endian(cpu
, false)) {
2581 msr
|= (1ULL << MSR_LE
);
2584 /* Anything for nested required here? MSR[HV] bit? */
2586 powerpc_set_excp_state(cpu
, vector
, msr
);
2589 bool ppc_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
2591 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2592 CPUPPCState
*env
= &cpu
->env
;
2595 if ((interrupt_request
& CPU_INTERRUPT_HARD
) == 0) {
2599 interrupt
= ppc_next_unmasked_interrupt(env
);
2600 if (interrupt
== 0) {
2604 ppc_deliver_interrupt(env
, interrupt
);
2605 if (env
->pending_interrupts
== 0) {
2606 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
2611 #endif /* !CONFIG_USER_ONLY */
2613 /*****************************************************************************/
2614 /* Exceptions processing helpers */
2616 void raise_exception_err_ra(CPUPPCState
*env
, uint32_t exception
,
2617 uint32_t error_code
, uintptr_t raddr
)
2619 CPUState
*cs
= env_cpu(env
);
2621 cs
->exception_index
= exception
;
2622 env
->error_code
= error_code
;
2623 cpu_loop_exit_restore(cs
, raddr
);
2626 void raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
2627 uint32_t error_code
)
2629 raise_exception_err_ra(env
, exception
, error_code
, 0);
2632 void raise_exception(CPUPPCState
*env
, uint32_t exception
)
2634 raise_exception_err_ra(env
, exception
, 0, 0);
2637 void raise_exception_ra(CPUPPCState
*env
, uint32_t exception
,
2640 raise_exception_err_ra(env
, exception
, 0, raddr
);
2644 void helper_raise_exception_err(CPUPPCState
*env
, uint32_t exception
,
2645 uint32_t error_code
)
2647 raise_exception_err_ra(env
, exception
, error_code
, 0);
2650 void helper_raise_exception(CPUPPCState
*env
, uint32_t exception
)
2652 raise_exception_err_ra(env
, exception
, 0, 0);
2656 #if !defined(CONFIG_USER_ONLY)
2658 void helper_store_msr(CPUPPCState
*env
, target_ulong val
)
2660 uint32_t excp
= hreg_store_msr(env
, val
, 0);
2663 cpu_interrupt_exittb(env_cpu(env
));
2664 raise_exception(env
, excp
);
2668 void helper_ppc_maybe_interrupt(CPUPPCState
*env
)
2670 ppc_maybe_interrupt(env
);
2673 #if defined(TARGET_PPC64)
2674 void helper_scv(CPUPPCState
*env
, uint32_t lev
)
2676 if (env
->spr
[SPR_FSCR
] & (1ull << FSCR_SCV
)) {
2677 raise_exception_err(env
, POWERPC_EXCP_SYSCALL_VECTORED
, lev
);
2679 raise_exception_err(env
, POWERPC_EXCP_FU
, FSCR_IC_SCV
);
2683 void helper_pminsn(CPUPPCState
*env
, uint32_t insn
)
2685 CPUState
*cs
= env_cpu(env
);
2689 /* Condition for waking up at 0x100 */
2690 env
->resume_as_sreset
= (insn
!= PPC_PM_STOP
) ||
2691 (env
->spr
[SPR_PSSCR
] & PSSCR_EC
);
2693 /* HDECR is not to wake from PM state, it may have already fired */
2694 if (env
->resume_as_sreset
) {
2695 PowerPCCPU
*cpu
= env_archcpu(env
);
2696 ppc_set_irq(cpu
, PPC_INTERRUPT_HDECR
, 0);
2699 ppc_maybe_interrupt(env
);
2701 #endif /* defined(TARGET_PPC64) */
2703 static void do_rfi(CPUPPCState
*env
, target_ulong nip
, target_ulong msr
)
2705 /* MSR:POW cannot be set by any form of rfi */
2706 msr
&= ~(1ULL << MSR_POW
);
2708 /* MSR:TGPR cannot be set by any form of rfi */
2709 if (env
->flags
& POWERPC_FLAG_TGPR
)
2710 msr
&= ~(1ULL << MSR_TGPR
);
2712 #if defined(TARGET_PPC64)
2713 /* Switching to 32-bit ? Crop the nip */
2714 if (!msr_is_64bit(env
, msr
)) {
2715 nip
= (uint32_t)nip
;
2718 nip
= (uint32_t)nip
;
2720 /* XXX: beware: this is false if VLE is supported */
2721 env
->nip
= nip
& ~((target_ulong
)0x00000003);
2722 hreg_store_msr(env
, msr
, 1);
2723 trace_ppc_excp_rfi(env
->nip
, env
->msr
);
2725 * No need to raise an exception here, as rfi is always the last
2728 cpu_interrupt_exittb(env_cpu(env
));
2729 /* Reset the reservation */
2730 env
->reserve_addr
= -1;
2732 /* Context synchronizing: check if TCG TLB needs flush */
2733 check_tlb_flush(env
, false);
2736 void helper_rfi(CPUPPCState
*env
)
2738 do_rfi(env
, env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
] & 0xfffffffful
);
2741 #if defined(TARGET_PPC64)
2742 void helper_rfid(CPUPPCState
*env
)
2745 * The architecture defines a number of rules for which bits can
2746 * change but in practice, we handle this in hreg_store_msr()
2747 * which will be called by do_rfi(), so there is no need to filter
2750 do_rfi(env
, env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
]);
2753 void helper_rfscv(CPUPPCState
*env
)
2755 do_rfi(env
, env
->lr
, env
->ctr
);
2758 void helper_hrfid(CPUPPCState
*env
)
2760 do_rfi(env
, env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
2764 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
2765 void helper_rfebb(CPUPPCState
*env
, target_ulong s
)
2767 target_ulong msr
= env
->msr
;
2770 * Handling of BESCR bits 32:33 according to PowerISA v3.1:
2772 * "If BESCR 32:33 != 0b00 the instruction is treated as if
2773 * the instruction form were invalid."
2775 if (env
->spr
[SPR_BESCR
] & BESCR_INVALID
) {
2776 raise_exception_err(env
, POWERPC_EXCP_PROGRAM
,
2777 POWERPC_EXCP_INVAL
| POWERPC_EXCP_INVAL_INVAL
);
2780 env
->nip
= env
->spr
[SPR_EBBRR
];
2782 /* Switching to 32-bit ? Crop the nip */
2783 if (!msr_is_64bit(env
, msr
)) {
2784 env
->nip
= (uint32_t)env
->spr
[SPR_EBBRR
];
2788 env
->spr
[SPR_BESCR
] |= BESCR_GE
;
2790 env
->spr
[SPR_BESCR
] &= ~BESCR_GE
;
2795 * Triggers or queues an 'ebb_excp' EBB exception. All checks
2796 * but FSCR, HFSCR and msr_pr must be done beforehand.
2798 * PowerISA v3.1 isn't clear about whether an EBB should be
2799 * postponed or cancelled if the EBB facility is unavailable.
2800 * Our assumption here is that the EBB is cancelled if both
2801 * FSCR and HFSCR EBB facilities aren't available.
2803 static void do_ebb(CPUPPCState
*env
, int ebb_excp
)
2805 PowerPCCPU
*cpu
= env_archcpu(env
);
2808 * FSCR_EBB and FSCR_IC_EBB are the same bits used with
2811 helper_fscr_facility_check(env
, FSCR_EBB
, 0, FSCR_IC_EBB
);
2812 helper_hfscr_facility_check(env
, FSCR_EBB
, "EBB", FSCR_IC_EBB
);
2814 if (ebb_excp
== POWERPC_EXCP_PERFM_EBB
) {
2815 env
->spr
[SPR_BESCR
] |= BESCR_PMEO
;
2816 } else if (ebb_excp
== POWERPC_EXCP_EXTERNAL_EBB
) {
2817 env
->spr
[SPR_BESCR
] |= BESCR_EEO
;
2820 if (FIELD_EX64(env
->msr
, MSR
, PR
)) {
2821 powerpc_excp(cpu
, ebb_excp
);
2823 ppc_set_irq(cpu
, PPC_INTERRUPT_EBB
, 1);
2827 void raise_ebb_perfm_exception(CPUPPCState
*env
)
2829 bool perfm_ebb_enabled
= env
->spr
[SPR_POWER_MMCR0
] & MMCR0_EBE
&&
2830 env
->spr
[SPR_BESCR
] & BESCR_PME
&&
2831 env
->spr
[SPR_BESCR
] & BESCR_GE
;
2833 if (!perfm_ebb_enabled
) {
2837 do_ebb(env
, POWERPC_EXCP_PERFM_EBB
);
2841 /*****************************************************************************/
2842 /* Embedded PowerPC specific helpers */
2843 void helper_40x_rfci(CPUPPCState
*env
)
2845 do_rfi(env
, env
->spr
[SPR_40x_SRR2
], env
->spr
[SPR_40x_SRR3
]);
2848 void helper_rfci(CPUPPCState
*env
)
2850 do_rfi(env
, env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
]);
2853 void helper_rfdi(CPUPPCState
*env
)
2855 /* FIXME: choose CSRR1 or DSRR1 based on cpu type */
2856 do_rfi(env
, env
->spr
[SPR_BOOKE_DSRR0
], env
->spr
[SPR_BOOKE_DSRR1
]);
2859 void helper_rfmci(CPUPPCState
*env
)
2861 /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
2862 do_rfi(env
, env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
2864 #endif /* CONFIG_TCG */
2865 #endif /* !defined(CONFIG_USER_ONLY) */
2868 void helper_tw(CPUPPCState
*env
, target_ulong arg1
, target_ulong arg2
,
2871 if (!likely(!(((int32_t)arg1
< (int32_t)arg2
&& (flags
& 0x10)) ||
2872 ((int32_t)arg1
> (int32_t)arg2
&& (flags
& 0x08)) ||
2873 ((int32_t)arg1
== (int32_t)arg2
&& (flags
& 0x04)) ||
2874 ((uint32_t)arg1
< (uint32_t)arg2
&& (flags
& 0x02)) ||
2875 ((uint32_t)arg1
> (uint32_t)arg2
&& (flags
& 0x01))))) {
2876 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
2877 POWERPC_EXCP_TRAP
, GETPC());
2881 #if defined(TARGET_PPC64)
2882 void helper_td(CPUPPCState
*env
, target_ulong arg1
, target_ulong arg2
,
2885 if (!likely(!(((int64_t)arg1
< (int64_t)arg2
&& (flags
& 0x10)) ||
2886 ((int64_t)arg1
> (int64_t)arg2
&& (flags
& 0x08)) ||
2887 ((int64_t)arg1
== (int64_t)arg2
&& (flags
& 0x04)) ||
2888 ((uint64_t)arg1
< (uint64_t)arg2
&& (flags
& 0x02)) ||
2889 ((uint64_t)arg1
> (uint64_t)arg2
&& (flags
& 0x01))))) {
2890 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
2891 POWERPC_EXCP_TRAP
, GETPC());
2898 static uint32_t helper_SIMON_LIKE_32_64(uint32_t x
, uint64_t key
, uint32_t lane
)
2900 const uint16_t c
= 0xfffc;
2901 const uint64_t z0
= 0xfa2561cdf44ac398ULL
;
2902 uint16_t z
= 0, temp
;
2903 uint16_t k
[32], eff_k
[32], xleft
[33], xright
[33], fxleft
[32];
2905 for (int i
= 3; i
>= 0; i
--) {
2906 k
[i
] = key
& 0xffff;
2909 xleft
[0] = x
& 0xffff;
2910 xright
[0] = (x
>> 16) & 0xffff;
2912 for (int i
= 0; i
< 28; i
++) {
2913 z
= (z0
>> (63 - i
)) & 1;
2914 temp
= ror16(k
[i
+ 3], 3) ^ k
[i
+ 1];
2915 k
[i
+ 4] = c
^ z
^ k
[i
] ^ temp
^ ror16(temp
, 1);
2918 for (int i
= 0; i
< 8; i
++) {
2919 eff_k
[4 * i
+ 0] = k
[4 * i
+ ((0 + lane
) % 4)];
2920 eff_k
[4 * i
+ 1] = k
[4 * i
+ ((1 + lane
) % 4)];
2921 eff_k
[4 * i
+ 2] = k
[4 * i
+ ((2 + lane
) % 4)];
2922 eff_k
[4 * i
+ 3] = k
[4 * i
+ ((3 + lane
) % 4)];
2925 for (int i
= 0; i
< 32; i
++) {
2926 fxleft
[i
] = (rol16(xleft
[i
], 1) &
2927 rol16(xleft
[i
], 8)) ^ rol16(xleft
[i
], 2);
2928 xleft
[i
+ 1] = xright
[i
] ^ fxleft
[i
] ^ eff_k
[i
];
2929 xright
[i
+ 1] = xleft
[i
];
2932 return (((uint32_t)xright
[32]) << 16) | xleft
[32];
2935 static uint64_t hash_digest(uint64_t ra
, uint64_t rb
, uint64_t key
)
2937 uint64_t stage0_h
= 0ULL, stage0_l
= 0ULL;
2938 uint64_t stage1_h
, stage1_l
;
2940 for (int i
= 0; i
< 4; i
++) {
2941 stage0_h
|= ror64(rb
& 0xff, 8 * (2 * i
+ 1));
2942 stage0_h
|= ((ra
>> 32) & 0xff) << (8 * 2 * i
);
2943 stage0_l
|= ror64((rb
>> 32) & 0xff, 8 * (2 * i
+ 1));
2944 stage0_l
|= (ra
& 0xff) << (8 * 2 * i
);
2949 stage1_h
= (uint64_t)helper_SIMON_LIKE_32_64(stage0_h
>> 32, key
, 0) << 32;
2950 stage1_h
|= helper_SIMON_LIKE_32_64(stage0_h
, key
, 1);
2951 stage1_l
= (uint64_t)helper_SIMON_LIKE_32_64(stage0_l
>> 32, key
, 2) << 32;
2952 stage1_l
|= helper_SIMON_LIKE_32_64(stage0_l
, key
, 3);
2954 return stage1_h
^ stage1_l
;
2957 static void do_hash(CPUPPCState
*env
, target_ulong ea
, target_ulong ra
,
2958 target_ulong rb
, uint64_t key
, bool store
)
2960 uint64_t calculated_hash
= hash_digest(ra
, rb
, key
), loaded_hash
;
2963 cpu_stq_data_ra(env
, ea
, calculated_hash
, GETPC());
2965 loaded_hash
= cpu_ldq_data_ra(env
, ea
, GETPC());
2966 if (loaded_hash
!= calculated_hash
) {
2967 raise_exception_err_ra(env
, POWERPC_EXCP_PROGRAM
,
2968 POWERPC_EXCP_TRAP
, GETPC());
2973 #include "qemu/guest-random.h"
2976 #define HELPER_HASH(op, key, store, dexcr_aspect) \
2977 void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
2980 if (env->msr & R_MSR_PR_MASK) { \
2981 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PRO_##dexcr_aspect##_MASK || \
2982 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
2984 } else if (!(env->msr & R_MSR_HV_MASK)) { \
2985 if (!(env->spr[SPR_DEXCR] & R_DEXCR_PNH_##dexcr_aspect##_MASK || \
2986 env->spr[SPR_HDEXCR] & R_HDEXCR_ENF_##dexcr_aspect##_MASK)) \
2988 } else if (!(env->msr & R_MSR_S_MASK)) { \
2989 if (!(env->spr[SPR_HDEXCR] & R_HDEXCR_HNU_##dexcr_aspect##_MASK)) \
2993 do_hash(env, ea, ra, rb, key, store); \
2996 #define HELPER_HASH(op, key, store, dexcr_aspect) \
2997 void helper_##op(CPUPPCState *env, target_ulong ea, target_ulong ra, \
3000 do_hash(env, ea, ra, rb, key, store); \
3002 #endif /* TARGET_PPC64 */
3004 HELPER_HASH(HASHST
, env
->spr
[SPR_HASHKEYR
], true, NPHIE
)
3005 HELPER_HASH(HASHCHK
, env
->spr
[SPR_HASHKEYR
], false, NPHIE
)
3006 HELPER_HASH(HASHSTP
, env
->spr
[SPR_HASHPKEYR
], true, PHIE
)
3007 HELPER_HASH(HASHCHKP
, env
->spr
[SPR_HASHPKEYR
], false, PHIE
)
3008 #endif /* CONFIG_TCG */
3010 #if !defined(CONFIG_USER_ONLY)
3014 /* Embedded.Processor Control */
3015 static int dbell2irq(target_ulong rb
)
3017 int msg
= rb
& DBELL_TYPE_MASK
;
3021 case DBELL_TYPE_DBELL
:
3022 irq
= PPC_INTERRUPT_DOORBELL
;
3024 case DBELL_TYPE_DBELL_CRIT
:
3025 irq
= PPC_INTERRUPT_CDOORBELL
;
3027 case DBELL_TYPE_G_DBELL
:
3028 case DBELL_TYPE_G_DBELL_CRIT
:
3029 case DBELL_TYPE_G_DBELL_MC
:
3038 void helper_msgclr(CPUPPCState
*env
, target_ulong rb
)
3040 int irq
= dbell2irq(rb
);
3046 ppc_set_irq(env_archcpu(env
), irq
, 0);
3049 void helper_msgsnd(target_ulong rb
)
3051 int irq
= dbell2irq(rb
);
3052 int pir
= rb
& DBELL_PIRTAG_MASK
;
3059 qemu_mutex_lock_iothread();
3061 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3062 CPUPPCState
*cenv
= &cpu
->env
;
3064 if ((rb
& DBELL_BRDCAST
) || (cenv
->spr
[SPR_BOOKE_PIR
] == pir
)) {
3065 ppc_set_irq(cpu
, irq
, 1);
3068 qemu_mutex_unlock_iothread();
3071 /* Server Processor Control */
3073 static bool dbell_type_server(target_ulong rb
)
3076 * A Directed Hypervisor Doorbell message is sent only if the
3077 * message type is 5. All other types are reserved and the
3078 * instruction is a no-op
3080 return (rb
& DBELL_TYPE_MASK
) == DBELL_TYPE_DBELL_SERVER
;
3083 void helper_book3s_msgclr(CPUPPCState
*env
, target_ulong rb
)
3085 if (!dbell_type_server(rb
)) {
3089 ppc_set_irq(env_archcpu(env
), PPC_INTERRUPT_HDOORBELL
, 0);
3092 static void book3s_msgsnd_common(int pir
, int irq
)
3096 qemu_mutex_lock_iothread();
3098 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3099 CPUPPCState
*cenv
= &cpu
->env
;
3101 /* TODO: broadcast message to all threads of the same processor */
3102 if (cenv
->spr_cb
[SPR_PIR
].default_value
== pir
) {
3103 ppc_set_irq(cpu
, irq
, 1);
3106 qemu_mutex_unlock_iothread();
3109 void helper_book3s_msgsnd(target_ulong rb
)
3111 int pir
= rb
& DBELL_PROCIDTAG_MASK
;
3113 if (!dbell_type_server(rb
)) {
3117 book3s_msgsnd_common(pir
, PPC_INTERRUPT_HDOORBELL
);
3120 #if defined(TARGET_PPC64)
3121 void helper_book3s_msgclrp(CPUPPCState
*env
, target_ulong rb
)
3123 helper_hfscr_facility_check(env
, HFSCR_MSGP
, "msgclrp", HFSCR_IC_MSGP
);
3125 if (!dbell_type_server(rb
)) {
3129 ppc_set_irq(env_archcpu(env
), PPC_INTERRUPT_DOORBELL
, 0);
3133 * sends a message to another thread on the same
3134 * multi-threaded processor
3136 void helper_book3s_msgsndp(CPUPPCState
*env
, target_ulong rb
)
3138 CPUState
*cs
= env_cpu(env
);
3139 PowerPCCPU
*cpu
= env_archcpu(env
);
3141 uint32_t nr_threads
= cs
->nr_threads
;
3142 int ttir
= rb
& PPC_BITMASK(57, 63);
3144 helper_hfscr_facility_check(env
, HFSCR_MSGP
, "msgsndp", HFSCR_IC_MSGP
);
3146 if (!(env
->flags
& POWERPC_FLAG_SMT_1LPAR
)) {
3147 nr_threads
= 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
3150 if (!dbell_type_server(rb
) || ttir
>= nr_threads
) {
3154 if (nr_threads
== 1) {
3155 ppc_set_irq(cpu
, PPC_INTERRUPT_DOORBELL
, 1);
3159 /* Does iothread need to be locked for walking CPU list? */
3160 qemu_mutex_lock_iothread();
3161 THREAD_SIBLING_FOREACH(cs
, ccs
) {
3162 PowerPCCPU
*ccpu
= POWERPC_CPU(ccs
);
3163 uint32_t thread_id
= ppc_cpu_tir(ccpu
);
3165 if (ttir
== thread_id
) {
3166 ppc_set_irq(ccpu
, PPC_INTERRUPT_DOORBELL
, 1);
3167 qemu_mutex_unlock_iothread();
3172 g_assert_not_reached();
3174 #endif /* TARGET_PPC64 */
3176 /* Single-step tracing */
3177 void helper_book3s_trace(CPUPPCState
*env
, target_ulong prev_ip
)
3179 uint32_t error_code
= 0;
3180 if (env
->insns_flags2
& PPC2_ISA207S
) {
3181 /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */
3182 env
->spr
[SPR_POWER_SIAR
] = prev_ip
;
3183 error_code
= PPC_BIT(33);
3185 raise_exception_err(env
, POWERPC_EXCP_TRACE
, error_code
);
3188 void ppc_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
3189 MMUAccessType access_type
,
3190 int mmu_idx
, uintptr_t retaddr
)
3192 CPUPPCState
*env
= cpu_env(cs
);
3195 /* Restore state and reload the insn we executed, for filling in DSISR. */
3196 cpu_restore_state(cs
, retaddr
);
3197 insn
= ppc_ldl_code(env
, env
->nip
);
3199 switch (env
->mmu_model
) {
3200 case POWERPC_MMU_SOFT_4xx
:
3201 env
->spr
[SPR_40x_DEAR
] = vaddr
;
3203 case POWERPC_MMU_BOOKE
:
3204 case POWERPC_MMU_BOOKE206
:
3205 env
->spr
[SPR_BOOKE_DEAR
] = vaddr
;
3208 env
->spr
[SPR_DAR
] = vaddr
;
3212 cs
->exception_index
= POWERPC_EXCP_ALIGN
;
3213 env
->error_code
= insn
& 0x03FF0000;
3217 void ppc_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
3218 vaddr vaddr
, unsigned size
,
3219 MMUAccessType access_type
,
3220 int mmu_idx
, MemTxAttrs attrs
,
3221 MemTxResult response
, uintptr_t retaddr
)
3223 CPUPPCState
*env
= cpu_env(cs
);
3225 switch (env
->excp_model
) {
3226 #if defined(TARGET_PPC64)
3227 case POWERPC_EXCP_POWER9
:
3228 case POWERPC_EXCP_POWER10
:
3230 * Machine check codes can be found in processor User Manual or
3231 * Linux or skiboot source.
3233 if (access_type
== MMU_DATA_LOAD
) {
3234 env
->spr
[SPR_DAR
] = vaddr
;
3235 env
->spr
[SPR_DSISR
] = PPC_BIT(57);
3236 env
->error_code
= PPC_BIT(42);
3238 } else if (access_type
== MMU_DATA_STORE
) {
3240 * MCE for stores in POWER is asynchronous so hardware does
3241 * not set DAR, but QEMU can do better.
3243 env
->spr
[SPR_DAR
] = vaddr
;
3244 env
->error_code
= PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45);
3245 env
->error_code
|= PPC_BIT(42);
3247 } else { /* Fetch */
3248 env
->error_code
= PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45);
3254 * TODO: Check behaviour for other CPUs, for now do nothing.
3255 * Could add a basic MCE even if real hardware ignores.
3260 cs
->exception_index
= POWERPC_EXCP_MCHECK
;
3261 cpu_loop_exit_restore(cs
, retaddr
);
3264 void ppc_cpu_debug_excp_handler(CPUState
*cs
)
3266 #if defined(TARGET_PPC64)
3267 CPUPPCState
*env
= cpu_env(cs
);
3269 if (env
->insns_flags2
& PPC2_ISA207S
) {
3270 if (cs
->watchpoint_hit
) {
3271 if (cs
->watchpoint_hit
->flags
& BP_CPU
) {
3272 env
->spr
[SPR_DAR
] = cs
->watchpoint_hit
->hitaddr
;
3273 env
->spr
[SPR_DSISR
] = PPC_BIT(41);
3274 cs
->watchpoint_hit
= NULL
;
3275 raise_exception(env
, POWERPC_EXCP_DSI
);
3277 cs
->watchpoint_hit
= NULL
;
3278 } else if (cpu_breakpoint_test(cs
, env
->nip
, BP_CPU
)) {
3279 raise_exception_err(env
, POWERPC_EXCP_TRACE
,
3280 PPC_BIT(33) | PPC_BIT(43));
3286 bool ppc_cpu_debug_check_breakpoint(CPUState
*cs
)
3288 #if defined(TARGET_PPC64)
3289 CPUPPCState
*env
= cpu_env(cs
);
3291 if (env
->insns_flags2
& PPC2_ISA207S
) {
3294 priv
= env
->spr
[SPR_CIABR
] & PPC_BITMASK(62, 63);
3296 case 0x1: /* problem */
3297 return env
->msr
& ((target_ulong
)1 << MSR_PR
);
3298 case 0x2: /* supervisor */
3299 return (!(env
->msr
& ((target_ulong
)1 << MSR_PR
)) &&
3300 !(env
->msr
& ((target_ulong
)1 << MSR_HV
)));
3301 case 0x3: /* hypervisor */
3302 return (!(env
->msr
& ((target_ulong
)1 << MSR_PR
)) &&
3303 (env
->msr
& ((target_ulong
)1 << MSR_HV
)));
3305 g_assert_not_reached();
3313 bool ppc_cpu_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
3315 #if defined(TARGET_PPC64)
3316 CPUPPCState
*env
= cpu_env(cs
);
3318 if (env
->insns_flags2
& PPC2_ISA207S
) {
3319 if (wp
== env
->dawr0_watchpoint
) {
3320 uint32_t dawrx
= env
->spr
[SPR_DAWRX0
];
3321 bool wt
= extract32(dawrx
, PPC_BIT_NR(59), 1);
3322 bool wti
= extract32(dawrx
, PPC_BIT_NR(60), 1);
3323 bool hv
= extract32(dawrx
, PPC_BIT_NR(61), 1);
3324 bool sv
= extract32(dawrx
, PPC_BIT_NR(62), 1);
3325 bool pr
= extract32(dawrx
, PPC_BIT_NR(62), 1);
3327 if ((env
->msr
& ((target_ulong
)1 << MSR_PR
)) && !pr
) {
3329 } else if ((env
->msr
& ((target_ulong
)1 << MSR_HV
)) && !hv
) {
3336 if (env
->msr
& ((target_ulong
)1 << MSR_DR
)) {
3355 #endif /* CONFIG_TCG */
3356 #endif /* !CONFIG_USER_ONLY */