tcg/tci/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "tcg-be-null.h"
  26
  27 /* TODO list:
  28  * - See TODO comments in code.
  29  */
  30
  31 /* Marker for missing code. */
  32 #define TODO() \
  33     do { \
  34         fprintf(stderr, "TODO %s:%u: %s()\n", \
  35                 __FILE__, __LINE__, __func__); \
  36         tcg_abort(); \
  37     } while (0)
  38
  39 /* Bitfield n...m (in 32 bit value). */
  40 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
  41
  42 /* Macros used in tcg_target_op_defs. */
  43 #define R       "r"
  44 #define RI      "ri"
  45 #if TCG_TARGET_REG_BITS == 32
  46 # define R64    "r", "r"
  47 #else
  48 # define R64    "r"
  49 #endif
  50 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  51 # define L      "L", "L"
  52 # define S      "S", "S"
  53 #else
  54 # define L      "L"
  55 # define S      "S"
  56 #endif
  57
  58 /* TODO: documentation. */
  59 static const TCGTargetOpDef tcg_target_op_defs[] = {
  60     { INDEX_op_exit_tb, { NULL } },
  61     { INDEX_op_goto_tb, { NULL } },
  62     { INDEX_op_br, { NULL } },
  63
  64     { INDEX_op_ld8u_i32, { R, R } },
  65     { INDEX_op_ld8s_i32, { R, R } },
  66     { INDEX_op_ld16u_i32, { R, R } },
  67     { INDEX_op_ld16s_i32, { R, R } },
  68     { INDEX_op_ld_i32, { R, R } },
  69     { INDEX_op_st8_i32, { R, R } },
  70     { INDEX_op_st16_i32, { R, R } },
  71     { INDEX_op_st_i32, { R, R } },
  72
  73     { INDEX_op_add_i32, { R, RI, RI } },
  74     { INDEX_op_sub_i32, { R, RI, RI } },
  75     { INDEX_op_mul_i32, { R, RI, RI } },
  76 #if TCG_TARGET_HAS_div_i32
  77     { INDEX_op_div_i32, { R, R, R } },
  78     { INDEX_op_divu_i32, { R, R, R } },
  79     { INDEX_op_rem_i32, { R, R, R } },
  80     { INDEX_op_remu_i32, { R, R, R } },
  81 #elif TCG_TARGET_HAS_div2_i32
  82     { INDEX_op_div2_i32, { R, R, "0", "1", R } },
  83     { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
  84 #endif
  85     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
  86        If both operands are constants, we can optimize. */
  87     { INDEX_op_and_i32, { R, RI, RI } },
  88 #if TCG_TARGET_HAS_andc_i32
  89     { INDEX_op_andc_i32, { R, RI, RI } },
  90 #endif
  91 #if TCG_TARGET_HAS_eqv_i32
  92     { INDEX_op_eqv_i32, { R, RI, RI } },
  93 #endif
  94 #if TCG_TARGET_HAS_nand_i32
  95     { INDEX_op_nand_i32, { R, RI, RI } },
  96 #endif
  97 #if TCG_TARGET_HAS_nor_i32
  98     { INDEX_op_nor_i32, { R, RI, RI } },
  99 #endif
 100     { INDEX_op_or_i32, { R, RI, RI } },
 101 #if TCG_TARGET_HAS_orc_i32
 102     { INDEX_op_orc_i32, { R, RI, RI } },
 103 #endif
 104     { INDEX_op_xor_i32, { R, RI, RI } },
 105     { INDEX_op_shl_i32, { R, RI, RI } },
 106     { INDEX_op_shr_i32, { R, RI, RI } },
 107     { INDEX_op_sar_i32, { R, RI, RI } },
 108 #if TCG_TARGET_HAS_rot_i32
 109     { INDEX_op_rotl_i32, { R, RI, RI } },
 110     { INDEX_op_rotr_i32, { R, RI, RI } },
 111 #endif
 112 #if TCG_TARGET_HAS_deposit_i32
 113     { INDEX_op_deposit_i32, { R, "0", R } },
 114 #endif
 115
 116     { INDEX_op_brcond_i32, { R, RI } },
 117
 118     { INDEX_op_setcond_i32, { R, R, RI } },
 119 #if TCG_TARGET_REG_BITS == 64
 120     { INDEX_op_setcond_i64, { R, R, RI } },
 121 #endif /* TCG_TARGET_REG_BITS == 64 */
 122
 123 #if TCG_TARGET_REG_BITS == 32
 124     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
 125     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
 126     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
 127     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
 128     { INDEX_op_mulu2_i32, { R, R, R, R } },
 129     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
 130 #endif
 131
 132 #if TCG_TARGET_HAS_not_i32
 133     { INDEX_op_not_i32, { R, R } },
 134 #endif
 135 #if TCG_TARGET_HAS_neg_i32
 136     { INDEX_op_neg_i32, { R, R } },
 137 #endif
 138
 139 #if TCG_TARGET_REG_BITS == 64
 140     { INDEX_op_ld8u_i64, { R, R } },
 141     { INDEX_op_ld8s_i64, { R, R } },
 142     { INDEX_op_ld16u_i64, { R, R } },
 143     { INDEX_op_ld16s_i64, { R, R } },
 144     { INDEX_op_ld32u_i64, { R, R } },
 145     { INDEX_op_ld32s_i64, { R, R } },
 146     { INDEX_op_ld_i64, { R, R } },
 147
 148     { INDEX_op_st8_i64, { R, R } },
 149     { INDEX_op_st16_i64, { R, R } },
 150     { INDEX_op_st32_i64, { R, R } },
 151     { INDEX_op_st_i64, { R, R } },
 152
 153     { INDEX_op_add_i64, { R, RI, RI } },
 154     { INDEX_op_sub_i64, { R, RI, RI } },
 155     { INDEX_op_mul_i64, { R, RI, RI } },
 156 #if TCG_TARGET_HAS_div_i64
 157     { INDEX_op_div_i64, { R, R, R } },
 158     { INDEX_op_divu_i64, { R, R, R } },
 159     { INDEX_op_rem_i64, { R, R, R } },
 160     { INDEX_op_remu_i64, { R, R, R } },
 161 #elif TCG_TARGET_HAS_div2_i64
 162     { INDEX_op_div2_i64, { R, R, "0", "1", R } },
 163     { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
 164 #endif
 165     { INDEX_op_and_i64, { R, RI, RI } },
 166 #if TCG_TARGET_HAS_andc_i64
 167     { INDEX_op_andc_i64, { R, RI, RI } },
 168 #endif
 169 #if TCG_TARGET_HAS_eqv_i64
 170     { INDEX_op_eqv_i64, { R, RI, RI } },
 171 #endif
 172 #if TCG_TARGET_HAS_nand_i64
 173     { INDEX_op_nand_i64, { R, RI, RI } },
 174 #endif
 175 #if TCG_TARGET_HAS_nor_i64
 176     { INDEX_op_nor_i64, { R, RI, RI } },
 177 #endif
 178     { INDEX_op_or_i64, { R, RI, RI } },
 179 #if TCG_TARGET_HAS_orc_i64
 180     { INDEX_op_orc_i64, { R, RI, RI } },
 181 #endif
 182     { INDEX_op_xor_i64, { R, RI, RI } },
 183     { INDEX_op_shl_i64, { R, RI, RI } },
 184     { INDEX_op_shr_i64, { R, RI, RI } },
 185     { INDEX_op_sar_i64, { R, RI, RI } },
 186 #if TCG_TARGET_HAS_rot_i64
 187     { INDEX_op_rotl_i64, { R, RI, RI } },
 188     { INDEX_op_rotr_i64, { R, RI, RI } },
 189 #endif
 190 #if TCG_TARGET_HAS_deposit_i64
 191     { INDEX_op_deposit_i64, { R, "0", R } },
 192 #endif
 193     { INDEX_op_brcond_i64, { R, RI } },
 194
 195 #if TCG_TARGET_HAS_ext8s_i64
 196     { INDEX_op_ext8s_i64, { R, R } },
 197 #endif
 198 #if TCG_TARGET_HAS_ext16s_i64
 199     { INDEX_op_ext16s_i64, { R, R } },
 200 #endif
 201 #if TCG_TARGET_HAS_ext32s_i64
 202     { INDEX_op_ext32s_i64, { R, R } },
 203 #endif
 204 #if TCG_TARGET_HAS_ext8u_i64
 205     { INDEX_op_ext8u_i64, { R, R } },
 206 #endif
 207 #if TCG_TARGET_HAS_ext16u_i64
 208     { INDEX_op_ext16u_i64, { R, R } },
 209 #endif
 210 #if TCG_TARGET_HAS_ext32u_i64
 211     { INDEX_op_ext32u_i64, { R, R } },
 212 #endif
 213 #if TCG_TARGET_HAS_bswap16_i64
 214     { INDEX_op_bswap16_i64, { R, R } },
 215 #endif
 216 #if TCG_TARGET_HAS_bswap32_i64
 217     { INDEX_op_bswap32_i64, { R, R } },
 218 #endif
 219 #if TCG_TARGET_HAS_bswap64_i64
 220     { INDEX_op_bswap64_i64, { R, R } },
 221 #endif
 222 #if TCG_TARGET_HAS_not_i64
 223     { INDEX_op_not_i64, { R, R } },
 224 #endif
 225 #if TCG_TARGET_HAS_neg_i64
 226     { INDEX_op_neg_i64, { R, R } },
 227 #endif
 228 #endif /* TCG_TARGET_REG_BITS == 64 */
 229
 230     { INDEX_op_qemu_ld_i32, { R, L } },
 231     { INDEX_op_qemu_ld_i64, { R64, L } },
 232
 233     { INDEX_op_qemu_st_i32, { R, S } },
 234     { INDEX_op_qemu_st_i64, { R64, S } },
 235
 236 #if TCG_TARGET_HAS_ext8s_i32
 237     { INDEX_op_ext8s_i32, { R, R } },
 238 #endif
 239 #if TCG_TARGET_HAS_ext16s_i32
 240     { INDEX_op_ext16s_i32, { R, R } },
 241 #endif
 242 #if TCG_TARGET_HAS_ext8u_i32
 243     { INDEX_op_ext8u_i32, { R, R } },
 244 #endif
 245 #if TCG_TARGET_HAS_ext16u_i32
 246     { INDEX_op_ext16u_i32, { R, R } },
 247 #endif
 248
 249 #if TCG_TARGET_HAS_bswap16_i32
 250     { INDEX_op_bswap16_i32, { R, R } },
 251 #endif
 252 #if TCG_TARGET_HAS_bswap32_i32
 253     { INDEX_op_bswap32_i32, { R, R } },
 254 #endif
 255
 256     { -1 },
 257 };
 258
 259 static const int tcg_target_reg_alloc_order[] = {
 260     TCG_REG_R0,
 261     TCG_REG_R1,
 262     TCG_REG_R2,
 263     TCG_REG_R3,
 264 #if 0 /* used for TCG_REG_CALL_STACK */
 265     TCG_REG_R4,
 266 #endif
 267     TCG_REG_R5,
 268     TCG_REG_R6,
 269     TCG_REG_R7,
 270 #if TCG_TARGET_NB_REGS >= 16
 271     TCG_REG_R8,
 272     TCG_REG_R9,
 273     TCG_REG_R10,
 274     TCG_REG_R11,
 275     TCG_REG_R12,
 276     TCG_REG_R13,
 277     TCG_REG_R14,
 278     TCG_REG_R15,
 279 #endif
 280 };
 281
 282 #if MAX_OPC_PARAM_IARGS != 5
 283 # error Fix needed, number of supported input arguments changed!
 284 #endif
 285
 286 static const int tcg_target_call_iarg_regs[] = {
 287     TCG_REG_R0,
 288     TCG_REG_R1,
 289     TCG_REG_R2,
 290     TCG_REG_R3,
 291 #if 0 /* used for TCG_REG_CALL_STACK */
 292     TCG_REG_R4,
 293 #endif
 294     TCG_REG_R5,
 295 #if TCG_TARGET_REG_BITS == 32
 296     /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
 297     TCG_REG_R6,
 298     TCG_REG_R7,
 299 #if TCG_TARGET_NB_REGS >= 16
 300     TCG_REG_R8,
 301     TCG_REG_R9,
 302     TCG_REG_R10,
 303 #else
 304 # error Too few input registers available
 305 #endif
 306 #endif
 307 };
 308
 309 static const int tcg_target_call_oarg_regs[] = {
 310     TCG_REG_R0,
 311 #if TCG_TARGET_REG_BITS == 32
 312     TCG_REG_R1
 313 #endif
 314 };
 315
 316 #ifndef NDEBUG
 317 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 318     "r00",
 319     "r01",
 320     "r02",
 321     "r03",
 322     "r04",
 323     "r05",
 324     "r06",
 325     "r07",
 326 #if TCG_TARGET_NB_REGS >= 16
 327     "r08",
 328     "r09",
 329     "r10",
 330     "r11",
 331     "r12",
 332     "r13",
 333     "r14",
 334     "r15",
 335 #if TCG_TARGET_NB_REGS >= 32
 336     "r16",
 337     "r17",
 338     "r18",
 339     "r19",
 340     "r20",
 341     "r21",
 342     "r22",
 343     "r23",
 344     "r24",
 345     "r25",
 346     "r26",
 347     "r27",
 348     "r28",
 349     "r29",
 350     "r30",
 351     "r31"
 352 #endif
 353 #endif
 354 };
 355 #endif
 356
 357 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
 358                         intptr_t value, intptr_t addend)
 359 {
 360     /* tcg_out_reloc always uses the same type, addend. */
 361     assert(type == sizeof(tcg_target_long));
 362     assert(addend == 0);
 363     assert(value != 0);
 364     if (TCG_TARGET_REG_BITS == 32) {
 365         tcg_patch32(code_ptr, value);
 366     } else {
 367         tcg_patch64(code_ptr, value);
 368     }
 369 }
 370
 371 /* Parse target specific constraints. */
 372 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 373 {
 374     const char *ct_str = *pct_str;
 375     switch (ct_str[0]) {
 376     case 'r':
 377     case 'L':                   /* qemu_ld constraint */
 378     case 'S':                   /* qemu_st constraint */
 379         ct->ct |= TCG_CT_REG;
 380         tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
 381         break;
 382     default:
 383         return -1;
 384     }
 385     ct_str++;
 386     *pct_str = ct_str;
 387     return 0;
 388 }
 389
 390 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 391 /* Show current bytecode. Used by tcg interpreter. */
 392 void tci_disas(uint8_t opc)
 393 {
 394     const TCGOpDef *def = &tcg_op_defs[opc];
 395     fprintf(stderr, "TCG %s %u, %u, %u\n",
 396             def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
 397 }
 398 #endif
 399
 400 /* Write value (native size). */
 401 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
 402 {
 403     if (TCG_TARGET_REG_BITS == 32) {
 404         tcg_out32(s, v);
 405     } else {
 406         tcg_out64(s, v);
 407     }
 408 }
 409
 410 /* Write opcode. */
 411 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
 412 {
 413     tcg_out8(s, op);
 414     tcg_out8(s, 0);
 415 }
 416
 417 /* Write register. */
 418 static void tcg_out_r(TCGContext *s, TCGArg t0)
 419 {
 420     assert(t0 < TCG_TARGET_NB_REGS);
 421     tcg_out8(s, t0);
 422 }
 423
 424 /* Write register or constant (native size). */
 425 static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
 426 {
 427     if (const_arg) {
 428         assert(const_arg == 1);
 429         tcg_out8(s, TCG_CONST);
 430         tcg_out_i(s, arg);
 431     } else {
 432         tcg_out_r(s, arg);
 433     }
 434 }
 435
 436 /* Write register or constant (32 bit). */
 437 static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
 438 {
 439     if (const_arg) {
 440         assert(const_arg == 1);
 441         tcg_out8(s, TCG_CONST);
 442         tcg_out32(s, arg);
 443     } else {
 444         tcg_out_r(s, arg);
 445     }
 446 }
 447
 448 #if TCG_TARGET_REG_BITS == 64
 449 /* Write register or constant (64 bit). */
 450 static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
 451 {
 452     if (const_arg) {
 453         assert(const_arg == 1);
 454         tcg_out8(s, TCG_CONST);
 455         tcg_out64(s, arg);
 456     } else {
 457         tcg_out_r(s, arg);
 458     }
 459 }
 460 #endif
 461
 462 /* Write label. */
 463 static void tci_out_label(TCGContext *s, TCGLabel *label)
 464 {
 465     if (label->has_value) {
 466         tcg_out_i(s, label->u.value);
 467         assert(label->u.value);
 468     } else {
 469         tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
 470         s->code_ptr += sizeof(tcg_target_ulong);
 471     }
 472 }
 473
 474 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
 475                        intptr_t arg2)
 476 {
 477     uint8_t *old_code_ptr = s->code_ptr;
 478     if (type == TCG_TYPE_I32) {
 479         tcg_out_op_t(s, INDEX_op_ld_i32);
 480         tcg_out_r(s, ret);
 481         tcg_out_r(s, arg1);
 482         tcg_out32(s, arg2);
 483     } else {
 484         assert(type == TCG_TYPE_I64);
 485 #if TCG_TARGET_REG_BITS == 64
 486         tcg_out_op_t(s, INDEX_op_ld_i64);
 487         tcg_out_r(s, ret);
 488         tcg_out_r(s, arg1);
 489         assert(arg2 == (int32_t)arg2);
 490         tcg_out32(s, arg2);
 491 #else
 492         TODO();
 493 #endif
 494     }
 495     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 496 }
 497
 498 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 499 {
 500     uint8_t *old_code_ptr = s->code_ptr;
 501     assert(ret != arg);
 502 #if TCG_TARGET_REG_BITS == 32
 503     tcg_out_op_t(s, INDEX_op_mov_i32);
 504 #else
 505     tcg_out_op_t(s, INDEX_op_mov_i64);
 506 #endif
 507     tcg_out_r(s, ret);
 508     tcg_out_r(s, arg);
 509     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 510 }
 511
 512 static void tcg_out_movi(TCGContext *s, TCGType type,
 513                          TCGReg t0, tcg_target_long arg)
 514 {
 515     uint8_t *old_code_ptr = s->code_ptr;
 516     uint32_t arg32 = arg;
 517     if (type == TCG_TYPE_I32 || arg == arg32) {
 518         tcg_out_op_t(s, INDEX_op_movi_i32);
 519         tcg_out_r(s, t0);
 520         tcg_out32(s, arg32);
 521     } else {
 522         assert(type == TCG_TYPE_I64);
 523 #if TCG_TARGET_REG_BITS == 64
 524         tcg_out_op_t(s, INDEX_op_movi_i64);
 525         tcg_out_r(s, t0);
 526         tcg_out64(s, arg);
 527 #else
 528         TODO();
 529 #endif
 530     }
 531     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 532 }
 533
 534 static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 535 {
 536     uint8_t *old_code_ptr = s->code_ptr;
 537     tcg_out_op_t(s, INDEX_op_call);
 538     tcg_out_ri(s, 1, (uintptr_t)arg);
 539     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 540 }
 541
 542 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
 543                        const int *const_args)
 544 {
 545     uint8_t *old_code_ptr = s->code_ptr;
 546
 547     tcg_out_op_t(s, opc);
 548
 549     switch (opc) {
 550     case INDEX_op_exit_tb:
 551         tcg_out64(s, args[0]);
 552         break;
 553     case INDEX_op_goto_tb:
 554         if (s->tb_jmp_offset) {
 555             /* Direct jump method. */
 556             assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
 557             s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
 558             tcg_out32(s, 0);
 559         } else {
 560             /* Indirect jump method. */
 561             TODO();
 562         }
 563         assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
 564         s->tb_next_offset[args[0]] = tcg_current_code_size(s);
 565         break;
 566     case INDEX_op_br:
 567         tci_out_label(s, arg_label(args[0]));
 568         break;
 569     case INDEX_op_setcond_i32:
 570         tcg_out_r(s, args[0]);
 571         tcg_out_r(s, args[1]);
 572         tcg_out_ri32(s, const_args[2], args[2]);
 573         tcg_out8(s, args[3]);   /* condition */
 574         break;
 575 #if TCG_TARGET_REG_BITS == 32
 576     case INDEX_op_setcond2_i32:
 577         /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
 578         tcg_out_r(s, args[0]);
 579         tcg_out_r(s, args[1]);
 580         tcg_out_r(s, args[2]);
 581         tcg_out_ri32(s, const_args[3], args[3]);
 582         tcg_out_ri32(s, const_args[4], args[4]);
 583         tcg_out8(s, args[5]);   /* condition */
 584         break;
 585 #elif TCG_TARGET_REG_BITS == 64
 586     case INDEX_op_setcond_i64:
 587         tcg_out_r(s, args[0]);
 588         tcg_out_r(s, args[1]);
 589         tcg_out_ri64(s, const_args[2], args[2]);
 590         tcg_out8(s, args[3]);   /* condition */
 591         break;
 592 #endif
 593     case INDEX_op_ld8u_i32:
 594     case INDEX_op_ld8s_i32:
 595     case INDEX_op_ld16u_i32:
 596     case INDEX_op_ld16s_i32:
 597     case INDEX_op_ld_i32:
 598     case INDEX_op_st8_i32:
 599     case INDEX_op_st16_i32:
 600     case INDEX_op_st_i32:
 601     case INDEX_op_ld8u_i64:
 602     case INDEX_op_ld8s_i64:
 603     case INDEX_op_ld16u_i64:
 604     case INDEX_op_ld16s_i64:
 605     case INDEX_op_ld32u_i64:
 606     case INDEX_op_ld32s_i64:
 607     case INDEX_op_ld_i64:
 608     case INDEX_op_st8_i64:
 609     case INDEX_op_st16_i64:
 610     case INDEX_op_st32_i64:
 611     case INDEX_op_st_i64:
 612         tcg_out_r(s, args[0]);
 613         tcg_out_r(s, args[1]);
 614         assert(args[2] == (int32_t)args[2]);
 615         tcg_out32(s, args[2]);
 616         break;
 617     case INDEX_op_add_i32:
 618     case INDEX_op_sub_i32:
 619     case INDEX_op_mul_i32:
 620     case INDEX_op_and_i32:
 621     case INDEX_op_andc_i32:     /* Optional (TCG_TARGET_HAS_andc_i32). */
 622     case INDEX_op_eqv_i32:      /* Optional (TCG_TARGET_HAS_eqv_i32). */
 623     case INDEX_op_nand_i32:     /* Optional (TCG_TARGET_HAS_nand_i32). */
 624     case INDEX_op_nor_i32:      /* Optional (TCG_TARGET_HAS_nor_i32). */
 625     case INDEX_op_or_i32:
 626     case INDEX_op_orc_i32:      /* Optional (TCG_TARGET_HAS_orc_i32). */
 627     case INDEX_op_xor_i32:
 628     case INDEX_op_shl_i32:
 629     case INDEX_op_shr_i32:
 630     case INDEX_op_sar_i32:
 631     case INDEX_op_rotl_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 632     case INDEX_op_rotr_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 633         tcg_out_r(s, args[0]);
 634         tcg_out_ri32(s, const_args[1], args[1]);
 635         tcg_out_ri32(s, const_args[2], args[2]);
 636         break;
 637     case INDEX_op_deposit_i32:  /* Optional (TCG_TARGET_HAS_deposit_i32). */
 638         tcg_out_r(s, args[0]);
 639         tcg_out_r(s, args[1]);
 640         tcg_out_r(s, args[2]);
 641         assert(args[3] <= UINT8_MAX);
 642         tcg_out8(s, args[3]);
 643         assert(args[4] <= UINT8_MAX);
 644         tcg_out8(s, args[4]);
 645         break;
 646
 647 #if TCG_TARGET_REG_BITS == 64
 648     case INDEX_op_add_i64:
 649     case INDEX_op_sub_i64:
 650     case INDEX_op_mul_i64:
 651     case INDEX_op_and_i64:
 652     case INDEX_op_andc_i64:     /* Optional (TCG_TARGET_HAS_andc_i64). */
 653     case INDEX_op_eqv_i64:      /* Optional (TCG_TARGET_HAS_eqv_i64). */
 654     case INDEX_op_nand_i64:     /* Optional (TCG_TARGET_HAS_nand_i64). */
 655     case INDEX_op_nor_i64:      /* Optional (TCG_TARGET_HAS_nor_i64). */
 656     case INDEX_op_or_i64:
 657     case INDEX_op_orc_i64:      /* Optional (TCG_TARGET_HAS_orc_i64). */
 658     case INDEX_op_xor_i64:
 659     case INDEX_op_shl_i64:
 660     case INDEX_op_shr_i64:
 661     case INDEX_op_sar_i64:
 662     case INDEX_op_rotl_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 663     case INDEX_op_rotr_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 664         tcg_out_r(s, args[0]);
 665         tcg_out_ri64(s, const_args[1], args[1]);
 666         tcg_out_ri64(s, const_args[2], args[2]);
 667         break;
 668     case INDEX_op_deposit_i64:  /* Optional (TCG_TARGET_HAS_deposit_i64). */
 669         tcg_out_r(s, args[0]);
 670         tcg_out_r(s, args[1]);
 671         tcg_out_r(s, args[2]);
 672         assert(args[3] <= UINT8_MAX);
 673         tcg_out8(s, args[3]);
 674         assert(args[4] <= UINT8_MAX);
 675         tcg_out8(s, args[4]);
 676         break;
 677     case INDEX_op_div_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 678     case INDEX_op_divu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 679     case INDEX_op_rem_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 680     case INDEX_op_remu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 681         TODO();
 682         break;
 683     case INDEX_op_div2_i64:     /* Optional (TCG_TARGET_HAS_div2_i64). */
 684     case INDEX_op_divu2_i64:    /* Optional (TCG_TARGET_HAS_div2_i64). */
 685         TODO();
 686         break;
 687     case INDEX_op_brcond_i64:
 688         tcg_out_r(s, args[0]);
 689         tcg_out_ri64(s, const_args[1], args[1]);
 690         tcg_out8(s, args[2]);           /* condition */
 691         tci_out_label(s, arg_label(args[3]));
 692         break;
 693     case INDEX_op_bswap16_i64:  /* Optional (TCG_TARGET_HAS_bswap16_i64). */
 694     case INDEX_op_bswap32_i64:  /* Optional (TCG_TARGET_HAS_bswap32_i64). */
 695     case INDEX_op_bswap64_i64:  /* Optional (TCG_TARGET_HAS_bswap64_i64). */
 696     case INDEX_op_not_i64:      /* Optional (TCG_TARGET_HAS_not_i64). */
 697     case INDEX_op_neg_i64:      /* Optional (TCG_TARGET_HAS_neg_i64). */
 698     case INDEX_op_ext8s_i64:    /* Optional (TCG_TARGET_HAS_ext8s_i64). */
 699     case INDEX_op_ext8u_i64:    /* Optional (TCG_TARGET_HAS_ext8u_i64). */
 700     case INDEX_op_ext16s_i64:   /* Optional (TCG_TARGET_HAS_ext16s_i64). */
 701     case INDEX_op_ext16u_i64:   /* Optional (TCG_TARGET_HAS_ext16u_i64). */
 702     case INDEX_op_ext32s_i64:   /* Optional (TCG_TARGET_HAS_ext32s_i64). */
 703     case INDEX_op_ext32u_i64:   /* Optional (TCG_TARGET_HAS_ext32u_i64). */
 704 #endif /* TCG_TARGET_REG_BITS == 64 */
 705     case INDEX_op_neg_i32:      /* Optional (TCG_TARGET_HAS_neg_i32). */
 706     case INDEX_op_not_i32:      /* Optional (TCG_TARGET_HAS_not_i32). */
 707     case INDEX_op_ext8s_i32:    /* Optional (TCG_TARGET_HAS_ext8s_i32). */
 708     case INDEX_op_ext16s_i32:   /* Optional (TCG_TARGET_HAS_ext16s_i32). */
 709     case INDEX_op_ext8u_i32:    /* Optional (TCG_TARGET_HAS_ext8u_i32). */
 710     case INDEX_op_ext16u_i32:   /* Optional (TCG_TARGET_HAS_ext16u_i32). */
 711     case INDEX_op_bswap16_i32:  /* Optional (TCG_TARGET_HAS_bswap16_i32). */
 712     case INDEX_op_bswap32_i32:  /* Optional (TCG_TARGET_HAS_bswap32_i32). */
 713         tcg_out_r(s, args[0]);
 714         tcg_out_r(s, args[1]);
 715         break;
 716     case INDEX_op_div_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 717     case INDEX_op_divu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 718     case INDEX_op_rem_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 719     case INDEX_op_remu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 720         tcg_out_r(s, args[0]);
 721         tcg_out_ri32(s, const_args[1], args[1]);
 722         tcg_out_ri32(s, const_args[2], args[2]);
 723         break;
 724     case INDEX_op_div2_i32:     /* Optional (TCG_TARGET_HAS_div2_i32). */
 725     case INDEX_op_divu2_i32:    /* Optional (TCG_TARGET_HAS_div2_i32). */
 726         TODO();
 727         break;
 728 #if TCG_TARGET_REG_BITS == 32
 729     case INDEX_op_add2_i32:
 730     case INDEX_op_sub2_i32:
 731         tcg_out_r(s, args[0]);
 732         tcg_out_r(s, args[1]);
 733         tcg_out_r(s, args[2]);
 734         tcg_out_r(s, args[3]);
 735         tcg_out_r(s, args[4]);
 736         tcg_out_r(s, args[5]);
 737         break;
 738     case INDEX_op_brcond2_i32:
 739         tcg_out_r(s, args[0]);
 740         tcg_out_r(s, args[1]);
 741         tcg_out_ri32(s, const_args[2], args[2]);
 742         tcg_out_ri32(s, const_args[3], args[3]);
 743         tcg_out8(s, args[4]);           /* condition */
 744         tci_out_label(s, arg_label(args[5]));
 745         break;
 746     case INDEX_op_mulu2_i32:
 747         tcg_out_r(s, args[0]);
 748         tcg_out_r(s, args[1]);
 749         tcg_out_r(s, args[2]);
 750         tcg_out_r(s, args[3]);
 751         break;
 752 #endif
 753     case INDEX_op_brcond_i32:
 754         tcg_out_r(s, args[0]);
 755         tcg_out_ri32(s, const_args[1], args[1]);
 756         tcg_out8(s, args[2]);           /* condition */
 757         tci_out_label(s, arg_label(args[3]));
 758         break;
 759     case INDEX_op_qemu_ld_i32:
 760         tcg_out_r(s, *args++);
 761         tcg_out_r(s, *args++);
 762         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 763             tcg_out_r(s, *args++);
 764         }
 765         tcg_out_i(s, *args++);
 766         break;
 767     case INDEX_op_qemu_ld_i64:
 768         tcg_out_r(s, *args++);
 769         if (TCG_TARGET_REG_BITS == 32) {
 770             tcg_out_r(s, *args++);
 771         }
 772         tcg_out_r(s, *args++);
 773         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 774             tcg_out_r(s, *args++);
 775         }
 776         tcg_out_i(s, *args++);
 777         break;
 778     case INDEX_op_qemu_st_i32:
 779         tcg_out_r(s, *args++);
 780         tcg_out_r(s, *args++);
 781         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 782             tcg_out_r(s, *args++);
 783         }
 784         tcg_out_i(s, *args++);
 785         break;
 786     case INDEX_op_qemu_st_i64:
 787         tcg_out_r(s, *args++);
 788         if (TCG_TARGET_REG_BITS == 32) {
 789             tcg_out_r(s, *args++);
 790         }
 791         tcg_out_r(s, *args++);
 792         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 793             tcg_out_r(s, *args++);
 794         }
 795         tcg_out_i(s, *args++);
 796         break;
 797     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
 798     case INDEX_op_mov_i64:
 799     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
 800     case INDEX_op_movi_i64:
 801     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
 802     default:
 803         tcg_abort();
 804     }
 805     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 806 }
 807
 808 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 809                        intptr_t arg2)
 810 {
 811     uint8_t *old_code_ptr = s->code_ptr;
 812     if (type == TCG_TYPE_I32) {
 813         tcg_out_op_t(s, INDEX_op_st_i32);
 814         tcg_out_r(s, arg);
 815         tcg_out_r(s, arg1);
 816         tcg_out32(s, arg2);
 817     } else {
 818         assert(type == TCG_TYPE_I64);
 819 #if TCG_TARGET_REG_BITS == 64
 820         tcg_out_op_t(s, INDEX_op_st_i64);
 821         tcg_out_r(s, arg);
 822         tcg_out_r(s, arg1);
 823         tcg_out32(s, arg2);
 824 #else
 825         TODO();
 826 #endif
 827     }
 828     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 829 }
 830
 831 /* Test if a constant matches the constraint. */
 832 static int tcg_target_const_match(tcg_target_long val, TCGType type,
 833                                   const TCGArgConstraint *arg_ct)
 834 {
 835     /* No need to return 0 or 1, 0 or != 0 is good enough. */
 836     return arg_ct->ct & TCG_CT_CONST;
 837 }
 838
 839 static void tcg_target_init(TCGContext *s)
 840 {
 841 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 842     const char *envval = getenv("DEBUG_TCG");
 843     if (envval) {
 844         qemu_set_log(strtol(envval, NULL, 0));
 845     }
 846 #endif
 847
 848     /* The current code uses uint8_t for tcg operations. */
 849     assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX);
 850
 851     /* Registers available for 32 bit operations. */
 852     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
 853                      BIT(TCG_TARGET_NB_REGS) - 1);
 854     /* Registers available for 64 bit operations. */
 855     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
 856                      BIT(TCG_TARGET_NB_REGS) - 1);
 857     /* TODO: Which registers should be set here? */
 858     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 859                      BIT(TCG_TARGET_NB_REGS) - 1);
 860
 861     tcg_regset_clear(s->reserved_regs);
 862     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
 863     tcg_add_target_add_op_defs(tcg_target_op_defs);
 864
 865     /* We use negative offsets from "sp" so that we can distinguish
 866        stores that might pretend to be call arguments.  */
 867     tcg_set_frame(s, TCG_REG_CALL_STACK,
 868                   -CPU_TEMP_BUF_NLONGS * sizeof(long),
 869                   CPU_TEMP_BUF_NLONGS * sizeof(long));
 870 }
 871
 872 /* Generate global QEMU prologue and epilogue code. */
 873 static inline void tcg_target_qemu_prologue(TCGContext *s)
 874 {
 875 }